1689 files changed, 146222 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/README b/testsuite/vests/vhdl-93/billowitch/compliant/README
new file mode 100644
index 0000000..d216c07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/README
@@ -0,0 +1,8 @@
+The following files have been modified to be VHDL 93 compliant.  (In 
+VHDL 87, string literals like B"0010" had to be of type bit vector.  Now,
+they can be of any character type.)
+
+tc2759.vhd
+tc2761.vhd
+tc2767.vhd 
+tc2768.vhd
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp b/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp
new file mode 100644
index 0000000..28a9624
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp
@@ -0,0 +1,1693 @@
+
+# Copyright (C) Clifton Labs, Inc
+# All rights reserved.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# This script should runs the tests in this subdirectory.  It should
+# only use functions that are defined (or redefined by the tool under
+# test) in vests.drivers.exp and the reporting functions in
+# vests-support.exp.  That way the integration of vests with another
+# VHDL system requires only the redefinition of the functions in
+# vests-drivers.exp. 
+
+setup_test_group "Billowitch:Compliant Cases" "1076-1993"
+
+run_compliant_test tc1.vhd
+
+run_compliant_test tc10.vhd
+run_compliant_test tc14.vhd
+run_compliant_test tc15.vhd
+run_compliant_test tc17.vhd
+run_compliant_test tc18.vhd
+run_compliant_test tc23.vhd
+run_compliant_test tc24.vhd
+run_compliant_test tc25.vhd
+run_compliant_test tc26.vhd
+run_compliant_test tc27.vhd
+run_compliant_test tc29.vhd
+run_compliant_test tc30.vhd
+run_compliant_test tc31.vhd
+run_compliant_test tc32.vhd
+run_compliant_test tc33.vhd
+run_compliant_test tc35.vhd
+run_compliant_test tc36.vhd
+run_compliant_test tc37.vhd
+run_compliant_test tc38.vhd
+run_compliant_test tc39.vhd
+run_compliant_test tc40.vhd
+run_compliant_test tc41.vhd
+run_compliant_test tc43.vhd
+run_compliant_test tc45.vhd
+run_compliant_test tc52.vhd
+run_compliant_test tc53.vhd
+run_compliant_test tc54.vhd
+run_compliant_test tc56.vhd
+run_compliant_test tc63.vhd
+run_compliant_test tc64.vhd
+run_compliant_test tc66.vhd
+run_compliant_test tc68.vhd
+run_compliant_test tc69.vhd
+run_compliant_test tc70.vhd
+run_compliant_test tc76.vhd
+run_compliant_test tc80.vhd
+run_compliant_test tc81.vhd
+run_compliant_test tc82.vhd
+run_compliant_test tc83.vhd
+run_compliant_test tc84.vhd
+run_compliant_test tc86.vhd
+run_compliant_test tc87.vhd
+run_compliant_test tc88.vhd
+run_compliant_test tc90.vhd
+run_compliant_test tc91.vhd
+run_compliant_test tc98.vhd
+run_compliant_test tc99.vhd
+
+run_compliant_test tc100.vhd
+run_compliant_test tc110.vhd
+run_compliant_test tc111.vhd
+run_compliant_test tc113.vhd
+run_compliant_test tc114.vhd
+run_compliant_test tc115.vhd
+run_compliant_test tc116.vhd
+run_compliant_test tc117.vhd
+run_compliant_test tc118.vhd
+run_compliant_test tc119.vhd
+run_compliant_test tc131.vhd
+run_compliant_test tc133.vhd
+run_compliant_test tc134.vhd
+run_compliant_test tc135.vhd
+run_compliant_test tc136.vhd
+run_compliant_test tc137.vhd
+run_compliant_test tc138.vhd
+run_compliant_test tc141.vhd
+run_compliant_test tc143.vhd
+run_compliant_test tc146.vhd
+run_compliant_test tc147.vhd
+run_compliant_test tc148.vhd
+run_compliant_test tc149.vhd
+run_compliant_test tc150.vhd
+run_compliant_test tc154.vhd
+run_compliant_test tc157.vhd
+run_compliant_test tc158.vhd
+run_compliant_test tc162.vhd
+run_compliant_test tc163.vhd
+run_compliant_test tc164.vhd
+run_compliant_test tc166.vhd
+run_compliant_test tc167.vhd
+run_compliant_test tc168.vhd
+run_compliant_test tc169.vhd
+run_compliant_test tc171.vhd
+run_compliant_test tc172.vhd
+run_compliant_test tc173.vhd
+run_compliant_test tc176.vhd
+run_compliant_test tc179.vhd
+run_compliant_test tc180.vhd
+run_compliant_test tc182.vhd
+run_compliant_test tc183.vhd
+run_compliant_test tc187.vhd
+run_compliant_test tc188.vhd
+run_compliant_test tc194.vhd
+run_compliant_test tc198.vhd
+run_compliant_test tc201.vhd
+run_compliant_test tc203.vhd
+run_compliant_test tc204.vhd
+run_compliant_test tc205.vhd
+run_compliant_test tc206.vhd
+run_compliant_test tc208.vhd
+run_compliant_test tc209.vhd
+run_compliant_test tc211.vhd
+run_compliant_test tc213.vhd
+run_compliant_test tc217.vhd
+run_compliant_test tc218.vhd
+run_compliant_test tc219.vhd
+run_compliant_test tc220.vhd
+run_compliant_test tc228.vhd
+run_compliant_test tc229.vhd
+run_compliant_test tc230.vhd
+run_compliant_test tc234.vhd
+run_compliant_test tc239.vhd
+run_compliant_test tc241.vhd
+run_compliant_test tc251.vhd
+run_compliant_test tc254.vhd
+run_compliant_test tc265.vhd
+run_compliant_test tc272.vhd
+run_compliant_test tc276.vhd
+run_compliant_test tc277.vhd
+run_compliant_test tc278.vhd
+run_compliant_test tc279.vhd
+run_compliant_test tc281.vhd
+run_compliant_test tc284.vhd
+run_compliant_test tc285.vhd
+run_compliant_test tc286.vhd
+run_compliant_test tc287.vhd
+run_compliant_test tc288.vhd
+run_compliant_test tc290.vhd
+run_compliant_test tc291.vhd
+run_compliant_test tc292.vhd
+run_compliant_test tc293.vhd
+run_compliant_test tc294.vhd
+run_compliant_test tc295.vhd
+run_compliant_test tc297.vhd
+run_compliant_test tc298.vhd
+run_compliant_test tc299.vhd
+run_compliant_test tc301.vhd
+run_compliant_test tc308.vhd
+run_compliant_test tc309.vhd
+run_compliant_test tc311.vhd
+run_compliant_test tc312.vhd
+run_compliant_test tc313.vhd
+run_compliant_test tc314.vhd
+run_compliant_test tc317.vhd
+run_compliant_test tc318.vhd
+run_compliant_test tc319.vhd
+run_compliant_test tc320.vhd
+run_compliant_test tc322.vhd
+run_compliant_test tc323.vhd
+run_compliant_test tc326.vhd
+run_compliant_test tc333.vhd
+run_compliant_test tc334.vhd
+run_compliant_test tc335.vhd
+run_compliant_test tc337.vhd
+run_compliant_test tc339.vhd
+run_compliant_test tc341.vhd
+run_compliant_test tc343.vhd
+run_compliant_test tc344.vhd
+run_compliant_test tc346.vhd
+run_compliant_test tc347.vhd
+run_compliant_test tc349.vhd
+run_compliant_test tc350.vhd
+run_compliant_test tc351.vhd
+run_compliant_test tc355.vhd
+run_compliant_test tc359.vhd
+run_compliant_test tc361.vhd
+run_compliant_test tc364.vhd
+run_compliant_test tc365.vhd
+run_compliant_test tc366.vhd
+run_compliant_test tc376.vhd
+run_compliant_test tc377.vhd
+run_compliant_test tc378.vhd
+run_compliant_test tc381.vhd
+run_compliant_test tc382.vhd
+run_compliant_test tc385.vhd
+run_compliant_test tc386.vhd
+run_compliant_test tc387.vhd
+run_compliant_test tc388.vhd
+run_compliant_test tc392.vhd
+run_compliant_test tc393.vhd
+run_compliant_test tc395.vhd
+run_compliant_test tc397.vhd
+run_compliant_test tc398.vhd
+run_compliant_test tc399.vhd
+run_compliant_test tc400.vhd
+run_compliant_test tc401.vhd
+run_compliant_test tc402.vhd
+run_compliant_test tc403.vhd
+run_compliant_test tc404.vhd
+run_compliant_test tc406.vhd
+run_compliant_test tc407.vhd
+run_compliant_test tc408.vhd
+run_compliant_test tc409.vhd
+run_compliant_test tc410.vhd
+run_compliant_test tc411.vhd
+run_compliant_test tc412.vhd
+run_compliant_test tc413.vhd
+run_compliant_test tc414.vhd
+run_compliant_test tc415.vhd
+run_compliant_test tc416.vhd
+run_compliant_test tc417.vhd
+run_compliant_test tc418.vhd
+run_compliant_test tc419.vhd
+run_compliant_test tc420.vhd
+run_compliant_test tc421.vhd
+run_compliant_test tc422.vhd
+run_compliant_test tc423.vhd
+run_compliant_test tc424.vhd
+run_compliant_test tc425.vhd
+run_compliant_test tc426.vhd
+run_compliant_test tc427.vhd
+run_compliant_test tc428.vhd
+run_compliant_test tc429.vhd
+run_compliant_test tc430.vhd
+run_compliant_test tc431.vhd
+run_compliant_test tc432.vhd
+run_compliant_test tc433.vhd
+run_compliant_test tc434.vhd
+run_compliant_test tc435.vhd
+run_compliant_test tc436.vhd
+run_compliant_test tc437.vhd
+run_compliant_test tc438.vhd
+run_compliant_test tc439.vhd
+run_compliant_test tc440.vhd
+run_compliant_test tc441.vhd
+run_compliant_test tc442.vhd
+run_compliant_test tc443.vhd
+run_compliant_test tc444.vhd
+run_compliant_test tc445.vhd
+run_compliant_test tc446.vhd
+run_compliant_test tc447.vhd
+run_compliant_test tc448.vhd
+run_compliant_test tc449.vhd
+run_compliant_test tc450.vhd
+run_compliant_test tc451.vhd
+run_compliant_test tc452.vhd
+run_compliant_test tc453.vhd
+run_compliant_test tc454.vhd
+run_compliant_test tc455.vhd
+run_compliant_test tc456.vhd
+run_compliant_test tc457.vhd
+run_compliant_test tc458.vhd
+run_compliant_test tc459.vhd
+run_compliant_test tc460.vhd
+run_compliant_test tc461.vhd
+run_compliant_test tc462.vhd
+run_compliant_test tc463.vhd
+run_compliant_test tc464.vhd
+run_compliant_test tc465.vhd
+run_compliant_test tc466.vhd
+run_compliant_test tc467.vhd
+run_compliant_test tc468.vhd
+run_compliant_test tc469.vhd
+run_compliant_test tc470.vhd
+run_compliant_test tc471.vhd
+run_compliant_test tc472.vhd
+run_compliant_test tc473.vhd
+run_compliant_test tc474.vhd
+run_compliant_test tc475.vhd
+run_compliant_test tc476.vhd
+run_compliant_test tc477.vhd
+run_compliant_test tc478.vhd
+run_compliant_test tc479.vhd
+run_compliant_test tc480.vhd
+run_compliant_test tc481.vhd
+run_compliant_test tc482.vhd
+run_compliant_test tc483.vhd
+run_compliant_test tc484.vhd
+run_compliant_test tc485.vhd
+run_compliant_test tc486.vhd
+run_compliant_test tc487.vhd
+run_compliant_test tc488.vhd
+run_compliant_test tc489.vhd
+run_compliant_test tc490.vhd
+run_compliant_test tc491.vhd
+run_compliant_test tc492.vhd
+run_compliant_test tc493.vhd
+run_compliant_test tc494.vhd
+run_compliant_test tc495.vhd
+run_compliant_test tc496.vhd
+run_compliant_test tc497.vhd
+run_compliant_test tc498.vhd
+run_compliant_test tc499.vhd
+run_compliant_test tc500.vhd
+run_compliant_test tc501.vhd
+run_compliant_test tc503.vhd
+run_compliant_test tc505.vhd
+run_compliant_test tc512.vhd
+run_compliant_test tc513.vhd
+run_compliant_test tc515.vhd
+run_compliant_test tc516.vhd
+run_compliant_test tc517.vhd
+run_compliant_test tc519.vhd
+run_compliant_test tc520.vhd
+run_compliant_test tc521.vhd
+run_compliant_test tc522.vhd
+run_compliant_test tc523.vhd
+run_compliant_test tc524.vhd
+run_compliant_test tc525.vhd
+run_compliant_test tc526.vhd
+run_compliant_test tc527.vhd
+run_compliant_test tc528.vhd
+run_compliant_test tc529.vhd
+run_compliant_test tc530.vhd
+run_compliant_test tc531.vhd
+run_compliant_test tc534.vhd
+run_compliant_test tc535.vhd
+run_compliant_test tc537.vhd
+run_compliant_test tc538.vhd
+run_compliant_test tc539.vhd
+run_compliant_test tc541.vhd
+run_compliant_test tc542.vhd
+run_compliant_test tc544.vhd
+run_compliant_test tc545.vhd
+run_compliant_test tc546.vhd
+run_compliant_test tc554.vhd INPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc555.vhd OUTPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc556.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc557.vhd OUTPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc558.vhd INPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc559.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc560.vhd OUTPUT=iofile.16:iofiles/iofile.16
+run_compliant_test tc561.vhd INPUT=iofile.16:iofiles/iofile.16
+run_compliant_test tc562.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc563.vhd OUTPUT=iofile.17:iofiles/iofile.17
+run_compliant_test tc564.vhd INPUT=iofile.17:iofiles/iofile.17
+run_compliant_test tc565.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc566.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc567.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc568.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc569.vhd OUTPUT=iofile.19:iofiles/iofile.19
+run_compliant_test tc570.vhd INPUT=iofile.19:iofiles/iofile.19
+run_compliant_test tc571.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc572.vhd OUTPUT=iofile.20:iofiles/iofile.20
+run_compliant_test tc573.vhd INPUT=iofile.20:iofiles/iofile.20
+run_compliant_test tc574.vhd OUTPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc575.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc576.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc577.vhd INPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc578.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc579.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc580.vhd OUTPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc581.vhd OUTPUT=iofile.21:iofiles/iofile.21
+run_compliant_test tc582.vhd INPUT=iofile.21:iofiles/iofile.21
+run_compliant_test tc583.vhd OUTPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc584.vhd OUTPUT=iofile.22:iofiles/iofile.22
+run_compliant_test tc585.vhd INPUT=iofile.22:iofiles/iofile.22
+run_compliant_test tc586.vhd OUTPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc587.vhd OUTPUT=iofile.23:iofiles/iofile.23
+run_compliant_test tc588.vhd INPUT=iofile.23:iofiles/iofile.23
+run_compliant_test tc589.vhd INPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc590.vhd OUTPUT=iofile.24:iofiles/iofile.24
+run_compliant_test tc591.vhd INPUT=iofile.24:iofiles/iofile.24
+run_compliant_test tc592.vhd INPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc593.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc594.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc595.vhd INPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc596.vhd OUTPUT=iofile.26:iofiles/iofile.26
+run_compliant_test tc597.vhd INPUT=iofile.26:iofiles/iofile.26
+run_compliant_test tc598.vhd OUTPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc599.vhd OUTPUT=iofile.27:iofiles/iofile.27
+run_compliant_test tc600.vhd INPUT=iofile.27:iofiles/iofile.27
+run_compliant_test tc601.vhd INPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc602.vhd OUTPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc603.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc604.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc605.vhd OUTPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc606.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc607.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc608.vhd INPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc609.vhd OUTPUT=iofile.33:iofiles/iofile.33
+run_compliant_test tc610.vhd INPUT=iofile.33:iofiles/iofile.33
+run_compliant_test tc611.vhd INPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc612.vhd OUTPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc613.vhd INPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc614.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc615.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc616.vhd OUTPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc617.vhd OUTPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc618.vhd INPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc619.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc620.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc621.vhd INPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc622.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc623.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc624.vhd OUTPUT=iofile.36:iofiles/iofile.36
+run_compliant_test tc625.vhd OUTPUT=iofile.35:iofiles/iofile.35
+run_compliant_test tc626.vhd INPUT=iofile.35:iofiles/iofile.35
+run_compliant_test tc627.vhd INPUT=iofile.36:iofiles/iofile.36
+run_compliant_test tc628.vhd OUTPUT=iofile.40:iofiles/iofile.40
+run_compliant_test tc629.vhd OUTPUT=iofile.37:iofiles/iofile.37
+run_compliant_test tc630.vhd INPUT=iofile.37:iofiles/iofile.37
+run_compliant_test tc631.vhd INPUT=iofile.40:iofiles/iofile.40
+run_compliant_test tc632.vhd OUTPUT=iofile.38:iofiles/iofile.38
+run_compliant_test tc633.vhd INPUT=iofile.38:iofiles/iofile.38
+run_compliant_test tc634.vhd OUTPUT=iofile.43:iofiles/iofile.43
+run_compliant_test tc635.vhd OUTPUT=iofile.39:iofiles/iofile.39
+run_compliant_test tc636.vhd INPUT=iofile.39:iofiles/iofile.39
+run_compliant_test tc637.vhd OUTPUT=iofile.41:iofiles/iofile.41
+run_compliant_test tc638.vhd INPUT=iofile.41:iofiles/iofile.41
+run_compliant_test tc639.vhd INPUT=iofile.43:iofiles/iofile.43
+run_compliant_test tc640.vhd OUTPUT=iofile.42:iofiles/iofile.42
+run_compliant_test tc641.vhd INPUT=iofile.42:iofiles/iofile.42
+run_compliant_test tc642.vhd OUTPUT=iofile.44:iofiles/iofile.44
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+run_compliant_test tc2699.vhd
+run_compliant_test tc2700.vhd
+run_compliant_test tc2701.vhd
+run_compliant_test tc2702.vhd
+run_compliant_test tc2703.vhd
+run_compliant_test tc2704.vhd
+run_compliant_test tc2705.vhd
+run_compliant_test tc2707.vhd
+run_compliant_test tc2708.vhd
+run_compliant_test tc2709.vhd
+run_compliant_test tc2710.vhd
+run_compliant_test tc2711.vhd
+run_compliant_test tc2712.vhd
+run_compliant_test tc2713.vhd
+run_compliant_test tc2718.vhd
+run_compliant_test tc2719.vhd
+run_compliant_test tc2722.vhd
+run_compliant_test tc2724.vhd
+run_compliant_test tc2725.vhd
+run_compliant_test tc2726.vhd
+run_compliant_test tc2733.vhd
+run_compliant_test tc2734.vhd
+run_compliant_test tc2735.vhd
+run_compliant_test tc2736.vhd
+run_compliant_test tc2737.vhd
+run_compliant_test tc2738.vhd
+run_compliant_test tc2739.vhd
+run_compliant_test tc2740.vhd
+run_compliant_test tc2742.vhd
+run_compliant_test tc2743.vhd
+run_compliant_test tc2744.vhd
+run_compliant_test tc2745.vhd
+run_compliant_test tc2747.vhd
+run_compliant_test tc2758.vhd
+run_compliant_test tc2759.vhd
+run_compliant_test tc2760.vhd
+run_compliant_test tc2761.vhd
+run_compliant_test tc2765.vhd
+run_compliant_test tc2767.vhd
+run_compliant_test tc2768.vhd
+run_compliant_test tc2769.vhd
+run_compliant_test tc2771.vhd
+run_compliant_test tc2853.vhd
+run_compliant_test tc2854.vhd
+run_compliant_test tc2860.vhd
+run_compliant_test tc2861.vhd
+run_compliant_test tc2862.vhd
+run_compliant_test tc2863.vhd
+run_compliant_test tc2864.vhd
+run_compliant_test tc2865.vhd
+run_compliant_test tc2866.vhd
+run_compliant_test tc2868.vhd
+run_compliant_test tc2870.vhd
+run_compliant_test tc2874.vhd
+run_compliant_test tc2876.vhd
+run_compliant_test tc2879.vhd
+run_compliant_test tc2880.vhd
+run_compliant_test tc2881.vhd
+run_compliant_test tc2882.vhd
+run_compliant_test tc2883.vhd
+run_compliant_test tc2900.vhd
+run_compliant_test tc2901.vhd
+run_compliant_test tc2902.vhd
+run_compliant_test tc2903.vhd
+run_compliant_test tc2904.vhd
+run_compliant_test tc2917.vhd
+run_compliant_test tc2918.vhd
+run_compliant_test tc2932.vhd
+run_compliant_test tc2945.vhd
+run_compliant_test tc2948.vhd
+run_compliant_test tc2949.vhd
+run_compliant_test tc2950.vhd
+run_compliant_test tc2951.vhd
+run_compliant_test tc2952.vhd
+run_compliant_test tc2955.vhd
+run_compliant_test tc2959.vhd
+run_compliant_test tc2960.vhd
+run_compliant_test tc2961.vhd
+run_compliant_test tc2962.vhd
+run_compliant_test tc2964.vhd
+run_compliant_test tc2966.vhd
+run_compliant_test tc2967.vhd
+run_compliant_test tc2968.vhd
+run_compliant_test tc2969.vhd
+run_compliant_test tc2972.vhd
+run_compliant_test tc2973.vhd
+run_compliant_test tc2974.vhd
+run_compliant_test tc2975.vhd
+run_compliant_test tc2976.vhd
+run_compliant_test tc2977.vhd
+run_compliant_test tc2978.vhd
+run_compliant_test tc2979.vhd
+run_compliant_test tc2980.vhd
+run_compliant_test tc2981.vhd
+run_compliant_test tc2982.vhd
+run_compliant_test tc2987.vhd
+run_compliant_test tc2988.vhd
+run_compliant_test tc2989.vhd
+run_compliant_test tc2990.vhd
+run_compliant_test tc3001.vhd
+run_compliant_test tc3005.vhd
+run_compliant_test tc3010.vhd
+run_compliant_test tc3016.vhd
+run_compliant_test tc3022.vhd
+run_compliant_test tc3023.vhd
+run_compliant_test tc3024.vhd
+run_compliant_test tc3029.vhd
+run_compliant_test tc3032.vhd
+run_compliant_test tc3033.vhd
+run_compliant_test tc3034.vhd
+run_compliant_test tc3035.vhd
+run_compliant_test tc3036.vhd
+run_compliant_test tc3037.vhd
+run_compliant_test tc3038.vhd
+run_compliant_test tc3039.vhd
+run_compliant_test tc3040.vhd
+run_compliant_test tc3041.vhd
+run_compliant_test tc3042.vhd
+run_compliant_test tc3043.vhd
+run_compliant_test tc3044.vhd
+run_compliant_test tc3045.vhd
+run_compliant_test tc3046.vhd
+run_compliant_test tc3047.vhd
+run_compliant_test tc3048.vhd
+run_compliant_test tc3049.vhd
+run_compliant_test tc3050.vhd
+run_compliant_test tc3051.vhd
+run_compliant_test tc3052.vhd
+run_compliant_test tc3053.vhd
+run_compliant_test tc3054.vhd
+run_compliant_test tc3055.vhd
+run_compliant_test tc3057.vhd
+run_compliant_test tc3059.vhd
+run_compliant_test tc3060.vhd
+run_compliant_test tc3061.vhd
+run_compliant_test tc3062.vhd
+run_compliant_test tc3063.vhd
+run_compliant_test tc3066.vhd
+run_compliant_test tc3067.vhd
+run_compliant_test tc3068.vhd
+run_compliant_test tc3069.vhd
+run_compliant_test tc3070.vhd
+run_compliant_test tc3071.vhd
+run_compliant_test tc3072.vhd
+run_compliant_test tc3073.vhd
+run_compliant_test tc3074.vhd
+run_compliant_test tc3075.vhd
+run_compliant_test tc3076.vhd
+run_compliant_test tc3077.vhd
+run_compliant_test tc3078.vhd
+run_compliant_test tc3079.vhd
+run_compliant_test tc3080.vhd
+run_compliant_test tc3081.vhd
+run_compliant_test tc3082.vhd
+run_compliant_test tc3083.vhd
+run_compliant_test tc3084.vhd
+run_compliant_test tc3085.vhd
+run_compliant_test tc3086.vhd
+run_compliant_test tc3099.vhd
+run_compliant_test tc3100.vhd
+run_compliant_test tc3101.vhd
+run_compliant_test tc3102.vhd
+run_compliant_test tc3109.vhd
+run_compliant_test tc3110.vhd
+run_compliant_test tc3111.vhd
+run_compliant_test tc3112.vhd
+run_compliant_test tc3113.vhd
+run_compliant_test tc3114.vhd
+run_compliant_test tc3115.vhd
+run_compliant_test tc3116.vhd
+run_compliant_test tc3117.vhd
+run_compliant_test tc3118.vhd
+run_compliant_test tc3119.vhd
+run_compliant_test tc3120.vhd
+run_compliant_test tc3121.vhd
+run_compliant_test tc3122.vhd
+run_compliant_test tc3123.vhd
+run_compliant_test tc3125.vhd
+run_compliant_test tc3126.vhd
+run_compliant_test tc3127.vhd
+run_compliant_test tc3128.vhd
+run_compliant_test tc3137.vhd
+run_compliant_test tc3138.vhd
+run_compliant_test tc3139.vhd
+run_compliant_test tc3140.vhd
+run_compliant_test tc3141.vhd
+run_compliant_test tc3142.vhd
+run_compliant_test tc3143.vhd
+run_compliant_test tc3144.vhd
+run_compliant_test tc3145.vhd
+run_compliant_test tc3146.vhd
+run_compliant_test tc3147.vhd
+run_compliant_test tc3148.vhd
+run_compliant_test tc3149.vhd
+run_compliant_test tc3150.vhd
+run_compliant_test tc3151.vhd
+run_compliant_test tc3152.vhd
+run_compliant_test tc3153.vhd
+run_compliant_test tc3154.vhd
+run_compliant_test tc3155.vhd
+run_compliant_test tc3156.vhd
+run_compliant_test tc3157.vhd
+run_compliant_test tc3158.vhd
+run_compliant_test tc3159.vhd
+run_compliant_test tc3160.vhd
+run_compliant_test tc3162.vhd
+run_compliant_test tc3163.vhd
+run_compliant_test tc3164.vhd
+run_compliant_test tc3165.vhd
+run_compliant_test tc3166.vhd
+run_compliant_test tc3167.vhd
+run_compliant_test tc3168.vhd
+run_compliant_test tc3169.vhd
+run_compliant_test tc3170.vhd
+run_compliant_test tc3171.vhd
+run_compliant_test tc3172.vhd
+run_compliant_test tc3173.vhd
+run_compliant_test tc3174.vhd
+run_compliant_test tc3175.vhd
+run_compliant_test tc3176.vhd
+run_compliant_test tc3177.vhd
+run_compliant_test tc3178.vhd
+run_compliant_test tc3179.vhd
+run_compliant_test tc3180.vhd
+run_compliant_test tc3181.vhd
+run_compliant_test tc3182.vhd
+run_compliant_test tc3183.vhd
+run_compliant_test tc3184.vhd
+run_compliant_test tc3185.vhd OUTPUT=iofile.02:iofiles/iofile.02
+run_compliant_test tc3186.vhd OUTPUT=iofile.01:iofiles/iofile.01
+run_compliant_test tc3187.vhd OUTPUT=iofile.04:iofiles/iofile.04
+run_compliant_test tc3188.vhd INPUT=iofile.06:iofiles/iofile.06
+run_compliant_test tc3189.vhd INPUT=iofile.02:iofiles/iofile.02
+run_compliant_test tc3190.vhd OUTPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc3191.vhd INPUT=iofile.04:iofiles/iofile.04
+run_compliant_test tc3192.vhd OUTPUT=iofile.06:iofiles/iofile.06
+run_compliant_test tc3193.vhd INPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc3194.vhd OUTPUT=iofile.09:iofiles/iofile.09
+run_compliant_test tc3195.vhd INPUT=iofile.09:iofiles/iofile.09
+run_compliant_test tc3196.vhd OUTPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc3197.vhd INPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc3198.vhd OUTPUT=iofile.12:iofiles/iofile.12
+run_compliant_test tc3199.vhd INPUT=iofile.12:iofiles/iofile.12
+run_compliant_test tc3200.vhd OUTPUT=iofile.14:iofiles/iofile.14
+run_compliant_test tc3201.vhd INPUT=iofile.14:iofiles/iofile.14
+run_compliant_test tc3202.vhd INPUT=iofile.61:iofiles/iofile.61
+run_compliant_test tc3203.vhd OUTPUT=iofile.61:iofiles/iofile.61
+run_compliant_test tc3204.vhd OUTPUT=iofile.47:iofiles/iofile.47
+run_compliant_test tc3205.vhd OUTPUT=iofile.64:iofiles/iofile.64
+run_compliant_test tc3206.vhd INPUT=iofile.64:iofiles/iofile.64
+
+end_test_group
+
+# $Log: compliant.exp,v $
+# Revision 1.6  2009-09-05 21:58:50  paw
+# Removing 4 empty shells of test cases from the list of test models to evaluate.
+#
+# Revision 1.5  2008-04-06 17:01:06  paw
+# Updated these vhdl files with filename strings that is consistent with the
+# rest of the regression setup.  Updated the runtest script (compliant.exp)
+# with these filenames.  This should change all these from failed to passed.
+#
+# Revision 1.4  2001-10-29 02:12:44  paw
+# Modifications for file IO.  I have replaced all the file names with
+# iofile.X and have placed all the files for savant in the subdirectory
+# iofiles.  Technically these files should be described using XML and we
+# should build translators to/from the files.  I'll leave that exercise for
+# another time.  In addition, I could build files only for those vhdl files
+# that we can build and simulate in savant; consequently there are still
+# about 5-6 tests with the old file names.  As the system matures so that
+# these tests execute, I will incorporate their iofiles (or point them at the
+# correct existing file should it already exist).
+#
+# Revision 1.3  2001/10/19 23:29:32  paw
+# Adding comments for cvs tracking information.
+#
+# Revision 1.2  2001/10/15 16:00:50  paw
+# Updating the compliant.exp script to properly use the functions in the new
+# savant test harness.
+#
+# Adding the scripts for non_compliant testing in the billowitch suite.
+#
+# When properly placed in the testsuite subdirectory of savant, a make check
+# will work.  Documentation will be added to the testsuite to describe how.
+#
+# Revision 1.1  2001/09/14 14:31:25  paw
+# This script sets up the group (Billowitch:Pass Cases) run and invokes
+# the run_compliant_test procedure for each file.  For those cases
+# requiring file input/output, additional modifications will be needed.
+#
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01
new file mode 100644
index 0000000..9e58d8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01
@@ -0,0 +1,5 @@
+This is string 1
+__Hello  World__
+This is string 3
+_Bird is a word_
+_Goodbye (ciao)_
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02
new file mode 100644
index 0000000..11b2fd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02
@@ -0,0 +1,100 @@
+1994
+1994
+1994
+1994
+1994
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03
new file mode 100644
index 0000000..257145b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03
@@ -0,0 +1,100 @@
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
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+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
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+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04
new file mode 100644
index 0000000..8bc3f65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04
@@ -0,0 +1,100 @@
+1.994500e+03
+1.994500e+03
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05
new file mode 100644
index 0000000..8278c45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.06 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.06
new file mode 100644
index 0000000..805caa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.06
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.07 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.07
new file mode 100644
index 0000000..e88cfec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.07
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08
new file mode 100644
index 0000000..0e51709
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.09 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.09
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.11 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.11
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12
new file mode 100644
index 0000000..5bb9123
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13
new file mode 100644
index 0000000..4aa1d6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13
@@ -0,0 +1,100 @@
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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14
new file mode 100644
index 0000000..46c0944
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15
new file mode 100644
index 0000000..aa79d35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15
@@ -0,0 +1,74 @@
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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.16 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.16
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index 0000000..26fb2a8
--- /dev/null
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.17 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.17
new file mode 100644
index 0000000..b7ea775
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.18 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.18
new file mode 100644
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.19 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.19
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new file mode 100644
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.25 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.25
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.28 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.28
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.29 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.29
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.30 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.30
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.31 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.31
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index 0000000..1b22109
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.33 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.33
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index 0000000..839aa9d
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.34 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.34
new file mode 100644
index 0000000..43230e5
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+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35
new file mode 100644
index 0000000..c446c27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35
@@ -0,0 +1,100 @@
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+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.51 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.51
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.52 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.52
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+WARNING
+WARNING
+WARNING
+WARNING
+WARNING
+WARNING
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56
new file mode 100644
index 0000000..7c8423a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56
@@ -0,0 +1,100 @@
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57
new file mode 100644
index 0000000..d09402f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57
@@ -0,0 +1,100 @@
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58
new file mode 100644
index 0000000..b43955f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58
@@ -0,0 +1,100 @@
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59
new file mode 100644
index 0000000..b8e7816
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59
@@ -0,0 +1,5 @@
+1 This is string 1
+2 __Hello  World__
+3 This is string 3
+4 _Bird is a word_
+5 _Goodbye (ciao)_
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60
new file mode 100644
index 0000000..885bec6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60
@@ -0,0 +1,2 @@
+0 1 2 3 4 2 4 6 8 10 -2 -1 0 1 2 13 2 -45 6 1
+1 4 16 64 256 1 4 9 16 25 1 2 4 8 16 5 4 3 2 1
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61
new file mode 100644
index 0000000..c7c491a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61
@@ -0,0 +1,40 @@
+hello world
+
+0*          *          1**
+0 *         *          1**
+0  *        *          1**
+0   *       *          1**
+0    *      *          1**
+0     *     *          1**
+0      *    *          1**
+0       *   *          1**
+0        *  *          1**
+0         * *          1**
+
+1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1
+1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0
+1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0
+0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0
+0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0
+0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1
+0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0
+1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0
+0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0
+0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1
+0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1
+0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0
+0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1
+0                              0                              0                              1                             *  *                               1                              1                              1                              1
+0                              1                             *  *                               1                              1
+
+FALSE     * * TRUE
+FALSE    *  *  TRUE
+FALSE   *   *   TRUE
+FALSE  *    *    TRUE
+FALSE *     *     TRUE 
+FALSE*      *      TRUE  
+FALSE*       *       TRUE   
+FALSE*        *        TRUE    
+FALSE*         *         TRUE     
+FALSE*          *          TRUE      
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62
new file mode 100644
index 0000000..5571755
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62
@@ -0,0 +1,100 @@
+1000000000 na
+1000000000 na
+1000000000 na
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63
new file mode 100644
index 0000000..7851b75
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63
@@ -0,0 +1,100 @@
+1000000 uohm
+1000000 uohm
+1000000 uohm
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64
new file mode 100644
index 0000000..6c45c8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64
@@ -0,0 +1,24 @@
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+
+-1 fs
+-1 fs
+-1 fs
+-1 fs
+-1 fs
+
+37582000000 fs
+37582000000 fs
+37582000000 fs
+37582000000 fs
+37582000000 fs
+
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd
new file mode 100644
index 0000000..0ab0d78
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p03n01i00001ent IS
+END c04s01b00x00p03n01i00001ent;
+
+ARCHITECTURE c04s01b00x00p03n01i00001arch OF c04s01b00x00p03n01i00001ent IS
+  type t1 is range 0.012345 to 300.012345;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : t1 := 10.0;
+  BEGIN
+    k := 123.0;
+    assert NOT( k=123.0 )
+      report "***PASSED TEST: c04s01b00x00p03n01i00001"
+      severity NOTE;
+    assert ( k=123.0 )
+      report "***FAILED TEST: c04s01b00x00p03n01i00001 - Type declaration has the format: the reserved word type followed by an identifier and the reserved word is."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p03n01i00001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd
new file mode 100644
index 0000000..17985ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc10.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p02n01i00010ent IS
+END c04s02b00x00p02n01i00010ent;
+
+ARCHITECTURE c04s02b00x00p02n01i00010arch OF c04s02b00x00p02n01i00010ent IS
+  subtype eight_bit       is integer range -32768 to 32767;       -- No_failure_here
+  subtype positive_8_bit    is eight_bit range 1 to 32767;     -- No_failure_here
+
+  -- an unconstrained array declaration
+  type  memory is array  (integer range <>) of bit;
+  subtype foo1 is memory (1 to 10);                      -- No_failure_here
+  subtype foo3 is memory (integer range 25 downto 2);    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k1 : eight_bit    := 0;
+    variable k2 : positive_8_bit    := 10;
+    variable k3 : foo1       := ("1111111111");
+    variable k5 : foo3       := ("111111111111111111111111");
+  BEGIN
+    assert NOT(    k1 = 0         and
+                   k2 = 10         and
+                   k3 = "1111111111"   and
+                   k5 = "111111111111111111111111")
+      report "***PASSED TEST: c04s02b00x00p02n01i00010"
+      severity NOTE;
+    assert (    k1 = 0         and
+                k2 = 10         and
+                k3 = "1111111111"   and
+                k5 = "111111111111111111111111")
+      report "***FAILED TEST: c04s02b00x00p02n01i00010 - Subtype declaration syntactic format test fail."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p02n01i00010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd
new file mode 100644
index 0000000..8c62564
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc100.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x00p29n06i00100pkg is
+  type int_1 is range 1 to 32;
+  attribute pin_number : int_1;
+end c04s03b02x00p29n06i00100pkg;
+
+use work.c04s03b02x00p29n06i00100pkg.all;
+ENTITY c04s03b02x00p29n06i00100ent IS
+  port ( P2 : out bit) ;
+  attribute pin_number of P2 : signal is 1;
+END c04s03b02x00p29n06i00100ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00100arch OF c04s03b02x00p29n06i00100ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable pn : int_1;
+  BEGIN
+    pn := 1;
+    assert NOT( P2'pin_number = pn )
+      report "***PASSED TEST: c04s03b02x00p29n06i00100"      severity NOTE;
+    assert ( P2'pin_number = pn )
+      report "***FAILED TEST: c04s03b02x00p29n06i00100 - Reading user defined attributes of interface elements of mode 'out' should be permitted."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd
new file mode 100644
index 0000000..9f9cfa9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01009pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p09n01i01009pkg;
+
+use work.c06s03b00x00p09n01i01009pkg.all;
+ENTITY c06s03b00x00p09n01i01009ent IS
+END c06s03b00x00p09n01i01009ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ;    -- No_failure_here
+  BEGIN
+    V1.S11    := '1';
+    V1.S12.S1 := '1';
+    V1.S12.S2 :=  1 ;
+    assert NOT(V1.S11    = '1' and 
+               V1.S12.S1 = '1' and 
+               V1.S12.S2 =  1 )
+      report "***PASSED TEST: c06s03b00x00p09n01i01009" 
+      severity NOTE;
+    assert    (V1.S11    = '1' and 
+               V1.S12.S1 = '1' and 
+               V1.S12.S2 =  1 )
+      report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01009arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd
new file mode 100644
index 0000000..8d4b1fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd
@@ -0,0 +1,252 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1010.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p10n01i01010pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- -----------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- -----------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8; 
+  
+END;
+
+
+
+USE WORK.c06s03b00x00p10n01i01010pkg.all;
+ENTITY c06s03b00x00p10n01i01010ent IS
+END c06s03b00x00p10n01i01010ent;
+
+USE WORK.c06s03b00x00p10n01i01010pkg.all;
+ENTITY c06s03b00x00p10n01i01010ent_a IS
+  GENERIC (  gene_1 : cst_scl7;
+             gene_2 : st_str2   );
+  PORT (  port_1 : cst_scl7;
+          port_2 : st_str2   );
+--
+  ATTRIBUTE atr_scl1 OF port_1: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_scl2 OF port_1: SIGNAL IS       '0';
+  ATTRIBUTE atr_scl3 OF port_1: SIGNAL IS       'z';
+  ATTRIBUTE atr_scl4 OF port_1: SIGNAL IS         0;
+  ATTRIBUTE atr_scl5 OF port_1: SIGNAL IS      10.0;
+  ATTRIBUTE atr_scl6 OF port_1: SIGNAL IS     10 ns;
+  ATTRIBUTE atr_scl7 OF port_1: SIGNAL IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF port_1: SIGNAL IS        FX;
+
+  ATTRIBUTE atr_str1 OF port_1: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF port_1: SIGNAL IS    "XXXX";
+--
+  ATTRIBUTE cat_scl1 OF port_1: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF port_2: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_str1 OF port_2: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF port_2: SIGNAL IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF port_2: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF gene_1: CONSTANT IS      TRUE;
+  ATTRIBUTE atr_str1 OF gene_1: CONSTANT IS  "signal";
+  ATTRIBUTE atr_str2 OF gene_1: CONSTANT IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF gene_1: CONSTANT IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF gene_2: CONSTANT IS      TRUE;
+  ATTRIBUTE atr_str1 OF gene_2: CONSTANT IS  "signal";
+  ATTRIBUTE atr_str2 OF gene_2: CONSTANT IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF gene_2: CONSTANT IS      TRUE;
+  
+END c06s03b00x00p10n01i01010ent_a;
+
+-----------------------------------------------------------------------
+-- ARCHITECTURAL DECLARATION
+-----------------------------------------------------------------------
+
+ARCHITECTURE c06s03b00x00p10n01i01010arch_a OF c06s03b00x00p10n01i01010ent_a IS
+  SIGNAL sign_1 : cst_scl7;
+  SIGNAL sign_2 : st_str2;
+--
+  ATTRIBUTE atr_scl1 OF sign_1: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_scl2 OF sign_1: SIGNAL IS       '0';
+  ATTRIBUTE atr_scl3 OF sign_1: SIGNAL IS       'z';
+  ATTRIBUTE atr_scl4 OF sign_1: SIGNAL IS         0;
+  ATTRIBUTE atr_scl5 OF sign_1: SIGNAL IS      10.0;
+  ATTRIBUTE atr_scl6 OF sign_1: SIGNAL IS     10 ns;
+  ATTRIBUTE atr_scl7 OF sign_1: SIGNAL IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF sign_1: SIGNAL IS        FX;
+  
+  ATTRIBUTE atr_str1 OF sign_1: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF sign_1: SIGNAL IS    "XXXX";
+--
+  ATTRIBUTE cat_scl1 OF sign_1: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF sign_2: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_str1 OF sign_2: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF sign_2: SIGNAL IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF sign_2: SIGNAL IS      TRUE;
+--
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    port_1'atr_scl1 =      TRUE    and 
+                   port_1'atr_scl2 =       '0'    and 
+                   port_1'atr_scl3 =       'z'    and 
+                   port_1'atr_scl4 =         0    and 
+                   port_1'atr_scl5 =      10.0    and 
+                   port_1'atr_scl6 =     10 ns    and 
+                   port_1'atr_scl7 =  10000 pf    and 
+                   port_1'atr_scl8 =        FX    and 
+                   port_1'atr_str1 =  "signal"    and 
+                   port_1'atr_str2 =    "XXXX"    and 
+                   port_1'cat_scl1 =      TRUE    and 
+                   port_2'atr_scl1 =      TRUE    and 
+                   port_2'atr_str1 =  "signal"    and 
+                   port_2'atr_str2 =    "XXXX"    and 
+                   port_2'cat_scl1 =      TRUE    and 
+                   gene_1'atr_scl1 =      TRUE    and 
+                   gene_1'atr_str1 =  "signal"    and 
+                   gene_1'atr_str2 =    "XXXX"    and 
+                   gene_1'cat_scl1 =      TRUE    and 
+                   gene_2'atr_scl1 =      TRUE    and 
+                   gene_2'atr_str1 =  "signal"    and 
+                   gene_2'atr_str2 =    "XXXX"    and 
+                   gene_2'cat_scl1 =      TRUE )   
+      report "***PASSED TEST: c06s03b00x00p10n01i01010"
+      severity NOTE;
+    assert (    port_1'atr_scl1 =      TRUE    and 
+                port_1'atr_scl2 =       '0'    and 
+                port_1'atr_scl3 =       'z'    and 
+                port_1'atr_scl4 =         0    and 
+                port_1'atr_scl5 =      10.0    and 
+                port_1'atr_scl6 =     10 ns    and 
+                port_1'atr_scl7 =  10000 pf    and 
+                port_1'atr_scl8 =        FX    and 
+                port_1'atr_str1 =  "signal"    and 
+                port_1'atr_str2 =    "XXXX"    and 
+                port_1'cat_scl1 =      TRUE    and 
+                port_2'atr_scl1 =      TRUE    and 
+                port_2'atr_str1 =  "signal"    and 
+                port_2'atr_str2 =    "XXXX"    and 
+                port_2'cat_scl1 =      TRUE    and 
+                gene_1'atr_scl1 =      TRUE    and 
+                gene_1'atr_str1 =  "signal"    and 
+                gene_1'atr_str2 =    "XXXX"    and 
+                gene_1'cat_scl1 =      TRUE    and 
+                gene_2'atr_scl1 =      TRUE    and 
+                gene_2'atr_str1 =  "signal"    and 
+                gene_2'atr_str2 =    "XXXX"    and 
+                gene_2'cat_scl1 =      TRUE )   
+      report "***FAILED TEST: c06s03b00x00p10n01i01010 - An expanded name denotes an entity, the prefix denotes a construct that is ports, signals and generics." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01010arch_a;
+
+
+ARCHITECTURE c06s03b00x00p10n01i01010arch OF c06s03b00x00p10n01i01010ent IS
+  COMPONENT c06s03b00x00p10n01i01010ent_a
+    GENERIC (  gene_1 : cst_scl7;
+               gene_2 : st_str2   );
+    PORT (  port_1 : cst_scl7;
+            port_2 : st_str2   );
+  END COMPONENT;
+  FOR  SUB : c06s03b00x00p10n01i01010ent_a USE ENTITY work.c06s03b00x00p10n01i01010ent_a(c06s03b00x00p10n01i01010arch_a);
+
+  SIGNAL s1 : cst_scl7;
+  SIGNAL s2 : st_str2;
+
+BEGIN
+  SUB : c06s03b00x00p10n01i01010ent_a GENERIC MAP ( 10 pf, "ABCD" )
+    PORT MAP (    s1,    s2 ); 
+  
+END c06s03b00x00p10n01i01010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd
new file mode 100644
index 0000000..8aec15c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01011ent IS
+END c06s03b00x00p10n01i01011ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
+  procedure check (x: in integer; y: in boolean; signal z :out integer) is
+  begin
+    z <= 5;
+  end;
+  signal p: integer ;
+  signal q: boolean ;
+  signal k: integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
+    wait for 10 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c06s03b00x00p10n01i01011"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd
new file mode 100644
index 0000000..7a864be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1012.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01012ent IS
+  port (p,q: in bit);
+END c06s03b00x00p10n01i01012ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01012arch OF c06s03b00x00p10n01i01012ent IS
+
+BEGIN
+  TESTING: PROCESS(c06s03b00x00p10n01i01012ent.p, c06s03b00x00p10n01i01012ent.q)
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c06s03b00x00p10n01i01012"
+      severity NOTE;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd
new file mode 100644
index 0000000..85f98a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1013.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01013ent IS
+END c06s03b00x00p10n01i01013ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01013arch OF c06s03b00x00p10n01i01013ent IS
+  signal q : bit;
+BEGIN
+  TESTING: PROCESS(c06s03b00x00p10n01i01013arch.q)
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c06s03b00x00p10n01i01013"
+      severity NOTE;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01013arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd
new file mode 100644
index 0000000..e5290e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1019.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01019ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01019ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01019arch OF c06s03b00x00p10n01i01019ent IS
+
+BEGIN
+  B1:Block
+    type chars is ('a', 'b', 'c', 'd', 'e');
+  begin
+    TESTING: PROCESS
+      variable c           : chars;
+      variable All_done    : boolean;
+    BEGIN
+      L1 : for LL1 in TRUE downto FALSE  loop
+        NULL; 
+        if L1.LL1 then       -- Selected prefix is loop,
+                                       -- suffix is identifier that
+                                                 -- refers to loop iteration id.
+          All_done := True;
+        end if;
+      end loop L1;
+      assert NOT(All_done=TRUE) 
+        report "***PASSED TEST: c06s03b00x00p10n01i01019"
+        severity NOTE;
+      assert (All_done=TRUE) 
+        report "***FAILED TEST: c06s03b00x00p10n01i01019 - Entity declaration does not occur in construct specifed by the prefix." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block B1;
+
+END c06s03b00x00p10n01i01019arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd
new file mode 100644
index 0000000..7c0ea9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1020.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01020ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01020ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01020arch OF c06s03b00x00p10n01i01020ent IS
+
+BEGIN
+  B1:Block
+    type chars is ('a', 'b', 'c', 'd', 'e');
+  begin
+    TESTING: PROCESS
+      variable c           : chars;
+      variable All_done    : boolean;
+    BEGIN
+      L1 : for LL1 in 0 to 5 loop
+        TESTING.c := 'a';
+      end loop L1;
+      assert NOT(TESTING.c='a')
+        report "***PASSED TEST: c06s03b00x00p10n01i01020" 
+        severity NOTE;
+      assert (TESTING.c='a')
+        report "***FAILED TEST: c06s03b00x00p10n01i01020 - Entity declaration does not occur in construct specifed by the prefix." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block B1;
+
+END c06s03b00x00p10n01i01020arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd
new file mode 100644
index 0000000..d081d0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1024.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n02i01024ent IS
+END c06s03b00x00p10n02i01024ent;
+
+ARCHITECTURE c06s03b00x00p10n02i01024arch OF c06s03b00x00p10n02i01024ent IS
+  signal pop  : bit;
+  signal done : bit;
+BEGIN
+  TESTING: PROCESS
+    variable done : bit := '1';
+    variable pop  : bit;
+  BEGIN
+    pop            :=    done;
+    c06s03b00x00p10n02i01024arch.pop   <=   TESTING.done;
+    c06s03b00x00p10n02i01024arch.done   <=   TESTING.pop;
+    wait for 1 ns;
+    assert NOT(c06s03b00x00p10n02i01024arch.pop='1' and c06s03b00x00p10n02i01024arch.done='1') 
+      report "***PASSED TEST: c06s03b00x00p10n02i01024" 
+      severity NOTE;
+    assert (c06s03b00x00p10n02i01024arch.pop='1' and c06s03b00x00p10n02i01024arch.done='1') 
+      report "***FAILED TEST: c06s03b00x00p10n02i01024 - An expanded name denoting an entity declared within a named construct is allowed only within the construct." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n02i01024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd
new file mode 100644
index 0000000..fde63bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1026.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p01n01i01026ent IS
+END c06s04b00x00p01n01i01026ent;
+
+ARCHITECTURE c06s04b00x00p01n01i01026arch OF c06s04b00x00p01n01i01026ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable E    : bit_vector (0 to 47);
+    variable F    : bit_vector (47 downto 0);
+    alias FF    : bit_vector (47 downto 0) is F;
+    variable G    : bit_vector (3 downto 0);
+    variable H    : bit_vector (0 to 3);
+  BEGIN
+
+    F    := x"555555555555";
+    E    := x"555555555555";
+    G    := b"1111";
+    G(1)    := '0';
+    H    := b"1111";
+    H(1)    := '0';
+
+    assert NOT(   ( F(47) = '0')   and
+                  ( F(42) = '1')   and
+                  ( F(37) = '0')   and
+                  ( F(32) = '1')   and
+                  ( F(27) = '0')   and
+                  ( F(22) = '1')   and
+                  ( F(17) = '0')   and
+                  ( F(12) = '1')   and
+                  ( F(7) = '0')   and
+                  ( F(2) = '1')   and
+                  ( FF(47) = '0')   and
+                  ( FF(42) = '1')   and
+                  ( FF(37) = '0')   and
+                  ( FF(32) = '1')   and
+                  ( FF(27) = '0')   and
+                  ( FF(22) = '1')   and
+                  ( FF(17) = '0')   and
+                  ( FF(12) = '1')   and
+                  ( FF(7) = '0')   and
+                  ( FF(2) = '1')   and
+                  ( E(47) = '1')   and
+                  ( E(42) = '0')   and
+                  ( E(37) = '1')   and
+                  ( E(32) = '0')   and
+                  ( E(27) = '1')   and
+                  ( E(22) = '0')   and
+                  ( E(17) = '1')   and
+                  ( E(12) = '0')   and
+                  ( E(7) = '1')   and
+                  ( E(2) = '0')   and
+                  ( E = F)   and 
+                  ( G = b"1101")   and
+                  ( H = b"1011")   )
+      report "***PASSED TEST: c06s04b00x00p01n01i01026"
+      severity NOTE;
+    assert (   ( F(47) = '0')   and
+               ( F(42) = '1')   and
+               ( F(37) = '0')   and
+               ( F(32) = '1')   and
+               ( F(27) = '0')   and
+               ( F(22) = '1')   and
+               ( F(17) = '0')   and
+               ( F(12) = '1')   and
+               ( F(7) = '0')   and
+               ( F(2) = '1')   and
+               ( FF(47) = '0')   and
+               ( FF(42) = '1')   and
+               ( FF(37) = '0')   and
+               ( FF(32) = '1')   and
+               ( FF(27) = '0')   and
+               ( FF(22) = '1')   and
+               ( FF(17) = '0')   and
+               ( FF(12) = '1')   and
+               ( FF(7) = '0')   and
+               ( FF(2) = '1')   and
+               ( E(47) = '1')   and
+               ( E(42) = '0')   and
+               ( E(37) = '1')   and
+               ( E(32) = '0')   and
+               ( E(27) = '1')   and
+               ( E(22) = '0')   and
+               ( E(17) = '1')   and
+               ( E(12) = '0')   and
+               ( E(7) = '1')   and
+               ( E(2) = '0')   and
+               ( E = F)   and 
+               ( G = b"1101")   and
+               ( H = b"1011")   )
+      report "***FAILED TEST: c06s04b00x00p01n01i01026 - Indexed reference test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p01n01i01026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd
new file mode 100644
index 0000000..e6c773d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1027.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p01n01i01027ent IS
+END c06s04b00x00p01n01i01027ent;
+
+ARCHITECTURE c06s04b00x00p01n01i01027arch OF c06s04b00x00p01n01i01027ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : BIT_VECTOR(1 to 2);
+    variable    V2    : BIT_VECTOR(3 to 4);
+    variable   pass   : integer := 0;
+  BEGIN
+    v1(1) := '1';
+    v1(2) := '0';
+    v2(3) := '0';
+    v2(4) := '1';
+
+    assert v1(1) = '1' report "v1(1) initial value is wrong.";
+    assert v1(2) = '0' report "v1(2) initial value is wrong.";
+    assert v2(3) = '0' report "v2(3) initial value is wrong.";
+    assert v2(4) = '1' report "v2(4) initial value is wrong.";
+    if (   V1(1) /= '1' or V1(2) /= '0' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    v1 := v2;         -- composite variable assignment
+    assert v1(1) = '0' report "v1(1) final value is wrong.";
+    assert v1(2) = '1' report "v1(2) final value is wrong.";
+    assert v2(3) = '0' report "v2(3) final value is wrong.";
+    assert v2(4) = '1' report "v2(4) final value is wrong.";
+    if (   V1(1) /= '0' or V1(2) /= '1' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    v1 := ('1', '1');      -- composite variable assignment
+    -- aggregate value
+    assert v1(1) = '1' report "v1(1) final value is wrong.";
+    assert v1(2) = '1' report "v1(2) final value is wrong.";
+    assert v2(3) = '0' report "v2(3) final value is wrong.";
+    assert v2(4) = '1' report "v2(4) final value is wrong.";
+    if (   V1(1) /= '1' or V1(2) /= '1' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT(   pass = 0   )
+      report "***PASSED TEST: c06s04b00x00p01n01i01027"
+      severity NOTE;
+    assert (   pass = 0   )
+      report "***FAILED TEST: c06s04b00x00p01n01i01027 - Indexed reference test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p01n01i01027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd
new file mode 100644
index 0000000..46e6495
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1028.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01028ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01028ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01028arch OF c06s04b00x00p02n01i01028ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V1.RE1(1);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01028"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01028 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01028arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd
new file mode 100644
index 0000000..ad3d710
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01029ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01029ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V2.RE2(2, 3);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01029"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd
new file mode 100644
index 0000000..d92909e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1030.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01030ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01030ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01030arch OF c06s04b00x00p02n01i01030ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V3.RE3(1)(3);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01030"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01030 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd
new file mode 100644
index 0000000..419aac9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1031.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01031ent IS
+END c06s04b00x00p02n01i01031ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01031arch OF c06s04b00x00p02n01i01031ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    TEN    is range 1 to 10;
+    type    ABASE1    is array (TEN range <>) of BOOLEAN;
+    subtype    A1    is ABASE1(TEN);
+    type    ABASE2    is array (TEN range <>) of A1;
+    subtype    A2    is ABASE2(TEN);
+    variable Sl_of_sl    : A2 ;
+    variable V2      : A2 ; -- := (others=>(others=>TRUE));
+  BEGIN
+    Sl_of_sl(1 to 8)(7)  := V2(2 to 9)(2);
+    assert NOT( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
+      report "***PASSED TEST: c06s04b00x00p02n01i01031"
+      severity NOTE;
+    assert ( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
+      report "***FAILED TEST: c06s04b00x00p02n01i01031 - The prefix of an indexed name can be a slice name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01031arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd
new file mode 100644
index 0000000..b8f40e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1032.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01032ent IS
+END c06s04b00x00p02n01i01032ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01032arch OF c06s04b00x00p02n01i01032ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    
+    type A0 is array (TWO) of BOOLEAN;
+    type A1 is array (TWO) of A0;
+    type A2 is array (TWO) of A1;
+    type A3 is array (TWO) of A2;
+    type A4 is array (TWO) of A3;
+    type A5 is array (TWO) of A4;
+    type A6 is array (TWO) of A5;
+    type A7 is array (TWO) of A6;
+    type A8 is array (TWO) of A7;
+    type A9 is array (TWO) of A8;
+    
+    variable V1: A9;
+  BEGIN
+    V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) := TRUE; 
+    assert NOT(V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01032"
+      severity NOTE;
+    assert (V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01032 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd
new file mode 100644
index 0000000..d743054
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1033.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01033ent IS
+END c06s04b00x00p02n01i01033ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01033arch OF c06s04b00x00p02n01i01033ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    
+    function F1(i : integer) return A1 is
+      variable AR : A1;
+    begin
+      return AR;
+    end F1;
+    
+    variable A : integer;
+    variable V: BOOLEAN;
+    
+    variable BOOL    : boolean;
+  BEGIN
+    V  := F1(A)(1);     -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01033"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01033 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd
new file mode 100644
index 0000000..927ef8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1034.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01034ent IS
+END c06s04b00x00p02n01i01034ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01034arch OF c06s04b00x00p02n01i01034ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    type A2 is array (THREE, THREE) of BOOLEAN;
+    
+    function F2(i : integer) return A2 is
+      variable AR2 : A2;
+    begin
+      return AR2;
+    end F2;
+    
+    variable A : integer;
+    variable V: BOOLEAN;
+    
+  BEGIN
+    V  := F2(A)(2, 3);  -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01034"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01034 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd
new file mode 100644
index 0000000..b59f476
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1035.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01035ent IS
+END c06s04b00x00p02n01i01035ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01035arch OF c06s04b00x00p02n01i01035ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    type A2 is array (THREE, THREE) of BOOLEAN;
+    type A3 is array (THREE) of A1;
+    
+    function F3(i : integer) return A3 is
+      variable AR3 : A3;
+    begin
+      return AR3;
+    end F3;
+    variable A  : integer;
+    variable V  : BOOLEAN;
+    
+  BEGIN
+    V := F3(A)(1)(3);   -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01035"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01035 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd
new file mode 100644
index 0000000..22021af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1037.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01037pkg is
+  type    THREE    is range 1 to 3;
+  type    A1    is array (THREE) of BOOLEAN;
+  function    Af1    (g : integer) return A1;
+end c06s04b00x00p02n01i01037pkg;
+
+package body c06s04b00x00p02n01i01037pkg is
+  function Af1 (g : integer) return A1 is
+    variable vaf1 : A1;
+  begin
+    return Vaf1;
+  end Af1;
+end c06s04b00x00p02n01i01037pkg;
+
+use work.c06s04b00x00p02n01i01037pkg.all;
+ENTITY c06s04b00x00p02n01i01037ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT1 : A1;
+  attribute AT1 of PT : signal is Af1(g) ;
+END c06s04b00x00p02n01i01037ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01037arch OF c06s04b00x00p02n01i01037ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT1(1);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01037"
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01037 - Indexed name be an attribute name test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd
new file mode 100644
index 0000000..1dda60f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1038.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01038pkg is
+  type    THREE    is range 1 to 3;
+  type    A2    is array (THREE, THREE) of BOOLEAN;
+  function    Af2    (g : integer) return A2;
+end c06s04b00x00p02n01i01038pkg;
+
+package body c06s04b00x00p02n01i01038pkg is
+  function Af2 (g : integer) return A2 is
+    variable vaf1 : A2;
+  begin
+    return Vaf1;
+  end Af2;
+end c06s04b00x00p02n01i01038pkg;
+
+use work.c06s04b00x00p02n01i01038pkg.all;
+ENTITY c06s04b00x00p02n01i01038ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT2 : A2;
+  attribute AT2 of PT : signal is Af2(g) ;
+END c06s04b00x00p02n01i01038ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01038arch OF c06s04b00x00p02n01i01038ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT2(2, 3);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01038" 
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01038 - Indexed name be an attribute name test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd
new file mode 100644
index 0000000..3a73163
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1039.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01039pkg is
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  function Af3(g : integer) return A3;
+end c06s04b00x00p02n01i01039pkg;
+
+package body c06s04b00x00p02n01i01039pkg is
+  function Af3(g : integer) return A3 is
+    variable vaf1 : A3;
+  begin
+    return Vaf1;
+  end Af3;
+end c06s04b00x00p02n01i01039pkg;
+
+use work.c06s04b00x00p02n01i01039pkg.all;
+ENTITY c06s04b00x00p02n01i01039ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT3 : A3;
+  attribute AT3 of PT : signal is Af3(g) ;
+END c06s04b00x00p02n01i01039ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01039arch OF c06s04b00x00p02n01i01039ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT3(1)(3);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01039" 
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01039 - Indexed name be an attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd
new file mode 100644
index 0000000..9d22685
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01040ent IS
+END c06s04b00x00p03n01i01040ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS
+  type A is array (1 to 10) of integer;
+  function foo (f:integer :=  3) return A is
+    variable v: A := (1,2,3,4,5,6,7,8,9,10);
+  begin
+    return v;
+  end foo;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := foo(3)(3);
+    assert NOT( k=3 )
+      report "***PASSED TEST: c06s04b00x00p03n01i01040"
+      severity NOTE;
+    assert ( k=3 )
+      report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd
new file mode 100644
index 0000000..fe4b014
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1050.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01050ent IS
+END c06s04b00x00p03n02i01050ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01050arch OF c06s04b00x00p03n02i01050ent IS
+  type arrtype is array (positive range 1 to 10, bit range '0' to '1') of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype ;
+  BEGIN
+    k(1,'0') := 1.2;
+    assert NOT(k(1,'0')=1.2)
+      report "***PASSED TEST: c06s04b00x00p03n02i01050"
+      severity NOTE;
+    assert (k(1,'0')=1.2)
+      report "***FAILED TEST: c06s04b00x00p03n02i01050 - The expressions specify the index values for the element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd
new file mode 100644
index 0000000..616346f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1067.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n04i01067ent IS
+END c06s04b00x00p03n04i01067ent;
+
+ARCHITECTURE c06s04b00x00p03n04i01067arch OF c06s04b00x00p03n04i01067ent IS
+  type arrtype is array (positive range 1 to 10) of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype;
+  BEGIN
+    k(1+2) := 1.2;
+    assert NOT( K(3)=1.2 )
+      report "***PASSED TEST: c06s04b00x00p03n04i01067"
+      severity NOTE;
+    assert ( K(3)=1.2 )
+      report "***FAILED TEST: c06s04b00x00p03n04i01067 - The index value belongs to the range of the corresponding index range of the array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n04i01067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd
new file mode 100644
index 0000000..d18a68a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1069.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01069ent IS
+  PORT ( ii: INOUT integer);
+  TYPE    A    IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE A6    IS A (1 TO 6);
+  SUBTYPE A8    IS A (1 TO 8);
+
+  FUNCTION func1 RETURN A6 IS
+  BEGIN
+    RETURN (1,2,3,4,5,6);
+  END;
+END c06s04b00x00p03n01i01069ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01069arch OF c06s04b00x00p03n01i01069ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(1);
+    q(2) := func1(2);
+    q(3) := func1(3);
+    q(4) := func1(4);
+    q(5) := func1(5);
+    q(6) := func1(6);
+    q(7) := func1(3);
+    q(8) := func1(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1)) 
+      report "***PASSED TEST: c06s04b00x00p03n01i01069" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1)) 
+      report "***FAILED TEST: c06s04b00x00p03n01i01069 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd
new file mode 100644
index 0000000..09277be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01070ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01070ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3,3)(1);
+    q(2) := func1(0,3)(2);
+    q(3) := func1(3,0)(3);
+    q(4) := func1(0,3)(4);
+    q(5) := func1(3,3)(5);
+    q(6) := func1(3,0)(6);
+    q(7) := func1(3,3)(3);
+    q(8) := func1(0,3)(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
+      report "***PASSED TEST: c06s04b00x00p03n01i01070" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
+      report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd
new file mode 100644
index 0000000..9ffe396
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1071.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01071ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01071ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01071arch OF c06s04b00x00p03n01i01071ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(1);
+    q(2) := func1(2);
+    q(3) := func1(3);
+    q(4) := func1(4);
+    q(5) := func1(5);
+    q(6) := func1(6);
+    q(7) := func1(3);
+    q(8) := func1(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***PASSED TEST: c06s04b00x00p03n01i01071"
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***FAILED TEST: c06s04b00x00p03n01i01071 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd
new file mode 100644
index 0000000..0dcffe6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1072.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01072ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01072ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01072arch OF c06s04b00x00p03n01i01072ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3)(1);
+    q(2) := func1(0)(2);
+    q(3) := func1(3)(3);
+    q(4) := func1(0)(4);
+    q(5) := func1(3)(5);
+    q(6) := func1(0)(6);
+    q(7) := func1(3)(3);
+    q(8) := func1(0)(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>3,4=>444,5=>5,6=>666,7=>3,8=>111))
+      report "***PASSED TEST: c06s04b00x00p03n01i01072" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>222,3=>3,4=>444,5=>5,6=>666,7=>3,8=>111))
+      report "***FAILED TEST: c06s04b00x00p03n01i01072 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd
new file mode 100644
index 0000000..a8d4f9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01073ent IS
+  PORT ( ii: INOUT integer);
+  TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE A8 IS A (1 TO 8);
+  SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
+  SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
+    ELSE
+      IF (a=3) THEN
+        RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
+      ELSE
+        RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01073ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3,0)(1,1,1);
+    q(2) := func1(0,3)(2,2,2);
+    q(3) := func1(0,0)(3,3,3);
+    q(4) := func1(4,4,4); -- Indexed name - function params defaulted
+    q(5) := func1(5,5,5);
+    q(6) := func1(6,6,6);
+    q(7) := func1(3,3,3);
+    q(8) := func1(1,1,1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***PASSED TEST: c06s04b00x00p03n01i01073" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd
new file mode 100644
index 0000000..0dcdb5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1075.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01075ent IS
+END c06s04b00x00p03n02i01075ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01075arch OF c06s04b00x00p03n02i01075ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CSTRING is array (CHARACTER range <>) of CHARACTER;
+
+    constant C1 : CSTRING('A' to 'H') := "BCDEFGHA";
+    constant C2 : CSTRING('A' to 'H') := "CDEFGHAB";
+    constant C3 : CSTRING('A' to 'H') := "DEFGHABC";
+
+    variable V1 : CHARACTER;
+    variable V2 : CHARACTER;
+    variable V3 : CHARACTER;
+  BEGIN
+    V1 := C1('A');          --      A -> B
+    assert V1 = 'B';
+    V2 := C2(C1('A'));      --      A -> B -> D
+    assert V2 = 'D';
+    V3 := C3(C2(C1('A')));  --      A -> B -> H
+    assert V3 = 'G';
+    wait for 5 ns;
+    assert NOT( V1 = 'B' and V2 = 'D' and V3 = 'G' ) 
+      report "***PASSED TEST: c06s04b00x00p03n02i01075" 
+      severity NOTE;
+    assert ( V1 = 'B' and V2 = 'D' and V3 = 'G' ) 
+      report "***FAILED TEST: c06s04b00x00p03n02i01075 - The expresion for index name check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd
new file mode 100644
index 0000000..23acba6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1076.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n01i01076ent IS
+  subtype    line      is integer range 0 to 15;
+  subtype    cmd      is integer range 0 to 3;
+  type    d_lines   is array (line range <>) of bit;
+  subtype    data_line is d_lines(line);
+  subtype    cmd_line  is d_lines(cmd);
+END c06s05b00x00p01n01i01076ent;
+
+ARCHITECTURE c06s05b00x00p01n01i01076arch OF c06s05b00x00p01n01i01076ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable d1    : data_line := (0 to 3 => '1', others => '0');
+    variable instr    : cmd_line;
+  BEGIN
+    --
+    -- Test assigning a slice to a full array
+    --
+    instr := d1(0 to 3);
+    for i in 0 to 3 loop
+      assert instr(i) = '1'
+        report "Slice to full array assignment failed."
+        severity note ;
+    end loop;
+
+    --
+    -- Now try a full array to a slice
+    --
+    d1(8 to 11) := instr;
+    for i in 8 to 11 loop
+      assert d1(i) = '1'
+        report "Full array to slice assignment failed."
+        severity note ;
+    end loop;
+
+    --
+    -- Now try assigning a slice to a slice
+    --
+    d1(8 to 11) := d1(4 to 7);
+    for i in 4 to 15 loop
+      assert d1(i) = '0'
+        report "Slice to slice assignment failed."
+        severity note ;
+    end loop;
+
+    assert NOT( instr = "1111" and d1 = "1111000000000000" )
+      report "***PASSED TEST: c06s05b00x00p01n01i01076"
+      severity NOTE;
+    assert ( instr = "1111" and d1 = "1111000000000000" )
+      report "***FAILED TEST: c06s05b00x00p01n01i01076 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n01i01076arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd
new file mode 100644
index 0000000..a541143
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1077.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n01i01077ent IS
+END c06s05b00x00p01n01i01077ent;
+
+ARCHITECTURE c06s05b00x00p01n01i01077arch OF c06s05b00x00p01n01i01077ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A    : bit_vector (1 to 32);
+    constant AA    : bit_vector (1 to 32) := x"0000ffff";
+    variable B    : bit_vector (32 downto 1);
+    variable C    : bit_vector (15 downto 0);
+    variable D, DD    : bit_vector (0 to 15);
+    variable E    : bit_vector (0 to 47);
+    variable F    : bit_vector (47 downto 0);
+    alias FF    : bit_vector (47 downto 0) is F;
+    alias FH    : bit_vector (0 to 31) is F (47 downto 16);
+  BEGIN
+    A := x"0000ffff";
+    B := x"00ff00ff";
+    C := x"00ff";
+    D := x"0f0f";
+    E := x"000000ffffff";
+    FF := x"000fff000fff";
+    assert NOT(   ( A(1 to 32) = x"0000ffff")   and
+                  ( A(1 to 20) = x"0000f")   and
+                  ( A(9 to 32) = x"00ffff")   and
+                  ( A(9 to 28) = x"00fff")   and
+                  ( C(15 downto 0) = x"00ff")   and
+                  ( C(11 downto 0) = x"0ff")   and
+                  ( C(15 downto 4) = x"00f")   and
+                  ( C(11 downto 4) = x"0f")   and
+                  ( F(47 downto 0) = x"000fff000fff")   and
+                  ( F(39 downto 0) = x"0fff000fff")   and
+                  ( F(47 downto 8) = x"000fff000f")   and
+                  ( F(39 downto 8) = x"0fff000f")   and
+                  ( F(47 downto 36) = x"000")   and
+                  ( F(11 downto 0) = x"fff")   and
+                  ( F(35 downto 20) = x"fff0")   and
+                  ( FF(47 downto 0) = x"000fff000fff")   and
+                  ( FF(39 downto 0) = x"0fff000fff")   and
+                  ( FF(47 downto 8) = x"000fff000f")   and
+                  ( FF(39 downto 8) = x"0fff000f")   and
+                  ( FF(47 downto 36) = x"000")   and
+                  ( FF(11 downto 0) = x"fff")   and
+                  ( FF(35 downto 20) = x"fff0")   and
+                  ( FH(0 to 31) = x"000fff00")   and
+                  ( FH(8 to 31) = x"0fff00")   and
+                  ( FH(0 to 11) = x"000")      and
+                  ( FH(12 to 27) = x"fff0")   ) 
+      report "***PASSED TEST: c06s05b00x00p01n01i01077"
+      severity NOTE;
+    assert (   ( A(1 to 32) = x"0000ffff")   and
+               ( A(1 to 20) = x"0000f")   and
+               ( A(9 to 32) = x"00ffff")   and
+               ( A(9 to 28) = x"00fff")   and
+               ( C(15 downto 0) = x"00ff")   and
+               ( C(11 downto 0) = x"0ff")   and
+               ( C(15 downto 4) = x"00f")   and
+               ( C(11 downto 4) = x"0f")   and
+               ( F(47 downto 0) = x"000fff000fff")   and
+               ( F(39 downto 0) = x"0fff000fff")   and
+               ( F(47 downto 8) = x"000fff000f")   and
+               ( F(39 downto 8) = x"0fff000f")   and
+               ( F(47 downto 36) = x"000")   and
+               ( F(11 downto 0) = x"fff")   and
+               ( F(35 downto 20) = x"fff0")   and
+               ( FF(47 downto 0) = x"000fff000fff")   and
+               ( FF(39 downto 0) = x"0fff000fff")   and
+               ( FF(47 downto 8) = x"000fff000f")   and
+               ( FF(39 downto 8) = x"0fff000f")   and
+               ( FF(47 downto 36) = x"000")   and
+               ( FF(11 downto 0) = x"fff")   and
+               ( FF(35 downto 20) = x"fff0")   and
+               ( FH(0 to 31) = x"000fff00")   and
+               ( FH(8 to 31) = x"0fff00")   and
+               ( FH(0 to 11) = x"000")      and
+               ( FH(12 to 27) = x"fff0")   ) 
+      report "***FAILED TEST: c06s05b00x00p01n01i01077 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n01i01077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd
new file mode 100644
index 0000000..37b345a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01078ent IS
+END c06s05b00x00p01n02i01078ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+  SIGNAL    resultt : boolean;
+
+  procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
+  begin
+    if ( v = B"1010" ) then
+      result <= true;
+    else
+      result <= false;
+    end if;
+  end ;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE  v_slice : bit_vector_8 := B"1010_1100";
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ), resultt );
+    wait for 1 ns;
+    assert NOT( resultt = true )
+      report "***PASSED TEST: c06s05b00x00p01n02i01078"
+      severity NOTE;
+    assert ( resultt = true )
+      report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd
new file mode 100644
index 0000000..626adde
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1079.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01079ent IS
+END c06s05b00x00p01n02i01079ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01079arch OF c06s05b00x00p01n02i01079ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+  SIGNAL    v_slice : bit_vector_8 := B"1010_1100";   
+
+  procedure subprogram ( signal v : out bit_vector_4 ) is
+  begin
+    v <= B"0101" after 10 ns;
+  end ;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ) );
+    wait for 11 ns;
+    assert NOT(v_slice = B"0101_1100") 
+      report "***PASSED TEST: c06s05b00x00p01n02i01079"
+      severity NOTE;
+    assert (v_slice = B"0101_1100") 
+      report "***FAILED TEST: c06s05b00x00p01n02i01079 - A slice of a signal should still be a signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd
new file mode 100644
index 0000000..d69ddda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1080.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01080ent IS
+END c06s05b00x00p01n02i01080ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01080arch OF c06s05b00x00p01n02i01080ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+  SIGNAL   result  : boolean;
+
+  CONSTANT    v_slice : bit_vector_8 := B"1010_1100";   
+
+  procedure subprogram ( constant v : in bit_vector_4; signal resultt : out boolean ) is
+  begin
+    if (v = "1010") then
+      resultt <= true;
+    else
+      resultt <= false;
+    end if;
+  end ;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ), result );
+    wait for 11 ns;
+    assert NOT(result = true)
+      report "***PASSED TEST: c06s05b00x00p01n02i01080"
+      severity NOTE;
+    assert (result = true)
+      report "***FAILED TEST: c06s05b00x00p01n02i01080 - A slice of a constant should still be a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd
new file mode 100644
index 0000000..569b7e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1081.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01081ent IS
+END c06s05b00x00p01n02i01081ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01081arch OF c06s05b00x00p01n02i01081ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var : bit_vector_8 := B"1110_0010";
+    VARIABLE v1  : bit_vector_4 := B"0011";
+    VARIABLE v2  : bit_vector_4 := B"1111";
+  BEGIN
+    var (0 to 3) := v1;
+    var (4 to 7) := v2;
+    assert NOT( var = B"0011_1111" )
+      report "***PASSED TEST: c06s05b00x00p01n02i01081"
+      severity NOTE;
+    assert ( var = B"0011_1111" )
+      report "***FAILED TEST: c06s05b00x00p01n02i01081 - Slices of a variable may be the target of a variable assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd
new file mode 100644
index 0000000..3dff0d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1086.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01086ent IS
+END c06s05b00x00p02n01i01086ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01086arch OF c06s05b00x00p02n01i01086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable str : string (1 to 25) := "This is array slice check";
+    variable k   : integer;
+  BEGIN
+    if str(1 to 3) = "Thi" then -- Success_here
+      k := 5;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01086" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01086 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd
new file mode 100644
index 0000000..d3bbfb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1087.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01087ent IS
+END c06s05b00x00p02n01i01087ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01087arch OF c06s05b00x00p02n01i01087ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    ABASE1    is array (FIVE range <>) of BOOLEAN;
+    subtype    A1    is ABASE1(FIVE);
+    type    ABASE2    is array (FIVE range <>) of A1;
+    subtype    A2    is ABASE2(FIVE);
+    variable    V1   : A1;
+    variable    V2   : A2 ; -- := (others=>(others=>TRUE));
+  BEGIN
+    V1(2 to 4) := V2(3)(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01087" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01087 - Indexed name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd
new file mode 100644
index 0000000..e8ed114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1088.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01088ent IS
+END c06s05b00x00p02n01i01088ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01088arch OF c06s05b00x00p02n01i01088ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type ABASE is array (FIVE range <>) of BOOLEAN;
+    subtype A1 is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+  BEGIN
+    V1(2 to 4) := V2.RE1(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01088" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01088 - Selected name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd
new file mode 100644
index 0000000..72808a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1089.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01089ent IS
+END c06s05b00x00p02n01i01089ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01089arch OF c06s05b00x00p02n01i01089ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type ABASE is array (FIVE range <>) of BOOLEAN;
+    subtype A1 is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V3.RE2.RE1(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01089" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01089 - Selected name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd
new file mode 100644
index 0000000..b06ad7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01090ent IS
+END c06s05b00x00p02n01i01090ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    I1    is range 0 to 11;
+    type    ABASE is array (I1 range <>) of BOOLEAN;
+    subtype    A1    is ABASE(I1);
+    variable    V1    : A1 ; -- := A1'(others=>TRUE);
+  BEGIN
+    V1(5 to 6) :=  V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
+    assert NOT(V1(5 to 6)=(false,false))
+      report "***PASSED TEST: c06s05b00x00p02n01i01090" 
+      severity NOTE;
+    assert (V1(5 to 6)=(false,false))
+      report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd
new file mode 100644
index 0000000..c660335
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1091.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s05b00x00p02n01i01091pkg is
+  type FIVE    is range 1 to 5;
+  type ABASE    is array (FIVE range <>) of BOOLEAN;
+  subtype A1    is ABASE(FIVE);
+  attribute    AT1 : A1;
+  function    fat1(i:integer) return a1;
+end c06s05b00x00p02n01i01091pkg;
+
+package body c06s05b00x00p02n01i01091pkg is
+  function fat1(i:integer) return a1 is
+    variable va1 : a1;
+  begin
+    return Va1;
+  end fat1;
+end c06s05b00x00p02n01i01091pkg;
+
+use work.c06s05b00x00p02n01i01091pkg.all;
+ENTITY c06s05b00x00p02n01i01091ent IS
+  port (PT: BOOLEAN) ;
+
+  attribute AT1 of PT : signal is fat1(8);
+END c06s05b00x00p02n01i01091ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01091arch OF c06s05b00x00p02n01i01091ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : A1;
+  BEGIN
+    V1(2 to 4) := PT'AT1(2 to 4);
+    assert NOT(V1(2 to 4)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p02n01i01091"
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p02n01i01091 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd
new file mode 100644
index 0000000..e5d9a7b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1092.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01092ent IS
+END c06s05b00x00p03n01i01092ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01092arch OF c06s05b00x00p03n01i01092ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable str : string(1 to 25) := "This is array slice check";
+    variable k   : integer;
+  BEGIN
+    if str(1 to 3) = "Thi" then
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c06s05b00x00p03n01i01092"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n01i01092 - The prefix of a slice must be appropriate for a one-dimensional array object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd
new file mode 100644
index 0000000..01a900b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00110ent IS
+  port (S1 : out BIT_VECTOR(0 to 3) := "1011");
+END c04s03b02x00p29n06i00110ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
+  signal S2,S3 : BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (S1'LOW = 0) then
+      S2 <= '1' after 10 ns;
+    end if;
+
+    if (S1'HIGH = 3) then
+      S3 <= '1' after 10 ns;
+    end if;
+    wait for 20 ns;
+    
+    assert NOT(S2='1' and S3='1') 
+      report "***PASSED TEST: c04s03b02x00p29n06i00110" 
+      severity NOTE;
+    assert (S2='1' and S3='1') 
+      report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd
new file mode 100644
index 0000000..332f1c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01103ent IS
+END c06s05b00x00p03n01i01103ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE    is range 1 to 5;
+    type ABASE    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V2.RE1(2 to 4);  -- No_failure_here
+    assert NOT(V1(2 to 4)=(false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01103" 
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd
new file mode 100644
index 0000000..59d5cbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1104.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01104ent IS
+END c06s05b00x00p03n01i01104ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01104arch OF c06s05b00x00p03n01i01104ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE    is range 1 to 5;
+    type ABASE    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V3.RE2.RE1(2 to 4);  -- No_failure_here
+    assert NOT(V1(2 to 4)=(false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01104" 
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01104 - Prefix of a slice can be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd
new file mode 100644
index 0000000..9f4c28f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc111.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00111ent IS
+END c04s03b02x00p29n06i00111ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00111arch OF c04s03b02x00p29n06i00111ent IS
+  PROCEDURE p1 ( prm_out : OUT INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_out : VARIABLE IS 300;
+  BEGIN
+    ASSERT prm_out'attr1 = 300 REPORT "ERROR: Bad value for prm_out'attr1" SEVERITY FAILURE;
+    assert NOT(prm_out'attr1 = 300)
+      report "***PASSED TEST: c04s03b02x00p29n06i00111"
+      severity NOTE;
+    assert (prm_out'attr1 = 300)
+      report "***FAILED TEST: c04s03b02x00p29n06i00111 - Reading of the attributes of the interface element of mode out in a subprogram testing failed." 
+      severity ERROR;
+  END;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE tmp : INTEGER;
+  BEGIN
+--
+    p1 ( tmp );
+--   
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd
new file mode 100644
index 0000000..e9963b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01117ent IS
+END c06s05b00x00p03n01i01117ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01117arch OF c06s05b00x00p03n01i01117ent IS
+
+  subtype FIVE    is INTEGER range 1 to 5;
+  type    ABASE    is array (FIVE range <>) of BOOLEAN;
+  subtype A1    is ABASE (FIVE);
+  function F (i: integer) return A1 is
+    variable ARR : A1;
+  begin
+    return ARR;
+  end F;
+
+BEGIN
+  TESTING: PROCESS
+    variable V1    : A1;
+  BEGIN
+    V1(2 to 4) := F(5)(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01117"
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01117 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd
new file mode 100644
index 0000000..f263a26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1119.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01119ent IS
+  subtype    idx     is integer range 1 to 10;
+  type    aray1    is array (idx) of bit;
+  type    aray2    is array (idx range <>) of aray1;
+END c06s05b00x00p03n01i01119ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01119arch OF c06s05b00x00p03n01i01119ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1   : aray1;
+    variable v2   : aray1;
+    variable v5    : aray1;
+    variable v3     : aray2(1 to 2);
+    variable v4     : aray2(1 to 3);
+  BEGIN
+    --
+    -- Try slices consisting of indexed names
+    --
+    v1 := "1111111111";
+    v1 := v3(1)(idx);                -- slice is a whole array
+    assert not (v2 = v1)
+      report "Slice of an indexed name as a value passed."
+      severity note;
+    
+    v5 := "1111111111";
+    v4(2)(idx) := v5;                -- slice is a whole array
+    assert not(v4(2) = v5)
+      report "Slice of an indexed name as a target passed."
+      severity note;
+    
+    v2(1) := v3(1)(1 to 1)(1);               -- a one element slice
+    assert not (v3(1)(1) = v2(1))
+      report "One element slice of an indexed name as a value passed." 
+      severity note;
+    
+    v3(1)(1 to 1)(1) := v1(1);               -- a one element slice
+    assert not (v3(1)(1) = v1(1))
+      report "One element slice of an indexed name as a target passed."
+      severity note;
+
+    assert NOT(   v1       = "0000000000"   and
+                  v4(2)       = "1111111111"   and
+                  v2(1)      = '0'      and
+                  v3(1)(1)   = '0') 
+      report "***PASSED TEST: c06s05b00x00p03n01i01119" 
+      severity NOTE;
+    assert (   v1       = "0000000000"   and
+               v4(2)       = "1111111111"   and
+               v2(1)      = '0'      and
+               v3(1)(1)   = '0') 
+      report "***FAILED TEST: c06s05b00x00p03n01i01119 - The prefix of a slice may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd
new file mode 100644
index 0000000..16ee4cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1121.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01121ent IS
+END c06s05b00x00p03n02i01121ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01121arch OF c06s05b00x00p03n02i01121ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     ENUM1  is (M1, M2, M3, M4, M5, M6);
+    type     A1     is array (ENUM1 range <>) of BOOLEAN;
+    subtype  A11    is A1 (M1 to M3);
+    subtype  A12    is A1 (M4 to M6);
+    variable V1     : A1 (M1 to M6) ;
+    variable V11    : A11;
+    variable V12    : A12;
+    variable k      : integer;
+  BEGIN
+    if (
+      (V11 = V12)
+      and (V11(M2 to M3) = V12(M4 to M5))
+      and (V1 (M1 to M3) = V11(M1 to M3))
+      and (V1 (M2 to M3) = V12(M4 to M5))
+      ) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s05b00x00p03n02i01121"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n02i01121 - The type of the slice is the same as the base type of the one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01121arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd
new file mode 100644
index 0000000..e901ab6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1122.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01122ent IS
+END c06s05b00x00p03n02i01122ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01122arch OF c06s05b00x00p03n02i01122ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5, M6);
+    type A1    is array (ENUM1 range <>) of BOOLEAN;
+    subtype A11 is A1 (M1 to M3);
+    subtype A12 is A1 (M4 to M6);
+    variable V1 : A1  (M1 to M6) ;
+    variable V11: A11;
+    variable V12: A12;
+    variable k : integer := 0;
+  BEGIN
+    if (
+      (V11 = V12)
+      and (V11(M2 to M3) = V12(M4 to M5))
+      and (V1 (M1 to M3) = V11(M1 to M3))
+      and (V1 (M2 to M3) = V12(M4 to M5))
+      ) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s05b00x00p03n02i01122"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n02i01122 - The type of the slice is the same as the base type of the one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01122arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd
new file mode 100644
index 0000000..6a5171f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1123.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01123ent IS
+END c06s05b00x00p03n02i01123ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01123arch OF c06s05b00x00p03n02i01123ent IS
+  TYPE       colors       is ( red, green, blue, yellow, orange, black );
+  TYPE       ncolor_array    is array ( NATURAL range <> ) of colors;
+  SUBTYPE       ncolor_4    is ncolor_array ( 0 to 3 );
+  TYPE       pcolor_array    is array ( POSITIVE range <> ) of colors;
+  SUBTYPE       pcolor_4    is ncolor_array ( 1 to 4 );
+BEGIN
+  TESTING: PROCESS
+    variable vn : ncolor_4 := ( red, red, green, black );
+    variable vp : pcolor_4 := ( blue, yellow, yellow, orange );
+  BEGIN
+    vn(1 to 3) := vp(2 to 4);
+    assert NOT( vn = ( red, yellow, yellow, orange ) ) 
+      report "***PASSED TEST: c06s05b00x00p03n02i01123"
+      severity NOTE;
+    assert ( vn = ( red, yellow, yellow, orange ) ) 
+      report "***FAILED TEST: c06s05b00x00p03n02i01123 - The base type of the array type is the type of the slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01123arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd
new file mode 100644
index 0000000..cac6262
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1126.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01126ent IS
+END c06s05b00x00p04n01i01126ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01126arch OF c06s05b00x00p04n01i01126ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE1 is range 1 to 5;
+    type    FIVE2 is range 1 to 5;
+    type    A3B   is array (FIVE1 range <>) of BOOLEAN;
+    subtype    A3    is A3B   (FIVE1);
+    type    A4B   is array (FIVE2 range <>) of A3;
+    subtype    A4    is A4B   (FIVE2);
+
+    variable    V4: A4 ;
+  BEGIN
+    V4(3)(1 to 5) := V4(4)(FIVE1);   -- legal assignments.
+    assert NOT(V4(3)(1 to 5) = (false,false,false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p04n01i01126" 
+      severity NOTE;
+    assert (V4(3)(1 to 5) = (false,false,false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p04n01i01126 - Bounds of the discrete range must be the type of the index of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01126arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd
new file mode 100644
index 0000000..58688f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc113.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00113pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00113pkg;
+
+use work.c04s03b02x00p29n10i00113pkg.all;
+ENTITY c04s03b02x00p29n10i00113ent IS
+  port (
+    p23 : inout Boolean        := FALSE;
+    p24 : inout Bit            := '0'  ;
+    p25 : inout Character      := NUL  ;
+    p26 : inout SEVERITY_LEVEL := NOTE ;
+    p27 : inout Integer        := -1   ;
+    p28 : inout Real           := -1.0 ;
+    p29 : inout TIME           := 1 fs ;
+    p30 : inout Natural        := 0    ;
+    p31 : inout Positive       := 1    ;
+    p32 : inout Apollo_string  := "abcdefgh";
+    p33 : inout V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00113ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00113arch OF c04s03b02x00p29n10i00113ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    p23 = FALSE   and
+                   p24 = '0'     and 
+                   p25 = NUL     and 
+                   p26 = NOTE    and 
+                   p27 = -1      and 
+                   p28 = -1.0    and 
+                   p29 = 1 fs    and 
+                   p30 = 0       and 
+                   p31 = 1       and 
+                   p32 = "abcdefgh"and
+                   p33 = B"10010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00113"
+      severity NOTE;
+    assert (    p23 = FALSE   and
+                p24 = '0'     and 
+                p25 = NUL     and 
+                p26 = NOTE    and 
+                p27 = -1      and 
+                p28 = -1.0    and 
+                p29 = 1 fs    and 
+                p30 = 0       and 
+                p31 = 1       and 
+                p32 = "abcdefgh"and
+                p33 = B"10010110"   )
+      report "***FAILED TEST:c04s03b02x00p29n10i00113 - Values of INOUT port reading failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00113arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd
new file mode 100644
index 0000000..f3b9543
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1137.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n02i01137ent IS
+  type aray1 is array (integer range <>) of bit;
+END c06s05b00x00p04n02i01137ent;
+
+ARCHITECTURE c06s05b00x00p04n02i01137arch OF c06s05b00x00p04n02i01137ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable nul : aray1(2 to 1); -- null array 
+    variable nu2 : aray1(9 to 1); -- null array
+  BEGIN
+    --
+    -- Test the range direction
+    --
+    assert NOT(nul = nu2) 
+      report "***PASSED TEST: c06s05b00x00p04n02i01137" 
+      severity NOTE;
+    assert (nul = nu2) 
+      report "***FAILED TEST: c06s05b00x00p04n02i01137- The slice is a null slice if the discrete range is a null range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n02i01137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd
new file mode 100644
index 0000000..2c25fda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01138ent IS
+END c06s05b00x00p05n02i01138ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
+  signal T1 : boolean;
+BEGIN
+  TESTING: PROCESS
+    variable B : Bit_vector (1 to 10) := B"01010_10101";
+  BEGIN
+    if B(1 to 2) = B"01"  then
+      T1 <= TRUE;
+    else
+      T1 <= FALSE;
+    end if;
+    wait for 1 ns;
+    assert NOT(T1=TRUE)
+      report "***PASSED TEST: c06s05b00x00p05n02i01138"
+      severity NOTE;
+    assert (T1=TRUE)
+      report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd
new file mode 100644
index 0000000..9d450fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01139ent IS
+END c06s05b00x00p05n02i01139ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    function F(i : integer) return ENUM1 is
+    begin
+      return M2;
+    end F;
+
+    function G(j : integer) return ENUM1 is
+    begin
+      return M4;
+    end G;
+    variable ii : integer;
+    variable jj : integer;
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(M1 to M3) := V1(F(ii) to G(jj));
+    assert NOT(V1(M1 to M3)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01139"
+      severity NOTE;
+    assert (V1(M1 to M3)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd
new file mode 100644
index 0000000..616be3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc114.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00114pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00114pkg;
+
+use work.c04s03b02x00p29n10i00114pkg.all;
+ENTITY c04s03b02x00p29n10i00114ent IS
+  port (
+    p23 : inout Boolean        := FALSE;
+    p24 : inout Bit            := '0'  ;
+    p25 : inout Character      := NUL  ;
+    p26 : inout SEVERITY_LEVEL := NOTE ;
+    p27 : inout Integer        := -1   ;
+    p28 : inout Real           := -1.0 ;
+    p29 : inout TIME           := 1 fs ;
+    p30 : inout Natural        := 0    ;
+    p31 : inout Positive       := 1    ;
+    p32 : inout Apollo_string  := "abcdefgh";
+    p33 : inout V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00114ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00114arch OF c04s03b02x00p29n10i00114ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    p23   <= not p23;
+    p24   <= not p24;
+    p25   <= character'succ(p25);
+    p26   <= severity_level'succ(p26);
+    p27   <= p27 + p27;
+    p28   <= p28 + p28;
+    p29   <= p29 + p29;
+    p30   <= p30 + p30;
+    p31   <= p31 + p31;
+    p32(2)   <= character'succ(p32(2));
+    p33(1)   <= not p33(1);
+    
+    wait on p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33;
+
+    assert NOT(    p23 = TRUE   and
+                   p24 = '1'     and 
+                   p25 = SOH     and 
+                   p26 = WARNING    and 
+                   p27 = -2      and 
+                   p28 = -2.0    and 
+                   p29 = 2 fs    and 
+                   p30 = 0       and 
+                   p31 = 2       and 
+                   p32 = "accdefgh"and
+                   p33 = B"11010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00114"
+      severity NOTE;
+    assert (    p23 = TRUE   and
+                p24 = '1'     and 
+                p25 = SOH     and 
+                p26 = WARNING    and 
+                p27 = -2      and 
+                p28 = -2.0    and 
+                p29 = 2 fs    and 
+                p30 = 0       and 
+                p31 = 2       and 
+                p32 = "accdefgh"and
+                p33 = B"11010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00114 - Interface object update test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00114arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd
new file mode 100644
index 0000000..e725695
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1140.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01140ent IS
+END c06s05b00x00p05n02i01140ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01140arch OF c06s05b00x00p05n02i01140ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(V2 to V3) := V4(V2 to V3);
+    assert NOT(V1(M1 to M3)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01140"
+      severity NOTE;
+    assert (V1(M1 to M3)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01140 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01140arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd
new file mode 100644
index 0000000..4a81abd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1145.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01145ent IS
+END c06s05b00x00p05n02i01145ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01145arch OF c06s05b00x00p05n02i01145ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(V2 to V3) := V4(V2 to V3);
+    assert NOT(V1=(false,false,false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01145"
+      severity NOTE;
+    assert (V1=(false,false,false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01145 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01145arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd
new file mode 100644
index 0000000..4d515a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1147.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n03i01147ent IS
+END c06s05b00x00p05n03i01147ent;
+
+ARCHITECTURE c06s05b00x00p05n03i01147arch OF c06s05b00x00p05n03i01147ent IS
+  SUBTYPE thirteen is INTEGER range 0 to 12;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE null_array    : bit_vector ( 1 to 0 ); -- OK, a nice clean null array
+    VARIABLE slice       : bit_vector ( thirteen );
+  BEGIN
+
+    assert NOT(    null_array = slice (11 to 10)   and
+                   null_array = slice (-1 to -5)   and
+                   null_array = slice (15 to 14)  )
+      report "***PASSED TEST: c06s05b00x00p05n03i01147"
+      severity NOTE;
+    assert ( null_array = slice (11 to 10)   and
+             null_array = slice (-1 to -5)   and
+             null_array = slice (15 to 14)  )
+      report "***FAILED TEST: c06s05b00x00p05n03i01147 - The bounds of a null slice need not belong to the subtype of the index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n03i01147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd
new file mode 100644
index 0000000..1792cb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1149.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n02i01149ent IS
+END c06s05b00x00p07n02i01149ent;
+
+ARCHITECTURE c06s05b00x00p07n02i01149arch OF c06s05b00x00p07n02i01149ent IS
+  type    A is array (10 downto 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (66,66,others=>6);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1) = 6 )
+      report "***PASSED TEST: c06s05b00x00p07n02i01149"
+      severity NOTE;
+    assert ( var(1) = 6 )
+      report "***FAILED TEST: c06s05b00x00p07n02i01149 - A(N) is an element of the array A(decline) and has the corresponding element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n02i01149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd
new file mode 100644
index 0000000..3063a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc115.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00115ent IS
+  PORT ( prt_inout : INOUT INTEGER );
+  
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF prt_inout : SIGNAL   IS 200;
+END c04s03b02x00p29n10i00115ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00115arch OF c04s03b02x00p29n10i00115ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    ASSERT prt_inout'attr1 = 200 REPORT "ERROR: Bad value for prt_inout'attr1" SEVERITY FAILURE;
+
+    assert NOT( prt_inout'attr1 = 200 )   
+      report "***PASSED TEST: c04s03b02x00p29n10i00115"
+      severity NOTE;
+    assert ( prt_inout'attr1 = 200 )   
+      report "***FAILED TEST: c04s03b02x00p29n10i00115 - Interface object attribute reading test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00115arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd
new file mode 100644
index 0000000..010c7db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1151.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n02i01151ent IS
+END c06s05b00x00p07n02i01151ent;
+
+ARCHITECTURE c06s05b00x00p07n02i01151arch OF c06s05b00x00p07n02i01151ent IS
+  type    A is array (1 to 10) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (6,6,others=>88);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1) = 6 )
+      report "***PASSED TEST: c06s05b00x00p07n02i01151"
+      severity NOTE;
+    assert ( var(1) = 6 )
+      report "***FAILED TEST: c06s05b00x00p07n02i01151 - A(N) is an element of the array A(ascending) and has the corresponding element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n02i01151arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd
new file mode 100644
index 0000000..e9bc582
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1152.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01152ent IS
+END c06s06b00x00p02n01i01152ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01152arch OF c06s06b00x00p02n01i01152ent IS
+  type iarray is array (1 to 10) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for foo in iarray'range(1) loop  -- Success_here
+      k := k + 1;
+    end loop;
+    assert NOT( k=10 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01152"
+      severity NOTE;
+    assert ( k=10 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01152 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01152arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd
new file mode 100644
index 0000000..d028f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1153.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01153ent IS
+END c06s06b00x00p02n01i01153ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01153arch OF c06s06b00x00p02n01i01153ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    A1 is array (1 to 2) of BOOLEAN;
+    type    A2 is array (1 to 2) of A1;
+    variable    V  : A2;
+    variable    k  : integer;
+  BEGIN
+    if V(1)'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01153"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01153 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd
new file mode 100644
index 0000000..6ab209b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1154.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01154pkg is
+  type A1 is array (1 to 2) of BOOLEAN;
+  type A2 is array (1 to 2) of A1;
+end c06s06b00x00p02n01i01154pkg;
+
+use work.c06s06b00x00p02n01i01154pkg.all;
+ENTITY c06s06b00x00p02n01i01154ent IS
+  port (PT: A2) ;
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01154ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01154arch OF c06s06b00x00p02n01i01154ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01154"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01154 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd
new file mode 100644
index 0000000..2f1f2c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1155.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01155ent IS
+END c06s06b00x00p02n01i01155ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01155arch OF c06s06b00x00p02n01i01155ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ABASE is array (INTEGER range <>) of BOOLEAN;            
+    subtype A1    is ABASE(1 to 5);
+    variable V : A1;
+    variable k : integer := 0;
+  BEGIN
+    if V(2 to 4)'LOW = 2 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01155"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01155 - The prefix of an attribute name may be a slice name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd
new file mode 100644
index 0000000..78444a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1156.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01156pkg is
+  type A1 is array (1 to 5) of BOOLEAN;
+end c06s06b00x00p02n01i01156pkg;
+
+use work.c06s06b00x00p02n01i01156pkg.all;
+ENTITY c06s06b00x00p02n01i01156ent IS
+  port      (PT: A1) ;
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01156ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01156arch OF c06s06b00x00p02n01i01156ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01156"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01156 - The prefix of an attribute name may be a slice name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd
new file mode 100644
index 0000000..54852cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1157.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01157ent IS
+END c06s06b00x00p02n01i01157ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01157arch OF c06s06b00x00p02n01i01157ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 5) of BOOLEAN;
+    type R1 is record
+                 RE1: REAL;
+                 RE2: A1;
+               end record;
+    variable V: R1;
+    variable k : integer := 0;
+  BEGIN
+    if V.RE2'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01157"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01157 - The prefix of an attribute name may be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd
new file mode 100644
index 0000000..a2ba4a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1159.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01159ent IS
+END c06s06b00x00p02n01i01159ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01159arch OF c06s06b00x00p02n01i01159ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array(0 to 50) of boolean;
+
+    function ret_arr(I : integer) return arr is
+      variable RA : arr ;
+    begin
+      return  RA;
+    end ret_arr;
+    variable k : integer := 0;
+  BEGIN
+    k := arr'low;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01159"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01159 - The prefix of an attribute name may be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd
new file mode 100644
index 0000000..f89f798
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc116.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00116ent IS
+END c04s03b02x00p29n10i00116ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00116arch OF c04s03b02x00p29n10i00116ent IS
+
+  PROCEDURE p1 ( prm_inout : INOUT INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_inout : VARIABLE IS 300;
+  BEGIN
+    ASSERT prm_inout'attr1 = 300 REPORT "ERROR: Bad value for prm_inout'attr1" SEVERITY FAILURE;
+    assert NOT(   prm_inout'attr1 = 300 ) 
+      report "***PASSED TEST: c04s03b02x00p29n10i00116"
+      severity NOTE;
+    assert (   prm_inout'attr1 = 300 ) 
+      report "***FAILED TEST: c04s03b02x00p29n10i00116 - Interface object attribute reading in a subprogram test failed."
+      severity ERROR;
+  END;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE tmp : INTEGER;
+  BEGIN
+--
+    p1 ( tmp );
+--
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00116arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd
new file mode 100644
index 0000000..74f6d22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1164.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01164pkg is
+  type A1 is array (1 to 2) of BOOLEAN;
+  type A2 is array (1 to 2) of A1;
+end c06s06b00x00p02n01i01164pkg;
+
+use work.c06s06b00x00p02n01i01164pkg.all;
+
+ENTITY c06s06b00x00p02n01i01164ent IS
+  port      (PT: A2);
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01164ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01164arch OF c06s06b00x00p02n01i01164ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01164"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01164 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd
new file mode 100644
index 0000000..585888d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1165.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01165ent IS
+END c06s06b00x00p02n01i01165ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01165arch OF c06s06b00x00p02n01i01165ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type A2 is array (1 to 2) of A1;
+    variable V : A2;
+    variable k : integer := 0;
+  BEGIN
+    if V(1)'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01165"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01165 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd
new file mode 100644
index 0000000..6ae1ccc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1166.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01166ent IS
+END c06s06b00x00p02n01i01166ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01166arch OF c06s06b00x00p02n01i01166ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type A2 is array (1 to 2) of A1;
+    variable V : A2;
+    variable k : integer := 0;
+  BEGIN
+    if V(1)'HIGH = 2 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01166"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01166 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd
new file mode 100644
index 0000000..fbb1bc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1167.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p04n02i01167ent IS
+END c06s06b00x00p04n02i01167ent;
+
+ARCHITECTURE c06s06b00x00p04n02i01167arch OF c06s06b00x00p04n02i01167ent IS
+  attribute p: POSITIVE;
+  signal    s: integer;
+  attribute p of s: signal is 10;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if s'p = 10 then  -- Success_here
+      s <=  12;
+    else
+      s <= 0;
+    end if;
+    wait for 10 ns;
+    assert NOT( s=12 )
+      report "***PASSED TEST: c06s06b00x00p04n02i01167"
+      severity NOTE;
+    assert ( s=12 )
+      report "***FAILED TEST: c06s06b00x00p04n02i01167 - The meaning of the prefix of an attribute must be determinable independently of the attribute designator and independently of the fact that it is the prefix of an attribute."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p04n02i01167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd
new file mode 100644
index 0000000..d9c943c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00117pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00117pkg;
+
+use work.c04s03b02x00p29n10i00117pkg.all;
+ENTITY c04s03b02x00p29n10i00117ent IS
+  port (
+    p23 : buffer Boolean        := FALSE;
+    p24 : buffer Bit            := '0'  ;
+    p25 : buffer Character      := NUL  ;
+    p26 : buffer SEVERITY_LEVEL := NOTE ;
+    p27 : buffer Integer        := -1   ;
+    p28 : buffer Real           := -1.0 ;
+    p29 : buffer TIME           := 1 fs ;
+    p30 : buffer Natural        := 0    ;
+    p31 : buffer Positive       := 1    ;
+    p32 : buffer Apollo_string  :=  "abcdefgh";
+    p33 : buffer V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00117ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00117arch OF c04s03b02x00p29n10i00117ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    p23 = FALSE   and
+                   p24 = '0'     and 
+                   p25 = NUL     and 
+                   p26 = NOTE    and 
+                   p27 = -1      and 
+                   p28 = -1.0    and 
+                   p29 = 1 fs    and 
+                   p30 = 0       and 
+                   p31 = 1       and 
+                   p32 = "abcdefgh"and
+                   p33 = B"10010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00117"
+      severity NOTE;
+    assert (    p23 = FALSE   and
+                p24 = '0'     and 
+                p25 = NUL     and 
+                p26 = NOTE    and 
+                p27 = -1      and 
+                p28 = -1.0    and 
+                p29 = 1 fs    and 
+                p30 = 0       and 
+                p31 = 1       and 
+                p32 = "abcdefgh"and
+                p33 = B"10010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00117 - The buffer ports on entities should be able to read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd
new file mode 100644
index 0000000..0ae0eaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1174.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01174ent IS
+END c06s06b00x00p06n01i01174ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01174arch OF c06s06b00x00p06n01i01174ent IS
+  signal    POS : Integer;
+  attribute PIO : positive;
+  attribute PIO of POS : signal is 10; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT(POS'PIO = 10) 
+      report "***PASSED TEST: c06s06b00x00p06n01i01174" 
+      severity NOTE;
+    assert (POS'PIO = 10) 
+      report "***FAILED TEST: c06s06b00x00p06n01i01174 - If the attribute designator does not denote a predefined attribute, the static expression in the attribute name must not be present."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd
new file mode 100644
index 0000000..b502e4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1175.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01175ent IS
+END c08s00b00x00p01n02i01175ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01175arch OF c08s00b00x00p01n02i01175ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 0;
+    variable b : integer := 1;
+  BEGIN
+    LP1 : for i in 1 to 10 loop
+      a := a + 1; 
+    end loop;
+
+    if a = 10 then
+      b := 10;
+    elsif a = 0 then
+      b := 0;
+    else
+      b := 5;
+    end if;
+
+    assert NOT( (a=10) and (b=10) )
+      report "***PASSED TEST: c08s00b00x00p01n02i01175"
+      severity NOTE;
+    assert ( (a=10) and (b=10) )
+      report "***FAILED TEST: c08s00b00x00p01n02i01175 - Sequential statements are permitted in a sequence of statements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd
new file mode 100644
index 0000000..c483172
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01176ent IS
+END c08s00b00x00p01n02i01176ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
+  signal k : integer := 0;
+BEGIN
+  L1 : process
+  begin
+    k <= 5;
+    wait for 1 ns;
+  end process L1;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(k = 5) 
+      report "***PASSED TEST: c08s00b00x00p01n02i01176"
+      severity NOTE;
+    assert (k = 5) 
+      report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd
new file mode 100644
index 0000000..c1ac855
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1177.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01177ent IS
+END c08s00b00x00p01n02i01177ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01177arch OF c08s00b00x00p01n02i01177ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if FALSE = FALSE then
+    end if;
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s00b00x00p01n02i01177"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s00b00x00p01n02i01177 - Empty sequence of statement is permitted in 'if statement'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd
new file mode 100644
index 0000000..d8c269f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1178.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01178ent IS
+END c08s00b00x00p01n02i01178ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01178arch OF c08s00b00x00p01n02i01178ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    case TRUE is
+      when TRUE   =>
+      when FALSE   =>
+    end case;
+    assert FALSE 
+      report "***PASSED TEST: c08s00b00x00p01n02i01178"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd
new file mode 100644
index 0000000..98b9b21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1179.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01179ent IS
+END c08s00b00x00p01n02i01179ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01179arch OF c08s00b00x00p01n02i01179ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in FALSE to TRUE loop
+    end loop;
+    assert FALSE 
+      report "***PASSED TEST: c08s00b00x00p01n02i01179"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd
new file mode 100644
index 0000000..4984bac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc118.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00118pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00118pkg;
+
+use work.c04s03b02x00p29n10i00118pkg.all;
+ENTITY c04s03b02x00p29n10i00118ent IS
+  port (
+    p23 : buffer Boolean        := FALSE;
+    p24 : buffer Bit            := '0'  ;
+    p25 : buffer Character      := NUL  ;
+    p26 : buffer SEVERITY_LEVEL := NOTE ;
+    p27 : buffer Integer        := -1   ;
+    p28 : buffer Real           := -1.0 ;
+    p29 : buffer TIME           := 1 ns ;
+    p30 : buffer Natural        := 0    ;
+    p31 : buffer Positive       := 1    ;
+    p32 : buffer Apollo_string  :=  "abcdefgh";
+    p33 : buffer V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00118ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00118arch OF c04s03b02x00p29n10i00118ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    p23  <= not p23 AFTER 10 ns;
+    p24  <= not p24 AFTER 10 ns;
+
+    if (p25 /= character'high) then
+      p25  <= character'succ (p25) AFTER 10 ns;
+    else
+      p25  <= character'low  AFTER 10 ns;
+    end if;
+    
+    if (p26 /= severity_level'high) then
+      p26  <= severity_level'succ(p26) AFTER 10 ns;
+    else
+      p26  <= severity_level'low  AFTER 10 ns;
+    end if;
+    
+    p27  <= integer'succ(p27) AFTER 10 ns; -- unlikely to overflow....
+    p28  <= p28 + 1.0 AFTER 10 ns;
+    p29  <= p29 * 2 AFTER 10 ns;
+    p30  <= p30 + 1 AFTER 10 ns;
+    p31  <= p31 * 2 AFTER 10 ns;
+    p32(2) <= character'succ (p32(2)) AFTER 10 ns;
+    p33(1) <= not p33(1) AFTER 10 ns;
+
+    WAIT ON p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33;
+
+    assert NOT(    p23 = TRUE   and
+                   p24 = '1'     and 
+                   p25 = SOH     and 
+                   p26 = WARNING    and 
+                   p27 = 0      and 
+                   p28 = 0.0    and 
+                   p29 = 2 ns    and 
+                   p30 = 1       and 
+                   p31 = 2       and 
+                   p32 = "accdefgh"and
+                   p33 = B"11010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00118"      severity NOTE;
+    assert (    p23 = TRUE   and
+                p24 = '1'     and 
+                p25 = SOH     and 
+                p26 = WARNING    and 
+                p27 = 0      and 
+                p28 = 0.0    and 
+                p29 = 2 ns    and 
+                p30 = 1       and 
+                p31 = 2       and 
+                p32 = "accdefgh"and
+                p33 = B"11010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00118 - The buffer ports on entities should be able to read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00118arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd
new file mode 100644
index 0000000..b8ddcac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1180.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p02n01i01180ent IS
+END c08s00b00x00p02n01i01180ent;
+
+ARCHITECTURE c08s00b00x00p02n01i01180arch OF c08s00b00x00p02n01i01180ent IS
+BEGIN
+  TESTING: PROCESS
+    procedure check (x : out boolean) is
+    begin
+      x := false;   
+    end;
+    variable k : boolean;
+  BEGIN
+    check (k);
+    assert NOT( k=false )
+      report "***PASSED TEST: c08s00b00x00p02n01i01180"
+      severity NOTE;
+    assert ( k=false )
+      report "***FAILED TEST: c08s00b00x00p02n01i01180 - Procedure call is a sequential statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p02n01i01180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd
new file mode 100644
index 0000000..89dab97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1182.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p01n01i01182ent IS
+END c08s01b00x00p01n01i01182ent;
+
+ARCHITECTURE c08s01b00x00p01n01i01182arch OF c08s01b00x00p01n01i01182ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : time := 0 ns;
+  BEGIN
+    k := now;
+    wait for 5 ns;
+    k := now - k;
+    assert NOT( k=5 ns )
+      report "***PASSED TEST: c08s01b00x00p01n01i01182"
+      severity NOTE;
+    assert ( k=5  ns)
+      report "***FAILED TEST: c08s01b00x00p01n01i01182 - A wait statement cause the suspension of the process statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p01n01i01182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd
new file mode 100644
index 0000000..99b90e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p02n01i01183ent IS
+END c08s01b00x00p02n01i01183ent;
+
+ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c08s01b00x00p02n01i01183"
+      severity NOTE;
+    wait;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c08s01b00x00p02n01i01183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd
new file mode 100644
index 0000000..46263fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1187.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01187ent IS
+END c08s01b00x00p03n01i01187ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01187arch OF c08s01b00x00p03n01i01187ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on k;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p03n01i01187"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c08s01b00x00p03n01i01187 - In wait statement, the reserved word 'on' followed by one or more signal names separated with commas(,)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd
new file mode 100644
index 0000000..c09d028
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc119.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00119ent IS
+  port ( prt_buffer : BUFFER INTEGER );
+
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF prt_buffer : SIGNAL   IS 200;
+END c04s03b02x00p29n10i00119ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00119arch OF c04s03b02x00p29n10i00119ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT prt_buffer'attr1 = 200 REPORT "ERROR: Bad value for prt_buffer'attr1" SEVERITY FAILURE;
+    assert NOT(   prt_buffer'attr1 = 200 ) 
+      report "***PASSED TEST: c04s03b02x00p29n10i00119"
+      severity NOTE;
+    assert (   prt_buffer'attr1 = 200 ) 
+      report "***FAILED TEST: c04s03b02x00p29n10i00119 - Reading the attributes of the interface object of buffer test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd
new file mode 100644
index 0000000..76ff5c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1192.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01192ent IS
+END c08s01b00x00p03n01i01192ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01192arch OF c08s01b00x00p03n01i01192ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on k, k, k;
+    assert NOT(k=5)
+      report "***PASSED TEST: c08s01b00x00p03n01i01192" 
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c08s01b00x00p03n01i01192 - Same signal multiple times. This is not made clearly in LRM" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd
new file mode 100644
index 0000000..926ba21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1197.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01197ent IS
+END c08s01b00x00p05n01i01197ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01197arch OF c08s01b00x00p05n01i01197ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait on k until (k=5); 
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p05n01i01197"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p05n01i01197 - In the wait statement, the reserved word 'until' is followed by a boolean statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd
new file mode 100644
index 0000000..72f1d42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1199.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p07n01i01199ent IS
+END c08s01b00x00p07n01i01199ent;
+
+ARCHITECTURE c08s01b00x00p07n01i01199arch OF c08s01b00x00p07n01i01199ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait for 70 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p07n01i01199"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p07n01i01199 - In timeout clause, the reserved word 'for' is followed by a time expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p07n01i01199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd
new file mode 100644
index 0000000..ed14023
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd
@@ -0,0 +1,192 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1205.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p08n03i01205pkg is
+  
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+  
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p08n03i01205pkg;
+
+package body c08s01b00x00p08n03i01205pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+    
+  begin
+    return( S(1) );
+  end switchf;
+  
+end c08s01b00x00p08n03i01205pkg;
+
+
+
+use work.c08s01b00x00p08n03i01205pkg.all;
+entity c08s01b00x00p08n03i01205ent_a is
+  
+  generic ( GenOne : in INTEGER ; GenTwo :INTEGER);
+  
+end c08s01b00x00p08n03i01205ent_a;
+
+-------------------------------------------------------------------------
+
+architecture c08s01b00x00p08n03i01205arch_a of c08s01b00x00p08n03i01205ent_a is
+  -- Type definitions.
+  type WORD2 is array( 0 to 31 ) of SWITCH_LEVEL;
+  
+  -- Local signals.
+  signal A, B    : WORD;
+  signal UnResolved    : WORD2;
+  
+  
+begin
+  
+  TEST_PROCESS:  process
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+
+    variable k    : integer := 0;
+    
+  begin
+    -- Test locally static signals.
+    A( 1 ) <= 'X' after 10 ns;
+    A( 2 ) <= 'X' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(1);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(1) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    if (A(1) /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but with a constant.
+    A( One ) <= '1' after 10 ns;
+    A( Two ) <= '1' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(One);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(One) = '1');
+    assert (ShouldBeTime = NOW);
+
+    if (A(One) /= '1' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but with a generic.   (globally static)
+    A( GenOne ) <= 'X' after 10 ns;
+    A( GenTwo ) <= 'X' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(GenOne);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(GenOne) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    if (A(GenOne) /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but assigning to the whole thing.
+    A <= ('1','1','1','1','1','1','1','1','1','1',
+          '1','1','1','1','1','1','1','1','1','1',
+          '1','1','1','1','1','1','1','1','1','1',
+          '1','1') after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(GenOne);
+    
+    -- Should wake up when the all assignments take place.
+    assert (A(GenOne) = '1');
+    assert (ShouldBeTime = NOW);
+
+    if (A(GenOne) /= '1' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Now, perform same test but assigning to a composite
+    -- signal which is NOT resolved at the scalar subelement
+    -- level.
+    UnResolved <= ('1','1','1','1','1','1','1','1','1','1',
+                   '1','1','1','1','1','1','1','1','1','1',
+                   '1','1','1','1','1','1','1','1','1','1',
+                   '1','1') after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on UnResolved(GenOne);
+    
+    -- Should wake up when the all assignments take place.
+    assert (UnResolved(GenOne) = '1');
+    assert (ShouldBeTime = NOW);
+    
+    if (UnResolved(GenOne) /= '1' and ShouldBeTime /= Now) then
+      k := 1;   
+    end if;
+    
+    assert NOT(k = 0) 
+      report "***PASSED TEST: c08s01b00x00p08n03i01205" 
+      severity NOTE;
+    assert (k = 0) 
+      report "***FAILED TEST: c08s01b00x00p08n03i01205 - All statically indexed signal names (both locally and globally static) may be used in the sensitivity clause of a wait statement." 
+      severity ERROR;
+    wait;
+  end process TEST_PROCESS;
+  
+end c08s01b00x00p08n03i01205arch_a;
+
+use work.c08s01b00x00p08n03i01205pkg.all;
+ENTITY c08s01b00x00p08n03i01205ent IS
+END c08s01b00x00p08n03i01205ent;
+
+ARCHITECTURE c08s01b00x00p08n03i01205arch OF c08s01b00x00p08n03i01205ent IS
+  
+  component c08s01b00x00p08n03i01205ent_a
+    generic( GenOne : in INTEGER;  GenTwo : INTEGER );
+  end component;
+  for T1 : c08s01b00x00p08n03i01205ent_a use entity work.c08s01b00x00p08n03i01205ent_a(c08s01b00x00p08n03i01205arch_a); 
+
+BEGIN
+
+  T1 : c08s01b00x00p08n03i01205ent_a generic map ( 1, 2 );
+
+END c08s01b00x00p08n03i01205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd
new file mode 100644
index 0000000..d9d1f10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1206.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p08n04i01206ent IS
+END c08s01b00x00p08n04i01206ent;
+
+ARCHITECTURE c08s01b00x00p08n04i01206arch OF c08s01b00x00p08n04i01206ent IS
+  signal cll : integer := 0;
+  signal del : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    cll   <= 5 after 55 ns;
+    del   <= 5 after 55 ns;   
+    wait until (cll = 5 or  del = 5);
+    assert NOT( cll=5 )
+      report "***PASSED TEST: c08s01b00x00p08n04i01206"
+      severity NOTE;
+    assert ( cll=5 )
+      report "***FAILED TEST: c08s01b00x00p08n04i01206 - if no sensitivity clause appears, the sensitivity set will contain the signals denoted by the longest static prefix of each signal name that appears as a primary in the condition of the condirion clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n04i01206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd
new file mode 100644
index 0000000..b639ef3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1207.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p08n04i01207pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p08n04i01207pkg;
+
+package body c08s01b00x00p08n04i01207pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c08s01b00x00p08n04i01207pkg;
+
+use work.c08s01b00x00p08n04i01207pkg.all;
+ENTITY c08s01b00x00p08n04i01207ent IS
+END c08s01b00x00p08n04i01207ent;
+
+ARCHITECTURE c08s01b00x00p08n04i01207arch OF c08s01b00x00p08n04i01207ent IS
+
+  -- Local types.
+  type WORD2 is array(0 to 31) of SWITCH_LEVEL;
+  
+  -- Local signals.
+  signal A, B    : WORD;
+  signal UnResolved    : WORD2;
+
+BEGIN
+  TESTING: PROCESS
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+    variable k        : integer := 0;
+  BEGIN
+    -- 1. Test waiting on static signals.
+    for I in 0 to 31 loop
+      A( I ) <= 'X' after (I * 1 ns);
+    end loop;
+    ShouldBeTime := NOW + 31 ns;
+    wait until (A(31) = 'X');
+    
+    -- Should wake up when the A(31) assignment takes place.
+    if (A(31) /= 'X' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (A(31) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    -- 2. Test waiting on non-static signals.  (should still have same behavior, but just be slower)
+    for I in 0 to 31 loop
+      A( I ) <= '1' after (I * 1 ns);
+    end loop;
+    ShouldBeTime := NOW + 31 ns;
+    I := 31;
+    wait until (A(I) = '1');
+    
+    -- Should wake up when the A(31) assignment takes place.
+    if (A(I) /= '1' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (A(I) = '1');
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Test that waiting on a variable expression merely times-out. 
+    ShouldBeTime := NOW + 35 ns;
+    wait until (I = 47) for 35 ns;
+    if (ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Perform same test as '1' on a signal not resolved at the scalar subelement level.
+    UnResolved <= ( 'X','X','X','X','X','X','X','X','X','X',
+                    'X','X','X','X','X','X','X','X','X','X',
+                    'X','X','X','X','X','X','X','X','X','X',
+                    'X','X' ) after 31 ns;
+    ShouldBeTime := NOW + 31 ns;
+    wait until (UnResolved(31) = 'X');
+    
+    -- Should wake up when the UnResolved(31) assignment takes place.
+    if (UnResolved(31) /= 'X' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (UnResolved(31) = 'X');
+    assert (ShouldBeTime = NOW);
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s01b00x00p08n04i01207"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s01b00x00p08n04i01207 - The sensitivity set of a wait statement will contain the signal denoted by the longest static prefix of each signal name if no sensitivity clause." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n04i01207arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd
new file mode 100644
index 0000000..691c892
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1208.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p24n01i01208ent IS
+END c08s01b00x00p24n01i01208ent;
+
+ARCHITECTURE c08s01b00x00p24n01i01208arch OF c08s01b00x00p24n01i01208ent IS
+  type    WOR is array (0 to 3) of BIT;
+  signal   TS   : WOR := "0000";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    TS <= "0101" after 20 ns;
+    wait on TS until (TS(1) = '1');
+    assert NOT( TS(1) = '1' )
+      report "***PASSED TEST: c08s01b00x00p24n01i01208"
+      severity NOTE;
+    assert ( TS(1) = '1' )
+      report "***FAILED TEST: c08s01b00x00p24n01i01208 - Composite signal in teh sensitivity list of the wait statement is equivalent to having each subelement of that composite signal in the list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p24n01i01208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd
new file mode 100644
index 0000000..6ddbec4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1209.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p24n01i01209pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p24n01i01209pkg;
+
+package body c08s01b00x00p24n01i01209pkg is
+
+-- A dumb resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c08s01b00x00p24n01i01209pkg;
+
+
+use work.c08s01b00x00p24n01i01209pkg.all;
+ENTITY c08s01b00x00p24n01i01209ent IS
+END c08s01b00x00p24n01i01209ent;
+
+ARCHITECTURE c08s01b00x00p24n01i01209arch OF c08s01b00x00p24n01i01209ent IS
+
+  -- Local types
+  type WORD2 is array(0 to 31) of SWITCH_LEVEL;
+  type REC   is RECORD
+                  R1    : SWITCH_T;
+                  R2    : SWITCH_T;
+                end RECORD;
+  
+  -- Local signals.
+  signal A : WORD;
+  signal UnResolved : WORD2;
+  signal RecSig     : REC;
+  
+BEGIN
+  TESTING: PROCESS
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+    variable   k    : integer := 0;
+
+
+  BEGIN
+    --1. Test waiting on an array of scalar resolved elements.
+    for I in 0 to 31 loop
+      ShouldBeTime := NOW + 1 ns;
+      A( I ) <= 'X' after 1 ns;
+      wait on A;
+      if (A(I) /= 'X' and ShouldBeTime /= Now) then
+        k := 1;
+      end if; 
+      -- Verify that we waited the right amount of time.
+      assert (ShouldBeTime = NOW);
+      assert (A( I ) = 'X');
+    end loop;
+    
+    -- 2. Test waiting on an array of scalar unresolved elements.
+    ShouldBeTime := NOW + 1 ns;
+    UnResolved <= ( '1','1','1','1','1','1','1','1','1','1',
+                    '1','1','1','1','1','1','1','1','1','1',
+                    '1','1','1','1','1','1','1','1','1','1',
+                    '1','1' ) after 1 ns;
+    wait on UnResolved;
+    if (UnResolved /= ( '1','1','1','1','1','1','1','1','1','1',
+                        '1','1','1','1','1','1','1','1','1','1',
+                        '1','1','1','1','1','1','1','1','1','1',
+                        '1','1' )  and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    -- Verify that we waited allright.
+    assert (ShouldBeTime = NOW);
+    for I in 0 to 31 loop
+      assert ( UnResolved( I ) = '1');
+    end loop;
+    
+    -- 3. Test waiting on a record.
+    RECSIG.R1 <= 'X' after 1 ns;
+    RECSIG.R2 <= 'X' after 2 ns;
+    ShouldBeTime := NOW + 1 ns;
+    wait on RECSIG;
+    if (RECSIG.R1 /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.R1 = 'X');
+    ShouldBeTime := NOW + 1 ns;
+    wait on RECSIG;
+    if (RECSIG.R2 /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.R2 = 'X');
+
+    assert NOT( k=0 ) 
+      report "***PASSED TEST: c08s01b00x00p24n01i01209"
+      severity NOTE;
+    assert ( k=0 ) 
+      report "***FAILED TEST: c08s01b00x00p24n01i01209 - The effect of a signal name denotes a signal of a composite type is as if name of each scalar subelement of that signal appears in the list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p24n01i01209arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd
new file mode 100644
index 0000000..4d7ed36
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1210.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n01i01210ent IS
+END c08s01b00x00p25n01i01210ent;
+
+ARCHITECTURE c08s01b00x00p25n01i01210arch OF c08s01b00x00p25n01i01210ent IS
+  signal T1 : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    T1 <= '1' after 15 ns;
+    wait on T1 until (T1 = '1');
+    assert NOT( T1 = '1' )
+      report "***PASSED TEST: c08s01b00x00p25n01i01210"
+      severity NOTE;
+    assert ( T1 = '1' )
+      report "***FAILED TEST: c08s01b00x00p25n01i01210 - Process resumes execution when the condition clause in a wait statement is met"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n01i01210arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd
new file mode 100644
index 0000000..d8e2a73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1211.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n01i01211ent IS
+END c08s01b00x00p25n01i01211ent;
+
+ARCHITECTURE c08s01b00x00p25n01i01211arch OF c08s01b00x00p25n01i01211ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- Check a condition clause that is NEVER true.
+    -- Should suspend until the timeout_clause is reached.
+    A <= '1' after 1 ns;
+    ShouldBeTime := NOW + 20 ns;
+    wait on A until (FALSE) for 20 ns;
+    assert NOT(ShouldBeTime = NOW)
+      report "***PASSED TEST: c08s01b00x00p25n01i01211"
+      severity NOTE;
+    assert (ShouldBeTime = NOW)
+      report "***FAILED TEST: c08s01b00x00p25n01i01211 - If the condition specified by the condition clause is FALSE, the wait statement will suspend itself again." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n01i01211arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd
new file mode 100644
index 0000000..833a3ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1212.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n02i01212ent IS
+END c08s01b00x00p25n02i01212ent;
+
+ARCHITECTURE c08s01b00x00p25n02i01212arch OF c08s01b00x00p25n02i01212ent IS
+  signal I : bit := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    I <= '1' after 10 ns;
+    wait on I;
+    assert NOT( I = '1' )
+      report "***PASSED TEST: c08s01b00x00p25n02i01212"
+      severity NOTE;
+    assert ( I = '1' )
+      report "***FAILED TEST: c08s01b00x00p25n02i01212 - The condition clause assumes the default value TRUE when no condition clause is present."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n02i01212arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd
new file mode 100644
index 0000000..8c590fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1213.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n02i01213ent IS
+END c08s01b00x00p25n02i01213ent;
+
+ARCHITECTURE c08s01b00x00p25n02i01213arch OF c08s01b00x00p25n02i01213ent IS
+  signal   A : BIT;
+BEGIN
+  TESTING: PROCESS
+    variable   ShouldBeTime : TIME;
+  BEGIN
+    A <= '1' after 1 ns;
+    ShouldBeTime := NOW + 1 ns;
+    wait on A for 20 ns;
+    assert NOT(ShouldBeTime = NOW) 
+      report "***PASSED TEST: c08s01b00x00p25n02i01213"
+      severity NOTE;
+    assert (ShouldBeTime = NOW) 
+      report "***FAILED TEST: c08s01b00x00p25n02i01213 - When NO condition_clause is present, the condition clause 'until TRUE' is assumed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n02i01213arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd
new file mode 100644
index 0000000..a01e7c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1214.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n01i01214ent IS
+END c08s01b00x00p26n01i01214ent;
+
+ARCHITECTURE c08s01b00x00p26n01i01214arch OF c08s01b00x00p26n01i01214ent IS
+  signal sig1 : integer;
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+    variable y : time    := 0 ns;
+  BEGIN
+    y := now;
+    wait on sig1 until x >= 12 for 20 ns;
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p26n01i01214"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p26n01i01214 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n01i01214arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd
new file mode 100644
index 0000000..fe98b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1215.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n01i01215ent IS
+END c08s01b00x00p26n01i01215ent;
+
+ARCHITECTURE c08s01b00x00p26n01i01215arch OF c08s01b00x00p26n01i01215ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k      : integer := 0;
+  BEGIN
+    -- Given that a particular condition will never be TRUE,
+    -- verify that we always wait for the desired amount of time.
+    for I in 0 to 100 loop
+      -- Perform the assignment.
+      if  ((I mod 2) = 0) then
+        A <= '1' after 1 ns;
+      else
+        A <= '0' after 1 ns;
+      end if;
+
+      -- Compute the time we should end the wait statement.
+      ShouldBeTime := NOW + 2 ns;
+
+      -- Wait the desired amount of time.  Note that the condition
+      -- will never be TRUE.
+      if  ((I mod 2) = 0) then
+        wait until (A = '0') for 2 ns;
+      else
+        wait until (A = '1') for 2 ns;
+      end if;
+      
+      -- Assert that we ended on time.
+      assert (ShouldBeTime = NOW);
+      if (ShouldBeTime /= NOW) then
+        k := 1;
+      end if;
+    end loop;
+    assert NOT(k=0)
+      report "***PASSED TEST: c08s01b00x00p26n01i01215"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s01b00x00p26n01i01215 - The timeout clause specifies the maximum amount of time the process will remain suspended at this wait statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n01i01215arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd
new file mode 100644
index 0000000..a9d5242
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n02i01216ent IS
+END c08s01b00x00p26n02i01216ent;
+
+ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
+  signal   A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+  BEGIN
+    -- First, wait for 1fs;
+    wait for 1 fs;
+
+    assert FALSE
+      report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
+      severity NOTE;
+    -- Then, wait until the end of time.
+    wait;
+    assert (FALSE)
+      report "Should never have executed this statement."  
+      severity FAILURE;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n02i01216arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd
new file mode 100644
index 0000000..280e593
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1218.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n03i01218ent IS
+END c08s01b00x00p26n03i01218ent;
+
+ARCHITECTURE c08s01b00x00p26n03i01218arch OF c08s01b00x00p26n03i01218ent IS
+  signal I : bit := '0';
+BEGIN
+  TESTING: PROCESS
+    constant t1 : time := 100 ns;
+    constant t2 : time := 10 ns;
+  BEGIN
+    I <= '1' after 200 ns;
+    wait on I for (t1 - t2);
+    assert NOT( I = '0' ) 
+      report "***PASSED TEST: c08s01b00x00p26n03i01218" 
+      severity NOTE;
+    assert ( I = '0' ) 
+      report "***FAILED TEST: c08s01b00x00p26n03i01218 - The FOR clause in a WAIT statement must evaluate to a positive value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n03i01218arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd
new file mode 100644
index 0000000..5158f61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1220.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01220ent IS
+END c08s01b00x00p27n01i01220ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01220arch OF c08s01b00x00p27n01i01220ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable y : time := 0 ns;
+  BEGIN
+    y := now;
+    wait for 20 ns;
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p27n01i01220"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p27n01i01220 - The suspended process does not resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01220arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd
new file mode 100644
index 0000000..da664a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1221.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01221ent IS
+END c08s01b00x00p27n01i01221ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01221arch OF c08s01b00x00p27n01i01221ent IS
+  signal  k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable y : time := 0 ns;
+  BEGIN
+    y := now;
+    k <= transport 5 after 20 ns;
+    wait until k = 5; 
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p27n01i01221"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p27n01i01221 - The suspended process does not resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01221arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd
new file mode 100644
index 0000000..c02f59d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1222.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01222ent IS
+END c08s01b00x00p27n01i01222ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01222arch OF c08s01b00x00p27n01i01222ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k       : integer := 0;
+  BEGIN
+    -- Assign same value to a signal.  Verify that the wait statement waits for the timeout interval.
+    ShouldBeTime := NOW + 3 ns;
+    A <= A after 2 ns;
+    wait until (A = '1') for 3 ns;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    -- Assign same value to a signal.  Verify that the wait statement waits for the timeout interval.
+    ShouldBeTime := NOW + 3 ns;
+    A <= A after 2 ns;
+    wait on A for 3 ns;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s01b00x00p27n01i01222"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s01b00x00p27n01i01222 - The suspended process should resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01222arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd
new file mode 100644
index 0000000..fc8d0f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1223.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01223ent IS
+END c08s01b00x00p27n01i01223ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01223arch OF c08s01b00x00p27n01i01223ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    ShouldBeTime : time := 0 fs;
+  BEGIN
+    ShouldBeTime := NOW + 1 fs;
+    wait for 1 fs;
+    assert NOT(ShouldBeTime = NOW)
+      report "***PASSED TEST: c08s01b00x00p27n01i01223"
+      severity NOTE;
+    assert (ShouldBeTime = NOW)
+      report "***FAILED TEST: c08s01b00x00p27n01i01223 - The minimum waiting time test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01223arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd
new file mode 100644
index 0000000..fd52d9e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1224.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p28n01i01224ent IS
+END c08s01b00x00p28n01i01224ent;
+
+ARCHITECTURE c08s01b00x00p28n01i01224arch OF c08s01b00x00p28n01i01224ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 20 ns;
+    wait until (k = 5);
+    assert NOT( k=5 )
+      report "***PASSED TEST:c08s01b00x00p28n01i01224"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p28n01i01224 - The process will resume if the result of an event occuring on sentivity set is TRUE."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p28n01i01224arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd
new file mode 100644
index 0000000..c1a0f6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1225.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p28n01i01225ent IS
+END c08s01b00x00p28n01i01225ent;
+
+ARCHITECTURE c08s01b00x00p28n01i01225arch OF c08s01b00x00p28n01i01225ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k       : integer := 0;
+  BEGIN
+    -- Make sure it takes an EVENT to trigger the WAIT statement.
+    A <= A after 2 ns,           -- NOT an event.
+         (not A) after 4 ns;      -- an event.
+    ShouldBeTime := NOW + 4 ns;   -- Should wait for event.   
+    wait on A;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 4ns";
+
+    -- If the value of the condition is FALSE, resuspend.
+    -- If the value is TRUE, the process will resume.
+    A <= '1' after 2 ns,
+         '0' after 4 ns;
+
+    -- Make sure that we wait until the second one for
+    -- the following wait statement to resume.
+    ShouldBeTime := NOW + 4 ns;
+    wait until (A = '0');
+    if (ShouldBeTime /= Now and A /= '0') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 4ns";
+    assert (A = '0')
+      report "Did not assign the correct value.";
+    
+    -- Such resuspension does not involve the recalculation of the timeout interval.
+    -- If the value of the condition is FALSE, resuspend.
+    -- IF the value is TRUE, the process will resume.
+    A <= '1' after 2 ns,
+         '0' after 4 ns;
+    
+    -- Make sure that we wait until the second one for
+    -- the following wait statement to resume.
+    ShouldBeTime := NOW + 3 ns;
+    wait until (A = '0') for 3 ns;
+    if (ShouldBeTime /= Now and A /= '1') then
+      k := 1;   
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 3ns";
+    assert (A = '1')
+      report "Did not assign the correct value to A.";
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s01b00x00p28n01i01225"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s01b00x00p28n01i01225 - The process will resume if the result of an event occuring on sentivity set is TRUE."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p28n01i01225arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd
new file mode 100644
index 0000000..5fc1d79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1230.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01230ent IS
+END c08s02b00x00p03n01i01230ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01230arch OF c08s02b00x00p03n01i01230ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert true;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p03n01i01230"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01230arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd
new file mode 100644
index 0000000..baa98a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1232.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01232ent IS
+END c08s02b00x00p03n01i01232ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01232arch OF c08s02b00x00p03n01i01232ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean := TRUE;
+  BEGIN
+    k := FALSE;
+    assert k 
+      report "***PASSED TEST: c08s02b00x00p03n01i01232"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01232arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd
new file mode 100644
index 0000000..8d1f760
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1233.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01233ent IS
+END c08s02b00x00p03n01i01233ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01233arch OF c08s02b00x00p03n01i01233ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p03n01i01233"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01233arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd
new file mode 100644
index 0000000..7abfc5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1234.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01234ent IS
+END c08s02b00x00p03n01i01234ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01234arch OF c08s02b00x00p03n01i01234ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+  BEGIN
+    assert ((k+1) < (k-3)) 
+      report "***PASSED TEST: c08s02b00x00p03n01i01234" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01234arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd
new file mode 100644
index 0000000..51feb14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1256.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01256ent IS
+END c08s02b00x00p04n02i01256ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01256arch OF c08s02b00x00p04n02i01256ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Note"
+      severity NOTE;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01256"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01256arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd
new file mode 100644
index 0000000..c268592
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1257.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01257ent IS
+END c08s02b00x00p04n02i01257ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01257arch OF c08s02b00x00p04n02i01257ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Warning"
+      severity WARNING;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01257 - This test needed manual check to see WARNING assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01257arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd
new file mode 100644
index 0000000..bfef1c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1258.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01258ent IS
+END c08s02b00x00p04n02i01258ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01258arch OF c08s02b00x00p04n02i01258ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Error"
+      severity ERROR;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01258 - This test needed manual check to see ERROR assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd
new file mode 100644
index 0000000..f9b4a87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1259.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01259ent IS
+END c08s02b00x00p04n02i01259ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01259arch OF c08s02b00x00p04n02i01259ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Failure"
+      severity FAILURE;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01259 - This test needed manual check to see FAILURE assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01259arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd
new file mode 100644
index 0000000..890f409
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1260.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n01i01260ent IS
+END c08s02b00x00p05n01i01260ent;
+
+ARCHITECTURE c08s02b00x00p05n01i01260arch OF c08s02b00x00p05n01i01260ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      severity NOTE;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n01i01260 - This test needs manual check to make sure that default value for the message ""Assertion violation"" appears."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n01i01260arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd
new file mode 100644
index 0000000..fbd0f45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1261.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n01i01261ent IS
+END c08s02b00x00p05n01i01261ent;
+
+ARCHITECTURE c08s02b00x00p05n01i01261arch OF c08s02b00x00p05n01i01261ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    -- Print out the NOTE message:
+    assert (FALSE)
+      report "Verify that the following says 'Assertion violation'."
+      severity NOTE;
+
+    -- Print out the default message.
+    assert (FALSE)
+      severity WARNING;
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n01i01261 - This test needs manual check. Messages as NOTE: Verify that the following says 'Asserion violation' and WARNING: Assertion violation should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n01i01261arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd
new file mode 100644
index 0000000..ee7f720
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1262.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n03i01262ent IS
+END c08s02b00x00p05n03i01262ent;
+
+ARCHITECTURE c08s02b00x00p05n03i01262arch OF c08s02b00x00p05n03i01262ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+
+    assert FALSE
+      report "Report this string";
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n03i01262 - This test needs manual check to see that default value of the severity level is ERROR."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n03i01262arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd
new file mode 100644
index 0000000..cb53f88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1263.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n03i01263ent IS
+END c08s02b00x00p05n03i01263ent;
+
+ARCHITECTURE c08s02b00x00p05n03i01263arch OF c08s02b00x00p05n03i01263ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Print out the NOTE message:
+    assert (FALSE)
+      report "Verify that the following assertion violation is an error'."
+      severity NOTE;
+
+    -- Print out the default message and severity level.
+    assert (FALSE);
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n03i01263 - This test needs manual check. Messages NOTE: Verify that the following assertion violation is an error and ERROR: Assertion violation should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n03i01263arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd
new file mode 100644
index 0000000..ecf9e6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1265.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p06n01i01265ent IS
+END c08s02b00x00p06n01i01265ent;
+
+ARCHITECTURE c08s02b00x00p06n01i01265arch OF c08s02b00x00p06n01i01265ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable I : integer := 1;
+  BEGIN
+
+    assert (I=1);
+    assert TRUE
+      report "Report on the message"; 
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p06n01i01265 - This test needs manual check. No other assertion messages should occur except this."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p06n01i01265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd
new file mode 100644
index 0000000..317f6ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1266.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p06n03i01266ent IS
+END c08s02b00x00p06n03i01266ent;
+
+ARCHITECTURE c08s02b00x00p06n03i01266arch OF c08s02b00x00p06n03i01266ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+    variable y : severity_level; 
+  BEGIN
+
+    assert k = true
+      report "Assertion violation"
+      severity y;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p06n03i01266"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p06n03i01266arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd
new file mode 100644
index 0000000..3bfb3db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1267.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p07n01i01267ent IS
+END c08s02b00x00p07n01i01267ent;
+
+ARCHITECTURE c08s02b00x00p07n01i01267arch OF c08s02b00x00p07n01i01267ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p07n01i01267 - This test needs manual check. The assertion message consists at least that 1.An indication that this message is from an assertion. 2.Severity level. 3.Value of the message string. 4.The name of the design unit."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p07n01i01267arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd
new file mode 100644
index 0000000..21c9675
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1268.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p07n01i01268ent IS
+END c08s02b00x00p07n01i01268ent;
+
+ARCHITECTURE c08s02b00x00p07n01i01268arch OF c08s02b00x00p07n01i01268ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p07n01i01268 - This test needs manual check."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p07n01i01268arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd
new file mode 100644
index 0000000..ce0ba6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1269.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01269ent IS
+END c08s04b00x00p02n01i01269ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01269arch OF c08s04b00x00p02n01i01269ent IS
+  signal X1    : integer := 1;
+  signal X2    : integer := 2;
+  signal T1    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    T1   <= X1 + X2;
+    wait for 1 ns;
+    assert NOT(T1 = 3) 
+      report "***PASSED TEST: c08s04b00x00p02n01i01269"
+      severity NOTE;
+    assert (T1 = 3) 
+      report "***FAILED TEST: c08s04b00x00p02n01i01269 - Signal assignment statement consists of a target, a signal assignment operator"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01269arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd
new file mode 100644
index 0000000..f830c57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1292.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p05n01i01292ent IS
+END c08s04b00x00p05n01i01292ent;
+
+ARCHITECTURE c08s04b00x00p05n01i01292arch OF c08s04b00x00p05n01i01292ent IS
+  signal done : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    done <= 1 after 10 ns,
+            0 after 20 ns,
+            5 after 35 ns;
+    wait for 70 ns;
+    assert NOT( done=5 )
+      report "***PASSED TEST: c08s04b00x00p05n01i01292"
+      severity NOTE;
+    assert (done=5)
+      report "***FAILED TEST: c08s04b00x00p05n01i01292 - The waveform consists of one or more waveform elements separated with commas(,)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p05n01i01292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd
new file mode 100644
index 0000000..21b5324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1294.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01294ent IS
+END c08s04b00x00p06n01i01294ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01294arch OF c08s04b00x00p06n01i01294ent IS
+  type   BIT_VECTOR is array (integer range <>) of BIT;
+  signal DID : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 7) := B"01010101";
+  BEGIN
+    DID <= NUM1;
+    wait on  DID;
+    assert NOT( DID = B"01010101" )
+      report "***PASSED TEST: c08s04b00x00p06n01i01294"
+      severity NOTE;
+    assert ( DID = B"01010101" )
+      report "***FAILED TEST: c08s04b00x00p06n01i01294 - Type of the right hand and left hand side of the signal assignment statement must be the same"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd
new file mode 100644
index 0000000..d54df2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1299.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01299ent IS
+END c08s04b00x00p06n01i01299ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01299arch OF c08s04b00x00p06n01i01299ent IS
+  signal   X : integer := 5;
+  signal  Y : integer := 3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Y <= X;
+    wait for 1 ns;
+    assert NOT( Y=5 )  
+      report "***PASSED TEST: c08s04b00x00p06n01i01299"
+      severity NOTE;
+    assert ( Y=5 )  
+      report "***FAILED TEST: c08s04b00x00p06n01i01299 - Signal assignment in a process block." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd
new file mode 100644
index 0000000..6130a0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1306.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01306ent IS
+END c08s04b00x00p06n01i01306ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01306arch OF c08s04b00x00p06n01i01306ent IS
+  signal   S1 : BIT := '1';
+  type REC_1 is record
+                  RE_1:BIT;
+                  RE_2:INTEGER;
+                end record;
+  signal  S3 : REC_1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3.RE_1 <= S1;
+    wait for 1 ns;
+    assert NOT(S3.RE_1 = '1') 
+      report "***PASSED TEST: c08s04b00x00p06n01i01306" 
+      severity NOTE;
+    assert (S3.RE_1 = '1') 
+      report "***FAILED TEST: c08s04b00x00p06n01i01306 - A indexed name can be used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01306arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd
new file mode 100644
index 0000000..ad21b83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01307ent IS
+END c08s04b00x00p06n01i01307ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
+  type UA is array (NATURAL range <>) of BIT;
+  subtype ARAY_1 is UA (0 to 500);
+  signal  S2 : ARAY_1;
+  signal   S1 : BIT := '1';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2(200) <= S1;
+    wait for 1 ns;
+    assert NOT(S2(200) = '1') 
+      report "***PASSED TEST: c08s04b00x00p06n01i01307" 
+      severity NOTE;
+    assert (S2(200) = '1') 
+      report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01307arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd
new file mode 100644
index 0000000..1bf2b64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1309.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s04b00x00p07n01i01309pkg is
+
+  -- Type declarations.
+  subtype     BV2  is BIT_VECTOR( 0 to 1 );
+  subtype     CH2  is STRING( 1 to 2 );
+
+  -- Constant declarations.
+  constant BVC  : BV2 := B"00";
+  constant CHC  : CH2 := "bb";
+
+  -- Function returns BV2.
+  function  returnBV2 return BV2;
+
+  -- Function returns CH2.
+  function  returnCH2 return CH2;
+
+end c08s04b00x00p07n01i01309pkg;
+
+package body c08s04b00x00p07n01i01309pkg is
+  
+  -- Function returns BV2.
+  function  returnBV2 return BV2 is
+  begin
+    return ( BVC );
+  end returnBV2;
+  
+  -- Function returns CH2.
+  function  returnCH2 return CH2 is
+  begin
+    return( CHC );
+  end returnCH2;
+  
+end c08s04b00x00p07n01i01309pkg;
+
+use work.c08s04b00x00p07n01i01309pkg.all;
+ENTITY c08s04b00x00p07n01i01309ent IS
+END c08s04b00x00p07n01i01309ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01309arch OF c08s04b00x00p07n01i01309ent IS
+  -- Local signals.
+  signal S       : BIT;
+  signal T       : BIT;
+  
+  signal C1, C2  : CHARACTER;
+BEGIN
+  TESTING: PROCESS
+    
+    -- local variables
+    variable BITV     : BV2 := B"11";
+    variable STRV     : CH2 := "ab";
+    variable ShouldBeTime : TIME;
+    
+    variable k : integer := 0;
+    
+  BEGIN
+    -- Assign with a variable as the expression.
+    ( S, T )  <= BITV after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= BITV(0) or T /= BITV(1)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = BITV( 0 )) and (T = BITV( 1 )));
+    
+    ( C1,C2 ) <= STRV after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= STRV(1) or C2 /= STRV(2)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = STRV( 1 )) and (C2 = STRV( 2 )));
+    
+    -- Assign with a function return value.
+    ( S, T )  <= returnBV2 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= BVC(0) or T /= BVC(1)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = BVC( 0 )) and (T = BVC( 1 )));
+    
+    ( C1,C2 ) <= returnCH2 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= CHC(1) or C2 /= CHC(2)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = CHC( 1 )) and (C2 = CHC( 2 )));
+    
+    -- Assign with a qualified expression.
+    ( S, T )  <= BV2'( '0', '1' ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= '0' or T /= '1') then
+      k := 1;   
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = '0') and (T = '1'));
+    
+    ( C1,C2 ) <= CH2'( 'c', 'c' ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= 'c' or C2 /= 'c') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = 'c') and (C2 = 'c'));
+    
+    assert NOT( k = 0 ) 
+      report "***PASSED TEST: c08s04b00x00p07n01i01309"
+      severity NOTE;
+    assert ( k = 0 ) 
+      report "***FAILED TEST: c08s04b00x00p07n01i01309 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd
new file mode 100644
index 0000000..d6080cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc131.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n01i00131ent IS
+  generic ( constant c1 : integer := 9090 );
+END c04s03b02x01p04n01i00131ent;
+
+ARCHITECTURE c04s03b02x01p04n01i00131arch OF c04s03b02x01p04n01i00131ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c1 = 9090 ) 
+      report "***PASSED TEST: c04s03b02x01p04n01i00131" 
+      severity NOTE;
+    assert ( c1 = 9090 ) 
+      report "***FAILED TEST: c04s03b02x01p04n01i00131 - Constant declarations in generic interface list in generic interface list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n01i00131arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd
new file mode 100644
index 0000000..debcc8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1310.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n02i01310ent IS
+END c08s04b00x00p07n02i01310ent;
+
+ARCHITECTURE c08s04b00x00p07n02i01310arch OF c08s04b00x00p07n02i01310ent IS
+  type sigrec is
+    record
+      A1 : bit;
+      A2 : integer;
+      A3 : character;
+      A4 : boolean;
+    end record;
+  signal   S1 : bit;
+  signal   S2 : integer;
+  signal   S3 : character;
+  signal   S4 : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3, S4) <= sigrec'('1', 1, '1', true);
+    wait for 1 ns;
+    assert NOT( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
+      report "***PASSED TEST: c08s04b00x00p07n02i01310"
+      severity NOTE;
+    assert ( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
+      report "***FAILED TEST: c08s04b00x00p07n02i01310 - A waveform element on the rigth-hand side must be the same as the base type of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n02i01310arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd
new file mode 100644
index 0000000..f00af5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1316.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n04i01316ent IS
+END c08s04b00x00p07n04i01316ent;
+
+ARCHITECTURE c08s04b00x00p07n04i01316arch OF c08s04b00x00p07n04i01316ent IS
+  type sigrec is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : boolean;
+    end record;
+  signal S1 : bit;
+  signal S2 : integer;
+  signal S3 : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3) <= sigrec'('0',2,false);
+    wait for 10 ns;
+    assert NOT( (S1 = '0') and (S2 = 2) and (S3 = false) )
+      report "***PASSED TEST: c08s04b00x00p07n04i01316"
+      severity NOTE;
+    assert ( (S1 = '0') and (S2 = 2) and (S3 = false) )
+      report "***FAILED TEST: c08s04b00x00p07n04i01316 - Right hand side values are assigned to the drivers associated with the signal named as the corresponding subelement of the aggreate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n04i01316arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd
new file mode 100644
index 0000000..41bd148
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1317.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n01i01317ent IS
+END c08s04b00x00p07n01i01317ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01317arch OF c08s04b00x00p07n01i01317ent IS
+  signal s1, s2 : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+    type RT is
+      record
+        a : CHARACTER;
+        b : CHARACTER;
+      end record;
+
+    variable rv : RT := ('1', '2'); 
+  BEGIN
+    assert s1 = NUL;
+    assert s2 = NUL;
+    (s1, s2) <= rv;
+    wait on s1;
+    assert s1 = '1';
+    assert s2 = '2'; 
+    assert NOT( s1 = '1' and s2 = '2' )
+      report "***PASSED TEST:c08s04b00x00p07n01i01317"
+      severity NOTE;
+    assert ( s1 = '1' and s2 = '2' )
+      report "***FAILED TEST: c08s04b00x00p07n01i01317 - Aggregate (record type) signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01317arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd
new file mode 100644
index 0000000..6aaa5e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1318.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n01i01318ent IS
+END c08s04b00x00p07n01i01318ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01318arch OF c08s04b00x00p07n01i01318ent IS
+  signal s1, s2 : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+    type       AT is array (INTEGER range <>) of CHARACTER;
+    variable    av : AT(0 to 1) := ('1', '2');
+  BEGIN
+    assert s1 = NUL;
+    assert s2 = NUL;
+    (s1, s2) <= av;
+    wait on s1;
+    assert s1 = '1';
+    assert s2 = '2'; 
+    assert NOT( s1 = '1' and s2 = '2' )
+      report "***PASSED TEST: c08s04b00x00p07n01i01318" 
+      severity NOTE;
+    assert ( s1 = '1' and s2 = '2' )
+      report "***FAILED TEST: c08s04b00x00p07n01i01318 - Aggregate (array type) signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01318arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd
new file mode 100644
index 0000000..7f2c4ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1321.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p09n03i01321ent IS
+END c08s04b00x00p09n03i01321ent;
+
+ARCHITECTURE c08s04b00x00p09n03i01321arch OF c08s04b00x00p09n03i01321ent IS
+  signal S1 : BIT := '1';
+  signal S2 : BIT := '1';
+  signal S  : BIT := '1';
+BEGIN
+  S1 <= transport '0' after 5  ns,
+        '1' after 10 ns;
+  S2 <= transport S1  after 15 ns;
+  TEST : PROCESS(S2)
+    variable k : integer := 0;
+  BEGIN
+    if ((S2 = '0') and (NOW = 20 ns)) then   
+      k := 1;
+    end if;
+    if ((S2 = '1') and (NOW = 25 ns) and (k = 1)) then   
+      S <= '0' after 10 ns;
+    end if;
+  END PROCESS TEST;
+
+  TESTING: PROCESS(S)
+  BEGIN
+    if (NOW > 1 ns) then
+      assert NOT(S = '0') 
+        report "***PASSED TEST: c08s04b00x00p09n03i01321"
+        severity NOTE;
+      assert (S = '0')
+        report "***FAILED TEST: c08s04b00x00p09n03i01321 - Any pulse is transmitted, not matter how short its durtion"
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c08s04b00x00p09n03i01321arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd
new file mode 100644
index 0000000..0877699
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1322.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p09n04i01322ent IS
+END c08s04b00x00p09n04i01322ent;
+
+ARCHITECTURE c08s04b00x00p09n04i01322arch OF c08s04b00x00p09n04i01322ent IS
+  signal S1 : BIT := '1';
+  signal S2 : BIT := '1';
+BEGIN
+  S1 <= transport '0' after 5 ns,
+        '1' after 10 ns;
+  S2 <= S1 after 15 ns;
+  TESTING: PROCESS(S2)
+  BEGIN
+    assert NOT( S2 = '1' )
+      report "***PASSED TEST: c08s04b00x00p09n04i01322"
+      severity NOTE;
+    assert ( S2 = '1' )
+      report "***FAILED TEST: c08s04b00x00p09n04i01322 - A pulse whose duration is shorter than the switching time of the circuit is not transmitted."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c08s04b00x00p09n04i01322arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd
new file mode 100644
index 0000000..c4b8645
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1323.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p02n01i01323ent IS
+END c08s04b01x00p02n01i01323ent;
+
+ARCHITECTURE c08s04b01x00p02n01i01323arch OF c08s04b01x00p02n01i01323ent IS
+  signal   k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= transport 5;
+    wait for 1 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s04b01x00p02n01i01323"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s04b01x00p02n01i01323 - waveform element in a signal assignment statement may either consist of a value expression and an after clause (optional)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p02n01i01323arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd
new file mode 100644
index 0000000..8f78287
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd
@@ -0,0 +1,228 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p03n02i01327ent IS
+END c08s04b01x00p03n02i01327ent;
+
+ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
+  -- enumerated types.
+  type    SWITCH_LEVEL is ('0', '1', 'X');
+  subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+
+  -- integer types.
+  type POSITIVE        is range 0 to INTEGER'HIGH;
+
+  -- user defined physical types.
+  type DISTANCE is range 0 to 1E9
+    units
+      -- Base units.
+      A;                    -- angstrom
+
+      -- Metric lengths.
+      nm       = 10 A;      -- nanometer
+      um       = 1000 nm;   -- micrometer (or micron)
+      mm       = 1000 um;   -- millimeter
+      cm       = 10 mm;     -- centimeter
+
+      -- English lengths.
+      mil      = 254000 A;  -- mil
+      inch     = 1000 mil;  -- inch
+    end units;
+
+  -- floating point types.
+  type POSITIVE_R    is range 0.0 to REAL'HIGH;
+
+  -- array types.
+  type MEMORY is array(INTEGER range <>) of BIT;
+  type WORD   is array(0 to 31) of BIT;
+  type BYTE   is array(7 downto 0) of BIT;
+  
+  -- record types.
+  type DATE is
+    record
+      DAY           : INTEGER range 1 to 31;
+      MONTH         : INTEGER range 1 to 12;
+      YEAR          : INTEGER range -10000 to 1988;
+    end record;
+  
+  -- Signals with no resolution function.
+  signal SWITCHSIG : SWITCH_LEVEL;
+  signal LOGICSIG  : LOGIC_SWITCH;
+  signal CHARSIG   : CHARACTER;
+  signal BOOLSIG   : BOOLEAN;
+  signal SEVERSIG  : SEVERITY_LEVEL;
+  signal INTSIG    : INTEGER;
+  signal POSSIG    : POSITIVE;
+  signal DISTSIG   : DISTANCE;
+  signal TIMESIG   : TIME;
+  signal REALSIG   : REAL;
+  signal POSRSIG   : POSITIVE_R;
+  signal BYTESIG   : BYTE;
+  signal RECSIG    : DATE;
+
+  -- Composite signals with resolution functions on the scalar subelements.
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable ShouldBeTime : TIME := 0 ns;
+
+    variable k : integer := 0;
+  BEGIN
+    -- Test each signal assignment.
+    SWITCHSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on SWITCHSIG;
+    if (ShouldBeTime /= now or switchsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (SWITCHSIG = '1');
+    
+    LOGICSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on LOGICSIG;
+    if (ShouldBeTime /= now or logicsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (LOGICSIG = '1');
+    
+    CHARSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on CHARSIG;
+    if (ShouldBeTime /= now or charsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (CHARSIG = '1');
+    
+    BOOLSIG <= TRUE after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on BOOLSIG;
+    if (ShouldBeTime /= now or boolsig /= true) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (BOOLSIG = TRUE);
+    
+    SEVERSIG <= ERROR after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on SEVERSIG;
+    if (ShouldBeTime /= now or seversig /= error) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (SEVERSIG = ERROR);
+    
+    INTSIG <= 47 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on INTSIG;
+    if (ShouldBeTime /= now or intsig /= 47) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (INTSIG = 47);
+    
+    POSSIG <= 47 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on POSSIG;
+    if (ShouldBeTime /= now or possig /= 47) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (POSSIG = 47);
+    
+    DISTSIG <= 1 A after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on DISTSIG;
+    if (ShouldBeTime /= now or distsig /= 1 A) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (DISTSIG = 1 A);
+    
+    TIMESIG <= 10 ns after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on TIMESIG;
+    if (ShouldBeTime /= now or timesig /= 10 ns) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (TIMESIG = 10 ns);
+    
+    REALSIG <= 47.0 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on REALSIG;
+    if (ShouldBeTime /= now or realsig /= 47.0) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (REALSIG = 47.0);
+    
+    POSRSIG <= 47.0 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on POSRSIG;
+    if (ShouldBeTime /= now or posrsig /= 47.0) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (POSRSIG = 47.0);
+    
+    BYTESIG <= B"10101010" after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on BYTESIG;
+    if (ShouldBeTime /= now or bytesig /= B"10101010") then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (BYTESIG = B"10101010");
+    
+    RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on RECSIG;
+    if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.DAY = 14);
+    assert (RECSIG.MONTH = 2);
+    assert (RECSIG.YEAR = 1988);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p03n02i01327"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p03n02i01327arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd
new file mode 100644
index 0000000..92c7a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1328.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s04b01x00p03n03i01328pkg is
+  
+  type MVL    is ('0', '1', 'Z');
+  type TVECT    is array (INTEGER RANGE <>) of MVL;
+  
+  function BUSFUNC(INPUT: TVECT) return MVL;
+
+  subtype TS1    is BUSFUNC MVL;
+  type    TSV    is array (INTEGER RANGE <>) of TS1;
+  subtype WORD    is TSV(1 downto 0);
+end c08s04b01x00p03n03i01328pkg;
+
+package body c08s04b01x00p03n03i01328pkg is
+  
+  function BUSFUNC(INPUT: TVECT) return MVL is
+    variable RESOLVED_VALUE: MVL := 'Z';
+  begin
+    for I in INPUT'RANGE loop
+      if INPUT(I) /= 'Z' then
+        RESOLVED_VALUE := INPUT(I);
+        exit;
+      end if;
+    end loop;
+    return RESOLVED_VALUE;
+  end BUSFUNC;
+
+end c08s04b01x00p03n03i01328pkg;
+
+use WORK.c08s04b01x00p03n03i01328pkg.all;
+ENTITY c08s04b01x00p03n03i01328ent IS
+END c08s04b01x00p03n03i01328ent;
+
+ARCHITECTURE c08s04b01x00p03n03i01328arch OF c08s04b01x00p03n03i01328ent IS
+  signal S1 : BIT :='1';
+  signal X  : BUSFUNC MVL BUS; 
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+
+    S1 <= transport '0' after 15 ns;
+
+    wait on S1;
+
+    if (S1 = '1') then
+      X <= '1';
+    else
+      X <= null after 5 ns;
+    end if;
+
+    wait for 6 ns;
+    assert NOT( X='Z' )
+      report "***PASSED TEST: c08s04b01x00p03n03i01328"
+      severity NOTE;
+    assert ( X='Z' )
+      report "***FAILED TEST: c08s04b01x00p03n03i01328 - The driver of the signal of the signal is turned off when the waveform element consists of the reserved word 'null' and an optional after clasuse."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p03n03i01328arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd
new file mode 100644
index 0000000..6a67b8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc133.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00133ent IS
+END c04s03b02x02p08n01i00133ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00133arch OF c04s03b02x02p08n01i00133ent IS
+  type RT1 is record
+                a : INTEGER;
+                b : INTEGER;
+              end record;
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout RT1; ref : in RT1; set : in RT1) is
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : RT1 := (1, 2);
+
+  BEGIN
+    V := (1, 2);
+    Proc1(P.a => V.b, P.b => V.a, ref => (2, 1), set => (2, 3));
+                                        -- test here
+    assert V = (3, 2) report "FAIL: P didn't get set right";
+    assert NOT( V = (3,2) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00133"
+      severity NOTE;
+    assert ( V = (3,2) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00133 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00133arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd
new file mode 100644
index 0000000..ec591a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1331.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01331ent IS
+END c08s04b01x00p04n01i01331ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01331arch OF c08s04b01x00p04n01i01331ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 5 after 0 ns;
+    wait for 1 ns;
+    assert NOT( X=5 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01331" 
+      severity NOTE;
+    assert ( X=5 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01331 - Time expression may have a static value of zero and it is of the type TIME." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01331arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd
new file mode 100644
index 0000000..5bd3512
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1332.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n02i01332ent IS
+END c08s04b01x00p04n02i01332ent;
+
+ARCHITECTURE c08s04b01x00p04n02i01332arch OF c08s04b01x00p04n02i01332ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable bef, aft, diff : TIME;
+  BEGIN
+    bef := NOW;   
+    k <= 5;
+    aft := NOW;
+    diff := aft - bef;
+    assert NOT( diff = 0 ns )
+      report "***PASSED TEST: c08s04b01x00p04n02i01332"
+      severity NOTE;
+    assert ( diff = 0 ns )
+      report "***FAILED TEST: c08s04b01x00p04n02i01332 - 0 ns is the default after clause"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n02i01332arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd
new file mode 100644
index 0000000..c555f34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1335.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01335ent IS
+END c08s04b01x00p04n01i01335ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01335arch OF c08s04b01x00p04n01i01335ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 fs;
+    wait for 10 fs;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01335" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01335 - Predefined TIME unit fs as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01335arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd
new file mode 100644
index 0000000..73c3865
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1337.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01337ent IS
+END c08s04b01x00p04n01i01337ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01337arch OF c08s04b01x00p04n01i01337ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ps;
+    wait for 10 ps;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01337" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01337 - Predefined TIME unit ps as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01337arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd
new file mode 100644
index 0000000..55b1dd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1338.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01338ent IS
+END c08s04b01x00p04n01i01338ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01338arch OF c08s04b01x00p04n01i01338ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ns;
+    wait for 10 ns;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01338"
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01338 - Predefined TIME unit ns as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01338arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd
new file mode 100644
index 0000000..3da648d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01339ent IS
+END c08s04b01x00p04n01i01339ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 us;
+    wait for 10 us;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01339" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01339arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd
new file mode 100644
index 0000000..395710d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00134ent IS
+END c04s03b02x02p08n01i00134ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
+  type    AT1 is array (INTEGER range <>) of INTEGER;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if ( P = ref ) then
+        P := set;
+      end if;
+    end;
+    
+    variable V1, V2 : INTEGER;
+
+  BEGIN
+    V1 := 1;
+    V2 := 2;
+    Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
+                                        -- test here
+    assert V1 = 3 report "FAIL: actual V1 didn't get set right";
+    assert V2 = 2 report "FAIL: actual V2 didn't get set right";
+
+    assert NOT( V1 = 3 and V2 = 2 )
+      report "***PASSED TEST: c04s03b02x02p08n01i00134"
+      severity NOTE;
+    assert ( V1 = 3 and V2 = 2 )
+      report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00134arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd
new file mode 100644
index 0000000..a2bc7e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1340.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01340ent IS
+END c08s04b01x00p04n01i01340ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01340arch OF c08s04b01x00p04n01i01340ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ms;
+    wait for 10 ms;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01340" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01340 - Predefined TIME unit ms as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01340arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd
new file mode 100644
index 0000000..57f5be6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1341.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01341ent IS
+END c08s04b01x00p04n01i01341ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01341arch OF c08s04b01x00p04n01i01341ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 sec;
+    wait for 10 sec;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01341"
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01341 - Predefined TIME unit sec as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01341arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd
new file mode 100644
index 0000000..79ed15f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1342.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01342ent IS
+END c08s04b01x00p04n01i01342ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01342arch OF c08s04b01x00p04n01i01342ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 min;
+    wait for 10 min;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01342" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01342 - Predefined TIME unit min as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01342arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd
new file mode 100644
index 0000000..5404b96
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1343.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01343ent IS
+END c08s04b01x00p04n01i01343ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01343arch OF c08s04b01x00p04n01i01343ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 1 hr;
+    wait for 1 hr;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01343" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01343 - Predefined TIME unit hr as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01343arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd
new file mode 100644
index 0000000..73a4434
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1344.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p06n05i01344ent IS
+END c08s04b01x00p06n05i01344ent;
+
+ARCHITECTURE c08s04b01x00p06n05i01344arch OF c08s04b01x00p06n05i01344ent IS
+  signal k : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <=   1 after 10 ns,
+           2 after 20 ns,
+           3 after 30 ns,
+           4 after 40 ns,
+           5 after 50 ns;
+    wait for 60 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s04b01x00p06n05i01344"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s04b01x00p06n05i01344 - The sequence of new transactions must be in ascending order with respect to time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p06n05i01344arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd
new file mode 100644
index 0000000..6c512fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1347.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p07n01i01347ent IS
+END c08s04b01x00p07n01i01347ent;
+
+ARCHITECTURE c08s04b01x00p07n01i01347arch OF c08s04b01x00p07n01i01347ent IS
+  signal Add_bus : integer := 67;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Add_bus <= 1 after 5 ns, 6 after 10 ns, 12 after 19 ns;
+    Add_bus <= 6 after 12 ns, 20 after 19 ns, 6 after 21 ns;
+    wait;
+  END PROCESS TESTING;
+
+  TEST : PROCESS(Add_bus)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if (Add_bus /= 67) then
+        ok := 0;
+      end if;
+    elsif (now = 10 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 12 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 19 ns) then
+      if (Add_bus /= 20) then
+        ok := 0;
+      end if;
+    end if;
+    if (now = 21 ns) then
+      assert NOT( Add_bus = 6 and ok = 1)
+        report "***PASSED TEST: c08s04b01x00p07n01i01347"
+        severity NOTE;
+      assert ( Add_bus = 6 and ok = 1)
+        report "***FAILED TEST: c08s04b01x00p07n01i01347 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement. And this test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TEST;
+
+END c08s04b01x00p07n01i01347arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
new file mode 100644
index 0000000..2227f81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p07n01i01348ent IS
+END c08s04b01x00p07n01i01348ent;
+
+ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS
+
+  -- Local signals.
+  signal S : BIT := '0';
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables.
+    variable S_INITIAL : BIT;
+    variable ShouldBeTime : TIME;
+
+    variable k : integer := 0;
+
+  BEGIN
+    -- 0. Keep around the initial value of S.
+    S_INITIAL := S;
+    
+    -- 1. When no preemption necessary, verify the results.
+    S <= transport (not S) after 10 ns, (S) after 20 ns;
+    -- a. Wait for first transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+
+    -- b. Wait for second transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+
+    -- 2. Preempt a transaction which is to occur at the same time as second one.
+    S_INITIAL := S;
+    S <= transport (S) after 10 ns;
+    S <= transport (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Preempt a transaction which is to occur at a later time than second one.
+    S_INITIAL := S;
+    S <= transport (S) after 15 ns;
+    S <= transport (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;  
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Preempt multiple transactions.
+    S_INITIAL := S;
+    S <= transport (S) after 15 ns, (not S) after 30 ns;
+    S <= transport (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p07n01i01348"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p07n01i01348arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd
new file mode 100644
index 0000000..e507c8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd
@@ -0,0 +1,207 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1349.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p10n01i01349ent IS
+END c08s04b01x00p10n01i01349ent;
+
+ARCHITECTURE c08s04b01x00p10n01i01349arch OF c08s04b01x00p10n01i01349ent IS
+  -- Local signals.
+  signal S : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+
+    -- local variables.
+    variable S_INITIAL : BIT;
+    variable ShouldBeTime : TIME;
+
+    variable k : integer := 0;
+
+  BEGIN
+    -- 0. Keep around the initial value of S.
+    S_INITIAL := S;
+
+    -- 1. When no preemption necessary, verify the results.  INERTIAL SAME AS TRANSPORT.
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Wait for first transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+
+    -- b. Wait for second transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+
+    -- 2. Preempt a transaction which is to occur at the same time as second one.
+    --    INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 10 ns;
+    S <= (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Preempt a transaction which is to occur at a later time than second one.
+    --   INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 15 ns;
+    S <= (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Preempt multiple transactions.  INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 15 ns, (not S) after 30 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 5. Preempt transactions which occur before the second inertial assignment.
+    S_INITIAL := S;
+    S <= (S) after 5 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    -- 6. Don't preempt transactions which occur before the second inertial assignment.
+    S_INITIAL := S;
+    S <= (not S) after 5 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the first transaction was NOT preempted.
+    ShouldBeTime := NOW + 5 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 15 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that there are no more transactions.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p10n01i01349"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p10n01i01349 - Interial signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p10n01i01349arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd
new file mode 100644
index 0000000..ae8a585
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc135.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00135ent IS
+END c04s03b02x02p08n01i00135ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00135arch OF c04s03b02x02p08n01i00135ent IS
+  type    AT1 is array (INTEGER range <>, INTEGER range <>) of INTEGER;
+  subtype ST1 is AT1(1 to 2, 1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if (P=ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : ST1 := ((1, 2), (3, 4));
+
+  BEGIN
+    V := ((1, 2), (3, 4));
+    Proc1(  P(1,1) => V(2,2), P(1,2) => V(2,1),
+            P(2,1) => V(1,2), P(2,2) => V(1,1),
+            ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6)));  -- test here
+    assert V = ((6, 7), (8, 9)) report "FAIL: actual V didn't get set right";
+
+    assert NOT( V = ((6,7),(8,9)) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00135"
+      severity NOTE;
+    assert ( V = ((6,7),(8,9)) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00135 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00135arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd
new file mode 100644
index 0000000..13d60f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1350.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p10n01i01350ent IS
+END c08s04b01x00p10n01i01350ent;
+
+ARCHITECTURE c08s04b01x00p10n01i01350arch OF c08s04b01x00p10n01i01350ent IS
+  signal Add_bus : integer := 67;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Add_bus <= 1 after 5 ns, 6 after 10 ns, 12 after 19 ns;
+    Add_bus <= 6 after 12 ns, 20 after 19 ns, 6 after 21 ns;
+    wait;
+  END PROCESS TESTING;
+  
+  TEST : PROCESS(Add_bus)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if (Add_bus /= 67) then
+        ok := 0;
+      end if;
+    elsif (now = 10 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 12 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 19 ns) then
+      if (Add_bus /= 20) then
+        ok := 0;
+      end if;
+    end if;
+    if (now = 21 ns) then
+      assert NOT( Add_bus = 6 and ok = 1)
+        report "***PASSED TEST: c08s04b01x00p10n01i01350"
+        severity NOTE;
+      assert ( Add_bus = 6 and ok = 1)
+        report "***FAILED TEST: c08s04b01x00p10n01i01350 - Projected output waveform with initial delay test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TEST;
+
+END c08s04b01x00p10n01i01350arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd
new file mode 100644
index 0000000..2665c21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1354.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p02n01i01354ent IS
+END c08s05b00x00p02n01i01354ent;
+
+ARCHITECTURE c08s05b00x00p02n01i01354arch OF c08s05b00x00p02n01i01354ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 1;
+  BEGIN
+    a := 10; 
+    assert NOT(a = 10)
+      report "***PASSED TEST: c08s05b00x00p02n01i01354" 
+      severity NOTE;
+    assert (a = 10)
+      report "***FAILED TEST: c08s05b00x00p02n01i01354 - Target of a variable assignment can only be a name or an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p02n01i01354arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd
new file mode 100644
index 0000000..1bccb66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01356ent IS
+END c08s05b00x00p03n01i01356ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t1 is record
+                 ele1 : integer;
+                 ele2 : real;
+               end record;
+    variable f1: t1;
+    variable i : integer := 0;
+    variable r : real    := 0.0;
+  BEGIN
+    f1.ele1 := 1;
+    f1.ele2 := 2.3;
+    i := f1.ele1;
+    r := f1.ele2;
+    assert NOT((i=1) and (r=2.3)) 
+      report "***PASSED TEST: c08s05b00x00p03n01i01356" 
+      severity NOTE;
+    assert ((i=1) and (r=2.3)) 
+      report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01356arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd
new file mode 100644
index 0000000..b73b2f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1359.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01359ent IS
+END c08s05b00x00p03n01i01359ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01359arch OF c08s05b00x00p03n01i01359ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2) 
+      report "***PASSED TEST: c08s05b00x00p03n01i01359" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2) 
+      report "***FAILED TEST: c08s05b00x00p03n01i01359 - Target of a variable assignment is not a variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd
new file mode 100644
index 0000000..ce868ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc136.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00136ent IS
+END c04s03b02x02p08n01i00136ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00136arch OF c04s03b02x02p08n01i00136ent IS
+  type    AT0 is array (INTEGER range <>) of INTEGER;
+  subtype ST0 is AT0(1 to 2);
+  type    AT1 is array (INTEGER range <>) of ST0;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : ST1 := ((1, 2), (3, 4));
+    variable V11, V12, V21, V22 : INTEGER; 
+
+  BEGIN
+    V11 := 1;
+    V12 := 2;
+    V21 := 3;
+    V22 := 4;
+    Proc1(  P(1)(1) => V22, P(1)(2) => V21, P(2)(1) => V12, P(2)(2) => V11,
+            ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6))); -- test here
+    assert V11 = 6 report "FAIL: actual V11 didn't get set right";
+    assert V12 = 7 report "FAIL: actual V12 didn't get set right";
+    assert V21 = 8 report "FAIL: actual V21 didn't get set right";
+    assert V22 = 9 report "FAIL: actual V22 didn't get set right";   
+    assert NOT( V11=6 and V12=7 and V21=8 and V22=9 )
+      report "***PASSED TEST: c04s03b02x02p08n01i00136"
+      severity NOTE;
+    assert ( V11=6 and V12=7 and V21=8 and V22=9 )
+      report "***FAILED TEST: c04s03b02x02p08n01i00136 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00136arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd
new file mode 100644
index 0000000..31173ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1360.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01360ent IS
+END c08s05b00x00p03n01i01360ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01360arch OF c08s05b00x00p03n01i01360ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 :=c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01360" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01360 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01360arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd
new file mode 100644
index 0000000..63bed44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1361.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01361ent IS
+END c08s05b00x00p03n01i01361ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01361arch OF c08s05b00x00p03n01i01361ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01361"
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01361 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01361arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd
new file mode 100644
index 0000000..d8547fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1362.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01362ent IS
+END c08s05b00x00p03n01i01362ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01362arch OF c08s05b00x00p03n01i01362ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01362" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01362 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01362arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd
new file mode 100644
index 0000000..837ec49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1363.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01363ent IS
+END c08s05b00x00p03n01i01363ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01363arch OF c08s05b00x00p03n01i01363ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2));
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01363" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01363 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01363arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd
new file mode 100644
index 0000000..39683ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01364ent IS
+END c08s05b00x00p03n01i01364ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01364" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd
new file mode 100644
index 0000000..b54e7b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1365.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01365ent IS
+END c08s05b00x00p03n01i01365ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01365arch OF c08s05b00x00p03n01i01365ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01365" 
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01365 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd
new file mode 100644
index 0000000..cad1786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1366.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01366ent IS
+END c08s05b00x00p03n01i01366ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01366arch OF c08s05b00x00p03n01i01366ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01366" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01366 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd
new file mode 100644
index 0000000..015838f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1367.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01367ent IS
+END c08s05b00x00p03n01i01367ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01367arch OF c08s05b00x00p03n01i01367ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01367" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01367 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01367arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd
new file mode 100644
index 0000000..21b561a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01368ent IS
+END c08s05b00x00p03n01i01368ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01368"
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01368arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd
new file mode 100644
index 0000000..e1adcb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd
@@ -0,0 +1,176 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1369.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01369ent IS
+END c08s05b00x00p03n01i01369ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01369arch OF c08s05b00x00p03n01i01369ent IS
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01369" 
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01369 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01369arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd
new file mode 100644
index 0000000..7f63631
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc137.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00137ent IS
+END c04s03b02x02p08n01i00137ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00137arch OF c04s03b02x02p08n01i00137ent IS
+  type    AT0 is array (INTEGER range <>) of INTEGER;
+  subtype ST0 is AT0(1 to 2);
+  type    AT1 is array (INTEGER range <>) of ST0;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is      
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V    : ST1 := ((1, 2), (3, 4));
+    variable V1    : ST0;
+    variable V2    : ST0;
+
+  BEGIN
+    V1 := (1, 2);
+    V2 := (3, 4);
+    Proc1(  P(1) => V2, P(2) => V1,
+            ref => ((3, 4), (1, 2)), set => ((9, 8), (7, 6))); -- test here
+    assert V1 = (7, 6) report "FAIL: actual V1 didn't get set right";
+    assert V2 = (9, 8) report "FAIL: actual V2 didn't get set right";
+    assert NOT( V1=(7,6) and V2=(9,8) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00137"
+      severity NOTE;
+    assert ( V1=(7,6) and V2=(9,8) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00137 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd
new file mode 100644
index 0000000..8f98d28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1370.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01370ent IS
+END c08s05b00x00p03n01i01370ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01370arch OF c08s05b00x00p03n01i01370ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01370"
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01370 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01370arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd
new file mode 100644
index 0000000..f8a4f9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1371.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01371ent IS
+END c08s05b00x00p03n01i01371ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01371arch OF c08s05b00x00p03n01i01371ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 :=c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01371" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01371 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01371arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd
new file mode 100644
index 0000000..c9f6073
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1372.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01372ent IS
+END c08s05b00x00p03n01i01372ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01372arch OF c08s05b00x00p03n01i01372ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01372" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST:c08s05b00x00p03n01i01372 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01372arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd
new file mode 100644
index 0000000..2819a3b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01373ent IS
+END c08s05b00x00p03n01i01373ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01373"
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01373arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd
new file mode 100644
index 0000000..2bccfd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01374ent IS
+END c08s05b00x00p03n01i01374ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01374" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01374arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd
new file mode 100644
index 0000000..d56afd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd
@@ -0,0 +1,120 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1375.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s05b00x00p03n01i01375pkg is
+
+  -- Type declarations.
+  subtype     BV2  is BIT_VECTOR( 0 to 1 );
+  subtype     CH2  is STRING( 1 to 2 );
+
+  -- Constant declarations.
+  constant BVC  : BV2 := B"00";
+  constant CHC  : CH2 := "bb";
+
+  -- Function returns BV2.
+  function  returnBV2 return BV2;
+
+  -- Function returns CH2.
+  function  returnCH2 return CH2;
+  
+end c08s05b00x00p03n01i01375pkg;
+
+package body c08s05b00x00p03n01i01375pkg is
+  
+  -- Function returns BV2.
+  function  returnBV2 return BV2 is
+  begin
+    return ( BVC );
+  end returnBV2;
+  
+  -- Function returns CH2.
+  function  returnCH2 return CH2 is
+  begin
+    return( CHC );
+  end returnCH2;
+  
+end c08s05b00x00p03n01i01375pkg;
+
+use work.c08s05b00x00p03n01i01375pkg.all;
+ENTITY c08s05b00x00p03n01i01375ent IS
+END c08s05b00x00p03n01i01375ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01375arch OF c08s05b00x00p03n01i01375ent IS
+
+BEGIN
+  TESTING: PROCESS
+    
+    -- local variables
+    variable BITV     : BV2 := B"11";
+    variable STRV     : CH2 := "ab";
+    
+    variable S, T        : BIT;
+    variable S1, T1        : BIT;
+    variable S11, T11        : BIT;
+    variable C1, C2      : CHARACTER;
+    variable C11, C22      : CHARACTER;
+    variable C111, C222      : CHARACTER;
+    
+  BEGIN
+    -- Assign with a variable as the expression.
+    ( S, T )  := BITV;
+    
+    ( C1,C2 ) := STRV;
+    
+    -- Assign with a function return value.
+    ( S1, T1 )  := returnBV2;
+    
+    ( C11,C22 ) := returnCH2;
+    
+    -- Assign with a qualified expression.
+    ( S11, T11 )  := BV2'( '0', '1' );
+    
+    ( C111,C222 ) := CH2'( 'c', 'c' );
+
+    assert NOT(((S = BITV( 0 )) and (T = BITV( 1 )))
+               and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
+               and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
+               and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
+               and ((S11 = '0') and (T11 = '1'))
+               and ((C111 = 'c') and (C222 = 'c')))
+      report "***PASSED TEST: c08s05b00x00p03n01i01375" 
+      severity NOTE;
+    assert (((S = BITV( 0 )) and (T = BITV( 1 )))
+            and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
+            and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
+            and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
+            and ((S11 = '0') and (T11 = '1'))
+            and ((C111 = 'c') and (C222 = 'c')))
+      report "***FAILED TEST: c08s05b00x00p03n01i01375 - Legal aggregate variable assignment fail." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01375arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd
new file mode 100644
index 0000000..d1294d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc138.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00138ent IS
+  CONSTANT a,b    : INTEGER := 2;
+  CONSTANT c       : INTEGER := 3; 
+
+  PROCEDURE addup (i1,i2,i3:IN INTEGER:=a**b+c-a;SIGNAL i4:OUT INTEGER) IS
+  BEGIN
+    i4 <= (i1+i2+i3);
+  END;
+END c04s03b02x02p09n01i00138ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00138arch OF c04s03b02x02p09n01i00138ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+  SIGNAL a11: INTEGER := 77;
+  SIGNAL a12: INTEGER := 77;
+  SIGNAL a13: INTEGER := 77;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    addup(i2=>a1,i1=>a1,i4=>a1);
+    WAIT FOR 1 ns;
+    IF (a1 = 119) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice plus default" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i3=>a2,i1=>a2,i2=>a3,i4=>a11);
+    WAIT FOR 1 ns;
+    IF (a11 = 213) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i3=>a3,i2=>a3,i1=>a3,i4=>a12);
+    WAIT FOR 1 ns;
+    IF (a12 = 231) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual thrice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i4=>a13);
+    WAIT FOR 1 ns;
+    IF (a13 = 15) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    wait for 5 ns;
+    assert NOT(   a1 = 119   and
+                  a11= 213   and
+                  a12= 231   and
+                  a13= 15      )   
+      report "***PASSED TEST: c04s03b02x02p09n01i00138"
+      severity NOTE;
+    assert (   a1 = 119   and
+               a11= 213   and
+               a12= 231   and
+               a13= 15      )   
+      report "***FAILED TEST: c04s03b02x02p09n01i00138 - Named association where 2 or more named formal signals are associated with the same actual signal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd
new file mode 100644
index 0000000..3aabe19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n02i01386ent IS
+END c08s05b00x00p03n02i01386ent;
+
+ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
+
+BEGIN
+  TESTING : PROCESS   
+
+    variable radix : natural := 10;
+    variable v1 : natural;
+
+    type r_array_index_type is range 1 to 3;
+    type r_array_type is array (r_array_index_type) of natural;
+    variable r_array : r_array_type;
+
+    procedure set_radix ( constant radix : natural
+                          ) is
+    begin
+      TESTING.radix := radix;             -- test selected name as target
+    end set_radix;
+
+  BEGIN
+    v1 := 8;   --test simple name as target
+    assert v1 = 8
+      report "Simple name as target failed."
+      severity note ;
+
+    set_radix (v1);
+    assert radix = v1
+      report "Selected name as target failed."
+      severity note ;
+
+    r_array ( 3 to 3 ) := (3 => 10);          -- test slice name as target
+    assert r_array ( 3 ) = 10
+      report "Slice name as target failed."
+      severity note ;
+
+    r_array ( 2 ) := 8;               -- test indexed name as target
+    assert r_array ( 2 ) = 8
+      report "Indexed name as target failed."
+      severity note ;
+
+    assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8) 
+      report "***PASSED TEST: c08s05b00x00p03n02i01386" 
+      severity NOTE;
+    assert (v1=8 and r_array(3)=10 and r_array(2)=8) 
+      report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n02i01386arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd
new file mode 100644
index 0000000..a38c9d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1387.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01387ent IS
+END c08s05b00x00p04n01i01387ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01387arch OF c08s05b00x00p04n01i01387ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 3) := ('0','0','0','0');
+  BEGIN
+    NUM1 := ('0', '0', '1', '1');   
+    assert NOT( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' ) 
+      report "***PASSED TEST: c08s05b00x00p04n01i01387"
+      severity NOTE;
+    assert ( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' ) 
+      report "***FAILED TEST: c08s05b00x00p04n01i01387 - Assigning to an aggregate variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd
new file mode 100644
index 0000000..d2044c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1389.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n02i01389ent IS
+END c08s05b00x00p04n02i01389ent;
+
+ARCHITECTURE c08s05b00x00p04n02i01389arch OF c08s05b00x00p04n02i01389ent IS
+  subtype C2 is BIT_VECTOR(1 to 2);
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BIT;
+    variable T1 : BIT;
+    variable BIT2 : C2 := B"11";
+  BEGIN
+    (S1, T1) := BIT2;
+    assert NOT((S1 = '1') and (T1 = '1')) 
+      report "***PASSED TEST: c08s05b00x00p04n02i01389" 
+      severity NOTE;
+    assert ((S1 = '1') and (T1 = '1')) 
+      report "***FAILED TEST: c08s05b00x00p04n02i01389 - Base types of the expression on the right hand side is the same as the base type of the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n02i01389arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd
new file mode 100644
index 0000000..900de44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n03i01390ent IS
+END c08s05b00x00p04n03i01390ent;
+
+ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : integer := 0;
+    variable B : integer := 0;
+    variable C : integer := 1;
+    variable D : integer := 2;
+    type array_of_ints is array (Positive range <>) of integer;
+  BEGIN
+    (A,B) := array_of_ints'(C,D);
+    assert NOT( (A=1) and (B=2) )
+      report "***PASSED TEST: c08s05b00x00p04n03i01390"
+      severity NOTE;
+    assert ( (A=1) and (B=2) )
+      report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n03i01390arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd
new file mode 100644
index 0000000..74f1c6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1392.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n04i01392ent IS
+END c08s05b00x00p04n04i01392ent;
+
+ARCHITECTURE c08s05b00x00p04n04i01392arch OF c08s05b00x00p04n04i01392ent IS
+--
+  TYPE rec_list IS RECORD
+                     a,b,c,d : INTEGER;
+                   END RECORD;
+
+BEGIN
+  TESTING: PROCESS
+--
+    VARIABLE rec1 : rec_list := (1,2,3,4);
+    VARIABLE rec2 : rec_list := (1,2,3,4);
+    VARIABLE rec3 : rec_list := (1,2,3,4);
+    VARIABLE rec4 : rec_list := (1,2,3,4);
+    VARIABLE rec5 : rec_list := (1,2,3,4);
+    VARIABLE rec6 : rec_list := (1,2,3,4);
+
+--
+  BEGIN
+--
+    rec1 := ( rec1.d, rec1.c, rec1.b, rec1.a);
+--
+    ( rec2.d, rec2.c, rec2.b, rec2.a) := rec2;
+--
+    (rec3.d, rec3.c, rec3.b, rec3.a)
+      :=  rec_list' (rec3.c, rec3.d, rec3.a, rec3.b);
+--
+    (rec4.a, rec4.b, rec4.c, rec4.d)
+      :=  rec_list' ( d=>rec4.a, c=>rec4.b, b=>rec4.c, a=>rec4.d);
+--
+    ( d=>rec5.a, c=>rec5.b, b=>rec5.c, a=>rec5.d) := rec5;
+--
+    (rec6.d, rec6.c, rec6.b, rec6.a)
+      :=  rec_list' ( d=>rec6.a, c=>rec6.b, b=>rec6.c, a=>rec6.d);
+    
+--
+    ASSERT NOT(   rec1 = (4,3,2,1)   and  
+                  rec2 = (4,3,2,1)    and 
+                  rec3 = (2,1,4,3)    and 
+                  rec4 = (4,3,2,1)    and 
+                  rec5 = (4,3,2,1)    and 
+                  rec6 = (1,2,3,4)) 
+      report "***PASSED TEST: c08s05b00x00p04n04i01392"
+      severity NOTE;
+    ASSERT (   rec1 = (4,3,2,1)   and  
+               rec2 = (4,3,2,1)    and 
+               rec3 = (2,1,4,3)    and 
+               rec4 = (4,3,2,1)    and 
+               rec5 = (4,3,2,1)    and 
+               rec6 = (1,2,3,4)) 
+      report "***FAILED TEST: c08s05b00x00p04n04i01392 - Record aggregates type variable assignment fail."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n04i01392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd
new file mode 100644
index 0000000..854a578
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01393ent IS
+END c08s05b00x00p04n01i01393ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type RT is
+      record
+        a : CHARACTER;
+        b : CHARACTER;
+      end record;
+    variable v1, v2    : CHARACTER := NUL;
+    variable rv       : RT := ('1', '2');
+  BEGIN
+    assert v1 = NUL;
+    assert v2 = NUL;
+    (v1, v2) := rv;
+    assert v1 = '1';
+    assert v2 = '2';
+    wait for 1 ns;
+    assert NOT( v1 = '1' and v2 = '2' )
+      report "***PASSED TEST: c08s05b00x00p04n01i01393"
+      severity NOTE;
+    assert ( v1 = '1' and v2 = '2' )
+      report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01393arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd
new file mode 100644
index 0000000..515babb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1394.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01394ent IS
+END c08s05b00x00p04n01i01394ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01394arch OF c08s05b00x00p04n01i01394ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type AT2 is array (0 to 1, 0 to 1) of CHARACTER;
+    type AT1 is array (0 to 1) of CHARACTER;
+    variable v1, v2    : AT1;
+    variable av       : AT2 := (('a', 'b'), ('c', 'd'));
+  BEGIN
+    assert v1 = (NUL, NUL);
+    assert v2 = (NUL, NUL);
+    v1(0) := av(0,0);
+    v1(1) := av(0,1);
+    v2(0) := av(1,0);
+    v2(1) := av(1,1);
+    assert v1 = ('a', 'b');
+    assert v2 = ('c', 'd');
+    wait for 1 ns;
+    assert NOT( v1 = ('a','b') and v2 = ('c', 'd') )
+      report "***PASSED TEST: c08s05b00x00p04n01i01394"
+      severity NOTE;
+    assert ( v1 = ('a','b') and v2 = ('c', 'd') )
+      report "***FAILED TEST: c08s05b00x00p04n01i01394 - Aggregate (2-d array type) assignment for variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01394arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd
new file mode 100644
index 0000000..b1d2968
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc14.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p03n01i00014ent IS
+END c04s02b00x00p03n01i00014ent;
+
+ARCHITECTURE c04s02b00x00p03n01i00014arch OF c04s02b00x00p03n01i00014ent IS
+  subtype sub1 is integer;
+  subtype sub2 is sub1;    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : sub2 := 0;
+  BEGIN
+    assert NOT( k=0 )
+      report "***PASSED TEST: c04s02b00x00p03n01i00014"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c04s02b00x00p03n01i00014 - Subtype indication syntactic test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p03n01i00014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd
new file mode 100644
index 0000000..2bd767b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01403ent IS
+END c08s05b00x00p06n01i01403ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    T    : INTEGER := 1;
+    subtype    ST    is BIT_VECTOR(T to 10);
+    variable    OK    : BIT_VECTOR(T+1 to 11);
+    variable    ILL    : BIT_VECTOR(T to 11);
+
+    variable    V    : ST;
+  BEGIN
+    V := OK;
+    assert NOT(V = "0000000000") 
+      report "***PASSED TEST: c08s05b00x00p06n01i01403" 
+      severity NOTE;
+    assert (V = "0000000000") 
+      report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd
new file mode 100644
index 0000000..31e3d69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1405.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p07n01i01405ent IS
+END c08s05b00x00p07n01i01405ent;
+
+ARCHITECTURE c08s05b00x00p07n01i01405arch OF c08s05b00x00p07n01i01405ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BIT;
+    variable T1 : BIT;
+    variable T2 : BIT;
+    variable B2 : BIT_VECTOR(0 to 2) := B"111";
+  BEGIN
+    (S1, T1, T2) := B2;
+    assert NOT( (S1='1') and (T1='1') and (T2='1') )
+      report "***PASSED TEST: c08s05b00x00p07n01i01405"
+      severity NOTE;
+    assert ( (S1='1') and (T1='1') and (T2='1') )
+      report "***FAILED TEST: c08s05b00x00p07n01i01405 - Subtypes of the subelements of the right-hand side and that of the names in the aggregate should match"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p07n01i01405arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd
new file mode 100644
index 0000000..d980782
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1409.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01409ent IS
+END c08s05b01x00p01n01i01409ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01409arch OF c08s05b01x00p01n01i01409ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      A1 is array (positive range <>) of integer;
+    type      A2 is array (0 to 10) of A1 (4 downto 1);
+    variable   XC : A2; 
+  BEGIN
+    XC (4) (1) := 1;
+    assert NOT(XC(4)(1) = 1) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01409" 
+      severity NOTE;
+    assert (XC(4)(1) = 1) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01409 - The types of the right hand side and left hand side are the same and for each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01409arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd
new file mode 100644
index 0000000..e42d57f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc141.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00141ent IS
+  FUNCTION addup (i1,i2,i3:INTEGER:=5) RETURN INTEGER IS
+  BEGIN
+    RETURN (i1+i2+i3);
+  END;
+END c04s03b02x02p09n01i00141ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00141arch OF c04s03b02x02p09n01i00141ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+  SIGNAL i1 : INTEGER := 0;
+  SIGNAL i2 : INTEGER := 0;
+  SIGNAL i3 : INTEGER := 0;
+  SIGNAL i4 : INTEGER := 0;
+  SIGNAL i5 : INTEGER := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    i1 <= addup(i2=>a1,i1=>a1);
+    WAIT FOR 1 ns;
+    IF (i1 = 119) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice plus default" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i2 <= addup(i3=>a2,i1=>a2,i2=>a1);
+    WAIT FOR 1 ns;
+    IF (i2 = 193) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i3 <= addup(i3=>a3,i2=>a3,i1=>a3);
+    WAIT FOR 1 ns;
+    IF (i3 = 231) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual thrice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i4 <= addup;
+    WAIT FOR 1 ns;
+    IF (i4 = 15) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i5 <= addup(addup(addup,addup,addup),addup(addup,addup,addup),addup(addup,addup,addup));
+    WAIT FOR 1 ns;
+    IF (i5 = 135) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value recursively" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    wait for 5 ns;
+    assert NOT(   i1 = 119   and
+                  i2 = 193   and
+                  i3 = 231   and
+                  i4 = 15      and
+                  i5 = 135   ) 
+      report "***PASSED TEST: c04s03b02x02p09n01i00141"
+      severity NOTE;
+    assert (   i1 = 119   and
+               i2 = 193   and
+               i3 = 231   and
+               i4 = 15      and
+               i5 = 135   ) 
+      report "***FAILED TEST: c04s03b02x02p09n01i00141 - Named association on function call test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00141arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd
new file mode 100644
index 0000000..9a07c6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1410.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01410ent IS
+END c08s05b01x00p01n01i01410ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01410arch OF c08s05b01x00p01n01i01410ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      BIT_VECTOR is array (natural range <>) of BIT;
+    variable   NUM1 : BIT_VECTOR(0 to 1); 
+    variable   NUM2 : BIT_VECTOR(0 to 1) := ('1','1'); 
+  BEGIN
+    NUM1 := NUM2;
+    assert NOT((NUM1(0)='1') and(NUM1(1)='1')) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01410" 
+      severity NOTE;
+    assert ((NUM1(0)='1') and(NUM1(1)='1')) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01410 - The types of the igth hand side and left hand side are the same and for each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01410arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd
new file mode 100644
index 0000000..434cacb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1412.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01412ent IS
+END c08s05b01x00p01n01i01412ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01412arch OF c08s05b01x00p01n01i01412ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : integer;
+        y : real;
+        z : boolean;
+        b : bit;
+      end record;
+    type array_type is array (1 to 10) of rec_type;
+    variable   v1 : array_type;   
+  BEGIN
+    v1 (1).x := 12;
+    v1 (1).y := 1.2;
+    v1 (1).z := true;
+    v1 (1).b := bit'('0');
+    assert NOT( v1(1).x = 12 and v1(1).y = 1.2 and v1(1).z = true and v1(1).b = '0') 
+      report "***PASSED TEST: c08s05b01x00p01n01i01412" 
+      severity NOTE;
+    assert ( v1(1).x = 12 and v1(1).y = 1.2 and v1(1).z = true and v1(1).b = '0') 
+      report "***FAILED TEST: c08s05b01x00p01n01i01412 - Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd
new file mode 100644
index 0000000..e23a5c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1413.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01413ent IS
+END c08s05b01x00p01n01i01413ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01413arch OF c08s05b01x00p01n01i01413ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (i : integer) return real is
+    begin
+      return (1.0);
+    end;
+    type rec_type is
+      record
+        x : integer;
+        y : real;
+        z : boolean;
+        b : bit;
+      end record;
+    type array_type is array (1 to 10) of rec_type;
+    variable   v1 : array_type;   
+    constant    i  : integer := 20;
+  BEGIN
+    v1 (1).x := i;
+    v1 (1).y := check(i);
+    v1 (1).z := true;
+    v1 (1).b := bit'('0');
+    assert NOT(v1(1).x=20 and v1(1).y=1.0 and v1(1).z=true and v1(1).b='0') 
+      report "***PASSED TEST: c08s05b01x00p01n01i01413" 
+      severity NOTE;
+    assert (v1(1).x=20 and v1(1).y=1.0 and v1(1).z=true and v1(1).b='0') 
+      report "***FAILED TEST: c08s05b01x00p01n01i01413 Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01413arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd
new file mode 100644
index 0000000..0a76d48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01414ent IS
+END c08s05b01x00p01n01i01414ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    variable   v1 : array_type;   
+  BEGIN
+    v1 (1) := integer'(12);
+    assert NOT(v1(1)=12) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01414" 
+      severity NOTE;
+    assert (v1(1)=12) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01414arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd
new file mode 100644
index 0000000..618cb3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1421.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p02n01i01421ent IS
+END c08s06b00x00p02n01i01421ent;
+
+ARCHITECTURE c08s06b00x00p02n01i01421arch OF c08s06b00x00p02n01i01421ent IS
+
+  procedure assert_msg  is
+  begin
+    assert FALSE
+      report "***PASSED TEST: c08s06b00x00p02n01i01421" 
+      severity NOTE;
+  end assert_msg;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert_msg;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p02n01i01421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd
new file mode 100644
index 0000000..c3b3408
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1422.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p04n01i01422ent IS
+END c08s06b00x00p04n01i01422ent;
+
+ARCHITECTURE c08s06b00x00p04n01i01422arch OF c08s06b00x00p04n01i01422ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    procedure proc1(
+      constant p : in    STRING;
+      variable l : out    INTEGER
+      ) is
+    begin
+      l := P'LENGTH;
+    end;
+
+    constant C : STRING := "Testing";
+    variable l : INTEGER := c'LENGTH - 1;
+
+  BEGIN
+    assert l /= c'LENGTH;
+    proc1(c, l);
+    assert NOT(l = c'LENGTH)
+      report "***PASSED TEST: c08s06b00x00p04n01i01422" 
+      severity NOTE;
+    assert (l = c'LENGTH)
+      report "***FAILED TEST: c08s06b00x00p04n01i01422 - Sequential procedure call test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p04n01i01422arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd
new file mode 100644
index 0000000..b48aac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1423.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01423ent IS
+END c08s06b00x00p05n01i01423ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01423arch OF c08s06b00x00p05n01i01423ent IS
+  procedure check (signal x   : in  integer;
+                   signal kkk : out integer ) is
+  begin
+    if (x = 0) then
+      kkk <= 5;
+      wait for 1 ns;
+    end if;
+  end check;
+  signal k  : integer := 0;
+  signal kk  : integer := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    check (k,kk);
+    assert NOT(kk = 5)
+      report "***PASSED TEST: c08s06b00x00p05n01i01423"
+      severity NOTE;
+    assert (kk = 5)
+      report "***FAILED TEST: c08s06b00x00p05n01i01423 - No actual parmeter is required for a formal parmeter with a default expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01423arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd
new file mode 100644
index 0000000..4ce750d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1424.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01424ent IS
+END c08s06b00x00p05n01i01424ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01424arch OF c08s06b00x00p05n01i01424ent IS
+
+  procedure copy_into ( variable dest : out integer;
+                        variable src  : in  integer := 0   ) is
+    --
+    -- This procedure copies the value of the second argument
+    -- into the first argument.
+    --
+  begin
+    dest := src;
+  end copy_into;
+
+BEGIN
+  TESTING : PROCESS
+    variable   v1 : integer := 0;
+  BEGIN
+
+    --
+    -- Try it with only one parameter
+    --
+    copy_into(v1);            -- v1 <- (0)
+    assert NOT(v1 = 0)
+      report "***PASSED TEST: c08s06b00x00p05n01i01424"
+      severity NOTE;
+    assert (v1 = 0)
+      report "***FAILED TEST: c08s06b00x00p05n01i01424 - Procedure call without an actual parameter part is permitted." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01424arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd
new file mode 100644
index 0000000..19cfc38
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1425.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01425ent IS
+END c08s06b00x00p05n01i01425ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01425arch OF c08s06b00x00p05n01i01425ent IS
+
+  procedure assert_same_int ( variable v1, v2 : in integer := 0 ) is
+    --
+    -- This procedure compares the value of the first argument
+    -- into the second argument and prints an assertion message
+    -- if they are the same.
+    --
+  begin
+    assert NOT(v1 = v2)
+      report "***PASSED TEST: c08s06b00x00p05n01i01425"
+      severity NOTE;
+    assert (v1 = v2)
+      report "***FAILED TEST: c08s06b00x00p05n01i01425 - Procedure call without an actual parameter part is permitted." 
+      severity ERROR;
+  end assert_same_int;
+
+BEGIN
+  TESTING : PROCESS
+    variable   v1 : integer := 1;
+  BEGIN
+
+    --
+    -- Try without any parameters; the procedure should
+    -- use the default values for the arguments.
+    --
+    v1 := 5;
+    assert_same_int;   
+
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd
new file mode 100644
index 0000000..3c27e48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00143pkg is
+  type fourstate is ('0','1','x','z');
+  function fourstate_to_bit(x : fourstate) return bit;
+  procedure simple ( crude : in bit;
+                     signal refined : out bit);
+end c04s03b02x02p12n01i00143pkg;
+
+package body c04s03b02x02p12n01i00143pkg is
+  procedure simple ( crude : in bit;
+                     signal refined : out bit) is
+  begin
+    refined <= crude after 5 ns;
+  end simple;
+  
+  function fourstate_to_bit(x : fourstate) return bit is
+    variable newval: bit := '0';
+  begin
+    case x is
+      when '0' => newval := '0';
+      when '1' => newval := '1';
+      when 'z' => newval := '0';
+      when 'x' => newval := '0';
+    end case;
+    return newval;
+  end fourstate_to_bit;
+end c04s03b02x02p12n01i00143pkg;
+
+use work.c04s03b02x02p12n01i00143pkg.all;
+ENTITY c04s03b02x02p12n01i00143ent IS
+  port( x, y: in fourstate);
+END c04s03b02x02p12n01i00143ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
+  signal yint : bit;
+BEGIN
+
+  simple ( fourstate_to_bit(y) , yint);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( yint = '0' )
+      report "***PASSED TEST: c04s03b02x02p12n01i00143"
+      severity NOTE;
+    assert ( yint = '0' )
+      report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00143arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd
new file mode 100644
index 0000000..530af35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1442.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01442ent IS
+END c08s07b00x00p02n01i01442ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01442arch OF c08s07b00x00p02n01i01442ent IS
+
+begin
+  TESTING: process
+    variable k : integer := 0;
+    variable m : integer := 6;
+    variable j : boolean := TRUE;
+  begin
+    if m > 5 then
+      case j is
+        when TRUE   => k := 1;
+        when FALSE   => NULL;
+      end case;
+    end if;
+    assert NOT(k = 1)
+      report "***PASSED TEST: c08s07b00x00p02n01i01442"
+      severity NOTE;
+    assert (k = 1)
+      report "***FAILED TEST: c08s07b00x00p02n01i01442 - CASE statement to be sequence statements of IF statement" 
+      severity ERROR;
+    wait;
+  end process TESTING;
+
+END c08s07b00x00p02n01i01442arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd
new file mode 100644
index 0000000..101ac09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01443ent IS
+END c08s07b00x00p02n01i01443ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      while (k > 5) loop
+        k := k - 1;
+      end loop;
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01443"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01443arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd
new file mode 100644
index 0000000..c8db78d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1444.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01444ent IS
+END c08s07b00x00p02n01i01444ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01444arch OF c08s07b00x00p02n01i01444ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+    variable n : integer ;
+  begin
+    if m > 5 then
+      for n in 1 to 5 loop
+        k := k - 1;
+      end loop;
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01444 - FOR LOOP statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01444"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01444arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd
new file mode 100644
index 0000000..636479b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1445.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01445ent IS
+END c08s07b00x00p02n01i01445ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01445arch OF c08s07b00x00p02n01i01445ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+    variable n : time    := 0 ns;
+  begin
+    if m > 5 then
+      n := now;
+      wait for 5 ns;
+      n := now - n;
+    end if;
+    assert NOT(n = 5 ns)
+      report "***PASSED TEST: c08s07b00x00p02n01i01445"
+      severity NOTE;
+    assert (n = 5 ns)
+      report "***FAILED TEST: c08s07b00x00p02n01i01445 - WAIT FOR statement to be sequence statements of IF statement" 
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01445arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd
new file mode 100644
index 0000000..45929ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1446.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01446ent IS
+END c08s07b00x00p02n01i01446ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01446arch OF c08s07b00x00p02n01i01446ent IS
+
+  signal     k : integer := 0;
+begin
+  transmit: process
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      k <= 5;
+    end if;
+    wait for 1 ns;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01446 - Signal Assignment statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01446"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd
new file mode 100644
index 0000000..1ba77d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01447ent IS
+END c08s07b00x00p02n01i01447ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
+
+begin
+  transmit: process
+    procedure ARITH(z  : out integer) is
+    begin
+      z := 5;
+    end ARITH;
+    variable k : integer ;
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      ARITH(k);
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01447"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01447arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd
new file mode 100644
index 0000000..9af36a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1448.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01448ent IS
+END c08s07b00x00p02n01i01448ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01448arch OF c08s07b00x00p02n01i01448ent IS
+
+begin
+  transmit: process
+    procedure ARITH(op : in  integer;
+                    z  : out integer) is
+    begin
+      if (op > 5) then
+        z := 5;
+        return;
+      end if;
+    end ARITH;
+    variable k : integer ;
+    variable m : integer := 6;
+  begin
+    ARITH(m,k);
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01448 - RETURN statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01448"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd
new file mode 100644
index 0000000..962b1e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01450ent IS
+END c08s07b00x00p01n01i01450ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
+
+begin
+  p: process
+    variable j : integer := 1;
+    variable i : integer := 0;   
+    variable k : integer := 0;
+    variable m : integer := 0;
+  begin
+    if    j = 1  then
+      i := 1;
+    elsif j = 2  then
+      k := 1;
+    else
+      m := 1;
+    end if;
+    assert (i = 0) and (k = 1) and (m = 1)
+      report "***PASSED TEST: c08s07b00x00p01n01i01450"
+      severity NOTE;
+    assert NOT((i = 0) and (k = 1) and (m = 1))
+      report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01450arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd
new file mode 100644
index 0000000..9e87805
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1451.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01451ent IS
+END c08s07b00x00p01n01i01451ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01451arch OF c08s07b00x00p01n01i01451ent IS
+
+begin
+  t: process
+    type some2 is (alpha,beta);   
+    variable j : some2 := alpha;
+    variable k : integer := 0;
+  begin
+    if  j = alpha  then
+      k := 1;
+    end if;
+    assert (k = 0)
+      report "***PASSED TEST: c08s07b00x00p01n01i01451"
+      severity NOTE;
+    assert NOT(k = 0)
+      report "***FAILED TEST: c08s07b00x00p01n01i01451 - BOOLEAN expression of IF statement using enumerated types"
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01451arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd
new file mode 100644
index 0000000..bf9bfd5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1452.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01452ent IS
+END c08s07b00x00p01n01i01452ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01452arch OF c08s07b00x00p01n01i01452ent IS
+
+begin
+  expr_check: process
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+    variable k : integer := 0;
+  begin
+    if -x + z < y + x and x * z > y -x then        -- no_failure_here
+      k := 1;
+    end if;
+    assert (k = 1)
+      report "***FAILED TEST: c08s07b00x00p01n01i01452 - expression type of IF statement wrong"
+      severity ERROR;
+    assert NOT(k = 1)
+      report "***PASSED TEST: c08s07b00x00p01n01i01452"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd
new file mode 100644
index 0000000..0b1502c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01456ent IS
+END c08s07b00x00p04n01i01456ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 1 then
+      k := 1;
+    elsif delay = 0 then
+      m := 1;
+    else
+      n := 1;
+    end if;
+    assert NOT((k = 1) and (m = 0) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01456"
+      severity NOTE;
+    assert (k = 1) and (m = 0) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd
new file mode 100644
index 0000000..2526d40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1457.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01457ent IS
+END c08s07b00x00p04n01i01457ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01457arch OF c08s07b00x00p04n01i01457ent IS
+
+BEGIN
+  TESTING : PROCESS
+    variable a    : integer := 1;
+    variable k        : integer := 0;
+    variable m        : integer := 0;
+  BEGIN
+    if    a = 0 then
+      m := 1;
+    elsif a = 1 then
+      k := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT((m = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01457"
+      severity NOTE;
+    assert (m = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01457 - only the condition after the ELSIF statement is TRUE, all others should be FALSE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s07b00x00p04n01i01457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd
new file mode 100644
index 0000000..ac8634a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1458.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01458ent IS
+END c08s07b00x00p04n01i01458ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01458arch OF c08s07b00x00p04n01i01458ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 4 then
+      n := 1;
+    else
+      k := 1;
+    end if;
+    assert NOT((m = 0) and (n = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01458"
+      severity NOTE;
+    assert (m = 0) and (n = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01458 - conditions after the if and elsif are evaluated to be FALSE, so should treat a final else as elsif TRUE then" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd
new file mode 100644
index 0000000..3709c5c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01459ent IS
+END c08s07b00x00p04n01i01459ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 4 then
+      n := 1;
+    end if;
+    assert NOT((m = 0) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01459"
+      severity NOTE;
+    assert (m = 0) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd
new file mode 100644
index 0000000..c765a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc146.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00146pkg is
+  procedure P1 (a : in integer; b: out integer);
+  function  F1 (I : in integer) return real;
+end c04s03b02x02p12n01i00146pkg;
+
+package body c04s03b02x02p12n01i00146pkg is
+  procedure P1 (a: in integer; b: out integer) is
+  begin
+    b := a;
+  end;
+  
+  function  F1 (I: in integer) return real is
+    variable y : real := 1.0;
+  begin
+    return (y * 10.0);
+  end;
+end c04s03b02x02p12n01i00146pkg;
+
+use work.c04s03b02x02p12n01i00146pkg.all;
+ENTITY c04s03b02x02p12n01i00146ent IS
+END c04s03b02x02p12n01i00146ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00146arch OF c04s03b02x02p12n01i00146ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : real := 1.0;
+    variable y : real ;
+  BEGIN
+    P1 (10, F1(b) => x );   -- no_failure_here                
+    -- b and x have the same type.
+    y := x;
+    assert NOT(y=10.0)
+      report "***PASSED TEST: c04s03b02x02p12n01i00146"
+      severity NOTE;
+    assert (y=10.0)
+      report "***FAILED TEST: c04s03b02x02p12n01i00146 - Element of an association list has a function act on it within the association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00146arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd
new file mode 100644
index 0000000..3e54918
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1460.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01460ent IS
+END c08s07b00x00p04n01i01460ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01460arch OF c08s07b00x00p04n01i01460ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    else
+      k := 1;
+    end if;
+    assert NOT((m = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01460"
+      severity NOTE;
+    assert (m = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01460 - conditions after the if is evalusted to be FALSE, so should treat a final else as elsif TRUE then" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd
new file mode 100644
index 0000000..58fa236
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1461.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01461ent IS
+END c08s07b00x00p04n01i01461ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01461arch OF c08s07b00x00p04n01i01461ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 1 then
+      k := 1;
+    end if;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s07b00x00p04n01i01461"
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s07b00x00p04n01i01461 - the condition after the IF statement is TRUE in 'if-end if' format"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd
new file mode 100644
index 0000000..93122e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1462.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01462ent IS
+END c08s07b00x00p04n01i01462ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01462arch OF c08s07b00x00p04n01i01462ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+    variable p     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 2 then
+      p := 1;
+    elsif delay = 1 then
+      k := 1;
+    else
+      n := 1;
+    end if;
+    assert NOT((m = 0) and (p = 0) and (k = 1) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01462"
+      severity NOTE;
+    assert (m = 0) and (p = 0) and (k = 1) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01462 - only the condition after the second ELSIF statement is TRUE, all others should be FALSE"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd
new file mode 100644
index 0000000..2b0a800
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01463ent IS
+END c08s08b00x00p02n01i01463ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable k : integer := 0;
+  BEGIN
+    case x is
+      when 1 => k := 5;
+      when 2 => NULL;
+      when 3 => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k=5 ) 
+      report "***PASSED TEST: c08s08b00x00p02n01i01463" 
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd
new file mode 100644
index 0000000..45f04e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc147.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00147ent IS
+  PORT ( ii: INOUT integer);
+  FUNCTION addup (i1,i2,i3:INTEGER:=5) RETURN INTEGER IS
+  BEGIN
+    IF (i1 = 0) THEN
+      RETURN (i2+i3);
+    ELSE
+      RETURN addup(i2=>i1*3,i1=>0,i3=>0)+i2+i3;
+    END IF;
+  END;
+END c04s03b02x02p14n01i00147ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00147arch OF c04s03b02x02p14n01i00147ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    ii <= addup(
+      i3=>addup(i3=>-8,i1=>addup(4,2,2),i2=>addup(i1=>0,i2=>0,i3=>0)),
+      i1=>addup(
+        i2=>addup(
+          i2=>addup(i2=>6,i3=>7),
+          i1=>addup(i3=>3,i1=>1,i2=>2),
+          i3=>addup(i2=>8,i3=>9,i1=>7)
+          ),
+        i1=>addup(i2=>2,i1=>1,i3=>3),
+        i3=>addup(i2=>a2,i3=>a3,i1=>a1)
+        ),
+      i2=>addup(i3=>-8,i2=>0,i1=>8)
+      );
+    WAIT FOR 1 ns;
+    assert NOT(ii=1346) 
+      report "***PASSED TEST: c04s03b02x02p14n01i00147"
+      severity NOTE;
+    assert (ii=1346) 
+      report "***FAILED TEST: c04s03b02x02p14n01i00147 - Function call does not use function call in parameter list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd
new file mode 100644
index 0000000..b2feed6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1473.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01473ent IS
+END c08s08b00x00p04n01i01473ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01473arch OF c08s08b00x00p04n01i01473ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : character := 'C';
+  BEGIN
+    case i is
+      when 'C' => k := 5;
+      when 'L' => NULL;
+      when 'S' => NULL;
+      when 'I' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01473"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01473 - expression of one dimension character array  type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01473arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd
new file mode 100644
index 0000000..5f120cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1474.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01474ent IS
+END c08s08b00x00p04n01i01474ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01474arch OF c08s08b00x00p04n01i01474ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : BIT     := '0';
+  BEGIN
+    case i is
+      when '0' => k := 5;
+      when '1' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01474"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01474 - expression of enumeration type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd
new file mode 100644
index 0000000..dc84b9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1475.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01475ent IS
+END c08s08b00x00p04n01i01475ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01475arch OF c08s08b00x00p04n01i01475ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : BIT     := '0';
+  BEGIN
+    case i is
+      when '0' => k := 5;
+      when '1' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01475"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01475 - expression of integer type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd
new file mode 100644
index 0000000..55abf23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc148.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00148ent IS
+END c04s03b02x02p14n01i00148ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00148arch OF c04s03b02x02p14n01i00148ent IS
+
+  FUNCTION FLOAT ( ival : in integer) return real is
+    VARIABLE v1 : real := 543.0;
+  begin
+    RETURN v1;
+  end FLOAT;
+
+  FUNCTION ROUND ( rval : in real) return integer is
+    VARIABLE v1 : integer := 543;
+  begin
+    RETURN v1;
+  end ROUND;
+  
+  PROCEDURE test_bed
+    ( in1  : in  integer;
+      out1 : out real ) is
+  begin
+    out1 := FLOAT (in1);
+  end test_bed;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var1 : real;
+    VARIABLE var2 : real := 543.2;
+  BEGIN
+    test_bed ( in1  => ROUND (var2),
+               out1 => var1   );
+    assert NOT( var1 = 543.0 )
+      report "***PASSED TEST: c04s03b02x02p14n01i00148"
+      severity NOTE;
+    assert ( var1 = 543.0 )
+      report "***FAILED TEST: c04s03b02x02p14n01i00148 - The actual part of a named element association may be in the form of a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00148arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd
new file mode 100644
index 0000000..2075f49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01483ent IS
+END c08s08b00x00p04n03i01483ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 2;
+  BEGIN
+    case i is
+      when 1 | 2   =>   k := 5;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01483"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd
new file mode 100644
index 0000000..71b3149
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1485.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01485ent IS
+END c08s08b00x00p04n03i01485ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01485arch OF c08s08b00x00p04n03i01485ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : severity_level := NOTE;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when severity_level'low | severity_level'high   =>   k := 5;
+      when others               =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01485"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01485 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd
new file mode 100644
index 0000000..40dca66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1486.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01486ent IS
+END c08s08b00x00p04n03i01486ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01486arch OF c08s08b00x00p04n03i01486ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : character := 'j';
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when 'a'|'b'|'c'|'d'|'j' =>   k := 5;
+      when 'e'|'f'|'g'|'h'|'i' =>   k := 4;
+      when others       =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01486"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01486 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd
new file mode 100644
index 0000000..e78ab79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1487.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01487ent IS
+END c08s08b00x00p04n03i01487ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01487arch OF c08s08b00x00p04n03i01487ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     t_enum1 is (en1, en2, en3, en4);
+    variable m : t_enum1 := en1;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when en1 | en2 =>   k := 5;
+      when en3 | en4 =>   k := 4;
+      when others    =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01487"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01487 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd
new file mode 100644
index 0000000..f81c251
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1488.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01488ent IS
+END c08s08b00x00p04n03i01488ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01488arch OF c08s08b00x00p04n03i01488ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : integer := 7;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when integer'Low to -11 | 6 to 100 =>   k := 5;
+      when others    =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01488"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01488 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01488arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd
new file mode 100644
index 0000000..869e7c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00149ent IS
+  PORT ( ii: INOUT integer);
+  PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
+  BEGIN
+    IF add THEN
+      i4 := (i1+i2+i3);
+    ELSE
+      i4 := (i1-i2)-i3;
+    END IF;
+  END;
+END c04s03b02x02p14n01i00149ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE a1 : INTEGER := 57;
+    VARIABLE a11: INTEGER := 57;
+    VARIABLE a12: INTEGER := 57;
+    VARIABLE a13: INTEGER := 57;
+    VARIABLE a2 : INTEGER := 68;
+    VARIABLE a3 : INTEGER := 77;
+    VARIABLE b1 : BIT := '1';
+    VARIABLE b2 : BIT := '0';
+    FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
+    BEGIN
+      IF (inp > 0) THEN
+        RETURN (TRUE);
+      ELSE
+        RETURN (FALSE);
+      END IF;
+    END;
+    FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
+    BEGIN
+      IF (inp = '1') THEN
+        RETURN (22);
+      ELSE
+        RETURN (23);
+      END IF;
+    END;
+
+  BEGIN
+    WAIT FOR 1 ns;
+    addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
+    WAIT FOR 1 ns;
+    IF (a1 = 102) THEN
+      ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
+    WAIT FOR 1 ns;
+    IF (a11 = 7) THEN
+      ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
+    WAIT FOR 1 ns;
+    IF (a12 = 67) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(15,5,5,convb(-1),a13);
+    WAIT FOR 1 ns;
+    IF (a13 = 5) THEN
+      ASSERT false REPORT "PASS: No named association used" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    WAIT FOR 1 ns;
+
+    assert NOT(   a1 = 102   and
+                  a11= 7      and
+                  a12= 67      and
+                  a13= 5      )
+      report "***PASSED TEST: c04s03b02x02p14n01i00149"
+      severity NOTE;
+    assert (   a1 = 102   and
+               a11= 7      and
+               a12= 67      and
+               a13= 5      )
+      report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd
new file mode 100644
index 0000000..d06c340
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1491.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p05n01i01491ent IS
+END c08s08b00x00p05n01i01491ent;
+
+ARCHITECTURE c08s08b00x00p05n01i01491arch OF c08s08b00x00p05n01i01491ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x is (Jan,Feb,Mar);
+    variable y:x := Jan;
+    variable k   : integer := 5;
+
+  BEGIN
+    case y is
+      when Jan   => k := 5;
+      when Feb   => NULL;
+      when Mar   => NULL;
+    end case;
+
+    assert NOT( k = 5 ) 
+      report "***PASSED TEST: c08s08b00x00p05n01i01491"
+      severity NOTE;
+    assert ( k = 5 ) 
+      report "***FAILED TEST: c08s08b00x00p05n01i01491 - each value of the subtype of the object of scalar type is represented only once in the set of choices of the case statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p05n01i01491arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd
new file mode 100644
index 0000000..d9c8b9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1493.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p07n01i01493ent IS
+END c08s08b00x00p07n01i01493ent;
+
+ARCHITECTURE c08s08b00x00p07n01i01493arch OF c08s08b00x00p07n01i01493ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Scal is array (0 to 1) of CHARACTER;
+    variable kk : Scal    := "TH"; 
+    variable k  : integer := 0;
+  BEGIN
+    case kk is
+      when "TH"   =>   k := 5;
+      when "AB"   =>    NULL;
+      when others   =>   NULL;
+    end case; 
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p07n01i01493"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p07n01i01493 - case expression is the name of an object whose subtype is locally static, when it is a one-dimensional character array type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p07n01i01493arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd
new file mode 100644
index 0000000..67af127
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1495.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p09n01i01495ent IS
+END c08s08b00x00p09n01i01495ent;
+
+ARCHITECTURE c08s08b00x00p09n01i01495arch OF c08s08b00x00p09n01i01495ent IS
+  SUBTYPE string_30 is STRING(1 to 30);
+  SUBTYPE string_4  is STRING(1 to 4);
+BEGIN
+  TESTING: PROCESS
+    VARIABLE str : string_30 := "1234567890abcdefghijlkmnopqrst";
+    variable k   : integer   := 0;
+  BEGIN
+    case string_4'(str(1 to 4)) is
+      when "1234" =>   k := 5; 
+      when OTHERS =>   k := 6; 
+    end case;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s08b00x00p09n01i01495" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s08b00x00p09n01i01495 - Expression being a qualified expression failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p09n01i01495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd
new file mode 100644
index 0000000..7caf885
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1496.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01496ent IS
+END c08s08b00x00p14n01i01496ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01496arch OF c08s08b00x00p14n01i01496ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable p : integer := 0;
+  BEGIN
+    case p is
+      when 0      =>   k := 5;
+      when 1      =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n01i01496"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n01i01496 - Simple expression and discrete range given as choice in a case statement must be locally static"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd
new file mode 100644
index 0000000..ed07f0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1497.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01497ent IS
+END c08s08b00x00p14n01i01497ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01497arch OF c08s08b00x00p14n01i01497ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable p : integer := 20;
+  BEGIN
+    case p>=20 and p<30 is
+      when TRUE   =>   k := 5;
+      when FALSE   =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n01i01497"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n01i01497 - Case expression may be a complex static expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01497arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd
new file mode 100644
index 0000000..8bc5cf8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01499ent IS
+END c08s08b00x00p14n01i01499ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype sub_int is integer range 1 to 2;
+    variable V1 : integer;
+    variable k1 : integer := 0;
+    variable k2 : integer := 0;
+    variable k3 : integer := 0;
+    variable k4 : integer := 0;
+  BEGIN
+    V1 := 0;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => assert (false)
+                             report "V1 in specified range"
+                             severity failure;
+      when others       => k1 := 1;
+    end case;
+    V1 := 1;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => k2 := 1;
+      when others       => assert (false)
+                             report "V1 NOT in specified range"
+                             severity failure;
+    end case;
+    V1 := 2;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => k3 := 1;
+      when others       => assert (false)
+                             report "V1 NOT in specified range"
+                             severity failure;
+    end case;
+    V1 := 3;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => assert (false)
+                             report "V1 in specified range"
+                             severity failure;
+      when others       => k4 := 1;
+    end case;
+    assert NOT(k1=1 and k2=1 and k3=1 and k4=1) 
+      report "***PASSED TEST: c08s08b00x00p14n01i01499" 
+      severity NOTE;
+    assert (k1=1 and k2=1 and k3=1 and k4=1) 
+      report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd
new file mode 100644
index 0000000..17f35f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p06n01i00015ent IS
+END c04s02b00x00p06n01i00015ent;
+
+ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    subtype   tboolean    is boolean       range FALSE to TRUE;
+    subtype tbit      is bit         range '0'   to '1';   
+    subtype tcharacter   is character      range 'A'   to 'Z';
+    subtype tseverity_level   is severity_level   range NOTE  to ERROR;
+    subtype tinteger   is integer      range 1111  to 2222;
+    subtype treal      is real         range 1.11  to 2.22;
+    subtype ttime      is time         range 1 ns  to 1 hr;
+    subtype tnatural   is natural      range 100   to 200;
+    subtype tpositive   is positive      range 1000  to 2000;
+
+    variable k1  : tboolean;
+    variable k2  : tbit;
+    variable k3  : tcharacter;
+    variable k4  : tseverity_level;
+    variable k5  : tinteger;
+    variable k6  : treal;
+    variable k7  : ttime;
+    variable k8  : tnatural;
+    variable k9  : tpositive;
+
+  BEGIN
+    assert NOT(   k1   = tboolean'left      and
+                  k2   = tbit'left       and
+                  k3   = tcharacter'left   and
+                  k4   = tseverity_level'left   and
+                  k5   = tinteger'left      and
+                  k6   = treal'left      and
+                  k7   = ttime'left      and
+                  k8   = tnatural'left      and
+                  k9   = tpositive'left   )
+      report "***PASSED TEST: c04s02b00x00p06n01i00015"
+      severity NOTE;
+    assert (   k1   = tboolean'left      and
+               k2   = tbit'left       and
+               k3   = tcharacter'left   and
+               k4   = tseverity_level'left   and
+               k5   = tinteger'left      and
+               k6   = treal'left      and
+               k7   = ttime'left      and
+               k8   = tnatural'left      and
+               k9   = tpositive'left   )
+      report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p06n01i00015arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd
new file mode 100644
index 0000000..94b0905
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00150ent IS
+END c04s03b02x02p14n01i00150ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
+
+  FUNCTION FLOAT ( ival : in integer) return real is
+    VARIABLE v1 : real := 543.0;
+  begin
+    RETURN v1;
+  end FLOAT;
+
+  FUNCTION ROUND ( rval : in real) return integer is
+    VARIABLE v1 : integer := 543;
+  begin
+    RETURN v1;
+  end ROUND;
+  
+  PROCEDURE test_bed
+    ( in1  : in  integer;
+      out1 : out real )
+  is
+  begin
+    out1 := FLOAT (in1);
+  end test_bed;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var1 : real;
+    VARIABLE var2 : real := 543.2;
+  BEGIN
+    test_bed ( ROUND (var2), var1 );
+    assert NOT( var1 = 543.0 )
+      report "***PASSED TEST:c04s03b02x02p14n01i00150"
+      severity NOTE;
+    assert ( var1 = 543.0 )
+      report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00150arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd
new file mode 100644
index 0000000..50a4e74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1500.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n02i01500ent IS
+END c08s08b00x00p14n02i01500ent;
+
+ARCHITECTURE c08s08b00x00p14n02i01500arch OF c08s08b00x00p14n02i01500ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 5;
+  BEGIN
+    case i is
+      when 1  to 19   => k := 5;
+      when 20 to 29   => NULL;
+      when 30 to 39   => NULL;
+      when others   => NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n02i01500"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n02i01500 - A choice defined by a discrete range stands for all values in the corresponding range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n02i01500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd
new file mode 100644
index 0000000..bf5a3d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1505.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n03i01505ent IS
+END c08s08b00x00p14n03i01505ent;
+
+ARCHITECTURE c08s08b00x00p14n03i01505arch OF c08s08b00x00p14n03i01505ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 19;
+    variable k : integer := 0;
+  BEGIN
+    case x is
+      when others    =>   k:=5;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n03i01505"
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s08b00x00p14n03i01505 - OTHERS choice may stand foe the full set of values of the expression in a case statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n03i01505arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd
new file mode 100644
index 0000000..e6adcb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1507.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p16n01i01507ent IS
+END c08s08b00x00p16n01i01507ent;
+
+ARCHITECTURE c08s08b00x00p16n01i01507arch OF c08s08b00x00p16n01i01507ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable s1, s2, s3, s4, s5, s6 : INTEGER := 0;
+  BEGIN
+
+    for i in 1 to 1000 loop
+      case i is
+        when 1 =>                           s1 := s1 + 1;
+        when 2 | 3 =>                       s2 := s2 + 1;
+        when 4 to 100 =>                    s3 := s3 + 1;
+        when 200 to 201 | 300 to 350 =>     s4 := s4 + 1;
+        when 400 to 450 =>                  s5 := s5 + 1;
+        when others =>                      s6 := s6 + 1;
+      end case;
+    end loop;
+    wait for 5 ns;
+    assert NOT(    s1 = 1   and
+                   s2 = 2   and
+                   s3 = 97   and
+                   s4 = 2 + 51   and
+                   s5 = 51   and
+                   s6 = 1000 - (s1+s2+s3+s4+s5)   )
+      report "***PASSED TEST: c08s08b00x00p16n01i01507"
+      severity NOTE;
+    assert (    s1 = 1   and
+                s2 = 2   and
+                s3 = 97   and
+                s4 = 2 + 51   and
+                s5 = 51   and
+                s6 = 1000 - (s1+s2+s3+s4+s5)   )
+      report "***FAILED TEST: c08s08b00x00p16n01i01507 - Case statement execution test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p16n01i01507arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd
new file mode 100644
index 0000000..ce5840e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1508.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01508ent IS
+END c08s09b00x00p02n01i01508ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01508arch OF c08s09b00x00p02n01i01508ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    loop
+      k := k + 1;
+      if k > 500 then
+        exit;
+      end if;
+    end loop;
+
+    assert FALSE 
+      report "***PASSED TEST: c08s09b00x00p02n01i01508"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01508arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd
new file mode 100644
index 0000000..166adb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1509.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01509ent IS
+END c08s09b00x00p02n01i01509ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01509arch OF c08s09b00x00p02n01i01509ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    L1 :
+    while counter < 10 loop
+      counter := counter + 1;
+    end loop L1;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01509"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01509 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01509arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd
new file mode 100644
index 0000000..6046b3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1510.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01510ent IS
+END c08s09b00x00p02n01i01510ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01510arch OF c08s09b00x00p02n01i01510ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    while counter < 10 loop
+      counter := counter + 1;
+    end loop;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01510"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01510 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01510arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd
new file mode 100644
index 0000000..bc852e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1511.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01511ent IS
+END c08s09b00x00p02n01i01511ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01511arch OF c08s09b00x00p02n01i01511ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    L2 :
+    for i in 1 to 10 loop
+      counter := counter + 1;
+    end loop L2;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01511"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01511 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01511arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd
new file mode 100644
index 0000000..851b4fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1512.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01512ent IS
+END c08s09b00x00p02n01i01512ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01512arch OF c08s09b00x00p02n01i01512ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      counter := counter + 1;
+    end loop;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01512"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01512 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01512arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd
new file mode 100644
index 0000000..ba9d1a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1514.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01514ent IS
+END c08s09b00x00p02n01i01514ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01514arch OF c08s09b00x00p02n01i01514ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 5 loop
+      k := k + 1;
+    end loop;
+
+    assert NOT( k = 5 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01514" 
+      severity NOTE;
+    assert ( k = 5 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01514 - Missing reserved word 'end loop' in a loop statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01514arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd
new file mode 100644
index 0000000..d954196
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1516.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p03n01i01516ent IS
+END c08s09b00x00p03n01i01516ent;
+
+ARCHITECTURE c08s09b00x00p03n01i01516arch OF c08s09b00x00p03n01i01516ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MY_WORD is array (0 to 31) of BIT;
+    variable k : integer := 0;
+  BEGIN
+
+    for foo in integer range MY_WORD'range loop
+      k := k + 1;
+    end loop;
+    assert NOT(k = 32) 
+      report "***PASSED TEST: /c08s09b00x00p03n01i01516"
+      severity NOTE;
+    assert (k = 32) 
+      report "***FAILED TEST: c08s09b00x00p03n01i01516 - FOR loop with a discrete range specification"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p03n01i01516arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd
new file mode 100644
index 0000000..7d3a2c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1521.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p05n01i01521ent IS
+END c08s09b00x00p05n01i01521ent;
+
+ARCHITECTURE c08s09b00x00p05n01i01521arch OF c08s09b00x00p05n01i01521ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    T:
+    while k < 5 loop
+      k := k + 1;
+    end loop T;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s09b00x00p05n01i01521"
+      severity NOTE; 
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s09b00x00p05n01i01521 - Syntax of a labeled while loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p05n01i01521arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd
new file mode 100644
index 0000000..492b76d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1522.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p07n01i01522ent IS
+END c08s09b00x00p07n01i01522ent;
+
+ARCHITECTURE c08s09b00x00p07n01i01522arch OF c08s09b00x00p07n01i01522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L1 : Loop
+      k := k + 1;
+      if (k = 20) then
+        assert FALSE
+          report "PASSED TEST: c08s09b00x00p07n01i01522 - test executing indefinetely"
+          severity NOTE;
+      end if;
+      if (k > 50) then
+        exit;
+      end if;
+    end loop L1;
+    assert ( k<50 )
+      report "***PASSED TEST: c08s09b00x00p07n01i01522 - Loop statement without an iteration scheme specifies repeated execution of the statement"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p07n01i01522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd
new file mode 100644
index 0000000..b44e6e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1523.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s09b00x00p07n01i01523pkg is
+
+  -- Global procedure.
+  procedure proc1;
+
+  -- Global function.
+  function  func1 return INTEGER;
+
+end c08s09b00x00p07n01i01523pkg;
+
+package body c08s09b00x00p07n01i01523pkg is
+
+  procedure proc1 is
+    -- Local variables
+    variable  INTV  : INTEGER := 0;
+
+  begin
+    -- Check initialization.
+    assert (INTV = 0);
+
+    -- Loop until the indicated condition has been met.
+    loop
+      -- Execute some meaningful function.
+      null;
+
+      -- Increment the counter.
+      INTV := INTV + 1;
+
+      -- If the condition has been met, terminate the loop.
+      if  (INTV = 10) then
+        return;
+      end if;
+
+      -- Verify that we have not exceeded the limits of the loop.
+      assert (INTV < 10);
+    end loop;
+    
+    -- Should NEVER get to this step.
+    assert (FALSE)
+      report "Return has not exited the procedure.";
+  end proc1;
+  
+  function func1 return INTEGER is
+    -- Local variables
+    variable  INTV  : INTEGER := 0;
+    
+  begin
+    -- Check initialization.
+    assert (INTV = 0);
+    
+    -- Loop until the indicated condition has been met.
+    loop
+      -- Execute some meaningful function.
+      null;
+      -- Increment the counter.
+      INTV := INTV + 1;
+      
+      -- If the condition has been met, terminate the loop.
+      if  (INTV = 10) then
+        return( INTV );
+      end if;
+      
+      -- Verify that we have not exceeded the limits of the loop.
+      assert (INTV < 10);
+    end loop;
+    
+    -- Should NEVER get to this step.
+    assert (FALSE)
+      report "Return has not exited the procedure.";
+  end func1;
+  
+end c08s09b00x00p07n01i01523pkg;
+
+use work.c08s09b00x00p07n01i01523pkg.all;
+ENTITY c08s09b00x00p07n01i01523ent IS
+END c08s09b00x00p07n01i01523ent;
+
+ARCHITECTURE c08s09b00x00p07n01i01523arch OF c08s09b00x00p07n01i01523ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    -- Call procedure to loop/return.
+    proc1;
+    
+    assert NOT(func1=10)
+      report "***PASSED TEST: c08s09b00x00p07n01i01523" 
+      severity NOTE;
+    assert (func1=10)
+      report "***PASSED TEST: c08s09b00x00p07n01i01523 - Function did not return proper value." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p07n01i01523arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd
new file mode 100644
index 0000000..7619eb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1524.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01524ent IS
+END c08s09b00x00p08n01i01524ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01524arch OF c08s09b00x00p08n01i01524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k > 3 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p08n01i01524"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p08n01i01524 - For a loop statement with a while iteration scheme, if the condition is evaluated to be FALSE, the execution of the loop statement is complete"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd
new file mode 100644
index 0000000..64e010a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1529.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01529ent IS
+END c08s09b00x00p08n01i01529ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01529arch OF c08s09b00x00p08n01i01529ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable INTV   : INTEGER := 0;
+    variable COUNTV : INTEGER := 0;
+    variable I      : INTEGER := 0;
+    variable   k      : integer := 0;
+  BEGIN
+
+    -- While condition is FALSE, so no stmts are executed.
+    while (FALSE) loop
+      assert (FALSE)
+        report "First loop was executed when it should not have been.";
+      k := 1;
+    end loop;
+
+    -- While condition is FALSE, so no stmts are executed.
+    while (I /= 0) loop
+      assert (FALSE)
+        report "Second loop was executed when it should not have been.";
+      k := 1;
+    end loop;
+
+    -- Verify that loop is executed right number of times.
+    COUNTV := 0;
+    while (I /= 10) loop
+      I := I + 1;
+      COUNTV := COUNTV + 1;
+    end loop;
+    if (I /= 10 and COUNTV /= 10) then
+      k := 1;
+    end if;
+    assert (I = 10);
+    assert (COUNTV = 10);
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s09b00x00p08n01i01529"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s09b00x00p08n01i01529 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd
new file mode 100644
index 0000000..8fa6eb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1530.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n01i01530ent IS
+END c08s09b00x00p09n01i01530ent;
+
+ARCHITECTURE c08s09b00x00p09n01i01530arch OF c08s09b00x00p09n01i01530ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable VAR    : REAL := 0.0;
+    variable k : integer := 0;
+  BEGIN
+    -- Outer scope's declaration of VAR is of type REAL.
+    assert (VAR = 0.0);
+    if (VAR /= 0.0) then
+      k := 1;
+    end if;
+
+    -- Loop using VAR as an integer.
+    for VAR in 0 to 10 loop
+      -- Verify that inner declaration is of type INTEGER.
+      assert (VAR <= 10);
+      if (VAR > 10) then
+        k := 1;
+      end if;
+    end loop;
+
+    -- Outer scope's declaration of VAR is of type REAL.
+    assert (VAR = 0.0);
+    if (VAR /= 0.0) then
+      k := 1;
+    end if;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p09n01i01530"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p09n01i01530 - The loop parameter specification is the declaration of the loop parameter with a given identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n01i01530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd
new file mode 100644
index 0000000..6968c26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1531.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n02i01531ent IS
+END c08s09b00x00p09n02i01531ent;
+
+ARCHITECTURE c08s09b00x00p09n02i01531arch OF c08s09b00x00p09n02i01531ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    type    MYFAVS is (RED, YELLOW, GREEN);
+
+    -- variable declarations.
+    variable COLSLOW      : COLORS := RED;
+    variable COLSHIGH     : COLORS := GREEN;
+    variable FAVSLOW      : MYFAVS := RED;
+    variable FAVSHIGH     : MYFAVS := GREEN;
+
+    variable k : integer := 0;
+  BEGIN
+    -- This loop should be fine.
+    for I in COLSLOW to COLSHIGH loop
+      if not((I >= COLSLOW) and (I <= COLSHIGH)) then
+        k := 1;
+      end if;
+    end loop;
+
+    -- This loop should be fine.
+    for I in FAVSLOW to FAVSHIGH loop
+      if not((I >= FAVSLOW) and (I <= FAVSHIGH)) then
+        k := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p09n02i01531"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p09n02i01531 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n02i01531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd
new file mode 100644
index 0000000..fbf25ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1536.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n03i01536ent IS
+END c08s09b00x00p09n03i01536ent;
+
+ARCHITECTURE c08s09b00x00p09n03i01536arch OF c08s09b00x00p09n03i01536ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 10;
+  BEGIN
+    for i in 1 to 5 loop
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p09n03i01536"
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s09b00x00p09n03i01536 -  The loop parameter can be the source of an assignment statement (but not the target)" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n03i01536arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd
new file mode 100644
index 0000000..435e069
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1539.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01539ent IS
+END c08s09b00x00p10n01i01539ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01539arch OF c08s09b00x00p10n01i01539ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 5 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01539"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01539 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01539arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd
new file mode 100644
index 0000000..764c204
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc154.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p16n01i00154pkg is
+  procedure P1 (a  : in integer; b: inout integer);
+  function  F1 (I1 : in integer) return real;
+  function  F2 (I2 : in real) return integer;
+end c04s03b02x02p16n01i00154pkg;
+
+package body c04s03b02x02p16n01i00154pkg is
+  procedure P1 (a  : in integer; b: inout integer) is
+  begin
+    b := a;
+  end P1;
+
+  function  F1 (I1 : in integer) return real is
+  begin
+    return 10.0;
+  end F1;
+
+  function  F2 (I2 : in real) return integer is
+  begin
+    return 10;
+  end F2;
+end c04s03b02x02p16n01i00154pkg;
+
+
+use work.c04s03b02x02p16n01i00154pkg.all;
+ENTITY c04s03b02x02p16n01i00154ent IS
+END c04s03b02x02p16n01i00154ent;
+
+ARCHITECTURE c04s03b02x02p16n01i00154arch OF c04s03b02x02p16n01i00154ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : real := 1.0;
+  BEGIN
+    P1 (10, F1(b) => F2(x));  -- No_failure_here
+    assert NOT(F2(x) = 10)
+      report "***PASSED TEST: c04s03b02x02p16n01i00154"
+      severity NOTE;
+    assert (F2(x) = 10)
+      report "***FAILED TEST: c04s03b02x02p16n01i00154 - Types of the actuals match those of the formals test failed.."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n01i00154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd
new file mode 100644
index 0000000..168deff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01540ent IS
+END c08s09b00x00p10n01i01540ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for j in 1 to 100 loop
+      for i in 1 to 5 loop
+        k := k + 1;
+      end loop;
+    end loop;
+    assert NOT( k=500 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01540"
+      severity NOTE;
+    assert ( k=500 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01540arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd
new file mode 100644
index 0000000..33618c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1543.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01543ent IS
+END c08s09b00x00p10n01i01543ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01543arch OF c08s09b00x00p10n01i01543ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in boolean loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01543" 
+      severity NOTE;
+    assert (counter=boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01543 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01543arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd
new file mode 100644
index 0000000..a4a2f02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1544.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01544ent IS
+END c08s09b00x00p10n01i01544ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01544arch OF c08s09b00x00p10n01i01544ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in bit loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01544" 
+      severity NOTE;
+    assert (counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01544 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01544arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd
new file mode 100644
index 0000000..bfe2343
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1545.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01545ent IS
+END c08s09b00x00p10n01i01545ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01545arch OF c08s09b00x00p10n01i01545ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in severity_level loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01545"
+      severity NOTE;
+    assert (counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01545 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01545arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd
new file mode 100644
index 0000000..904fb79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1546.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01546ent IS
+END c08s09b00x00p10n01i01546ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01546arch OF c08s09b00x00p10n01i01546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in character loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=character'Pos(character'High)-character'Pos(character'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01546" 
+      severity NOTE;
+    assert (counter=character'Pos(character'High)-character'Pos(character'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01546 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd
new file mode 100644
index 0000000..1fbdfe7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1547.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01547ent IS
+END c08s09b00x00p10n01i01547ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01547arch OF c08s09b00x00p10n01i01547ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     t_enum1 is (en1, en2, en3, en4) ;
+    subtype  st_enum1 is t_enum1 range en4 downto en1 ;
+    variable counter : integer := 0;
+  BEGIN
+    for i in st_enum1 loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01547" 
+      severity NOTE;
+    assert (counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01547 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01547arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd
new file mode 100644
index 0000000..20b58fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01548ent IS
+END c08s09b00x00p10n01i01548ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    variable k : integer := 0;
+  BEGIN
+
+    -- None of these loops should EVER execute any of their statements.
+    for I in INTEGER'HIGH to 0 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    for I in INTEGER'LOW downto 0 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'HIGH to COLORS'LOW loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop    
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'LOW downto COLORS'HIGH loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01548"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01548arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd
new file mode 100644
index 0000000..a38fa83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd
@@ -0,0 +1,178 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01549ent IS
+END c08s09b00x00p10n01i01549ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    -- local variables
+    variable EXECUTED_ONCE : BOOLEAN;
+    variable COUNT         : INTEGER;
+    variable k : integer := 0;
+  BEGIN
+    -- 1. These for-loops should only execute one time.
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'HIGH to INTEGER'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in first loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'LOW to INTEGER'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in second loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'HIGH downto INTEGER'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in third loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'LOW downto INTEGER'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in fourth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'HIGH to COLORS'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in fifth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'LOW to COLORS'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in sixth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'HIGH downto COLORS'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in seventh loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'LOW downto COLORS'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in eighth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    -- 2. These for-loops should be executed COUNT number of times.
+    COUNT := 0;
+    for I in 3 to 13 loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= 11) then
+      k := 1;
+    end if;
+    assert (COUNT = 11)
+      report "Failing in 9th loop.";
+    
+    COUNT := 0;
+    for I in 13 downto 3 loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= 11) then
+      k := 1;
+    end if;
+    assert (COUNT = 11)
+      report "Failing in 10th loop.";
+    
+    COUNT := 0;
+    for I in COLORS'LOW to COLORS'HIGH loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
+      k := 1;
+    end if;
+    assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
+      report "Failing in 11th loop.";
+    
+    COUNT := 0;
+    for I in COLORS'HIGH downto COLORS'LOW loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
+      k := 1;
+    end if;
+    assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
+      report "Failing in 12th loop.";
+
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01549"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01549arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd
new file mode 100644
index 0000000..5719e98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1550.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01550ent IS
+END c08s09b00x00p10n01i01550ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01550arch OF c08s09b00x00p10n01i01550ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type colors is (red, yellow, blue);
+    variable k : integer := 0;
+  BEGIN
+    --
+    -- Test for loop; loop should initialize
+    -- the loop variable and sequence through
+    -- all three colors if implemented correctly
+    --
+    -- 'c' is declared in the loop parameter spec.
+    --
+    L1: for c in red to blue loop
+      case c is
+        when red =>
+          k := k + 1;
+        when yellow =>
+          k := k + 10;
+        when blue =>
+          k := k + 100;
+        when others =>
+          k := 0;
+      end case;
+    end loop L1;
+
+    assert NOT( k=111 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01550"
+      severity NOTE;
+    assert ( k=111 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01550 - The loop parameter is declared by its appearance in the loop parameter specification and its scope is limited to the loop statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01550arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd
new file mode 100644
index 0000000..c30c0bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1551.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n03i01551ent IS
+END c08s09b00x00p10n03i01551ent;
+
+ARCHITECTURE c08s09b00x00p10n03i01551arch OF c08s09b00x00p10n03i01551ent IS
+
+  type t1 is (a,b);
+  type t2 is (b,c);
+  type t3 is (c,d);
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in c downto b loop
+      k := 5;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p10n03i01551"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s09b00x00p10n03i01551 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n03i01551arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd
new file mode 100644
index 0000000..d2b54ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1552.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n03i01552ent IS
+END c08s09b00x00p10n03i01552ent;
+
+ARCHITECTURE c08s09b00x00p10n03i01552arch OF c08s09b00x00p10n03i01552ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- enumerated type.
+    type    COLORS is (RED, GREEN, BLUE, ORANGE, PINK, GRAY, YELLOW);
+
+    -- local variables
+    variable EXECUTED_ONCE : BOOLEAN;
+    variable LAST_INT      : INTEGER;
+    variable LAST_COLOR    : COLORS;
+
+    variable k : integer := 0;
+  BEGIN
+    -- 1. Test ascending and descending integer discrete ranges.
+    EXECUTED_ONCE := FALSE;
+    LAST_INT := INTEGER'LOW + 1;
+    for I in (INTEGER'LOW+1) to (INTEGER'LOW + 10) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= (integer'low + 1)) then
+          k := 1;
+        end if;
+        assert (I = (INTEGER'LOW+1))
+          report "First value is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (integer'succ(last_int) /= I) then
+          k := 1;
+        end if;
+        assert (INTEGER'SUCC( LAST_INT ) = I)
+          report "Subsequent values are bad.";
+        LAST_INT := I;
+      end if;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    LAST_INT := INTEGER'HIGH - 1;
+    for I in (INTEGER'HIGH-1) downto (INTEGER'HIGH - 10) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= integer'high-1) then
+          k := 1;
+        end if;
+        assert (I = (INTEGER'HIGH-1))
+          report "First value, second loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (integer'pred(last_int) /= I) then
+          k := 1;
+        end if;
+        assert (INTEGER'PRED( LAST_INT ) = I)
+          report "Subsequent values, second loop, are bad.";
+        LAST_INT := I;
+      end if;
+    end loop;
+    
+    -- 2. Test ascending and descending enumerated type ranges.
+    EXECUTED_ONCE := FALSE;
+    LAST_COLOR := COLORS'SUCC( COLORS'LOW );
+    for I in (COLORS'SUCC( COLORS'LOW )) to (COLORS'HIGH) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= colors'succ(colors'low)) then
+          k := 1;
+        end if;
+        assert (I = (COLORS'SUCC( COLORS'LOW )))
+          report "First value, third loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (colors'succ(last_color) /= I) then
+          k := 1;
+        end if;
+        assert (COLORS'SUCC( LAST_COLOR ) = I)
+          report "Subsequent values, third loop, are bad.";
+        LAST_COLOR := I;
+      end if;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    LAST_COLOR := COLORS'PRED( COLORS'HIGH );
+    for I in (COLORS'PRED( COLORS'HIGH )) downto (COLORS'LOW) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= colors'pred(colors'high)) then
+          k := 1;
+        end if;
+        assert (I = (COLORS'PRED( COLORS'HIGH )))
+          report "First value, fourth loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (colors'pred(last_color) /= I) then
+          k := 1;
+        end if;
+        assert (COLORS'PRED( LAST_COLOR ) = I)
+          report "Subsequent values, fourth loop, are bad.";
+        LAST_COLOR := I;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n03i01552"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n03i01552 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n03i01552arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd
new file mode 100644
index 0000000..6ea4d5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1553.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01553ent IS
+END c08s09b00x00p10n01i01553ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01553arch OF c08s09b00x00p10n01i01553ent IS
+  signal VS : STRING(1 to 14) := "This is a test";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in VS'range loop
+      VS <= VS(VS'LEFT + 1 to VS'RIGHT) & '_' after 1 ns;
+      wait for 2 ns;
+    end loop;
+    wait for 5 ns;
+    assert NOT( VS = "______________" )
+      report "***PASSED TEST: c08s09b00x00p10n01i01553"
+      severity NOTE;
+    assert ( VS = "______________" )
+      report "***FAILED TEST: c08s09b00x00p10n01i01553 - The loop parameter is declared by its appearance in the loop parameter specification and its scope is limited to the loop statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01553arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd
new file mode 100644
index 0000000..554ff86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1554.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01554ent IS
+END c08s10b00x00p02n01i01554ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01554arch OF c08s10b00x00p02n01i01554ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p02n01i01554"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s10b00x00p02n01i01554 - A next statement is allowed in a loop without a label"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01554arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd
new file mode 100644
index 0000000..60ca71e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1555.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01555ent IS
+END c08s10b00x00p02n01i01555ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01555arch OF c08s10b00x00p02n01i01555ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L1 : for i in 1 to 10 loop
+      next L1;
+      k := 5;
+    end loop L1;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p02n01i01555"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s10b00x00p02n01i01555 - The when clause is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01555arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd
new file mode 100644
index 0000000..2143938
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01558ent IS
+END c08s10b00x00p03n01i01558ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next L;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01558"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd
new file mode 100644
index 0000000..9f611d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01560ent IS
+END c08s10b00x00p03n01i01560ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable s : integer := 0;
+  BEGIN
+    K : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        next K when ( (j = 3) and (i = 1) );
+        s := s + 1;
+      end loop L;
+    end loop K;
+    assert NOT(s = 90) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01560"
+      severity NOTE;
+    assert (s = 90) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01560arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd
new file mode 100644
index 0000000..ac40569
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1565.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01565ent IS
+END c08s10b00x00p03n01i01565ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01565arch OF c08s10b00x00p03n01i01565ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next when i = 3;
+      k := k + 1;
+    end loop;
+    assert NOT( k=9 ) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01565"
+      severity NOTE;
+    assert ( k=9 ) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01565 - A NEXT statement must be inside a loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd
new file mode 100644
index 0000000..c7cd1e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1566.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01566ent IS
+END c08s10b00x00p03n01i01566ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01566arch OF c08s10b00x00p03n01i01566ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    P : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        next when j = 3;
+        k := k + 1;
+      end loop L;
+    end loop;
+    assert NOT( k=90 ) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01566"
+      severity NOTE;
+    assert ( k=90 ) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01566 - A NEXT statement inside nested FOR loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd
new file mode 100644
index 0000000..84597ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1567.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01567ent IS
+END c08s10b00x00p03n01i01567ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01567arch OF c08s10b00x00p03n01i01567ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 0;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      L2: for j in 1 to 3 loop
+        next L2;
+        k := 3;
+      end loop L2;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01567"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01567 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd
new file mode 100644
index 0000000..6278635
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1568.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01568ent IS
+END c08s10b00x00p03n01i01568ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01568arch OF c08s10b00x00p03n01i01568ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant c_boolean_2 : boolean := true;
+    variable v_boolean   : boolean := false;
+    variable counter     : integer := 0;
+  BEGIN
+    L1 :
+    while v_boolean /= c_boolean_2 loop
+      v_boolean := c_boolean_2 ;
+      for j in 1 to 3 loop
+        next L1 when j = j ;
+      end loop ;
+      counter := counter + 1 ;
+    end loop L1;
+    assert NOT( counter = 0 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01568"
+      severity NOTE;
+    assert ( counter = 0 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01568 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01568arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd
new file mode 100644
index 0000000..11f6552
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1569.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01569ent IS
+END c08s10b00x00p03n01i01569ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01569arch OF c08s10b00x00p03n01i01569ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 0;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      L2: for j in 1 to 3 loop
+        next;
+        k := 3;
+      end loop L2;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01569"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01569 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd
new file mode 100644
index 0000000..b2dac23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc157.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p18n01i00157ent IS
+END c04s03b02x02p18n01i00157ent;
+
+ARCHITECTURE c04s03b02x02p18n01i00157arch OF c04s03b02x02p18n01i00157ent IS
+  TYPE TwoBy3By4Type IS ARRAY (1 TO 2,1 TO 3,1 TO 4) OF integer RANGE 111 TO 234;
+
+  FUNCTION func1(fp1:TwoBy3By4Type:=
+                 (
+                   (  (111,112,113,114),
+                      (121,122,123,124),
+                      (131,132,133,134) ),
+
+                   (  (211,212,213,214),
+                      (221,222,223,224),
+                      (231,232,233,234) )
+                   )) RETURN BOOLEAN;
+
+  FUNCTION func1(fp1:TwoBy3By4Type:=
+                 (
+                   (  (111,112,113,114),
+                      (121,122,123,124),
+                      (131,132,133,134) ),
+
+                   (  (211,212,213,214),
+                      (221,222,223,224),
+                      (231,232,233,234) )
+                   )) RETURN BOOLEAN IS
+    VARIABLE fv1 : TwoBy3By4Type :=
+      (
+        (  (111,112,113,114),
+           (121,122,123,124),
+           (131,132,133,134) ),
+
+        (  (211,212,213,214),
+           (221,222,223,224),
+           (231,232,233,234) )
+        );
+  BEGIN
+    RETURN ((fv1 = fp1) AND (fp1(2,2,3) = 223));
+  END;
+
+BEGIN
+  TESTING: PROCESS
+    
+    VARIABLE v1,v2 : TwoBy3By4Type :=
+      (
+        (  (111,112,113,114),
+           (121,122,123,124),
+           (131,132,133,134) ),
+        
+        (  (211,212,213,214),
+           (221,222,223,224),
+           (231,232,233,234) )
+        );
+    
+  BEGIN
+    wait for 5 ns;
+    assert NOT( func1(v1))
+      report "***PASSED TEST: c04s03b02x02p18n01i00157"
+      severity NOTE;
+    assert ( func1(v1))
+      report "***FAILED TEST: c04s03b02x02p18n01i00157 - Multi-dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p18n01i00157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd
new file mode 100644
index 0000000..28202ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01570ent IS
+END c08s10b00x00p03n01i01570ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer    := 0;
+    variable m : integer    := 0;
+    variable done : boolean := false;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      while not done loop
+        done := true ;
+        next ;
+        k := 3;
+      end loop ;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01570"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd
new file mode 100644
index 0000000..767953c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1571.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01571ent IS
+END c08s10b00x00p03n01i01571ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01571arch OF c08s10b00x00p03n01i01571ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant c_boolean_2 : boolean := true;
+    variable v_boolean   : boolean := false;
+    variable counter     : integer := 0;
+  BEGIN
+    L1 :
+    while v_boolean /= c_boolean_2 loop
+      v_boolean := c_boolean_2 ;
+      for j in 1 to 3 loop
+        next when j = j ;
+      end loop ;
+      counter := counter + 1 ;
+    end loop L1;
+    assert NOT( counter = 1 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01571"
+      severity NOTE;
+    assert ( counter = 1 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01571 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01571arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd
new file mode 100644
index 0000000..aab8f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1572.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01572ent IS
+END c08s10b00x00p03n01i01572ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01572arch OF c08s10b00x00p03n01i01572ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable k    : integer := 0;
+  BEGIN
+    -- TEST1:  Should always go to outer loop.
+    OUTERLOOP:
+    for I in 1 to 10 loop
+
+      INNERLOOP:
+      for J in 1 to 10 loop
+        -- Skip to next iteration of outerloop.
+        next OUTERLOOP;
+
+        k := 1;
+        -- This should never be executed.
+        assert (FALSE)
+          report "Statement should never be executed.";
+      end loop INNERLOOP;
+
+      k := 1;
+      -- This should never be executed.
+      assert (FALSE)
+        report "Statement should never be executed.";
+    end loop OUTERLOOP;
+    
+    -- TEST2:  Should always go to inner loop.
+    -- Set the flag initially.
+    DIDIT := TRUE;
+    
+    -- Execute the loops.
+    OUTERLOOP2:
+    for I in 1 to 10 loop
+      
+      INNERLOOP2:
+      for J in 1 to 10 loop
+        -- Check that last statement of OUTERLOOP2 got done.
+        if  (J = 1) then
+          assert (DIDIT)
+            report "Last statement of OUTERLOOP2 was not executed.";
+          if (DIDIT /= true) then   
+            k := 1;
+          end if;
+          DIDIT := FALSE;
+        end if;
+        
+        -- Skip to next iteration of outerloop.
+        next INNERLOOP2;
+        k := 1; 
+        -- This should never be executed.
+        assert (FALSE)
+          report "Statement should never be executed.";
+      end loop INNERLOOP2;
+      
+      -- This should ALWAYS be executed.
+      DIDIT := TRUE;
+    end loop OUTERLOOP2;
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01572"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01572 - The NEXT statement did not properly associated with the loop whose label it matchs." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01572arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd
new file mode 100644
index 0000000..a7536bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1573.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01573ent IS
+END c08s10b00x00p04n01i01573ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01573arch OF c08s10b00x00p04n01i01573ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next when i > 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s10b00x00p04n01i01573"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s10b00x00p04n01i01573 - The current iteration of the loop is terminated if the value of the condition is TRUE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd
new file mode 100644
index 0000000..2bd2bd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01574ent IS
+END c08s10b00x00p04n01i01574ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next L when i > 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s10b00x00p04n01i01574"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01574arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd
new file mode 100644
index 0000000..87f7d54
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1576.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01576ent IS
+END c08s10b00x00p04n01i01576ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01576arch OF c08s10b00x00p04n01i01576ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable   k     : integer := 0;
+  BEGIN
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      next when FALSE;
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+    
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      next when (CONSTONE /= 1);
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+
+    assert NOT( k=0 ) 
+      report "***PASSED TEST: c08s10b00x00p04n01i01576" 
+      severity NOTE;
+    assert ( k=0 ) 
+      report "***FAILED TEST: c08s10b00x00p04n01i01576 - If the condition in the next statement is FALSE, it should execute the sequence of statements enclosed within the loop condition with the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01576arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd
new file mode 100644
index 0000000..9b1ce80
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc158.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p19n01i00158pkg is
+  type rec_type is
+    record
+      a, b, c : integer;
+    end record;
+  procedure P1 (p : in rec_type; q: in integer; r: out integer);
+end c04s03b02x02p19n01i00158pkg;
+
+package body c04s03b02x02p19n01i00158pkg is
+  procedure P1 (p : in rec_type; q: in integer; r: out integer) is
+  begin
+  end P1;
+end c04s03b02x02p19n01i00158pkg;
+
+use work.c04s03b02x02p19n01i00158pkg.all;
+ENTITY c04s03b02x02p19n01i00158ent IS
+END c04s03b02x02p19n01i00158ent;
+
+ARCHITECTURE c04s03b02x02p19n01i00158arch OF c04s03b02x02p19n01i00158ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 ((a => 1, b => 2, c => 3),      q => 10, r => x);  -- No_failure_here
+    P1 (p => (a => 1, b => 2, c => 3), q => 10, r => x);  -- No_failure_here
+    P1 (p.a => 1, p.b => 2, p.c => 3,  q => 10, r => x);  -- No_failure_here
+    P1 (p => (1, 2, 3),                q => 10, r => x);  -- No_failure_here
+    assert FALSE
+      report "***PASSED TEST: c04s03b02x02p19n01i00158"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p19n01i00158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd
new file mode 100644
index 0000000..0db6f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1581.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01581ent IS
+END c08s11b00x00p02n01i01581ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01581arch OF c08s11b00x00p02n01i01581ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      exit when i = 6;
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01581"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01581 - Exit statement consists of the reserved word 'exit' and optionally the reserved word 'when' followed by a condition "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01581arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd
new file mode 100644
index 0000000..ff436c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1582.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01582ent IS
+END c08s11b00x00p02n01i01582ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01582arch OF c08s11b00x00p02n01i01582ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+  BEGIN
+    while i < 10 loop
+      exit when i = 5;
+      i := i + 1;
+    end loop;
+    assert NOT( i=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01582"
+      severity NOTE;
+    assert ( i=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01582 - Exit statement consists of the reserved word 'exit' and optionally the reserved word 'when' followed by a condition "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01582arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd
new file mode 100644
index 0000000..2334510
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1583.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01583ent IS
+END c08s11b00x00p02n01i01583ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01583arch OF c08s11b00x00p02n01i01583ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k < 10 loop
+      exit ;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01583"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01583 - The when clause in the exit statement is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01583arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd
new file mode 100644
index 0000000..295cfbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01585ent IS
+END c08s11b00x00p02n01i01585ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k < 10 loop
+      exit when k = 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01585"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01585arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd
new file mode 100644
index 0000000..e3b5a7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1587.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01587ent IS
+END c08s11b00x00p03n01i01587ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01587arch OF c08s11b00x00p03n01i01587ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      k := i;
+      exit L;
+    end loop;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01587"
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01587 - A loop label is allowed within a labeled loop."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01587arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd
new file mode 100644
index 0000000..15b1f13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1589.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01589ent IS
+END c08s11b00x00p03n01i01589ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01589arch OF c08s11b00x00p03n01i01589ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    K : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        exit K when j = 3;
+        p := p + 1;
+      end loop L;
+    end loop;
+    assert NOT( p = 20 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01589"
+      severity NOTE;
+    assert ( p = 20 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01589 - An exit statement with a loop label within a labeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01589arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd
new file mode 100644
index 0000000..66a0ab7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1594.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01594ent IS
+END c08s11b00x00p03n01i01594ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01594arch OF c08s11b00x00p03n01i01594ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      k := i;
+      exit;
+    end loop;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01594" 
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01594 - A exit statement inside a FOR loop without a loop label" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01594arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd
new file mode 100644
index 0000000..1cec019
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1596.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01596ent IS
+END c08s11b00x00p03n01i01596ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01596arch OF c08s11b00x00p03n01i01596ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    L : for j in 1 to 10 loop
+      K : for i in 1 to 20 loop
+        exit when j = 5;
+        p := p + 1;
+      end loop K;
+    end loop;
+    assert NOT( p=180 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01596"
+      severity NOTE;
+    assert ( p=180 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01596 - Exit applies only to inner loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01596arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd
new file mode 100644
index 0000000..8ad4755
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01597ent IS
+END c08s11b00x00p03n01i01597ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    L1 :
+    for i in boolean loop
+      p := 5 + p;
+      L2 :
+      for j in 1 to 3 loop
+        exit ;
+        p := 0;
+      end loop L2 ;
+    end loop L1;
+    assert NOT( p=10 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01597" 
+      severity NOTE;
+    assert ( p=10 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01597arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd
new file mode 100644
index 0000000..90aebb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1598.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01598ent IS
+END c08s11b00x00p03n01i01598ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01598arch OF c08s11b00x00p03n01i01598ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p    : integer := 0;
+    variable done    : boolean := false;
+  BEGIN
+    L1 : for i in boolean loop
+      while not done loop
+        done := true ;
+        exit ;
+        p := 0;
+      end loop ;
+      p := p + 1;
+    end loop L1;
+    assert NOT( p=2 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01598" 
+      severity NOTE;
+    assert ( p=2 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01598 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01598arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd
new file mode 100644
index 0000000..6743b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1599.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01599ent IS
+END c08s11b00x00p03n01i01599ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01599arch OF c08s11b00x00p03n01i01599ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable done       : boolean := false;
+    variable v_boolean : boolean := false;
+  BEGIN
+    L1 : while v_boolean /= boolean'High loop
+      while not done loop
+        done := true ;
+        exit ;
+        p := 0;
+      end loop ;
+      p := p + 1;
+      v_boolean := boolean'Succ(v_boolean);
+    end loop L1;
+    assert NOT( p=1 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01599"
+      severity NOTE;
+    assert ( p=1 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01599 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01599arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
new file mode 100644
index 0000000..7c7a958
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc16.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p06n03i00016ent IS
+END c04s02b00x00p06n03i00016ent;
+
+ARCHITECTURE c04s02b00x00p06n03i00016arch OF c04s02b00x00p06n03i00016ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype of a subtype.
+    subtype ZERO is NATURAL;
+
+    -- Define variables of these subtypes.
+    variable ZEROV     : ZERO := 0;
+    variable NATURALV  : NATURAL := 0;
+  BEGIN
+    -- Verify that these two variables have the same base type.
+    assert NOT( Naturalv = zerov and zerov = zero'low )
+      report "***PASSED TEST: c04s02b00x00p06n03i00016"
+      severity NOTE;
+    assert ( Naturalv = zerov and zerov = zero'low )
+      report "***FAILED TEST: c04s02b00x00p06n03i00016 - The base type of a subtype is the base type of the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p06n03i00016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd
new file mode 100644
index 0000000..c1b3691
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1600.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01600ent IS
+END c08s11b00x00p03n01i01600ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01600arch OF c08s11b00x00p03n01i01600ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable done       : boolean := false;
+    variable v_boolean : boolean := false;
+  BEGIN
+    L1 : while v_boolean /= boolean'High loop
+      for j in 1 to 3 loop
+        exit;
+        p := 0;
+      end loop;
+      p := p + 1;
+      v_boolean := boolean'Succ(v_boolean);
+    end loop L1;
+    assert NOT( p=1 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01600" 
+      severity NOTE;
+    assert ( p=1 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01600 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01600arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd
new file mode 100644
index 0000000..1ea6957
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01601ent IS
+END c08s11b00x00p03n01i01601ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable counter   : integer := 0;
+  BEGIN
+    L1 :
+    for i in boolean loop
+      L2 :
+      for j in 1 to 3 loop
+        exit L2 ;
+        p := 5 ;
+      end loop L2 ;
+      counter := counter + 1 ;
+    end loop L1 ;
+    assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1))) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01601" 
+      severity NOTE;
+    assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1))) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01601arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd
new file mode 100644
index 0000000..e650aa7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1603.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01603ent IS
+END c08s11b00x00p04n01i01603ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01603arch OF c08s11b00x00p04n01i01603ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when i = 6;
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p04n01i01603"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p04n01i01603 - Exit from the labeled loop when the condition of the WHEN clause evaluates to be true"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01603arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd
new file mode 100644
index 0000000..14f1da0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1606.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01606ent IS
+END c08s11b00x00p04n01i01606ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01606arch OF c08s11b00x00p04n01i01606ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
+    variable k : integer := 0;
+  BEGIN
+    for I in 0 to 10 loop
+      -- Check to see if we have gone through this more than once.
+      if  (not(GONE_THROUGH_ONCE)) then
+        GONE_THROUGH_ONCE := TRUE;
+      else
+        assert (FALSE)
+          report "Going through loop more than once.";
+      end if;
+
+      -- Exit the loop.
+      exit when TRUE;
+      k := 1;
+      -- The following should never be executed.
+      assert (FALSE)
+        report "This statement should NEVER be executed.";
+    end loop;
+
+    -- Verify that we went through at least once.
+    assert( GONE_THROUGH_ONCE )
+      report "Did not go through the loop at all.";
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01606"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01606 - The loop should terminate when the condition is TRUE." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01606arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd
new file mode 100644
index 0000000..ca50fb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1607.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01607ent IS
+END c08s11b00x00p04n01i01607ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01607arch OF c08s11b00x00p04n01i01607ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
+    variable k : integer := 0;
+  BEGIN
+    for I in 0 to 10 loop
+      -- Check to see if we have gone through this more than once.
+      if  (not(GONE_THROUGH_ONCE)) then
+        GONE_THROUGH_ONCE := TRUE;
+      else
+        assert (FALSE)
+          report "Going through loop more than once.";
+      end if;
+
+      -- Exit the loop.
+      exit;
+      k := 1;
+      -- The following should never be executed.
+      assert (FALSE)
+        report "This statement should NEVER be executed.";
+    end loop;
+
+    -- Verify that we went through at least once.
+    assert( GONE_THROUGH_ONCE )
+      report "Did not go through the loop at all.";
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01607"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01607 - The loop should terminate when the condition is TRUE." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01607arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd
new file mode 100644
index 0000000..4d743cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1608.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01608ent IS
+END c08s11b00x00p04n01i01608ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01608arch OF c08s11b00x00p04n01i01608ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable k : integer := 0;
+  BEGIN
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+
+      -- This condition is NEVER true.
+      exit when FALSE;
+
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+    
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      exit when (CONSTONE /= 1);
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01608"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01608 - If the condition evaluate to FALSE, the execution of the sequence of the statements enclosed within the loop condition with the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01608arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd
new file mode 100644
index 0000000..f18176a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1613.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p01n01i01613ent IS
+END c08s12b00x00p01n01i01613ent;
+
+ARCHITECTURE c08s12b00x00p01n01i01613arch OF c08s12b00x00p01n01i01613ent IS
+
+  --
+  -- Nested functions to test return statement.
+  --
+  function two  return integer is
+    function one  return integer is
+    begin
+      return 1;
+    end one;
+  begin
+    return one + one;
+  end two;
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( two=2 )
+      report "***PASSED TEST: c08s12b00x00p01n01i01613"
+      severity NOTE;
+    assert ( two=2 )
+      report "***FAILED TEST: c08s12b00x00p01n01i01613 - Return statement applies to the innermost enclosing function."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c08s12b00x00p01n01i01613arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd
new file mode 100644
index 0000000..80ca038
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p01n01i01614ent IS
+END c08s12b00x00p01n01i01614ent;
+
+ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
+
+  --
+  -- Nested procedures to test return statement.
+  --
+  procedure two ( variable val : inout integer ) is
+    procedure one ( variable val : out integer ) is
+    begin
+      val := 1;
+      return;
+      val := 2;                     -- should never get here
+    end one;
+  begin
+    one(val);
+    val := val * 2;
+    return;
+    val := val * 2;                   -- should never get here
+  end two;
+
+BEGIN
+  TESTING : PROCESS
+    variable v1 : integer;
+  BEGIN
+    two (v1);
+    assert NOT( v1=2 )
+      report "***PASSED TEST: c08s12b00x00p01n01i01614"
+      severity NOTE;
+    assert ( v1=2 )
+      report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p01n01i01614arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd
new file mode 100644
index 0000000..95bf769
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1617.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01617ent IS
+END c08s12b00x00p03n01i01617ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01617arch OF c08s12b00x00p03n01i01617ent IS
+  function f1 (in1:real) return integer is
+  begin
+    return(12);
+  end f1;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := f1(2.3);   
+    assert NOT(k = 12) 
+      report "***PASSED TEST: c08s12b00x00p03n01i01617" 
+      severity NOTE;
+    assert (k = 12) 
+      report "***FAILED TEST: c08s12b00x00p03n01i01617 - A return statement is only allowed within the body of a function" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01617arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd
new file mode 100644
index 0000000..df89239
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1619.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01619ent IS
+END c08s12b00x00p03n01i01619ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01619arch OF c08s12b00x00p03n01i01619ent IS
+  function F (p : integer) return BIT is
+  begin
+    if p = 5 then
+      return '0';
+    else
+      return '1';
+    end if; 
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : BIT ;
+  BEGIN
+    k := F(5);
+    assert NOT(k = '0') 
+      report "***PASSED TEST: c08s12b00x00p03n01i01619" 
+      severity NOTE;
+    assert (k = '0') 
+      report "***FAILED TEST: c08s12b00x00p03n01i01619 - Multiple return statements in a function body." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01619arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd
new file mode 100644
index 0000000..ccacfec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc162.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p20n02i00162pkg is
+  subtype string_v is string(1 to 32);
+  CONSTANT null_string_v : string_v := (
+    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+    'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f');
+end c04s03b02x02p20n02i00162pkg;
+
+ENTITY c04s03b02x02p20n02i00162ent IS
+END c04s03b02x02p20n02i00162ent;
+
+use work.c04s03b02x02p20n02i00162pkg.all;
+ARCHITECTURE c04s03b02x02p20n02i00162arch OF c04s03b02x02p20n02i00162ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable buf : string_v := null_string_v; 
+
+    PROCEDURE sprintf
+      (
+        buff   : out string_v;
+        str1   : in  string := null_string_v;
+        str2   : in  string := null_string_v;
+        str3   : in  string := null_string_v
+        )
+    is
+      VARIABLE index : integer := 1;
+    begin
+
+      buff := null_string_v;
+
+      for i in str1'range LOOP
+        exit when str1(i) = ' ';
+        buff (index) := str1 (i);
+        index := index + 1;
+      end LOOP;
+      for i in str2'range LOOP
+        exit when str2(i) = ' ';
+        buff (index) := str2 (i);
+        index := index + 1;
+      end LOOP;
+      for i in str3'range LOOP
+        exit when str3(i) = ' ';
+        buff (index) := str3 (i);
+        index := index + 1;
+      end LOOP;
+    end sprintf;
+
+  BEGIN
+    sprintf ( buf,
+              "VHDL ",
+              "TECHNOLOGY ",
+              "GROUP " );
+    wait for 10 ns;
+
+    assert NOT( buf(1  to 19) = "VHDLTECHNOLOGYGROUP"   and
+                buf(20 to 32) = "TUVWXYZabcdef")
+      report "***PASSED TEST: c04s03b02x02p20n02i00162"
+      severity NOTE;
+    assert ( buf(1  to 19) = "VHDLTECHNOLOGYGROUP"   and
+             buf(20 to 32) = "TUVWXYZabcdef")
+      report "***FAILED TEST: c04s03b02x02p20n02i00162- The value of the default expression is used as the actual expression in an implicit association element fot that interface element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p20n02i00162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd
new file mode 100644
index 0000000..b57d89c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc163.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p20n01i00163pkg is
+  procedure P1 (p : in integer := 0; r: inout integer);
+end c04s03b02x02p20n01i00163pkg;
+
+package body c04s03b02x02p20n01i00163pkg is
+  procedure P1 (p : in integer := 0; r: inout integer) is
+  begin
+    r := p / 3 ;
+  end;
+end c04s03b02x02p20n01i00163pkg;
+
+
+use work.c04s03b02x02p20n01i00163pkg.all;
+ENTITY c04s03b02x02p20n01i00163ent IS
+END c04s03b02x02p20n01i00163ent;
+
+ARCHITECTURE c04s03b02x02p20n01i00163arch OF c04s03b02x02p20n01i00163ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 (r => x);  -- No_failure_here
+    -- no association for p
+    assert NOT( x=0 )
+      report "***PASSED TEST: c04s03b02x02p20n01i00163"
+      severity NOTE;
+    assert ( x=0 )
+      report "***FAILED TEST: c04s03b02x02p20n01i00163 - Defualt value in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p20n01i00163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd
new file mode 100644
index 0000000..3d89b5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1630.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p04n01i01630ent IS
+END c08s12b00x00p04n01i01630ent;
+
+ARCHITECTURE c08s12b00x00p04n01i01630arch OF c08s12b00x00p04n01i01630ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+    procedure return_exp_check is
+    begin
+      i := 10;
+    end;
+  BEGIN
+    return_exp_check;
+    assert NOT(i = 10) 
+      report "***PASSED TEST: c08s12b00x00p04n01i01630" 
+      severity NOTE;
+    assert (i = 10) 
+      report "***FAILED TEST: c08s12b00x00p04n01i01630 - A return statement is not required in a procedure body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p04n01i01630arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd
new file mode 100644
index 0000000..20a31d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01633ent IS
+END c08s12b00x00p05n01i01633ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type AR2 is array (0 to 2) of BIT;
+    function K return AR2 is
+    begin
+      return (1 => '1', others => '0');
+    end K;
+    variable kk : AR2;
+  BEGIN
+    kk := K;
+    assert (kk = "010") 
+      report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    assert NOT(kk = "010") 
+      report "***PASSED TEST: c08s12b00x00p05n01i01633"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01633arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd
new file mode 100644
index 0000000..a2b5390
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1634.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01634ent IS
+END c08s12b00x00p05n01i01634ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01634arch OF c08s12b00x00p05n01i01634ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type E is (A,B,C,D);
+    subtype E1 is E range C to D;
+    function F return E is
+      variable V : E1 := C;
+    begin
+      return V;
+    end F;
+    variable k : E := A; 
+  BEGIN
+    k := F;
+    assert NOT(k = C)
+      report "***PASSED TEST: c08s12b00x00p05n01i01634" 
+      severity NOTE;
+    assert (k = C) 
+      report "***FAILED TEST: c08s12b00x00p05n01i01634 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01634arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd
new file mode 100644
index 0000000..d838d6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1635.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01635ent IS
+END c08s12b00x00p05n01i01635ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01635arch OF c08s12b00x00p05n01i01635ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PH is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+    subtype PH1 is PH range X to Y;
+    function J return PH1 is
+    begin
+      return X;
+    end J;
+    variable k : PH1 := 2 X; 
+  BEGIN
+    k := J;
+    assert NOT(k = X)
+      report "***PASSED TEST: c08s12b00x00p05n01i01635" 
+      severity NOTE;
+    assert (k = X) 
+      report "***FAILED TEST: c08s12b00x00p05n01i01635 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01635arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd
new file mode 100644
index 0000000..0bcd8b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1636.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01636ent IS
+END c08s12b00x00p05n01i01636ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01636arch OF c08s12b00x00p05n01i01636ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PH is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+    type AR1 is array (POSITIVE range <>) of PH;   
+    function K return AR1 is
+      variable V : AR1(49 to 50) ;
+    begin
+      V := (5 U,X) ;
+      return V;
+    end K;
+    variable kk : AR1(49 to 50); 
+  BEGIN
+    kk := K;
+    assert NOT(kk = (5 U,X))
+      report "***PASSED TEST: c08s12b00x00p05n01i01636" 
+      severity NOTE;
+    assert (kk = (5 U,X))
+      report "***FAILED TEST: c08s12b00x00p05n01i01636 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01636arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd
new file mode 100644
index 0000000..0db0ff8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd
@@ -0,0 +1,238 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p05n01i01637pkg is
+
+  -- type declarations
+  type ENUM is ( E1, E2, E3 );
+  type DISTANCE is range 0 to 1E9
+    units
+      -- Base units.
+      A;                    -- angstrom
+
+      -- Metric lengths.
+      nm       = 10 A;      -- nanometer
+      um       = 1000 nm;   -- micrometer (or micron)
+      mm       = 1000 um;   -- millimeter
+      cm       = 10 mm;     -- centimeter
+
+      -- English lengths.
+      mil      = 254000 A;  -- mil
+      inch     = 1000 mil;  -- inch
+    end units;
+  type ANARRAY is ARRAY( 0 to 1 ) of REAL;
+  type ARECORD is
+    RECORD
+      Field1      : INTEGER;
+      Field2      : BOOLEAN;
+    end record;
+
+  -- constant declarations
+  CONSTANT CONSTI     : INTEGER  := 47;
+  CONSTANT CONSTR     : REAL     := 47.0;
+  CONSTANT CONSTE     : ENUM     := E1;
+  CONSTANT CONSTD     : DISTANCE := 1 A;
+  CONSTANT CONSTT     : TIME     := 1 hr;
+  CONSTANT CONSTB     : BIT      := '1';
+  CONSTANT CONSTS     : SEVERITY_LEVEL := WARNING;
+  CONSTANT CONSTBO    : BOOLEAN  := FALSE;
+  CONSTANT CONSTA     : ANARRAY  := ( 3.1415926, 4.0 );
+  CONSTANT CONSTRE    : ARECORD  := ( Field1 => 2, Field2 => TRUE );
+  
+  -- function declarations.
+  function funcI return INTEGER;
+  function funcR return REAL;
+  function funcE return ENUM;
+  function funcD return DISTANCE;
+  function funcT return TIME;
+  function funcB return BIT;
+  function funcS return SEVERITY_LEVEL;
+  function funcBO return BOOLEAN;
+  function funcA return ANARRAY;
+  function funcRE return ARECORD;
+  
+end c08s12b00x00p05n01i01637pkg;
+
+package body c08s12b00x00p05n01i01637pkg is
+  
+  function funcI return INTEGER is
+  begin
+    return( CONSTI );
+  end;
+  
+  function funcR return REAL is
+  begin
+    return( CONSTR );
+  end;
+  
+  function funcE return ENUM is
+  begin
+    return( CONSTE );
+  end;
+  
+  function funcD return DISTANCE is
+  begin
+    return( CONSTD );
+  end;
+  
+  function funcT return TIME is
+  begin
+    return( CONSTT );
+  end;
+  
+  function funcB return BIT is
+  begin
+    return( CONSTB );
+  end;
+  
+  function funcS return SEVERITY_LEVEL is
+  begin
+    return( CONSTS );
+  end;
+  
+  function funcBO return BOOLEAN is
+  begin
+    return( CONSTBO );
+  end;
+  
+  function funcA return ANARRAY is
+  begin
+    return( CONSTA );
+  end;
+  
+  function funcRE return ARECORD is
+  begin
+    return( CONSTRE );
+  end;
+  
+end c08s12b00x00p05n01i01637pkg;
+
+use work.c08s12b00x00p05n01i01637pkg.all;
+ENTITY c08s12b00x00p05n01i01637ent IS
+END c08s12b00x00p05n01i01637ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- variable declarations.
+    VARIABLE VARI     : INTEGER;
+    VARIABLE VARR     : REAL;
+    VARIABLE VARE     : ENUM;
+    VARIABLE VARD     : DISTANCE;
+    VARIABLE VART     : TIME;
+    VARIABLE VARB     : BIT;
+    VARIABLE VARS     : SEVERITY_LEVEL;
+    VARIABLE VARBO    : BOOLEAN;
+    VARIABLE VARA     : ANARRAY;
+    VARIABLE VARRE    : ARECORD;
+  BEGIN
+    -- Call each function, verify that it returns the proper value.
+    assert (funcI = CONSTI);
+    assert (funcR = CONSTR);
+    assert (funcE = CONSTE);
+    assert (funcD = CONSTD);
+    assert (funcT = CONSTT);
+    assert (funcB = CONSTB);
+    assert (funcS = CONSTS);
+    assert (funcBO = CONSTBO);
+    assert (funcA = CONSTA);
+    assert (funcRE = CONSTRE);
+    
+    -- Assign function values to variables, make sure they're OK.
+    VARI  := funcI;
+    VARR  := funcR;
+    VARE  := funcE;
+    VARD  := funcD;
+    VART  := funcT;
+    VARB  := funcB;
+    VARS  := funcS;
+    VARBO := funcBO;
+    VARA  := funcA;
+    VARRE := funcRE;
+    assert (VARI = CONSTI);
+    assert (VARR = CONSTR);
+    assert (VARE = CONSTE);
+    assert (VARD = CONSTD);
+    assert (VART = CONSTT);
+    assert (VARB = CONSTB);
+    assert (VARS = CONSTS);
+    assert (VARBO = CONSTBO);
+    assert (VARA = CONSTA);
+    assert (VARRE = CONSTRE);
+
+    assert NOT((funcI = CONSTI)   and
+               (funcR = CONSTR)   and
+               (funcE = CONSTE)   and
+               (funcD = CONSTD)   and
+               (funcT = CONSTT)   and
+               (funcB = CONSTB)   and
+               (funcS = CONSTS)   and
+               (funcBO = CONSTBO)   and
+               (funcA = CONSTA)   and
+               (funcRE = CONSTRE)   and
+               (VARI = CONSTI)   and
+               (VARR = CONSTR)   and
+               (VARE = CONSTE)   and
+               (VARD = CONSTD)   and
+               (VART = CONSTT)   and
+               (VARB = CONSTB)   and
+               (VARS = CONSTS)   and
+               (VARBO = CONSTBO)   and
+               (VARA = CONSTA)   and
+               (VARRE = CONSTRE))   
+      report "***PASSED TEST: c08s12b00x00p05n01i01637"
+      severity NOTE;
+    assert   ((funcI = CONSTI)   and
+              (funcR = CONSTR)   and
+              (funcE = CONSTE)   and
+              (funcD = CONSTD)   and
+              (funcT = CONSTT)   and
+              (funcB = CONSTB)   and
+              (funcS = CONSTS)   and
+              (funcBO = CONSTBO)   and
+              (funcA = CONSTA)   and
+              (funcRE = CONSTRE)   and
+              (VARI = CONSTI)   and
+              (VARR = CONSTR)   and
+              (VARE = CONSTE)   and
+              (VARD = CONSTD)   and
+              (VART = CONSTT)   and
+              (VARB = CONSTB)   and
+              (VARS = CONSTS)   and
+              (VARBO = CONSTBO)   and
+              (VARA = CONSTA)   and
+              (VARRE = CONSTRE))   
+      report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01637arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd
new file mode 100644
index 0000000..b3f2e64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1639.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p06n01i01639ent IS
+END c08s12b00x00p06n01i01639ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01639arch OF c08s12b00x00p06n01i01639ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable correct : boolean := true;
+    procedure Proc1(constant p_boolean :boolean ) is
+    begin
+      if p_boolean = p_boolean then
+        return;
+      else
+        return;   
+      end if;
+      correct := false;
+    end Proc1;
+  BEGIN
+    Proc1(false);
+    assert NOT( correct = true )
+      report "***PASSED TEST: c08s12b00x00p06n01i01639"
+      severity NOTE;
+    assert ( correct = true )
+      report "***FAILED TEST: c08s12b00x00p06n01i01639 - A return statement stops execution of a procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01639arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd
new file mode 100644
index 0000000..440307c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc164.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p23n01i00164ent IS
+END c04s03b02x02p23n01i00164ent;
+
+ARCHITECTURE c04s03b02x02p23n01i00164arch OF c04s03b02x02p23n01i00164ent IS
+  signal p1 : bit;   --added to make it compile
+BEGIN
+  TESTING: PROCESS(p1)
+    VARIABLE v1,v2,v3,v4 : integer;
+
+    PROCEDURE default_test
+      (
+        param_1 : in integer;
+        default : in integer := 22;
+        param_3 : out integer;
+        param_4 : out integer
+        )
+    is
+    begin
+      param_3 := param_1;
+      param_4 := default;
+    end default_test;
+
+  BEGIN
+    v1 := 1919;
+    default_test (v1,
+                  -- missing association
+                  param_3 => v3,
+                  param_4 => v4
+                  );
+    assert NOT( v3=1919 and v4=22 )
+      report "***PASSED TEST: c04s03b02x02p23n01i00164"
+      severity NOTE;
+    assert ( v3=1919 and v4=22 )
+      report "***FAILED TEST: c04s03b02x02p23n01i00164 - If an association element is omitted from an association list in order to make use of the default expression on the corresponding interface element, all subsequent association elements in that association list must be named associations."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c04s03b02x02p23n01i00164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd
new file mode 100644
index 0000000..d25733b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1641.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p06n01i01641ent IS
+END c08s12b00x00p06n01i01641ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01641arch OF c08s12b00x00p06n01i01641ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function ts (x1:bit) return integer is
+    begin
+      return (5);
+    end ts;
+    variable k : integer := 0;
+  BEGIN
+    k := ts('1');   
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s12b00x00p06n01i01641"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s12b00x00p06n01i01641 - Value of the expression is of different subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01641arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd
new file mode 100644
index 0000000..a38810c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1642.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p06n01i01642pkg is
+
+  procedure procI;
+  function  funcI return INTEGER;
+
+end c08s12b00x00p06n01i01642pkg;
+
+package body c08s12b00x00p06n01i01642pkg is
+
+  procedure procI is
+  begin
+    -- Return.
+    return;
+
+    -- Statement should NEVER be executed.
+    assert (FALSE)
+      report "Statement in procedure was executed in error.";
+  end procI;
+
+  function funcI return INTEGER is
+  begin
+    -- Return from the function.
+    return( 4 );
+
+    -- Statement should NEVER be executed.
+    assert (FALSE)
+      report "Statement in function was executed in error.";
+  end funcI;
+
+end c08s12b00x00p06n01i01642pkg;
+
+use work.c08s12b00x00p06n01i01642pkg.all;
+ENTITY c08s12b00x00p06n01i01642ent IS
+END c08s12b00x00p06n01i01642ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01642arch OF c08s12b00x00p06n01i01642ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Execute the procedure.
+    procI;
+    
+    -- Execute the function.
+    assert NOT(funcI = 4)
+      report "***PASSED TEST: c08s12b00x00p06n01i01642" 
+      severity NOTE;
+    assert (funcI = 4)
+      report "***FAILED TEST: c08s12b00x00p06n01i01642 - The execution of the return statement completes if the type of the expression is of teh result subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd
new file mode 100644
index 0000000..91a6a25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1643.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p08n01i01643pkg is
+
+
+  -- function declarations.
+  function funcI  return INTEGER;
+  function funcI2 return INTEGER;
+
+end c08s12b00x00p08n01i01643pkg;
+
+package body c08s12b00x00p08n01i01643pkg is
+
+  function funcI return INTEGER is
+  begin
+    return ( 3 );
+  end;
+
+  function funcI2 return INTEGER is
+  begin
+    return ( 3  );
+  end;
+
+end c08s12b00x00p08n01i01643pkg;
+
+use work.c08s12b00x00p08n01i01643pkg.all;
+ENTITY c08s12b00x00p08n01i01643ent IS
+END c08s12b00x00p08n01i01643ent;
+
+ARCHITECTURE c08s12b00x00p08n01i01643arch OF c08s12b00x00p08n01i01643ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( funcI = 3 and funcI2 = 3)         
+      report "***PASSED TEST: c08s12b00x00p08n01i01643"
+      severity NOTE;
+    assert ( funcI = 3 and funcI2 = 3)         
+      report "***FAILED TEST: c08s12b00x00p08n01i01643 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p08n01i01643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd
new file mode 100644
index 0000000..33fb02c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1644.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p02n01i01644ent IS
+END c08s13b00x00p02n01i01644ent;
+
+ARCHITECTURE c08s13b00x00p02n01i01644arch OF c08s13b00x00p02n01i01644ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if TRUE then
+      NULL;
+    end if;
+    assert FALSE
+      report "***PASSED TEST: c08s13b00x00p02n01i01644"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p02n01i01644arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd
new file mode 100644
index 0000000..8c52a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01646ent IS
+END c08s13b00x00p03n01i01646ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if TRUE then
+      k := 5;
+      NULL;
+    elsif FALSE then
+      k := 5;
+      NULL;
+    end if;
+    assert NOT(k = 5) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01646"
+      severity NOTE;
+    assert (k = 5) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01646arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd
new file mode 100644
index 0000000..79a482f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1647.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01647ent IS
+END c08s13b00x00p03n01i01647ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01647arch OF c08s13b00x00p03n01i01647ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean := true;
+    variable kk: integer := 0;
+  BEGIN
+    case k is
+      when false    => NULL;
+      when true   => NULL;
+                     kk := 5;
+    end case;
+    assert NOT(kk=5) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01647"
+      severity NOTE;
+    assert (kk=5) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01647 - The execution of the null statement has no effect other than to pass on to the next statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01647arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd
new file mode 100644
index 0000000..7a7f0d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1648.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01648ent IS
+END c08s13b00x00p03n01i01648ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01648arch OF c08s13b00x00p03n01i01648ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      k := k + 1;
+      null;
+    end loop;
+    assert NOT(k = 10) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01648"
+      severity NOTE;
+    assert (k = 10) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01648 - The execution of the null statement has no effect other than to pass on to the next statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01648arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd
new file mode 100644
index 0000000..c68064b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1649.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01649ent IS
+END c08s13b00x00p03n01i01649ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01649arch OF c08s13b00x00p03n01i01649ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable FIRST_DONE  : BOOLEAN := FALSE;
+    variable SECOND_DONE : BOOLEAN := FALSE;
+  BEGIN
+    FIRST_DONE := TRUE;
+    null;
+    SECOND_DONE := TRUE;
+
+    -- Make sure that both statements surrounding the null
+    -- statement got executed.
+    assert NOT(FIRST_DONE and SECOND_DONE)
+      report "***PASSED TEST: c08s13b00x00p03n01i01649"
+      severity NOTE;
+    assert (FIRST_DONE and SECOND_DONE)
+      report "***FAILED TEST: c08s13b00x00p03n01i01649 - The execution of the null statement has no effect other than to pass on to the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01649arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd
new file mode 100644
index 0000000..83b90dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01650ent IS
+END c08s13b00x00p03n01i01650ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable LOCALI      : INTEGER := 47;
+    variable LOCALR      : REAL    := 47.0;
+    variable LOCALB      : BOOLEAN := TRUE;
+  BEGIN
+    -- Check for proper initialization.
+    assert (LOCALI = 47);
+    assert (LOCALR = 47.0);
+    assert (LOCALB = TRUE);
+
+    -- Execute the NULL statement.
+    null;
+
+    -- Verify that nothing has changed as a result.
+    assert NOT((LOCALI = 47)   and
+               (LOCALR = 47.0)   and
+               (LOCALB = TRUE))
+      report "***PASSED TEST: c08s13b00x00p03n01i01650"
+      severity NOTE;
+    assert ((LOCALI = 47)      and
+            (LOCALR = 47.0)      and
+            (LOCALB = TRUE))
+      report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01650arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd
new file mode 100644
index 0000000..087ad2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1651.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01651ent IS
+  procedure passive is
+  begin
+    null;                             -- or is that "dull"?
+  end passive;
+begin
+  passive;
+END c08s13b00x00p03n01i01651ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01651arch OF c08s13b00x00p03n01i01651ent IS
+  function troo return boolean is
+  begin
+    null;
+    return true;
+  end troo;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : integer := 1;
+    variable v2 : integer := 0;
+  BEGIN
+    if v1 > v2 then
+      null;
+    elsif v1 < v2 then
+      null;
+    else
+      null;
+    end if;
+
+    case troo is
+      when false => null;
+      when true => null;
+    end case;
+
+    loop
+      null;
+      exit;                         -- jump out of the infinite loop
+    end loop;
+
+    null;
+    assert FALSE 
+      report "***PASSED TEST: c08s13b00x00p03n01i01651"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01651arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd
new file mode 100644
index 0000000..2b83fb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c09s00b00x00p02n01i01653ent_a is
+  port (signal ss : in integer);
+end c09s00b00x00p02n01i01653ent_a;
+
+architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
+begin
+  process
+  begin
+    wait;
+  end process;
+end c09s00b00x00p02n01i01653arch_a;
+
+ENTITY c09s00b00x00p02n01i01653ent IS
+  port ( Pt    : in BOOLEAN;
+         PTO    : out BIT) ;
+END c09s00b00x00p02n01i01653ent;
+
+ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
+
+  component FO 
+    port (signal ss : in INTEGER);
+  end component ;
+  for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
+
+  signal S1, S2    : Integer;
+  signal S       : INTEGER;
+
+BEGIN
+  -- concurrent signal statement
+  S <= transport 5;
+  
+  -- concurrent assertion statement
+  assert ( not PT)
+    report " dead wire "
+    severity WARNING;
+  
+  -- generate
+  L_G_1:  for I in 1 to 1 generate
+    L_X_2:    block
+      signal S3 : Bit;
+    begin
+      S2 <= transport 1;
+    end block;
+  end generate;
+  
+  -- component instatiation
+  Ls : FO port map (S1);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s00b00x00p02n01i01653" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s00b00x00p02n01i01653arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd
new file mode 100644
index 0000000..db00e36
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1654.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s00b00x00p04n01i01654ent IS
+END c09s00b00x00p04n01i01654ent;
+
+ARCHITECTURE c09s00b00x00p04n01i01654arch OF c09s00b00x00p04n01i01654ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE                            -- force assertion violation
+      report "PASS: process TESTING executes."
+      severity NOTE;
+
+    assert FALSE
+      report "***PASSED TEST: c09s00b00x00p04n01i01654 - it is really uncertain that which assertion note appear first for different simulator."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+  TEST: PROCESS
+  begin
+    assert FALSE
+      report "PASS: process TEST executes."
+      severity NOTE;
+    
+    -- Note: It does not matter which process executes first. (The order
+    --      of process execution is not defined by the LRM, and dependence
+    --      on the execution order is not allowed.)
+    
+    wait;                                   -- wait forever
+  END PROCESS TEST;
+
+END c09s00b00x00p04n01i01654arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd
new file mode 100644
index 0000000..90eb032
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd
@@ -0,0 +1,142 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s00b00x00p05n01i01655pkg is
+  procedure cpc (constant loc : string);
+end c09s00b00x00p05n01i01655pkg;
+
+package body c09s00b00x00p05n01i01655pkg is
+  procedure cpc (constant loc : string) is      -- concurrent procedure
+  begin
+    assert false
+      report "Concurrent procedure called from " & loc            
+      severity note ;
+  end cpc;
+end c09s00b00x00p05n01i01655pkg;
+
+use work.c09s00b00x00p05n01i01655pkg.all;
+
+entity c09s00b00x00p05n01i01655ent_a is
+  port (signal pi : in  bit;
+        signal po : out bit
+        );
+begin
+  cas : assert false
+    report "Labeled concurrent assert called from component."
+    severity note ;
+
+  cpcc : cpc("component entity");
+
+  ppsc :                                -- passive process stmt
+  process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in component."
+      severity note ;
+  end process;
+end c09s00b00x00p05n01i01655ent_a;
+
+architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
+begin
+  cpc("component architecture");
+end;
+
+use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
+
+ENTITY c09s00b00x00p05n01i01655ent IS
+  port (signal pi : in  bit;
+        signal po : out bit
+        );
+begin
+  cas : assert false
+    report "Labeled concurrent assert called from entity."
+    severity note ;
+  
+  cpce : cpc("entity.");
+  
+  ppse :                                -- passive process stmt
+  process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in entity."
+      severity note ;
+  end process;
+END c09s00b00x00p05n01i01655ent;
+
+ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
+  signal lab_sig : boolean := true;
+  
+  component comp
+    port (signal pi : in bit;
+          signal po : out bit
+          );
+  end component; -- comp
+  for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
+    port map (pi, po);
+BEGIN
+  casa : assert false
+    report "Labeled concurrent assert called from architecture."
+    severity note ;
+  
+  cpca : cpc("architecture.");
+  
+  ppsa : process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in architecture."
+      severity note ;
+  end process;
+  
+  lba: block
+  begin
+    cpcb : cpc("block.");
+    
+    casb : assert false
+      report "Labeled concurrent assert called from labeled block."
+      severity note ;
+  end block lba;
+  
+  csa : lab_sig <= false;
+  assert lab_sig
+    report "Labeled concurrent signal assignment executed in architecture."
+    severity note ;
+  
+  lcia : comp
+    port map (pi => pi, po => po);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s00b00x00p05n01i01655arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd
new file mode 100644
index 0000000..8d34ca4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1658.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity E  is
+  port ( S_in : in bit; S_out : out bit) ;
+end E;
+
+entity C1  is
+  port ( A : bit; B :out bit) ;
+end C1;
+
+use work.c1;
+
+ENTITY c09s01b00x00p02n01i01658ent IS
+  port ( B : bit ) ;
+END c09s01b00x00p02n01i01658ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01658arch OF c09s01b00x00p02n01i01658ent IS
+
+BEGIN
+
+  lab : block 
+    component C1
+      port ( A : bit; B : out bit );
+    end component ; -- C1
+    
+    for all : C1 use entity work.E
+      port map ( S_in => A, S_out => B ) ;
+    
+    type    T1 is ('0', '1');
+    subtype T2 is integer range 0 to 7;
+    
+    signal S1    : real;
+    alias  S1_too    : real is S1;
+    
+    attribute ATTR : T1;
+    attribute ATTR of ALL : signal is '1';
+
+  begin
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***PASSED TEST: c09s01b00x00p02n01i01658" 
+        severity NOTE;
+      wait;
+    END PROCESS TESTING;
+  end block lab;
+
+
+END c09s01b00x00p02n01i01658arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd
new file mode 100644
index 0000000..61c30e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1659.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01659ent IS
+END c09s01b00x00p02n01i01659ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01659arch OF c09s01b00x00p02n01i01659ent IS
+
+BEGIN
+
+  B1:block --<< no guard condition here
+  begin
+    process
+    begin
+      null ;
+      wait;
+    end process ;
+  end block ;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p02n01i01659" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p02n01i01659arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd
new file mode 100644
index 0000000..1b54754
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc166.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00166ent IS
+END c04s03b03x00p01n01i00166ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00166arch OF c04s03b03x00p01n01i00166ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : INTEGER := 1;
+    alias       V1_A1    : INTEGER is V1;
+    variable   pass   : integer := 0;
+  BEGIN
+    assert V1    = 1;
+    assert V1_A1    = 1;
+    if (V1 /= 1 or V1_A1 /= 1) then
+      pass := 1;
+    end if;
+
+
+    V1 := 2;      -- change value...
+    assert V1    = 2;
+    assert V1_A1    = 2;   -- ... check read
+    if (V1 /= 2 or V1_A1 /= 2) then
+      pass := 1;
+    end if;
+
+    V1_A1 := 3;      -- change value using alias
+    assert V1    = 3;   -- ... check that value changed
+    assert V1_A1    = 3;
+    if (V1 /= 3 or V1_A1 /= 3) then
+      pass := 1;
+    end if;
+
+    wait for 5 ns;
+    assert NOT(   pass = 0   ) 
+      report "***PASSED TEST: c04s03b03x00p01n01i00166"
+      severity NOTE;
+    assert (   pass = 0   ) 
+      report "***FAILED TEST: c04s03b03x00p01n01i00166 - Alias for variable object test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd
new file mode 100644
index 0000000..bf54c72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1662.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p03n01i01662ent IS
+  port (A, B: inout bit);
+END c09s01b00x00p03n01i01662ent;
+
+ARCHITECTURE c09s01b00x00p03n01i01662arch OF c09s01b00x00p03n01i01662ent IS
+  signal       S1, S2, S3   : bit       := '0';
+  constant    gm      : natural    := 0;
+BEGIN
+
+  BL: block                          -- no_failure_here
+    generic    (n: natural:= 2);
+    generic map    (gm);
+    port       (A, B: inout bit);
+    port map    (S1, S2);
+  begin
+  end block BL;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p03n01i01662"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p03n01i01662arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd
new file mode 100644
index 0000000..3da3c45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1665.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01665ent IS
+  port (A,B : inout bit);
+END c09s01b00x00p05n01i01665ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01665arch OF c09s01b00x00p05n01i01665ent IS
+
+BEGIN
+  BL: block
+  begin
+  end block BL; -- No_failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p05n01i01665" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01665arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd
new file mode 100644
index 0000000..427f106
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc167.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00167ent IS
+END c04s03b03x00p01n01i00167ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00167arch OF c04s03b03x00p01n01i00167ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant    C1 : INTEGER := 1;
+    alias       a1 : INTEGER is C1;
+
+    constant    C2 : STRING := "Hello";
+    alias       a2 : STRING(4 downto 1) is C2(1 to 4);
+    alias       a3 : STRING(1 to 5)    is C2;
+
+    alias       a4 : CHARACTER is C2(2);
+  BEGIN
+    assert C1 = 1;
+    assert A1 = 1;
+    assert C2 = "Hello";
+    assert A2 = "Hell";
+    assert A3 = "Hello";
+    assert A4 = 'e';
+    assert NOT(    C1 = 1   and
+                   A1 = 1   and
+                   C2 = "Hello"   and
+                   A2 = "Hell"   and
+                   A3 = "Hello"   and
+                   A4 = 'e'   )
+      report "***PASSED TEST: c04s03b03x00p01n01i00167"
+      severity NOTE;
+    assert (    C1 = 1   and
+                A1 = 1   and
+                C2 = "Hello"   and
+                A2 = "Hell"   and
+                A3 = "Hello"   and
+                A4 = 'e'   )
+      report "***FAILED TEST: c04s03b03x00p01n01i00167 - Alias for constant object test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd
new file mode 100644
index 0000000..3d2b300
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01677ent IS
+END c09s01b00x00p08n01i01677ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
+
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+  SIGNAL     v_slice : bit_vector_8 := B"1010_1100";
+
+BEGIN
+
+  labeled : block
+    port ( v : OUT bit_vector_4 := "1010");
+    port map ( v_slice ( 0 to 3 ));
+  begin
+    v <= B"0101" after 10 ns; -- only driver created ..
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert (v_slice = B"1010_1100")
+      report "Condition error: value of signal V_SLICE incorrect"
+      severity failure;
+
+    wait for 10 ns;
+
+    assert NOT(v_slice = B"0101_1100")
+      report "***PASSED TEST: c09s01b00x00p08n01i01677"
+      severity NOTE;
+    assert (v_slice = B"0101_1100")
+      report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p08n01i01677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd
new file mode 100644
index 0000000..2074ee3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01678ent IS
+END c09s01b00x00p08n01i01678ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
+  signal   S2 : integer := 2;
+BEGIN
+  B: block
+    generic (    G1 : INTEGER;
+                 G2 : STRING);
+    generic map (    G1 => 10, 
+                     G2 => "Hi");
+    port (      P1 : INTEGER);
+    port map (   P1 => S2);
+  begin
+    assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
+      report "***PASSED TEST: c09s01b00x00p08n01i01678"
+      severity NOTE;
+    assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
+      report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
+      severity ERROR;
+  end block;
+
+END c09s01b00x00p08n01i01678arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd
new file mode 100644
index 0000000..c50c895
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1679.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01679ent IS
+END c09s01b00x00p08n01i01679ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01679arch OF c09s01b00x00p08n01i01679ent IS
+  constant    size    : INTEGER := 3;
+  signal    S    : STRING(1 to size) := "Hi!";
+BEGIN
+  B: block
+    generic    (size : INTEGER);
+    generic map    (size => size);
+    port       (P : in STRING(1 to size));
+    port map    (P => S);
+  begin
+    assert NOT(P="Hi!") 
+      report "***PASSED TEST: c09s01b00x00p08n01i01679"
+      severity NOTE;
+    assert (P="Hi!") 
+      report "***FAILED TEST: c09s01b00x00p08n01i01679 - Block statement test failed."
+      severity ERROR;
+  end block;
+
+END c09s01b00x00p08n01i01679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd
new file mode 100644
index 0000000..88d9b4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc168.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00168ent IS
+END c04s03b03x00p01n01i00168ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00168arch OF c04s03b03x00p01n01i00168ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : INTEGER := 1;
+    alias       V1_A1    : INTEGER is V1;
+    -- scalar alias of scalar
+    -- alias of variable
+    alias       V1_A2    : INTEGER is V1_A1;
+    -- alias of alias
+    
+    variable   pass   : integer := 0;
+  BEGIN
+    assert V1    = 1;
+    assert V1_A1    = 1;
+    assert V1_A2    = 1;
+    if (V1 /= 1 or V1_A1 /= 1 or V1_A2 /= 1) then   
+      pass := 1;
+    end if;
+    
+    V1 := 2;         -- change value...
+    assert V1    = 2;
+    assert V1_A1    = 2;      -- ... check read
+    assert V1_A2    = 2;      -- ... check read
+    if (V1 /= 2 or V1_A1 /= 2 or V1_A2 /= 2) then   
+      pass := 1;
+    end if;
+    
+    V1_A1 := 3;         -- change value using alias
+    assert V1    = 3;      -- ... check that value changed
+    assert V1_A1    = 3;
+    assert V1_A2    = 3;
+    if (V1 /= 3 or V1_A1 /= 3 or V1_A2 /= 3) then   
+      pass := 1;
+    end if;
+
+    V1_A2 := 4;         -- change value using alias
+    assert V1    = 4;      -- ... check that value changed
+    assert V1_A1    = 4;
+    assert V1_A2    = 4;
+    if (V1 /= 4 or V1_A1 /= 4 or V1_A2 /= 4) then   
+      pass := 1;
+    end if;
+
+    wait for 5 ns;
+    assert NOT(   pass = 0   ) 
+      report "***PASSED TEST: c04s03b03x00p01n01i00168"
+      severity NOTE;
+    assert (   pass = 0   ) 
+      report "***FAILED TEST: c04s03b03x00p01n01i00168 - Alias of alias variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd
new file mode 100644
index 0000000..2a7c1ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p09n01i01681ent IS
+END c09s01b00x00p09n01i01681ent;
+
+ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
+
+BEGIN
+
+  lab : block
+  begin
+  end block lab;                       -- labels match
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p09n01i01681" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p09n01i01681arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd
new file mode 100644
index 0000000..2c6e00e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1684.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01684ent IS
+END c09s02b00x00p02n01i01684ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01684arch OF c09s02b00x00p02n01i01684ent IS
+  signal done : bit;
+  signal bomb : bit;
+BEGIN
+  process (done, bomb)
+  begin
+  end process;
+  
+  TESTING : PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p02n01i01684" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p02n01i01684arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd
new file mode 100644
index 0000000..ac04354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc169.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00169ent IS
+END c04s03b03x00p01n01i00169ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00169arch OF c04s03b03x00p01n01i00169ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V2 : STRING(1 to 5) := "Hello";
+    alias       a3 : STRING(1 to 5) is V2;   -- composite alias of composite
+    alias       a2 : STRING(4 downto 1) is V2(1 to 4);
+    
+    alias       a4 : CHARACTER is V2(4);   -- scalar alias of composite
+  BEGIN
+    assert V2    = "Hello";
+    assert A2    = "Hell";
+    assert V2(1)    = 'H';
+    assert A2(4)    = 'H';
+    assert V2(2)    = 'e';
+    assert A2(3)    = 'e';
+    assert A3    = "Hello";
+    assert A4    = 'l';
+
+    wait for 5 ns;
+    assert NOT(   V2       = "Hello"   and 
+                  A2       = "Hell"   and 
+                  V2(1)    = 'H'      and 
+                  A2(4)    = 'H'      and 
+                  V2(2)    = 'e'      and 
+                  A2(3)    = 'e'      and 
+                  A3       = "Hello"   and 
+                  A4       = 'l'      )
+      report "***PASSED TEST: c04s03b03x00p01n01i00169"
+      severity NOTE;
+    assert (   V2       = "Hello"   and 
+               A2       = "Hell"   and 
+               V2(1)    = 'H'      and 
+               A2(4)    = 'H'      and 
+               V2(2)    = 'e'      and 
+               A2(3)    = 'e'      and 
+               A3       = "Hello"   and 
+               A4       = 'l'      )
+      report "***FAILED TEST: c04s03b03x00p01n01i00169 - Alias of alias composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd
new file mode 100644
index 0000000..798b154
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1690.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01690ent IS
+END c09s02b00x00p03n01i01690ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01690arch OF c09s02b00x00p03n01i01690ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    bus_idx is         range 0 to 63;
+    subtype cmd_idx is bus_idx range 0 to 7;
+    variable         v : cmd_idx := 5;
+    variable    untrue : boolean := false;
+  BEGIN
+    assert NOT(v=5 and untrue = false) 
+      report "***PASSED TEST: c09s02b00x00p03n01i01690" 
+      severity NOTE;
+    assert (v=5 and untrue = false) 
+      report "***FAILED TEST: c09s02b00x00p03n01i01690 - Configuration  declarations are not permitted in process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd
new file mode 100644
index 0000000..e755c9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1691.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01691ent IS
+  port (P: in Bit);
+END c09s02b00x00p03n01i01691ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01691arch OF c09s02b00x00p03n01i01691ent IS
+
+BEGIN
+  process (P)
+  begin
+  end process;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p03n01i01691" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01691arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd
new file mode 100644
index 0000000..e6e2186
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1698.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01698ent IS
+END c09s02b00x00p05n01i01698ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01698arch OF c09s02b00x00p05n01i01698ent IS
+  signal s : integer;
+BEGIN
+  TEST : PROCESS(s)
+  BEGIN
+  END PROCESS TEST;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p05n01i01698"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd
new file mode 100644
index 0000000..2845166
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc17.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p08n01i00017ent IS
+END c04s02b00x00p08n01i00017ent;
+
+ARCHITECTURE c04s02b00x00p08n01i00017arch OF c04s02b00x00p08n01i00017ent IS
+
+  -- Forward declaration of the function.
+  function WIRED_OR( S : BIT_VECTOR ) return BIT;
+
+  -- Declare the subtype.
+  subtype RBIT is WIRED_OR BIT;
+
+  -- Declare the actual function.
+  function WIRED_OR( S : BIT_VECTOR ) return BIT is
+  begin
+    assert FALSE 
+      report "***PASSED TEST: c04s02b00x00p08n01i00017" 
+      severity NOTE;
+    if  ( (S(0) = '1') OR (S(1) = '1')) then
+      return '1';
+    end if;
+    return '0';
+  end WIRED_OR;
+
+  -- Declare a signal of that type.  A resolved signal.
+  signal S : RBIT;
+
+BEGIN
+
+  -- A concurrent signal assignment.  Driver # 1.
+  S <= '1';
+
+  TESTING: PROCESS
+  BEGIN
+    -- Verify that resolution function getting called.
+    S <= '1' after 10 ns;
+    wait on S;
+    assert NOT( S = '1' ) 
+      report "***PASSED TEST: c04s02b00x00p08n01i00017"
+      severity NOTE;
+    assert ( S = '1' )
+      report "***FAILED TEST: c04s02b00x00p08n01i00017 - If a resolution function name appears in a subtype, all signals declared to be of that subtype are resolved by that function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p08n01i00017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd
new file mode 100644
index 0000000..2c8d26f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01703ent IS
+END c09s02b00x00p05n01i01703ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
+  signal s : boolean := false;
+BEGIN
+
+  TESTING: PROCESS
+    type result_type is (fail, pass);
+    variable result : result_type := fail;
+    variable i, j   : integer;
+    variable k   : integer := 0;
+  BEGIN
+    --
+    -- Test all sequential statements in this process
+    --
+    s <= true;                        -- signal assignment        
+    j := 1;                           -- variable assignment
+    i := 0;
+    
+    L1: while  ( i < 10 )  loop       -- conditional loop
+      if i > 2 then
+        exit;
+      end if;
+      case i is
+        when 0 =>
+          L2: for j in 1 to 3 loop
+            case j is
+              when 3 =>       -- should never execute because of
+                i := i + 1; -- alternative 2
+                k := 1;
+                exit;
+                assert false
+                  report "exit in loop 2 case failed."
+                  severity note;
+              when 2 =>
+                i := i + 1;
+                next L1;
+                k := 1;
+                assert false     -- should never execute
+                  report "next in loop 2 case failed."
+                  severity note;
+              when 1 =>
+                assert false
+                  report "first iteration of loop 2."
+                  severity note ;
+                next;     -- applies to loop L2
+              when others =>
+                --
+                -- This should never be executed but is
+                -- required by the 1076-1987 spec. which
+                -- says the subtype of 'j' is the same as
+                -- the base type (integer) and not constrained
+                -- to the range "1 to 3".
+                --
+                k := 1;
+                assert false
+                  report "Should never get here."
+                  severity note ;
+            end case;
+            k := 1;
+            assert false      -- should never execute
+              report "next in loop 2 failed."
+              severity note;
+          end loop L2;
+        when 2 =>
+          s <= false after 5 ns;
+          wait for 6 ns;
+          assert not s
+            report "wait statement in loop L1 failed."
+            severity note ;
+          
+          i := i +1;
+        when 1 =>
+          null;
+          assert false
+            report "null statement and next statement worked."
+            severity note ;
+          i := i +1;
+        when others =>
+          k := 1;
+          assert false
+            report "exit in if statement in loop L1 failed."
+            severity note ;
+          exit;
+      end case;
+    end loop L1;
+
+    wait for 50 ns;
+
+    assert NOT(s=false and k = 0 and j=1) 
+      report "***PASSED TEST: c09s02b00x00p05n01i01703" 
+      severity NOTE;
+    assert (s=false and k = 0 and j=1) 
+      report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd
new file mode 100644
index 0000000..329120b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1704.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01704ent IS
+END c09s02b00x00p07n01i01704ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01704arch OF c09s02b00x00p07n01i01704ent IS
+  signal   S :    Bit;
+BEGIN
+  TESTING: PROCESS( S )
+    -- local variables.
+    variable INITED : BOOLEAN := FALSE;
+    variable CNT    : INTEGER := 0;
+    variable NEWTIME: TIME;
+    variable k      : integer := 1;
+  BEGIN
+    -- Take care of the first run.
+    if  (not( INITED )) then
+      INITED  := TRUE;
+      CNT     := 0;
+      S       <= (not S) after 1 ns;
+      NEWTIME := NOW + 1 ns;
+
+      -- Otherwise, take care of all subsequent runs.
+      -- NOTE:  Take care of the last time we will get awakened.
+    elsif (NOW /= TIME'HIGH) then
+      
+      -- Verify that we woke up when S was updated.
+      if NOT(( S'EVENT ) and ( NEWTIME = NOW )) then
+        k := 0;
+      end if;
+      
+      -- See if we should continue.  If so, do it.
+      CNT    := CNT + 1;
+      if  (CNT <= 50) then
+        S       <= (not S) after 1 ns;
+        NEWTIME := NOW + 1 ns;
+      end if;
+    end if;
+    if (CNT = 50) then
+      assert NOT( k=1 )
+        report "***PASSED TEST: c09s02b00x00p07n01i01704"
+        severity NOTE;
+      assert ( k=1 )
+        report "***FAILED TEST: c09s02b00x00p07n01i01704 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p07n01i01704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd
new file mode 100644
index 0000000..992a567
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1705.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01705ent IS
+END c09s02b00x00p07n01i01705ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01705arch OF c09s02b00x00p07n01i01705ent IS
+  signal   S1 :    Bit;
+  signal   S2 :    Bit;
+BEGIN
+  TESTING: PROCESS( S1 )
+  BEGIN
+    S1   <=   '1' after 10 ns;
+  END PROCESS TESTING;
+
+  TESTING1: PROCESS
+  BEGIN
+    S2   <=   '1' after 10 ns;
+    wait on S2;
+    assert NOT(S1=S2) 
+      report "***PASSED TEST: c09s02b00x00p07n01i01705"
+      severity NOTE;
+    assert (S1=S2) 
+      report "***FAILED TEST: c09s02b00x00p07n01i01705 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING1;
+
+END c09s02b00x00p07n01i01705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd
new file mode 100644
index 0000000..879ad90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s02b00x00p10n01i01709pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c09s02b00x00p10n01i01709pkg;
+
+package body c09s02b00x00p10n01i01709pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c09s02b00x00p10n01i01709pkg;
+
+
+ENTITY c09s02b00x00p10n01i01709ent IS
+END c09s02b00x00p10n01i01709ent;
+
+use work.c09s02b00x00p10n01i01709pkg.all;
+ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
+  signal A       : WORD;
+BEGIN
+  -- Test signal arrays indexed using literal constants.  (locally static)
+  TESTING: PROCESS(A(1))
+    variable INITED : BOOLEAN := FALSE;
+    variable NewTime: TIME;
+  BEGIN
+    -- Perform the first piece of assignments.
+    if  (not(INITED)) then
+      INITED := TRUE;
+      A( 1 ) <= 'X' after 10 ns;
+      NewTime := NOW + 10 ns;
+    end if;
+    if (now = NewTime) then
+      assert NOT( A(1) = 'X' )
+        report "***PASSED TEST: c09s02b00x00p10n01i01709"
+        severity NOTE;
+      assert ( A(1) = 'X' )
+        report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd
new file mode 100644
index 0000000..4679ace
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc171.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n01i00171ent IS
+  port (ABus    : in      bit;
+        DBus    : out     bit;
+        MemReq  : in      bit;
+        BusReq  : inout   bit;
+        BusAck  : buffer  bit;
+        DataRdy : linkage bit);
+  constant Board : integer := 7 ;
+END c04s03b03x01p03n01i00171ent;
+
+ARCHITECTURE c04s03b03x01p03n01i00171arch OF c04s03b03x01p03n01i00171ent IS
+  alias SIGN1 : bit is BusReq;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c04s03b03x01p03n01i00171" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n01i00171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd
new file mode 100644
index 0000000..345de2e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1710.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01710ent IS
+END c09s02b00x00p10n01i01710ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01710arch OF c09s02b00x00p10n01i01710ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c09s02b00x00p10n01i01710"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c09s02b00x00p10n01i01710"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c09s02b00x00p10n01i01710arch;
+
+-- CONFIGURATION c09s02b00x00p10n01i01710cfg OF c09s02b00x00p10n01i01710ent IS
+--     FOR c09s02b00x00p10n01i01710arch
+--     END FOR;
+-- END c09s02b00x00p10n01i01710cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd
new file mode 100644
index 0000000..b799872
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1711.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s02b00x00p10n01i01711pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+--   type    WORD           is array(0 to 31) of SWITCH_T;
+  type    WORD           is array(1 to 32) of SWITCH_T;
+
+end c09s02b00x00p10n01i01711pkg;
+
+package body  c09s02b00x00p10n01i01711pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c09s02b00x00p10n01i01711pkg;
+
+
+ENTITY c09s02b00x00p10n01i01711ent IS
+  generic ( GenFive : in INTEGER := 12 );
+END c09s02b00x00p10n01i01711ent;
+use work.c09s02b00x00p10n01i01711pkg.all;
+ARCHITECTURE c09s02b00x00p10n01i01711arch OF c09s02b00x00p10n01i01711ent IS
+  -- Local constants.
+  constant  Three : integer := 3; 
+
+  -- Local signals.
+  signal A       : WORD;
+
+BEGIN
+  -- Test signal arrays indexed using a generic constants.  (locally static)
+  TESTING: PROCESS(A(GenFive))
+    -- Local variables.
+    variable INITED : BOOLEAN := FALSE;
+    variable NewTime: TIME;
+  BEGIN
+    -- Perform the first piece of assignments.
+    if  (not(INITED)) then
+      INITED       := TRUE;
+      A( GenFive ) <= 'X' after 10 ns;
+      NewTime    := NOW + 10 ns;
+    end if;
+    if (now = NewTime) then
+      assert NOT( A(GenFive) = 'X' )
+        report "***PASSED TEST: c09s02b00x00p10n01i01711"
+        severity NOTE;
+      assert ( A(GenFive) = 'X' )
+        report "***FAILED TEST: c09s02b00x00p10n01i01711 - Signal arrays indexed using a generic constants may be used in the sentitivity list of a porcess statement."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd
new file mode 100644
index 0000000..f2f3173
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1717.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p13n01i01717ent IS
+END c09s02b00x00p13n01i01717ent;
+
+ARCHITECTURE c09s02b00x00p13n01i01717arch OF c09s02b00x00p13n01i01717ent IS
+  -- Local signals.
+  signal A, B : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable STARTED: BOOLEAN    := FALSE;
+    variable OldTime: TIME    := 250 ns;
+    variable OldInt : INTEGER    := 13;
+    variable OldA,
+      OldB   : BIT;
+    variable I      : INTEGER;
+  BEGIN
+    -- Initialize variables for this first pass.
+    if  (NOT(STARTED)) then
+      OldTime := NOW;
+      OldInt  := 47;
+      OldA    := A;
+      OldB    := B;
+      I       := 0;
+      STARTED := TRUE;
+    elsif (I > 15) then
+      assert NOT(I = 16) 
+        report "***PASSED TEST: c09s02b00x00p13n01i01717"
+        severity NOTE;
+      assert (I = 16) 
+        report "***FAILED TEST: c09s02b00x00p13n01i01717 - The execution of a process statement consists of the repetitive execution of its sequence of statements."
+        severity ERROR;
+      wait;
+    end if;
+    -- Verify that no variables, time or signals have changed.
+    assert( OldInt = 47 )   severity ERROR;
+    assert( OldTime = NOW ) severity ERROR;
+    assert( OldA = A )      severity ERROR;
+    assert( OldB = B )      severity ERROR;
+    I := I + 1;
+  END PROCESS TESTING;
+
+  -- This process merely makes assignments to the signals A and B.
+  ASSIGN_PROCESS:   process
+  begin
+    A <= '1' ;
+    B <= '1';
+    wait;
+  end process;
+
+END c09s02b00x00p13n01i01717arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd
new file mode 100644
index 0000000..1b27aa7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1718.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p14n01i01718ent IS
+
+  -- Local procedure.
+  procedure proccall;
+  procedure proccall is
+  begin
+    assert( TRUE ) severity NOTE;
+  end;
+
+begin
+
+  -- Try a concurrent assertion statement.
+  assert( TRUE ) severity NOTE;
+
+  -- Try a passive concurrent procedure call.
+  proccall;
+
+  -- Try a passive process statement.
+  process
+  begin
+    assert( TRUE ) severity NOTE;
+    wait;
+  end process;
+
+END c09s02b00x00p14n01i01718ent;
+
+ARCHITECTURE c09s02b00x00p14n01i01718arch OF c09s02b00x00p14n01i01718ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p14n01i01718"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p14n01i01718arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd
new file mode 100644
index 0000000..cb4ea2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1719.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p16n02i01719ent IS
+END c09s02b00x00p16n02i01719ent;
+
+ARCHITECTURE c09s02b00x00p16n02i01719arch OF c09s02b00x00p16n02i01719ent IS
+  SUBTYPE bit_4 is bit_vector ( 0 to 3);
+  SUBTYPE bit_8 is bit_vector ( 0 to 7);
+
+  SIGNAL  s  : bit_8 := B"0000_0000";
+  SIGNAL  s4 : bit_4;
+  SIGNAL  s5 : bit_4;
+BEGIN
+
+  -- trigger only one element.
+  s (6) <= '1' after 10 ns;
+
+  TESTING: PROCESS(s(0 to 3))
+  BEGIN
+    assert (NOW <= 0 fs ) 
+      report "***FAILED TEST: c09s02b00x00p16n02i01719 - This process should be inactive."
+      severity ERROR;
+  END PROCESS TESTING;
+
+  p2 : PROCESS (s(3 to 6))
+  begin
+    assert NOT((s(3 to 6) = B"0001") and (NOW = 10 ns))
+      report "***PASSED TEST: c09s02b00x00p16n02i01719 - This test is passed only is the FAILED assertion did not appear."
+      severity NOTE;
+  end process p2;
+
+
+END c09s02b00x00p16n02i01719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd
new file mode 100644
index 0000000..9b4ef8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00172ent IS
+END c04s03b03x01p03n02i00172ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
+  signal    Data    : integer;
+  alias    SIGN2    : integer is Data;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Data   <= 100 after 50 ns;
+    wait for 50 ns;
+    assert NOT( SIGN2 = 100 )
+      report "***PASSED TEST: c04s03b03x01p03n02i00172"      severity NOTE;
+    assert ( SIGN2 = 100 )
+      report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd
new file mode 100644
index 0000000..237ecee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1720.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p01n02i01720ent IS
+END c12s06b01x00p01n02i01720ent;
+
+ARCHITECTURE c12s06b01x00p01n02i01720arch OF c12s06b01x00p01n02i01720ent IS
+
+  -- Global type declaration.
+  type NIBBLE is array( 0 to 3 ) of BIT;
+
+  -- Global signals.
+  SIGNAL B   : BIT := '1';
+  SIGNAL N   : NIBBLE := B"1111";
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- If one driver created, it will take on the indicated value.
+    B <= '0' after 10 ns;
+    N <= B"0000" after 10 ns;
+    wait on N,B;
+    assert NOT( B='0' and N=B"0000" )
+      report "***PASSED TEST: c12s06b01x00p01n02i01720"
+      severity NOTE;
+    assert ( B='0' and N=B"0000" )
+      report "***FAILED TEST: c12s06b01x00p01n02i01720 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p01n02i01720arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd
new file mode 100644
index 0000000..9e4a264
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1721.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p01n02i01721ent IS
+END c12s06b01x00p01n02i01721ent;
+
+ARCHITECTURE c12s06b01x00p01n02i01721arch OF c12s06b01x00p01n02i01721ent IS
+
+  -- Global signals.
+  SIGNAL B   : BIT := '1';
+
+BEGIN
+  -- If one driver created, it will take on the indicated value.
+  TESTING: PROCESS
+  BEGIN
+    B <= '0' after 10 ns;
+    B <= '1' after 10 ns;
+    B <= '0' after 10 ns;
+    wait on B;
+    assert NOT( B='0' ) 
+      report "***PASSED TEST: c12s06b01x00p01n02i01721"
+      severity NOTE;
+    assert ( B='0' ) 
+      report "***FAILED TEST: c12s06b01x00p01n02i01721 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p01n02i01721arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd
new file mode 100644
index 0000000..fa05621
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1723.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p03n01i01723ent IS
+END c12s06b01x00p03n01i01723ent;
+
+ARCHITECTURE c12s06b01x00p03n01i01723arch OF c12s06b01x00p03n01i01723ent IS
+  signal k : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= '1';
+    wait for 1 ns;
+    assert NOT(k = '1') 
+      report "***PASSED TEST: c12s06b01x00p03n01i01723" 
+      severity NOTE;
+    assert (k = '1') 
+      report "***FAILED TEST: c12s06b01x00p03n01i01723 - A driver contains at least one transaction. This should be OK."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p03n01i01723arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd
new file mode 100644
index 0000000..626bbac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1724.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p03n02i01724ent IS
+END c12s06b01x00p03n02i01724ent;
+
+ARCHITECTURE c12s06b01x00p03n02i01724arch OF c12s06b01x00p03n02i01724ent IS
+  type    SWITCH_LEVEL is ( 'X', '0', '1' );
+  subtype    LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+
+  -- Global signals.
+  SIGNAL B   : LOGIC_SWITCH := '1';
+  SIGNAL B2  : LOGIC_SWITCH;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (B='1') and (B2='0') )
+      report "***PASSED TEST: c12s06b01x00p03n02i01724"
+      severity NOTE;
+    assert ( (B='1') and (B2='0') )
+      report "***FAILED TEST: c12s06b01x00p03n02i01724 - The initial contents of a driver associated with a given signal is defined by the default value associated with the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p03n02i01724arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd
new file mode 100644
index 0000000..0945620
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p04n03i01727ent IS
+END c12s06b01x00p04n03i01727ent;
+
+ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
+  signal   B : BIT := '1';
+BEGIN
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME; 
+  BEGIN
+    B <= '1','0' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on B;
+    assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
+      report "***PASSED TEST: c12s06b01x00p04n03i01727"
+      severity NOTE;
+    assert (( NOW = ShouldBeTime ) and ( B = '0' ))
+      report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p04n03i01727arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd
new file mode 100644
index 0000000..0d3e39c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p02n01i01728ent IS
+END c09s03b00x00p02n01i01728ent;
+
+ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
+
+  procedure check (x: in integer; y: in boolean) is
+  begin
+    assert NOT( x=3 and y=true )
+      report "***PASSED TEST: c09s03b00x00p02n01i01728"
+      severity NOTE;
+    assert ( x=3 and y=true )
+      report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
+      severity ERROR;
+  end;
+
+  signal p: integer := 3;
+  signal q: boolean := true;
+
+BEGIN
+
+  check (p,q);    -- No_failure_here
+
+END c09s03b00x00p02n01i01728arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd
new file mode 100644
index 0000000..f37a21f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1729.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p02n01i01729ent IS
+END c09s03b00x00p02n01i01729ent;
+
+ARCHITECTURE c09s03b00x00p02n01i01729arch OF c09s03b00x00p02n01i01729ent IS
+
+  procedure check (x: in integer; y: in boolean) is
+  begin
+    assert NOT( x=3 and y=true )
+      report "***PASSED TEST: c09s03b00x00p02n01i01729"
+      severity NOTE;
+    assert ( x=3 and y=true )
+      report "***FAILED TEST: c09s03b00x00p02n01i01729 - A label can be used before a procedure call statement."
+      severity ERROR;
+  end;
+
+  signal p: integer := 3;
+  signal q: boolean := true;
+
+BEGIN
+
+  L1 :   check (p,q);    -- No_failure_here
+
+END c09s03b00x00p02n01i01729arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd
new file mode 100644
index 0000000..9bf2221
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc173.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00173ent IS
+END c04s03b03x01p03n02i00173ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00173arch OF c04s03b03x01p03n02i00173ent IS
+  signal    Addr : bit;
+  alias    SIGN : bit is Addr;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Addr <= '1' after 10 ns;
+    wait for 10 ns;
+    assert NOT( SIGN = '1' )
+      report "***PASSED TEST: c04s03b03x01p03n02i00173"
+      severity NOTE;
+    assert ( SIGN = '1' )
+      report "***FAILED TEST: c04s03b03x01p03n02i00173 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd
new file mode 100644
index 0000000..4ee5378
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1732.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p14n01i01732ent IS
+END c09s03b00x00p14n01i01732ent;
+
+ARCHITECTURE c09s03b00x00p14n01i01732arch OF c09s03b00x00p14n01i01732ent IS
+  signal    s1 : bit;
+  signal    s2 : integer;
+  signal    s3 : integer;
+
+  procedure unguarded_proc (where : in integer; signal here : out integer) is
+  begin
+    if where = 1 then
+      here <= 5;
+    else
+      here <= 6;
+    end if;
+  end;
+
+BEGIN
+  s3   <= 1 after 20 ns;
+
+  block_label1 : BLOCK ( s1 = '1' )
+  begin
+    unguarded_proc (s3,s2);
+  end block block_label1;
+
+  TESTING: PROCESS(s2)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT( s2=5 )
+        report "***PASSED TEST: c09s03b00x00p14n01i01732"
+        severity NOTE;
+      assert ( s2=5 )
+        report "***FAILED TEST: c09s03b00x00p14n01i01732 - The value of an implicitly declared signal GUARD has no effect on evaluation of a concurrent procedure call."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s03b00x00p14n01i01732arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd
new file mode 100644
index 0000000..c45979a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1733.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p14n01i01733ent IS
+END c09s03b00x00p14n01i01733ent;
+
+ARCHITECTURE c09s03b00x00p14n01i01733arch OF c09s03b00x00p14n01i01733ent IS
+  signal    s1 : bit;
+  signal    s2 : integer;
+
+  procedure guarded_proc (signal guard_signal : in boolean; where : in integer; signal here : out integer) is
+  begin
+    if (where = 1) and (guard_signal = true) then
+      here <= 5;
+    else
+      here <= 6;
+    end if;
+  end;
+
+BEGIN
+  s1   <= '1' after 45 ns;
+
+  block_label1 : BLOCK ( s1 = '1' )
+  begin
+    guarded_proc (GUARD,1,s2);
+  end block block_label1;
+
+  TESTING: PROCESS(s2)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT(s2 = 5)
+        report "***PASSED TEST: c09s03b00x00p14n01i01733"
+        severity NOTE;
+      assert (s2 = 5)
+        report "***FAILED TEST: c09s03b00x00p14n01i01733 - If the value of an implicitly declared signal GUARD is explicitly referenced in the actual parameter part of the concurrent proccedure call, then it has effect on evaluation of a concurrent procedure call."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s03b00x00p14n01i01733arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd
new file mode 100644
index 0000000..2579ad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1734.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p02n01i01734ent IS
+begin
+  l1: assert false
+    report "Labeled concurrent assert OK in entity."
+    severity note ;
+  assert false
+    report "Unlabeled concurrent assert OK in entity."
+    severity note ;
+END c09s04b00x00p02n01i01734ent;
+
+ARCHITECTURE c09s04b00x00p02n01i01734arch OF c09s04b00x00p02n01i01734ent IS
+
+BEGIN
+  l2: assert false
+    report "Labeled concurrent assert OK in architecture."
+    severity note ;
+  assert false
+    report "Unlabeled concurrent assert OK in architecture."
+    severity note ;
+
+  B : block
+  BEGIN
+    l1: assert false
+      report "Labeled concurrent assert OK in block."
+      severity note ;
+    assert false
+      report "Unlabeled concurrent assert OK in block."
+      severity note ;
+
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p02n01i01734 - This test is passed if and only if we get other six assertion sentence."
+      severity NOTE;
+  end block B;
+
+END c09s04b00x00p02n01i01734arch;
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd
new file mode 100644
index 0000000..24214d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1735.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p06n01i01735ent IS
+END c09s04b00x00p06n01i01735ent;
+
+ARCHITECTURE c09s04b00x00p06n01i01735arch OF c09s04b00x00p06n01i01735ent IS
+  signal arch_s1 : bit;
+  signal arch_s2 : boolean;
+  signal arch_s3 : character;
+  signal arch_s4 : severity_level;
+  signal arch_s5 : integer;
+  signal arch_s6 : real;
+  signal arch_s7 : time;
+  signal arch_s8 : positive;
+  signal arch_s9 : natural;
+BEGIN
+  ASSERT arch_s1 /= bit'left 
+    REPORT "bit concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s2 /= boolean'left 
+    REPORT "boolean concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s3 /= character'left 
+    REPORT "character concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s4 /= severity_level'left 
+    REPORT "severity_level concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s5 /= integer'left 
+    REPORT "integer concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s6 /= real'left 
+    REPORT "real concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s7 /= time'left 
+    REPORT "time concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s8 /= positive'left 
+    REPORT "positive concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s9 /= natural'left 
+    REPORT "natural concurrent assertion" 
+    severity NOTE;
+  TESTING: PROCESS
+  BEGIN
+    ASSERT arch_s1 /= bit'left 
+      REPORT "bit concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s2 /= boolean'left 
+      REPORT "boolean concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s3 /= character'left 
+      REPORT "character concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s4 /= severity_level'left 
+      REPORT "severity_level concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s5 /= integer'left 
+      REPORT "integer concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s6 /= real'left 
+      REPORT "real concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s7 /= time'left 
+      REPORT "time concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s8 /= positive'left 
+      REPORT "positive concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s9 /= natural'left 
+      REPORT "natural concurrent assertion" 
+      severity NOTE;
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p06n01i01735 - This need manual check - The concurrent assertion statement and the sequential assertion should print out the same ASSERTION NOTES."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s04b00x00p06n01i01735arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd
new file mode 100644
index 0000000..b759bd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1736.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p08n01i01736ent IS
+END c09s04b00x00p08n01i01736ent;
+
+ARCHITECTURE c09s04b00x00p08n01i01736arch OF c09s04b00x00p08n01i01736ent IS
+
+BEGIN
+  assert FALSE 
+    report "***PASSED TEST: c09s04b00x00p08n01i01736 - This test need manual check. No other assertion note should appear."
+    severity NOTE;
+  assert TRUE 
+    report "***FAILED TEST: c09s04b00x00p08n01i01736 - Only when the assertion is false, then the specified message will be sent to the simulation report."
+    severity ERROR;
+
+END c09s04b00x00p08n01i01736arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd
new file mode 100644
index 0000000..2da9b79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p10n01i01739ent IS
+begin
+  assert false 
+    report "Success:entity assertion with static expression" 
+    severity NOTE;
+END c09s04b00x00p10n01i01739ent;
+
+ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
+
+BEGIN
+  assert false 
+    report "Success:architecture assertion with static expression" 
+    severity NOTE;
+
+  b: block
+  begin
+    assert false 
+      report "Success:architecture in block: assertion with static expression" 
+      severity NOTE;
+  end block b;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s04b00x00p10n01i01739arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd
new file mode 100644
index 0000000..7d26a88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1744.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p03n01i01744ent IS
+  port   (parallel_in    : bit_vector (7 downto 0);
+          clock      : bit;
+          serial_out   : out bit);
+END c09s05b00x00p03n01i01744ent;
+
+ARCHITECTURE c09s05b00x00p03n01i01744arch OF c09s05b00x00p03n01i01744ent IS
+  constant    bit_time    : time    := 1 ns;
+  signal       GUARD      : boolean:= TRUE;
+BEGIN
+  serial_out <= guarded transport    -- No_failure_here
+                parallel_in(7) after 1*bit_time,
+                parallel_in(6) after 2*bit_time,
+                parallel_in(5) after 3*bit_time,
+                parallel_in(4) after 4*bit_time,
+                parallel_in(3) after 5*bit_time,
+                parallel_in(2) after 6*bit_time,
+                parallel_in(1) after 7*bit_time,
+                parallel_in(0) after 8*bit_time,
+                '0' after 9*bit_time;
+  PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s05b00x00p03n01i01744" 
+      severity NOTE;
+    wait;
+  END PROCESS;
+
+END c09s05b00x00p03n01i01744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd
new file mode 100644
index 0000000..9768509
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p05n03i01745ent IS
+END c09s05b00x00p05n03i01745ent;
+
+ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
+  signal   A    : bit    := '0';
+BEGIN
+  A   <= transport '1' after 10 ns;
+  TESTING: PROCESS(A)
+    variable NEWTIME : TIME;
+  BEGIN
+    NEWTIME := now;
+    if ( now > 1 ns ) then
+      assert NOT( A= '1' and NEWTIME = 10 ns )
+        report "***PASSED TEST: c09s05b00x00p05n03i01745"
+        severity NOTE;
+      assert ( A= '1' and NEWTIME = 10 ns )
+        report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b00x00p05n03i01745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd
new file mode 100644
index 0000000..91a4913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p12n02i01747ent IS
+  function resolve_bit ( inputs : bit_vector) return bit is
+    VARIABLE val : bit := '0';
+  begin
+    if inputs'length = 0 then
+      return val;
+    else
+      for i in inputs'range LOOP
+        if inputs(i) = '1' then return '1'; end if;
+      END LOOP;
+      return '0';
+    end if;
+  end resolve_bit;
+END c09s05b00x00p12n02i01747ent;
+
+ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
+  signal      a      : resolve_bit bit BUS;
+  signal    b      : resolve_bit bit BUS;
+  signal    grd    : boolean;
+
+BEGIN
+  grd <=    TRUE    after 10 ns,
+            FALSE   after 20 ns; 
+
+  block_label : BLOCK (grd)
+  begin
+    b <= guarded '1' after 1 ns;
+  end block block_label;
+
+  block_label_1 : BLOCK (grd)
+  begin
+    TESTING: PROCESS
+    BEGIN
+      if GUARD then
+        a <= '1' after 1 ns;
+      else
+        a <= NULL;
+      end if;
+      wait on GUARD, a;
+    END PROCESS TESTING;
+  end block block_label_1;
+  
+  process(a,b)
+    variable f1, f2 : integer := 0;
+  begin
+    if    (now = 11 ns) and (a=b) then
+      f1 := 1;
+    end if;
+    if    (now = 20 ns) and (a=b) then
+      f2 := 1;
+    end if;
+    if (now = 20 ns) then   
+      assert NOT((f1=1) and (f2=1)) 
+        report "***PASSED TEST: c09s05b00x00p12n02i01747"
+        severity NOTE;
+      assert ((f1=1) and (f2=1)) 
+        report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
+        severity ERROR;
+    end if;
+  end process;
+
+END c09s05b00x00p12n02i01747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd
new file mode 100644
index 0000000..bc9624f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1748.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p16n01i01748ent IS
+END c09s05b00x00p16n01i01748ent;
+
+ARCHITECTURE c09s05b00x00p16n01i01748arch OF c09s05b00x00p16n01i01748ent IS
+  signal gate_1    : BIT;
+  signal gate_2    : BIT;
+  signal data_in    : BIT;
+  signal data_pass    : BIT;
+  signal data_latch    : BIT;
+BEGIN
+
+  gate_1    <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
+  gate_2    <= gate_1 after 1 ns;
+  data_in    <=    '1' after  5 ns, '0' after 25 ns,
+                   '1' after 35 ns, '0' after 36 ns,
+                   '1' after 37 ns, '0' after 38 ns,
+                   '1' after 39 ns, '0' after 40 ns,
+                   '1' after 41 ns, '0' after 42 ns;
+
+  B: block ((gate_1 and gate_2) = '1')
+  begin
+    data_pass    <=       data_in;
+    data_latch    <= guarded    data_in;
+  end block;
+
+  TESTING: PROCESS(data_pass,data_latch)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if not(data_pass'event and data_pass = '1' and data_latch'quiet and data_latch = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 11 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'quiet and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 25 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 31 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'quiet and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 35 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 36 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 37 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 38 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 39 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 40 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 41 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    end if;
+
+    if (now > 41 ns) then   
+      assert NOT( ok=1 )
+        report "***PASSED TEST: c09s05b00x00p16n01i01748"
+        severity NOTE;
+      assert ( ok=1 )
+        report "***FAILED TEST: c09s05b00x00p16n01i01748 - Concurrent signal assignment test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b00x00p16n01i01748arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd
new file mode 100644
index 0000000..da754bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1753.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p25n01i01753ent IS
+END c09s05b00x00p25n01i01753ent;
+
+ARCHITECTURE c09s05b00x00p25n01i01753arch OF c09s05b00x00p25n01i01753ent IS
+  type byte is array (positive range <>) of bit;
+
+  function F (constant S: byte) return bit is
+  begin
+    return '0';
+  end;
+
+  constant    N    : integer := 4;
+  signal       UG,I   : bit_vector(1 to 4);
+  signal       GS, UGS   : bit;
+  signal       UGT   : F bit register;
+BEGIN
+  A: (I(1), I(2), I(3), I(N)) <= transport UG(1 to N) after 20 ns;  -- No_failure_here
+  
+  GS   <=   '1' after 10 ns; 
+  B:block (GS = '1')
+  begin
+    C: UGT <= guarded UGS after 10 ns;  -- No_failure_here
+  end block;
+  TESTING: PROCESS(I,UGT)
+  BEGIN
+    assert NOT(I="0000" and UGT='0')  
+      report "***PASSED TEST: c09s05b00x00p25n01i01753" 
+      severity NOTE;
+    assert (I="0000" and UGT='0')  
+      report "***FAILED TEST: c09s05b00x00p25n01i01753 - An aggregate target in a concurrent signal assignment statement contains only locally static names, and no two signal names identify the same object, or subelement thereof." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b00x00p25n01i01753arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd
new file mode 100644
index 0000000..2a60eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p01n01i01756ent IS
+END c09s05b01x00p01n01i01756ent;
+
+ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  ECLK <=  U   after 1 ns WHEN count=0 ELSE
+           D   after 1 ns WHEN count=1 ELSE
+           Z0  after 1 ns WHEN count=2 ELSE
+           Z1  after 1 ns WHEN count=3 ELSE
+           ZDX after 1 ns WHEN count=4 ELSE
+           DZX after 1 ns WHEN count=5 ELSE
+           ZX  after 1 ns ;
+  TESTING: PROCESS(count)
+  BEGIN
+    if   count = 0 then
+      ECLK2 <= U   after 1 ns;
+    elsif   count = 1 then
+      ECLK2 <= D   after 1 ns;
+    elsif   count = 2 then
+      ECLK2 <= Z0  after 1 ns;
+    elsif   count = 3 then
+      ECLK2 <= Z1  after 1 ns;
+    elsif   count = 4 then
+      ECLK2 <= ZDX after 1 ns;
+    elsif   count = 5 then
+      ECLK2 <= DZX after 1 ns;
+    else
+      ECLK2 <= ZX  after 1 ns;
+    end if;   
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if       now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if      (now > 60 ns) and (ECL = 1) then
+      assert FALSE
+        report "***PASSED TEST: c09s05b01x00p01n01i01756"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE
+        report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b01x00p01n01i01756arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd
new file mode 100644
index 0000000..18b7cf7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p01n01i01757ent IS
+END c09s05b01x00p01n01i01757ent;
+
+ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  ECLK <= transport 
+          U   after 1 ns WHEN count=0 ELSE
+          D   after 1 ns WHEN count=1 ELSE
+          Z0  after 1 ns WHEN count=2 ELSE
+          Z1  after 1 ns WHEN count=3 ELSE
+          ZDX after 1 ns WHEN count=4 ELSE
+          DZX after 1 ns WHEN count=5 ELSE
+          ZX  after 1 ns ;
+  TESTING: PROCESS(count)
+  BEGIN
+    if   count = 0 then
+      ECLK2 <= transport U   after 1 ns;
+    elsif   count = 1 then
+      ECLK2 <= transport D   after 1 ns;
+    elsif   count = 2 then
+      ECLK2 <= transport Z0  after 1 ns;
+    elsif   count = 3 then
+      ECLK2 <= transport Z1  after 1 ns;
+    elsif   count = 4 then
+      ECLK2 <= transport ZDX after 1 ns;
+    elsif   count = 5 then
+      ECLK2 <= transport DZX after 1 ns;
+    else
+      ECLK2 <= transport ZX  after 1 ns;
+    end if;   
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if       now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if      (now > 60 ns) and (ECL = 1) then
+      assert FALSE
+        report "***PASSED TEST: c09s05b01x00p01n01i01757"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE
+        report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b01x00p01n01i01757arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd
new file mode 100644
index 0000000..f7f746b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc176.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00176ent IS
+END c04s03b03x01p03n02i00176ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00176arch OF c04s03b03x01p03n02i00176ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable REAL_NUMBER: BIT_VECTOR(0 to 31);
+    alias    SIGN:        bit          is REAL_NUMBER(0);
+    alias    MANTISSA:    BIT_VECTOR(23 downto 0)    is REAL_NUMBER(8 to 31);
+    alias    EXPONENT:    BIT_VECTOR(1 to 7)    is REAL_NUMBER(1 to 7);
+  BEGIN
+    REAL_NUMBER := "00011011000110111110010011100100";
+    wait for 10 ns;
+    assert NOT(   SIGN   = '0'         and
+                  MANTISSA= "000110111110010011100100"and
+                  EXPONENT= "0011011"   )
+      report "***PASSED TEST:c04s03b03x01p03n02i00176" 
+      severity NOTE;
+    assert (   SIGN   = '0'         and
+               MANTISSA= "000110111110010011100100"and
+               EXPONENT= "0011011"   )
+      report "***FAILED TEST: c04s03b03x01p03n02i00176 - A single dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd
new file mode 100644
index 0000000..7d679bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1761.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p21n01i01761ent IS
+END c09s05b01x00p21n01i01761ent;
+
+ARCHITECTURE c09s05b01x00p21n01i01761arch OF c09s05b01x00p21n01i01761ent IS
+  signal TS1,TS2   : integer;
+  signal B,C   : integer;
+  signal D,E,F   : bit;
+BEGIN
+  TS1 <= transport 1 after 10 ns when B = C else
+         2 after 10 ns when B > C else
+         3 after 10 ns;
+
+  TS2 <= transport 4-1 after 10 ns when D = '1' else
+         5+1 after 10 ns when E = '1' else
+         6*2 after 10 ns when F = '1' else
+         8/2 after 10 ns;
+
+  TESTING: PROCESS(TS1,TS2)
+  BEGIN
+    if ( now > 1 ns) then
+      assert NOT(TS1=1 and TS2=4) 
+        report "***PASSED TEST: c09s05b01x00p21n01i01761" 
+        severity NOTE;
+      assert (TS1=1 and TS2=4) 
+        report "***FAILED TEST: c09s05b01x00p21n01i01761 - Conditions in the conditional signal assignment statement should be valid." 
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b01x00p21n01i01761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd
new file mode 100644
index 0000000..f9c2248
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1762.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p01n01i01762ent IS
+END c09s05b02x00p01n01i01762ent;
+
+ARCHITECTURE c09s05b02x00p01n01i01762arch OF c09s05b02x00p01n01i01762ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  WITH count SELECT
+    ECLK <=  U   after 1 ns WHEN 0,
+    D   after 1 ns WHEN 1,
+    Z0  after 1 ns WHEN 2,
+    Z1  after 1 ns WHEN 3,
+    ZDX after 1 ns WHEN 4,
+    DZX after 1 ns WHEN 5,
+    ZX  after 1 ns WHEN OTHERS;
+  TESTING: PROCESS(count)
+  BEGIN
+    case count is
+      WHEN 0      => ECLK2 <= U   after 1 ns;
+      WHEN 1      => ECLK2 <= D   after 1 ns;
+      WHEN 2      => ECLK2 <= Z0  after 1 ns;
+      WHEN 3      => ECLK2 <= Z1  after 1 ns;
+      WHEN 4      => ECLK2 <= ZDX after 1 ns;
+      WHEN 5      => ECLK2 <= DZX after 1 ns;
+      WHEN OTHERS   => ECLK2 <= ZX  after 1 ns;
+    end case;
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif    (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    (now > 60 ns) and (ECL = 1) then
+      assert FALSE 
+        report "***PASSED TEST: c09s05b02x00p01n01i01762"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE 
+        report "***FAILED TEST: c09s05b02x00p01n01i01762 - The selected signal assignment represents a process statement in which the signal transform is a case statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b02x00p01n01i01762arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd
new file mode 100644
index 0000000..bebd842
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1763.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p01n01i01763ent IS
+END c09s05b02x00p01n01i01763ent;
+
+ARCHITECTURE c09s05b02x00p01n01i01763arch OF c09s05b02x00p01n01i01763ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,   
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  WITH count SELECT
+    ECLK <=    transport 
+    U   after 1 ns WHEN 0,
+    D   after 1 ns WHEN 1,
+    Z0  after 1 ns WHEN 2,
+    Z1  after 1 ns WHEN 3,
+    ZDX after 1 ns WHEN 4,
+    DZX after 1 ns WHEN 5,
+    ZX  after 1 ns WHEN OTHERS;
+  TESTING: PROCESS(count)
+  BEGIN
+    case count is
+      WHEN 0      => ECLK2 <= transport U   after 1 ns;
+      WHEN 1      => ECLK2 <= transport D   after 1 ns;
+      WHEN 2      => ECLK2 <= transport Z0  after 1 ns;
+      WHEN 3      => ECLK2 <= transport Z1  after 1 ns;
+      WHEN 4      => ECLK2 <= transport ZDX after 1 ns;
+      WHEN 5      => ECLK2 <= transport DZX after 1 ns;
+      WHEN OTHERS   => ECLK2 <= transport ZX  after 1 ns;
+    end case;
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif    (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    (now > 60 ns) and (ECL = 1) then
+      assert FALSE 
+        report "***PASSED TEST: c09s05b02x00p01n01i01763"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE 
+        report "***FAILED TEST: c09s05b02x00p01n01i01763 - The transport selected signal assignment represents a process statement in which the signal transform is a case statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b02x00p01n01i01763arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd
new file mode 100644
index 0000000..af96b37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1766.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p02n01i01766ent IS
+END c09s05b02x00p02n01i01766ent;
+
+ARCHITECTURE c09s05b02x00p02n01i01766arch OF c09s05b02x00p02n01i01766ent IS
+  signal   i,j   : integer := 1;
+BEGIN
+
+  with i select                        -- No_failure_here
+            j <= transport 1 when 1,
+                 2 when 2,
+                 3 when others;
+  TESTING: PROCESS(j)
+  BEGIN
+    assert NOT(j = 1) 
+      report "***PASSED TEST: c09s05b02x00p02n01i01766"
+      severity NOTE;
+    assert (j = 1) 
+      report "***FAILED TEST: c09s05b02x00p02n01i01766 - In the selected signal assignment, the reserved word with must be followed by an expression and the reserved word select." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b02x00p02n01i01766arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd
new file mode 100644
index 0000000..280e424
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1775.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01775ent IS
+END c09s05b02x00p11n01i01775ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01775arch OF c09s05b02x00p11n01i01775ent IS
+  signal i : integer := 21;
+  signal j : boolean ;
+BEGIN
+
+  with i select
+    j <= transport
+    TRUE  when 1  to 19,  -- No_failure_here
+                              -- Valid expression for a choice
+    FALSE when 20 to 29,
+    TRUE  when 30 to 49,
+    FALSE when others;
+
+  TESTING: PROCESS(j)
+  BEGIN
+    assert NOT(j = FALSE) 
+      report "***PASSED TEST: c09s05b02x00p11n01i01775" 
+      severity NOTE;
+    assert (j = FALSE) 
+      report "***FAILED TEST: c09s05b02x00p11n01i01775 - Each value of the type of the select expression should be represented once and exactly once." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01775arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd
new file mode 100644
index 0000000..d031c04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1776.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01776ent IS
+END c09s05b02x00p11n01i01776ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01776arch OF c09s05b02x00p11n01i01776ent IS
+  SUBTYPE string_30 is STRING(1 to 30);
+  SUBTYPE string_4  is STRING(1 to 4);
+  CONSTANT    str    : string_30 := "1234567890abcdefghijlkmnopqrst";
+  SIGNAL    s    : bit;
+BEGIN
+
+  -- test point
+  with string_4'(str(1 to 4)) select
+    s <=    '1' after 10 ns when "1234",
+    '0' after 10 ns when OTHERS;
+
+  TESTING : PROCESS(s)
+  BEGIN
+    if (now = 10 ns) then
+      assert NOT(s='1') 
+        report "***PASSED TEST: c09s05b02x00p11n01i01776" 
+        severity NOTE;
+      assert (s='1')
+        report "***FAILED TEST: c09s05b02x00p11n01i01776 - Qualified expression used as the expression in a selected signal assignment fialed." 
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01776arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd
new file mode 100644
index 0000000..9f37834
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n05i01781pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n05i01781pkg;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+entity c09s06b00x00p04n05i01781ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector     ;
+    gB  :   stuff
+    );
+end c09s06b00x00p04n05i01781ent_a;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   g0 = True                   and 
+                  g1 = '0'                      and  
+                  g2 = '@'                      and 
+                  g3 = NOTE                     and 
+                  g4 = 123456789                and 
+                  g5 = 987654321.5              and 
+                  g6 = 110  ns                   and 
+                  g7 = 12312                    and 
+                  g8 = 3423                     and 
+                  g9 = "16 characters OK"       and 
+                  gA = B"01010010100101010010101001010100"and 
+                  gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n05i01781"
+      severity NOTE;
+    assert (   g0 = True                   and 
+               g1 = '0'                      and  
+               g2 = '@'                      and 
+               g3 = NOTE                     and 
+               g4 = 123456789                and 
+               g5 = 987654321.5              and 
+               g6 = 110  ns                   and 
+               g7 = 12312                    and 
+               g8 = 3423                     and 
+               g9 = "16 characters OK"       and 
+               gA = B"01010010100101010010101001010100"and 
+               gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c09s06b00x00p04n05i01781arch_a;
+
+-------------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n05i01781ent IS
+END c09s06b00x00p04n05i01781ent;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector     ;
+      gB  :   stuff
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
+
+BEGIN
+  u1 : MultiType
+    generic map (
+      True,
+      '0',
+      '@',
+      NOTE,
+      123456789,
+      987654321.5,
+      110 ns,
+      12312,
+      3423,
+      "16 characters OK",
+      B"0101_0010_1001_0101_0010_1010_0101_0100",
+      gB(2) => ( 890, 135.7 ),
+      gB(1) => ( 123, 456.7 )
+      );
+
+END c09s06b00x00p04n05i01781arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd
new file mode 100644
index 0000000..567dca0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1782.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n05i01782pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n05i01782pkg;
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+entity c09s06b00x00p04n05i01782ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector     ;
+    gB  :   stuff      := ((234,567.7),(429,35.7))
+    );
+end c09s06b00x00p04n05i01782ent_a;
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+architecture c09s06b00x00p04n05i01782arch_a of c09s06b00x00p04n05i01782ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT(   g0 = True                   and 
+                  g1 = '0'                      and  
+                  g2 = '@'                      and 
+                  g3 = NOTE                     and 
+                  g4 = 123456789                and 
+                  g5 = 987654321.5              and 
+                  g6 = 110  ns                   and 
+                  g7 = 12312                    and 
+                  g8 = 3423                     and 
+                  g9 = "16 characters OK"       and 
+                  gA = B"01010010100101010010101001010100"and 
+                  gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n05i01782"
+      severity NOTE;
+    assert (   g0 = True                   and 
+               g1 = '0'                      and  
+               g2 = '@'                      and 
+               g3 = NOTE                     and 
+               g4 = 123456789                and 
+               g5 = 987654321.5              and 
+               g6 = 110  ns                   and 
+               g7 = 12312                    and 
+               g8 = 3423                     and 
+               g9 = "16 characters OK"       and 
+               gA = B"01010010100101010010101001010100"and 
+               gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n05i01782 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c09s06b00x00p04n05i01782arch_a;
+
+-------------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n05i01782ent IS
+END c09s06b00x00p04n05i01782ent;
+
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+ARCHITECTURE c09s06b00x00p04n05i01782arch OF c09s06b00x00p04n05i01782ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector     ;
+      gB  :   stuff      :=((123,456.7),(890,135.7))); 
+  end component; 
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01782ent_a(c09s06b00x00p04n05i01782arch_a); 
+BEGIN 
+  u1 : MultiType generic map ( 
+    True, 
+    '0', 
+    '@', 
+    NOTE, 
+    123456789,
+    987654321.5,
+    110 ns,
+    12312,
+    3423,
+    "16 characters OK",
+    B"0101_0010_1001_0101_0010_1010_0101_0100"
+    );
+
+END c09s06b00x00p04n05i01782arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd
new file mode 100644
index 0000000..b76d370
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd
@@ -0,0 +1,154 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1785.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n07i01785pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n07i01785pkg;
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+entity c09s06b00x00p04n07i01785ent_a is
+  port    (
+    port_0  : in Boolean        ;
+    port_1  : in Bit            ;
+    port_2  : in Character      ;
+    port_3  : in SEVERITY_LEVEL ;
+    port_4  : in Integer        ;
+    port_5  : in Real           ;
+    port_6  : in TIME           ;
+    port_7  : in Natural        ;
+    port_8  : in Positive       ;
+    port_9  : in String         ; 
+    port_A  : in Bit_vector     ;
+    port_B  : in stuff
+    );
+end c09s06b00x00p04n07i01785ent_a;
+
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+architecture c09s06b00x00p04n07i01785arch_a of c09s06b00x00p04n07i01785ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING: PROCESS(port_0,port_1,port_2,port_3,port_4,port_5,port_6,port_7,port_8)
+  BEGIN
+    assert NOT(   port_0 = True                and 
+                  port_1 = '0'                and 
+                  port_2 = '@'                  and 
+                  port_3 = NOTE                and 
+                  port_4 = 123456789                 and
+                  port_5 = 987654321.5              and
+                  port_6 = 110 ns                  and
+                  port_7 = 12312                  and 
+                  port_8 = 3423                  and 
+                  port_9 = "16 characters OK"          and 
+                  port_A = B"01010010100101010010101001010100"    and 
+                  port_B = ((123, 456.7), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n07i01785"
+      severity NOTE;
+    assert (   port_0 = True                and 
+               port_1 = '0'                and 
+               port_2 = '@'                  and 
+               port_3 = NOTE                and 
+               port_4 = 123456789                 and
+               port_5 = 987654321.5              and
+               port_6 = 110 ns                  and
+               port_7 = 12312                  and 
+               port_8 = 3423                  and 
+               port_9 = "16 characters OK"          and 
+               port_A = B"01010010100101010010101001010100"    and 
+               port_B = ((123, 456.7), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n07i01785 - Port map aspect associates a single actual with each local port in the corresponding component declaration test failed."
+      severity ERROR;
+  END PROCESS TESTING;
+end c09s06b00x00p04n07i01785arch_a;
+
+-----------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n07i01785ent IS
+END c09s06b00x00p04n07i01785ent;
+
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+ARCHITECTURE c09s06b00x00p04n07i01785arch OF c09s06b00x00p04n07i01785ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  
+  signal sig_0  :   Boolean        := TRUE;
+  signal sig_1  :   Bit            := '0';
+  signal sig_2  :   Character      := '@';
+  signal sig_3  :   SEVERITY_LEVEL := NOTE;
+  signal sig_4  :   Integer        := 123456789;
+  signal sig_5  :   Real           := 987654321.5;
+  signal sig_6  :   TIME           := 110 NS;
+  signal sig_7  :   Natural        := 12312;
+  signal sig_8  :   Positive       := 3423;
+  signal sig_9  :   String16       := "16 characters OK";
+  signal sig_A  :   REG32          := B"0101_0010_1001_0101_0010_1010_0101_0100";
+  signal sig_B  :   stuff          := (( 123, 456.7 ), ( 890, 135.7 ));
+
+  component MultiType
+    port    (
+      port_0  : in Boolean        ;
+      port_1  : in Bit            ;
+      port_2  : in Character      ;
+      port_3  : in SEVERITY_LEVEL ;
+      port_4  : in Integer        ;
+      port_5  : in Real           ;
+      port_6  : in TIME           ;
+      port_7  : in Natural        ;
+      port_8  : in Positive       ;
+      port_9  : in String         ;
+      port_A  : in Bit_vector     ;
+      port_B  : in stuff
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n07i01785ent_a (c09s06b00x00p04n07i01785arch_a);
+
+BEGIN
+  u1 : MultiType
+    port map (
+      port_0 => sig_0,
+      port_1 => sig_1,
+      port_2 => sig_2,
+      port_3 => sig_3,
+      port_4 => sig_4,
+      port_5 => sig_5,
+      port_6 => sig_6,
+      port_7 => sig_7,
+      port_8 => sig_8,
+      port_9 => sig_9,
+      port_A => sig_A,
+      port_B => sig_B
+      );
+
+END c09s06b00x00p04n07i01785arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd
new file mode 100644
index 0000000..9088d0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c09s06b00x00p04n05i01787ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector
+    );
+  port    (
+    port0  : out  Boolean        ;
+    port1  : out  Bit            ;
+    port2  : out  Character      ;
+    port3  : out  SEVERITY_LEVEL ;
+    port4  : out  Integer        ;
+    port5  : out  Real           ;
+    port6  : out  TIME           ;
+    port7  : out  Natural        ;
+    port8  : out  Positive       ;
+    port9  : out  String         ;
+    portA  : out  Bit_vector
+    );
+end c09s06b00x00p04n05i01787ent_a;
+
+architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
+begin
+  port0 <= g0 after 11 ns;
+  port1 <= g1 after 11 ns;
+  port2 <= g2 after 11 ns;
+  port3 <= g3 after 11 ns;
+  port4 <= g4 after 11 ns;
+  port5 <= g5 after 11 ns;
+  port6 <= g6 after 11 ns;
+  port7 <= g7 after 11 ns;
+  port8 <= g8 after 11 ns;
+  port9 <= g9 after 11 ns;
+  portA <= gA after 11 ns;
+end c09s06b00x00p04n05i01787arch_a;
+
+ENTITY c09s06b00x00p04n05i01787ent IS
+END c09s06b00x00p04n05i01787ent;
+
+ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector
+      );
+    port    (
+      port0  : out  Boolean        ;
+      port1  : out  Bit            ;
+      port2  : out  Character      ;
+      port3  : out  SEVERITY_LEVEL ;
+      port4  : out  Integer        ;
+      port5  : out  Real           ;
+      port6  : out  TIME           ;
+      port7  : out  Natural        ;
+      port8  : out  Positive       ;
+      port9  : out  String         ;
+      portA  : out  Bit_vector
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
+
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  
+  signal signal0  :   Boolean        ;
+  signal signal1  :   Bit            ;
+  signal signal2  :   Character      ;
+  signal signal3  :   SEVERITY_LEVEL ;
+  signal signal4  :   Integer        ;
+  signal signal5  :   Real           ;
+  signal signal6  :   TIME           ;
+  signal signal7  :   Natural        ;
+  signal signal8  :   Positive       ;
+  signal signal9  :   String16       ;
+  signal signalA  :   Reg32          ;
+  
+
+BEGIN
+  u1 : MultiType
+    generic map (
+      True,
+      '0',
+      '@',
+      NOTE,
+      123456789,
+      987654321.5,
+      110 ns,
+      12312,
+      3423,
+      "16 characters OK",
+      B"0101_0010_1001_0101_0010_1010_0101_0100"
+      )
+    port map (
+      signal0  ,
+      signal1  ,
+      signal2  ,
+      signal3  ,
+      signal4  ,
+      signal5  ,
+      signal6  ,
+      signal7  ,
+      signal8  ,
+      signal9  ,
+      signalA
+      );
+
+  TESTING: PROCESS
+  BEGIN
+    wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
+    assert NOT(   signal0 = True                  and 
+                  signal1 = '0'                   and    
+                  signal2 = '@'                  and 
+                  signal3 = NOTE                and 
+                  signal4 = 123456789          and 
+                  signal5 = 987654321.5          and 
+                  signal6 = 110 ns              and 
+                  signal7 = 12312              and 
+                  signal8 = 3423              and 
+                  signal9 = "16 characters OK"    and 
+                  signalA = B"01010010100101010010101001010100")
+      report "***PASSED TEST: c09s06b00x00p04n05i01787"
+      severity NOTE;
+    assert (   signal0 = True                  and 
+               signal1 = '0'                   and    
+               signal2 = '@'                  and 
+               signal3 = NOTE                and 
+               signal4 = 123456789          and 
+               signal5 = 987654321.5          and 
+               signal6 = 110 ns              and 
+               signal7 = 12312              and 
+               signal8 = 3423              and 
+               signal9 = "16 characters OK"    and 
+               signalA = B"01010010100101010010101001010100")
+      report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p04n05i01787arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd
new file mode 100644
index 0000000..cf6d060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc179.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p02n01i00179ent IS
+  attribute attr : INTEGER;
+END c04s04b00x00p02n01i00179ent;
+
+ARCHITECTURE c04s04b00x00p02n01i00179arch OF c04s04b00x00p02n01i00179ent IS
+  constant    C : INTEGER    := 1;
+  attribute    attr of C : CONSTANT       is 40;
+  constant    D : INTEGER    := C'attr;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( C = 1 and D = 40 )
+      report "***PASSED TEST: c04s04b00x00p02n01i00179"
+      severity NOTE;
+    assert ( C = 1 and D = 40 )
+      report "***FAILED TEST: c04s04b00x00p02n01i00179 - User-defined attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p02n01i00179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd
new file mode 100644
index 0000000..b397f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1792.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p05n01i01792ent IS
+END c09s07b00x00p05n01i01792ent;
+
+ARCHITECTURE c09s07b00x00p05n01i01792arch OF c09s07b00x00p05n01i01792ent IS
+
+BEGIN
+  L1: for I in 1 to 3 generate
+  end generate L1;
+
+  L2: if true generate
+  end generate L2;            -- No_failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s07b00x00p05n01i01792" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p05n01i01792arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd
new file mode 100644
index 0000000..c50f943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1793.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p06n02i01793ent IS
+END c09s07b00x00p06n02i01793ent;
+
+ARCHITECTURE c09s07b00x00p06n02i01793arch OF c09s07b00x00p06n02i01793ent IS
+  type   Day is (Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday);
+
+  procedure i_proof_1 (x : integer) is
+  begin
+  end i_proof_1;
+
+  procedure i_proof_2 (x : character) is
+  begin
+  end i_proof_2;
+
+  procedure i_proof_3 (x : Day) is
+  begin
+  end i_proof_3;
+
+BEGIN
+
+  glabel1 : FOR i in 0 to 8 generate
+    i_proof_1(i);
+  end generate glabel1;
+
+  glabel2 : FOR i in 'A' to 'Z' generate
+    i_proof_2(i);
+  end generate glabel2;
+
+  glabel3 : FOR i in Monday to Sunday generate
+    i_proof_3(i);
+  end generate glabel3;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s07b00x00p06n02i01793"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p06n02i01793arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd
new file mode 100644
index 0000000..919825e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1798.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p02n01i01798ent IS
+END c07s01b00x00p02n01i01798ent;
+
+ARCHITECTURE c07s01b00x00p02n01i01798arch OF c07s01b00x00p02n01i01798ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if -x + z <  y + x and x * z > y - x then  -- No_failure_here
+      x := x - z;
+    end if;
+    assert NOT(x=-6) 
+      report "***PASSED TEST: c07s01b00x00p02n01i01798"
+      severity NOTE;
+    assert (x=-6) 
+      report "***FAILED TEST: c07s01b00x00p02n01i01798 - The expression is a valid expression according to the rules of the syntactic diagram." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p02n01i01798arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd
new file mode 100644
index 0000000..4d3f6b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc18.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n01i00018ent IS
+END c04s02b00x00p09n01i00018ent;
+
+ARCHITECTURE c04s02b00x00p09n01i00018arch OF c04s02b00x00p09n01i00018ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype.
+    subtype DEC is INTEGER range 1 to 10;
+
+    -- Define a subtype based on DEC.
+    subtype DEC2 is DEC;
+
+    -- Define two variable counters.
+    variable CNT1, CNT2 : INTEGER := 0;
+  BEGIN
+    -- Verify that the range of DEC is the same as DEC2.
+    for I in DEC loop
+      CNT1 := CNT1 + 1;
+    end loop;
+    for I in DEC2 loop
+      CNT2 := CNT2 + 1;
+    end loop;
+    assert NOT( CNT1 = CNT2 )
+      report "***PASSED TEST: c04s02b00x00p09n01i00018"
+      severity NOTE;
+    assert ( CNT1 = CNT2 )
+      report "***FAILED TEST: c04s02b00x00p09n01i00018 - If the subtype indication does not indicate a type constraint, the subtype is the same as that denoted by the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n01i00018arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd
new file mode 100644
index 0000000..889f01f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p03n01i00180ent IS
+END c04s04b00x00p03n01i00180ent;
+
+ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
+  attribute p: POSITIVE;
+  signal s: integer;
+  attribute p of s: signal is 10;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( s'p=10 )
+      report "***PASSED TEST: c04s04b00x00p03n01i00180"
+      severity NOTE;
+    assert ( s'p=10 )
+      report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p03n01i00180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd
new file mode 100644
index 0000000..4850bdd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1801.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p03n01i01801ent IS
+END c07s01b00x00p03n01i01801ent;
+
+ARCHITECTURE c07s01b00x00p03n01i01801arch OF c07s01b00x00p03n01i01801ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s01b00x00p03n01i01801"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s01b00x00p03n01i01801"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s01b00x00p03n01i01801arch;
+
+-- CONFIGURATION c07s01b00x00p03n01i01801cfg OF c07s01b00x00p03n01i01801ent IS
+--     FOR c07s01b00x00p03n01i01801arch
+--     END FOR;
+-- END c07s01b00x00p03n01i01801cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd
new file mode 100644
index 0000000..ae2157c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1803.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p05n01i01803ent IS
+END c07s01b00x00p05n01i01803ent;
+
+ARCHITECTURE c07s01b00x00p05n01i01803arch OF c07s01b00x00p05n01i01803ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((-x + z) < (y + x)) then     -- NO_Failure_here
+      -- sign can appear before the first term.
+      x := y * z;
+    end if;
+    assert NOT(x = 45) 
+      report "***PASSED TEST: c07s01b00x00p05n01i01803"
+      severity NOTE;
+    assert (x = 45) 
+      report "***FAILED TEST: c07s01b00x00p05n01i01803 - Sign appear before the first term in a simple expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p05n01i01803arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd
new file mode 100644
index 0000000..853be07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p06n01i01804ent IS
+END c07s01b00x00p06n01i01804ent;
+
+ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+    variable y : integer := 2;
+    variable z : integer := 5;
+  BEGIN
+    x := y * 10 * z;  -- No_failure_here
+    assert NOT( x=100 )
+      report "***PASSED TEST: c07s01b00x00p06n01i01804"
+      severity NOTE;
+    assert ( x=100 )
+      report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p06n01i01804arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd
new file mode 100644
index 0000000..0385ce0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1807.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01807ent IS
+END c07s01b00x00p07n01i01807ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01807arch OF c07s01b00x00p07n01i01807ent IS
+  signal POS : integer;
+  signal P1  : integer := 2;
+  signal P2  : integer := 2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <= P1 ** P2 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = 4) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01807"
+      severity NOTE;
+    assert (POS = 4) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01807 - Primary**primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01807arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd
new file mode 100644
index 0000000..ab589dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01808ent IS
+END c07s01b00x00p07n01i01808ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
+  signal POS : integer;
+  signal P1  : integer := -2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <=  abs P1 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = 2) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01808" 
+      severity NOTE;
+    assert (POS = 2) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01808arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd
new file mode 100644
index 0000000..4f077bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1809.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01809ent IS
+END c07s01b00x00p07n01i01809ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01809arch OF c07s01b00x00p07n01i01809ent IS
+  signal POS : boolean;
+  signal P1  : boolean := false;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <=  not P1 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = true) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01809" 
+      severity NOTE;
+    assert (POS = true) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01809 - not Primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01809arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd
new file mode 100644
index 0000000..e577081
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1810.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01810ent IS
+END c07s01b00x00p08n01i01810ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01810arch OF c07s01b00x00p08n01i01810ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a1 : boolean := true;
+    variable b1 : boolean;
+    variable x1 : integer := 12;
+    variable y1 : real := 12.3;
+    variable p1 : real := 12.5;
+    variable z1 : integer := 10;
+  BEGIN
+    b1 := (x1 < z1) or (y1 > p1) or (x1 = z1) or a1; -- No_failure_here
+    assert NOT(b1 = true)
+      report "***PASSED TEST: c07s01b00x00p08n01i01810"
+      severity NOTE;
+    assert ( b1 = true )
+      report "***FAILED TEST: c07s01b00x00p08n01i01810 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01810arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd
new file mode 100644
index 0000000..3fd1be3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1813.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01813ent IS
+END c07s01b00x00p08n01i01813ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01813arch OF c07s01b00x00p08n01i01813ent IS
+  type A1  is array (1 to 5) of integer;
+  type Acc is access A1;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Acc := new A1'(1,2,3,4,5);
+    variable V2 : integer;
+    variable V3 : integer;
+    variable V4 : integer;
+    variable V5 : integer;
+    variable V6 : integer;
+  BEGIN
+    V2 := V1(1); -- No_failure_here
+    V3 := V1(2); -- No_failure_here
+    V4 := V1(3); -- No_failure_here
+    V5 := V1(4); -- No_failure_here
+    V6 := V1(5); -- No_failure_here
+    assert NOT(V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
+      report "***PASSED TEST: c07s01b00x00p08n01i01813"
+      severity NOTE;
+    assert (V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
+      report "***FAILED TEST: c07s01b00x00p08n01i01813 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed within parentheses."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01813arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd
new file mode 100644
index 0000000..842d3d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc182.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p04n02i00182ent IS
+END c04s04b00x00p04n02i00182ent;
+
+ARCHITECTURE c04s04b00x00p04n02i00182arch OF c04s04b00x00p04n02i00182ent IS
+  type COORDINATE is
+    record
+      X, Y: INTEGER;
+    end record;
+  attribute    LOCATION         : COORDINATE;
+  signal       loc1, loc2    : COORDINATE;
+  attribute LOCATION    of loc1   : signal is (10, 15);
+  attribute LOCATION    of others : signal is (25, 77);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    loc1'LOCATION = (10, 15)   and
+                   loc2'LOCATION = (25, 77)   )
+      report "***PASSED TEST: c04s04b00x00p04n02i00182"
+      severity NOTE;
+    assert (    loc1'LOCATION = (10, 15)   and
+                loc2'LOCATION = (25, 77)   )
+      report "***FAILED TEST: c04s04b00x00p04n02i00182 - Attribute associated with a signal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p04n02i00182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd
new file mode 100644
index 0000000..ddbf5b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc183.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s04b00x00p04n02i00183pkg is
+  attribute    a1    : integer;
+  attribute    a2    : integer;
+  attribute    a1    of c04s04b00x00p04n02i00183pkg : package is 3;
+  constant     c1    : integer  := c04s04b00x00p04n02i00183pkg'a1;
+  attribute    a2    of c04s04b00x00p04n02i00183pkg : package is c1 * 2;
+  function    fn1    return integer;
+  function    fn2    return integer;
+end c04s04b00x00p04n02i00183pkg;
+
+package body c04s04b00x00p04n02i00183pkg is
+  constant t1 : integer := 3; --testgen'a1;
+  constant t2 : integer := 6; --testgen'a2;
+  function fn1 return integer is
+  begin
+    return t1;
+  end;
+  function fn2 return integer is
+  begin
+    return t2;
+  end;
+end c04s04b00x00p04n02i00183pkg;
+
+
+use work.c04s04b00x00p04n02i00183pkg.all;
+ENTITY c04s04b00x00p04n02i00183ent IS
+END c04s04b00x00p04n02i00183ent;
+
+ARCHITECTURE c04s04b00x00p04n02i00183arch OF c04s04b00x00p04n02i00183ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )   
+      report "***PASSED TEST: c04s04b00x00p04n02i00183"
+      severity NOTE;
+    assert ( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )   
+      report "***FAILED TEST: c04s04b00x00p04n02i00183 - Package attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p04n02i00183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd
new file mode 100644
index 0000000..2f21fa3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc187.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p12n01i00187ent IS
+  attribute ATE             : INTEGER;
+  attribute ATE of  c04s04b00x00p12n01i00187ent   : entity is 2;
+  --Correct placement in interface declaration
+END c04s04b00x00p12n01i00187ent;
+
+ARCHITECTURE c04s04b00x00p12n01i00187arch OF c04s04b00x00p12n01i00187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S : integer;
+  BEGIN
+    S := c04s04b00x00p12n01i00187ent'ATE;
+    assert NOT( S = 2 )
+      report "***PASSED TEST: c04s04b00x00p12n01i00187"
+      severity NOTE;
+    assert ( S = 2 )
+      report "***FAILED TEST: c04s04b00x00p12n01i00187 - Attribute specification of the entity test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p12n01i00187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd
new file mode 100644
index 0000000..5d8f147
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc188.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p13n01i00188ent IS
+  port ( S2 : in    integer;
+         V2 : inout Real    ) ;
+  
+  attribute    V1 : REAL;
+  attribute    V1 of V2 : signal is 1.0;
+  alias    A2 : real is V2;
+  
+  attribute    S1 : INTEGER;
+  attribute    S1 of S2 : signal is 1;
+  alias    A1 : integer is S2;
+END c04s04b00x00p13n01i00188ent;
+
+ARCHITECTURE c04s04b00x00p13n01i00188arch OF c04s04b00x00p13n01i00188ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype    BTRUE    is BOOLEAN range TRUE to TRUE;
+    variable    B1    : BTRUE;
+  BEGIN
+    assert NOT( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
+      report "***PASSED TEST: c04s04b00x00p13n01i00188"
+      severity NOTE;
+    assert ( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
+      report "***FAILED TEST: c04s04b00x00p13n01i00188 - Attribute of an object applies to any alias of the object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p13n01i00188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd
new file mode 100644
index 0000000..53f1f34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1906.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p10n01i01906ent IS
+END c07s01b00x00p10n01i01906ent;
+
+ARCHITECTURE c07s01b00x00p10n01i01906arch OF c07s01b00x00p10n01i01906ent IS
+  type    MVL    is ('0','1','X','Z') ;
+  signal    Q    : MVL;
+  signal    PP,P2    : BIT := '1' ;
+  signal    R1    : BIT;
+BEGIN
+  TESTING: PROCESS
+    function "and" (L,R : MVL) return MVL is
+      variable V1 : MVL;
+    begin
+      if (L = '1') then
+        V1 := '1' ;
+      end if;
+      return V1;
+    end;
+  BEGIN
+    Q    <= "and"('1','Z');  -- No_failure_here
+    R1    <= PP and P2;
+    wait for 1 ns;
+    assert NOT((Q='1') and (R1='1'))
+      report "***PASSED TEST: c07s01b00x00p10n01i01906"
+      severity NOTE;
+    assert (( Q='1' ) and (R1='1'))
+      report "***FAILED TEST: c07s01b00x00p10n01i01906 - The identification of an overloaded operator depends on the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p10n01i01906arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd
new file mode 100644
index 0000000..67ad1b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1907.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p11n01i01907ent IS
+END c07s01b00x00p11n01i01907ent;
+
+ARCHITECTURE c07s01b00x00p11n01i01907arch OF c07s01b00x00p11n01i01907ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable b1a, b2a, b3a, b4a : BOOLEAN;
+    variable b1o, b2o, b3o, b4o : BOOLEAN;
+    variable b1x, b2x, b3x, b4x : BOOLEAN;
+  BEGIN
+    -- Test that the following operators can be used associatively.
+    -- 1. AND.
+    b1a := TRUE;
+    b2a := TRUE;
+    b3a := FALSE;
+    assert (NOT (b1a AND b2a AND b3a))
+      report "AND operator cannot be used associatively.";
+    b4a := TRUE;
+    assert (b1a AND b2a AND b4a)
+      report "AND operator cannot be used associatively.";
+
+    -- 2. OR.
+    b1o := FALSE;
+    b2o := FALSE;
+    b3o := TRUE;
+    assert (b1o OR b2o OR b3o)
+      report "OR operator cannot be used associatively.";
+    b4o := FALSE;
+    assert (NOT (b1o OR b2o OR b4o))
+      report "OR operator cannot be used associatively.";
+    
+    -- 3. XOR.
+    b1x := TRUE;
+    b2x := TRUE;
+    b3x := FALSE;
+    assert (NOT (b1x XOR b2x XOR b3x))
+      report "XOR operator cannot be used associatively.";
+    b4x := TRUE;
+    assert (b1x XOR b2x XOR b4x)
+      report "XOR operator cannot be used associatively.";
+
+    wait for 5 ns;
+
+    assert NOT(    (NOT (b1a AND b2a AND b3a))    and
+                   (b1a AND b2a AND b4a)      and
+                   (b1o OR b2o OR b3o)      and
+                   (NOT (b1o OR b2o OR b4o))   and
+                   (NOT (b1x XOR b2x XOR b3x))   and
+                   (b1x XOR b2x XOR b4x)      )
+      report "***PASSED TEST: /src/ch07/sc01/p012/s010101.vhd"
+      severity NOTE;
+    assert (    (NOT (b1a AND b2a AND b3a))    and
+                (b1a AND b2a AND b4a)      and
+                (b1o OR b2o OR b3o)      and
+                (NOT (b1o OR b2o OR b4o))   and
+                (NOT (b1x XOR b2x XOR b3x))   and
+                (b1x XOR b2x XOR b4x)      )
+      report "***FAILED TEST: c07s01b00x00p11n01i01907 - Associative test for and or and xor failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p11n01i01907arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd
new file mode 100644
index 0000000..18e837c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n01i01908ent IS
+END c07s02b00x00p09n01i01908ent;
+
+ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
+      report "***PASSED TEST: c07s02b00x00p09n01i01908"
+      severity NOTE;
+    assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
+      report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n01i01908arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd
new file mode 100644
index 0000000..6705646
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1909.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n03i01909ent IS
+END c07s02b00x00p09n03i01909ent;
+
+ARCHITECTURE c07s02b00x00p09n03i01909arch OF c07s02b00x00p09n03i01909ent IS
+  signal Q     : BIT := '1';
+  signal R     : BIT := '0';
+  signal S     : BIT := '1';
+  signal PP,P2 : BIT := '1' ;
+  signal R1    : BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    R1 <= ((Q and S) or R) and (P2 and PP) ;
+    wait for 5 ns;
+    assert NOT( R1 = '1' )
+      report "***PASSED TEST: c07s02b00x00p09n03i01909"
+      severity NOTE;
+    assert ( R1 = '1' )
+      report "***FAILED TEST: c07s02b00x00p09n03i01909 - The parentheses can be used to control the association of operators and operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n03i01909arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd
new file mode 100644
index 0000000..4228e66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1910.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n01i01910ent IS
+END c07s02b00x00p09n01i01910ent;
+
+ARCHITECTURE c07s02b00x00p09n01i01910arch OF c07s02b00x00p09n01i01910ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable ValueB1 : BOOLEAN;
+    variable ValueB2 : BOOLEAN;
+    variable ValueB3 : BOOLEAN;
+    variable ValueB4 : BOOLEAN;
+    variable ValueI1, SameValueI1, DifferentValueI1 : INTEGER;
+    variable ValueI2, SameValueI2, DifferentValueI2 : INTEGER;
+    variable ValueI3, SameValueI3, DifferentValueI3 : INTEGER;
+    variable ValueI4, SameValueI4, DifferentValueI4 : INTEGER;
+    variable ValueI5, SameValueI5, DifferentValueI5 : INTEGER;
+    variable ValueI6, SameValueI6, DifferentValueI6 : INTEGER;
+    variable ValueI7, SameValueI7, DifferentValueI7 : INTEGER;
+  BEGIN
+    -- "+" (addition) operator, and the "-" operator.
+    --     - NOTE:  The following expression would not be able to parse
+    --              if the precedence used was such that the "=" operator
+    --              had a higher precedence than the "+" operator.  Thus,
+    --              if this parses you are guaranteed that the precedence
+    --              relative to these two levels is correctly defined.Same
+    --              goes for the "-" operator.
+    ValueB1         := 1 + 3 = 3 + 1;
+    assert (ValueB1)
+      report "The expression has not been processed correctly.(5)";
+    ValueB2         := 3 - 1 = 5 - 3;
+    assert (ValueB2)
+      report "The expression has not been processed correctly.(6)";
+    
+    -- "+" (sign) operator, and the "-" (sign) operator.
+    --     - NOTE:  The following expression would not be able to parse
+    --              if the precedence used was such that the "=" operator
+    --              had a higher precedence than the "+" operator.  Thus,
+    --              if this parses you are guaranteed that the precedence
+    --              relative to these two levels is correctly defined.Same
+    --              goes for the "-" operator.
+    ValueB3         := + 1 = + 1;
+    assert (ValueB3)
+      report "The expression has not been processed correctly.(7)";
+    ValueB4         := - 3 = - 3;
+    assert (ValueB4)
+      report "The expression has not been processed correctly.(8)";
+
+    ValueI1         := -3 + 4;
+    SameValueI1     := (-3) + 4;
+    DifferentValueI1:= -(3 + 4);
+    assert (ValueI1 = SameValueI1)
+      report "Values of lower precedence associated before those of higher precedence.(9)";
+    assert (ValueI1 /= DifferentValueI1)
+      report "Values of lower precedence associated before those of higher precedence.(10)";
+    
+    -- "*" operator.
+    ValueI2         := 3 + 4 * 5;
+    SameValueI2     := 3 + (4 * 5);
+    DifferentValueI2:= (3 + 4) * 5;
+    assert (ValueI2 = SameValueI2)
+      report "Values of lower precedence associated before those of higher precedence.(13)";
+    assert (ValueI2 /= DifferentValueI2)
+      report "Values of lower precedence associated before those of higher precedence.(14)";
+    
+    -- "/" operator.
+    ValueI3         := 5 + 10 / 5;
+    SameValueI3     := 5 + (10 / 5);
+    DifferentValueI3:= (5 + 10) / 5;
+    assert (ValueI3 = SameValueI3)
+      report "Values of lower precedence associated before those of higher precedence.(15)";
+    assert (ValueI3 /= DifferentValueI3)
+      report "Values of lower precedence associated before those of higher precedence.(16)";
+    
+    -- "mod" operator.
+    ValueI4         := 4 + 11 mod 3;
+    SameValueI4     := 4 + (11 mod 3);
+    DifferentValueI4:= (4 + 11) mod 3;
+    assert (ValueI4 = SameValueI4)
+      report "Values of lower precedence associated before those of higher precedence.(17)";
+    assert (ValueI4 /= DifferentValueI4)
+      report "Values of lower precedence associated before those of higher precedence.(18)";
+    
+    -- "rem" operator.
+    ValueI5         := 4 + 11 rem 3;
+    SameValueI5     := 4 + (11 rem 3);
+    DifferentValueI5:= (4 + 11) rem 3;
+    assert (ValueI5 = SameValueI5)
+      report "Values of lower precedence associated before those of higher precedence.(19)";
+    assert (ValueI5 /= DifferentValueI5)
+      report "Values of lower precedence associated before those of higher precedence.(20)";
+
+    -- "**" operator.
+    ValueI6         := 3 * 4 ** 2;
+    SameValueI6     := 3 * (4 ** 2);
+    DifferentValueI6:= (3 * 4) ** 2;
+    assert (ValueI6 = SameValueI6)
+      report "Values of lower precedence associated before those of higher precedence.(21)";
+    assert (ValueI6 /= DifferentValueI6)
+      report "Values of lower precedence associated before those of higher precedence.(22)";
+    
+    -- "abs" operator.
+    ValueI7         := abs (-5) * (-7);
+    SameValueI7     := (abs (-5)) * (-7);
+    DifferentValueI7:= abs((-5) * (-7));
+    assert (ValueI7 = SameValueI7)
+      report "Values of lower precedence associated before those of higher precedence.(23)";
+    assert (ValueI7 /= DifferentValueI7)
+      report "Values of lower precedence associated before those of higher precedence.(24)";
+
+    wait for 5 ns;
+
+    assert NOT(   (ValueB1)   and
+                  (ValueB2)   and 
+                  (ValueB3)   and 
+                  (ValueB4)   and 
+                  (ValueI1 = SameValueI1)      and
+                  (ValueI1 /= DifferentValueI1)   and
+                  (ValueI2 = SameValueI2)      and
+                  (ValueI2 /= DifferentValueI2)   and
+                  (ValueI3 = SameValueI3)      and
+                  (ValueI3 /= DifferentValueI3)   and
+                  (ValueI4 = SameValueI4)      and
+                  (ValueI4 /= DifferentValueI4)   and
+                  (ValueI5 = SameValueI5)      and
+                  (ValueI5 /= DifferentValueI5)   and
+                  (ValueI6 = SameValueI6)      and
+                  (ValueI6 /= DifferentValueI6)   and
+                  (ValueI7 = SameValueI7)      and
+                  (ValueI7 /= DifferentValueI7)   )
+      report "***PASSED TEST: c07s02b00x00p09n01i01910"
+      severity NOTE;
+    assert (   (ValueB1)   and
+               (ValueB2)   and 
+               (ValueB3)   and 
+               (ValueB4)   and 
+               (ValueI1 = SameValueI1)      and
+               (ValueI1 /= DifferentValueI1)   and
+               (ValueI2 = SameValueI2)      and
+               (ValueI2 /= DifferentValueI2)   and
+               (ValueI3 = SameValueI3)      and
+               (ValueI3 /= DifferentValueI3)   and
+               (ValueI4 = SameValueI4)      and
+               (ValueI4 /= DifferentValueI4)   and
+               (ValueI5 = SameValueI5)      and
+               (ValueI5 /= DifferentValueI5)   and
+               (ValueI6 = SameValueI6)      and
+               (ValueI6 /= DifferentValueI6)   and
+               (ValueI7 = SameValueI7)      and
+               (ValueI7 /= DifferentValueI7)   )
+      report "***FAILED TEST: c07s02b00x00p09n01i01910 - Operators of higher precedence are associated with their operands before operators of lower precedence."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n01i01910arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd
new file mode 100644
index 0000000..ba8d49a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1911.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n02i01911ent IS
+END c07s02b00x00p09n02i01911ent;
+
+ARCHITECTURE c07s02b00x00p09n02i01911arch OF c07s02b00x00p09n02i01911ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ValueI1, SameValueI1, DifferentValueI1 : INTEGER;
+    variable ValueI2, SameValueI2, DifferentValueI2 : INTEGER;
+    variable ValueI3, SameValueI3, DifferentValueI3 : INTEGER;
+    variable ValueI4, SameValueI4, DifferentValueI4 : INTEGER;
+  BEGIN
+    -- adding operators.  
+    --   Cannot compare the "&" operator against either the "+" or 
+    --   "-" operators.  The only two we can compare are the "+"
+    --         and the "-" operators.
+    -- "+", "-"
+    ValueI1         := 14 + 1 - 9 - 7;
+    SameValueI1     := ((14 + 1) - 9) - 7;
+    DifferentValueI1:= 14 + (1 - (9 - 7));
+    assert (ValueI1 = SameValueI1)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI1 /= DifferentValueI1)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    -- multiplying operators.
+    -- "*", "/"
+    ValueI2          := 14 / 7 * 3;
+    SameValueI2      := (14 / 7) * 3;   -- 6
+    DifferentValueI2 := 14 / (7 * 3);   -- 0
+    assert (ValueI2 = SameValueI2)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI2 /= DifferentValueI2)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    -- "*", "mod"
+    ValueI3          := 14 mod 7 * 3;
+    SameValueI3      := (14 mod 7) * 3;   -- 0
+    DifferentValueI3 := 14 mod (7 * 3);   -- 14
+    assert (ValueI3 = SameValueI3)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI3 /= DifferentValueI3)
+      report "Values of same precedence are not evaluated left to right.";
+
+    -- "*", "rem"
+    ValueI4          := 14 rem 7 * 3;
+    SameValueI4      := (14 rem 7) * 3;   -- 0
+    DifferentValueI4 := 14 rem (7 * 3);   -- 14
+    assert (ValueI4 = SameValueI4)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI4 /= DifferentValueI4)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    wait for 5 ns;
+    assert NOT(    (ValueI1 = SameValueI1)   and
+                   (ValueI1 /= DifferentValueI1)   and
+                   (ValueI2 = SameValueI2)   and
+                   (ValueI2 /= DifferentValueI2)   and
+                   (ValueI3 = SameValueI3)   and
+                   (ValueI3 /= DifferentValueI3)   and
+                   (ValueI4 = SameValueI4)   and
+                   (ValueI4 /= DifferentValueI4)   )
+      report "***PASSED TEST: c07s02b00x00p09n02i01911"
+      severity NOTE;
+    assert (    (ValueI1 = SameValueI1)   and
+                (ValueI1 /= DifferentValueI1)   and
+                (ValueI2 = SameValueI2)   and
+                (ValueI2 /= DifferentValueI2)   and
+                (ValueI3 = SameValueI3)   and
+                (ValueI3 /= DifferentValueI3)   and
+                (ValueI4 = SameValueI4)   and
+                (ValueI4 /= DifferentValueI4)   )
+      report "***FAILED TEST: c07s02b00x00p09n02i01911 - Operators are not associated with their operands in textual order."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n02i01911arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd
new file mode 100644
index 0000000..41819b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1912.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n03i01912ent IS
+END c07s02b00x00p09n03i01912ent;
+
+ARCHITECTURE c07s02b00x00p09n03i01912arch OF c07s02b00x00p09n03i01912ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1a,b2a,b3a   : BOOLEAN;
+    variable   b1b,b2b,b3b   : BOOLEAN;
+    variable   b1c,b2c,b3c   : BOOLEAN;
+    variable   i1a,i2a,i3a   : INTEGER;
+    variable   i1b,i2b,i3b   : INTEGER;
+  BEGIN
+    -- I. logical operator and relational operator.
+    b1a              := FALSE;
+    b2a              := FALSE;
+    b3a              := TRUE;
+    assert ((b1a and b2a) /= b3a)
+      report "1:Parentheses do NOT change the precedence of operation.";
+    
+    -- V. logical operator and miscellaneous operator.
+    b1b              := FALSE;
+    b2b              := TRUE;
+    assert (not (b1b and b2b))
+      report "2:Parentheses do NOT change the precedence of operation.";
+    
+    -- VI. relational operators cannot be thus compared to ANY other operators
+    --     but the NOT operator, because they return boolean values and no other
+    --     higher precedence operators work on this type.
+    b1c              := FALSE;
+    b2c              := TRUE;
+    assert (not (b1c >= b2c))
+      report "3:Parentheses do NOT change the precedence of operation.";
+
+    -- VIII. adding operator and multiplying operator.
+    i1a              := 3;
+    i2a              := 4;
+    i3a              := 5;
+    assert (((i1a + i2a) * i3a) = 35)
+      report "4:Parentheses do NOT change the precedence of operation.";
+    
+    -- XII. multiplying operator and miscellaneous operator.
+    i1b              := 2;
+    i2b              := 3;
+    i3b              := 2;
+    assert (((i1b + i2b) ** i3b) = 25)
+      report "5:Parentheses do NOT change the precedence of operation.";
+
+    wait for 5 ns;
+    assert NOT(   ((b1a and b2a) /= b3a)      and
+                  (not (b1b and b2b))      and
+                  (not (b1c >= b2c))      and
+                  (((i1a + i2a) * i3a) = 35)   and
+                  (((i1b + i2b) ** i3b) = 25)   )
+      report "***PASSED TEST: c07s02b00x00p09n03i01912"
+      severity NOTE;
+    assert (   ((b1a and b2a) /= b3a)      and
+               (not (b1b and b2b))      and
+               (not (b1c >= b2c))      and
+               (((i1a + i2a) * i3a) = 35)   and
+               (((i1b + i2b) ** i3b) = 25)   )
+      report "***FAILED TEST: c07s02b00x00p09n03i01912 - The parentheses should be able to control the association of operators and operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n03i01912arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd
new file mode 100644
index 0000000..813da17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01914ent IS
+END c07s02b01x00p01n01i01914ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := not b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01914" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01914arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd
new file mode 100644
index 0000000..572302c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1915.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01915ent IS
+END c07s02b01x00p01n01i01915ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01915arch OF c07s02b01x00p01n01i01915ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 and b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01915"
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01915 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01915arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd
new file mode 100644
index 0000000..9be00fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1916.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01916ent IS
+END c07s02b01x00p01n01i01916ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01916arch OF c07s02b01x00p01n01i01916ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 or b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01916" 
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01916 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01916arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd
new file mode 100644
index 0000000..dedff4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1917.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01917ent IS
+END c07s02b01x00p01n01i01917ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01917arch OF c07s02b01x00p01n01i01917ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 nand b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01917" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01917 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd
new file mode 100644
index 0000000..7c6e53e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1918.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01918ent IS
+END c07s02b01x00p01n01i01918ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01918arch OF c07s02b01x00p01n01i01918ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 xor b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01918" 
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01918 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd
new file mode 100644
index 0000000..7d6340a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1919.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01919ent IS
+END c07s02b01x00p01n01i01919ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01919arch OF c07s02b01x00p01n01i01919ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 nor b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01919" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01919 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01919arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd
new file mode 100644
index 0000000..2167a6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1920.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01920ent IS
+END c07s02b01x00p01n01i01920ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01920arch OF c07s02b01x00p01n01i01920ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := not b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01920" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01920 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01920arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd
new file mode 100644
index 0000000..a4a2a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01921ent IS
+END c07s02b01x00p01n01i01921ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 and b1;
+    assert NOT(b1 = TRUE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01921"
+      severity NOTE;
+    assert (b1 = TRUE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01921arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd
new file mode 100644
index 0000000..30b0aed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1922.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01922ent IS
+END c07s02b01x00p01n01i01922ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01922arch OF c07s02b01x00p01n01i01922ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 or b1;
+    assert NOT(b1 = TRUE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01922"
+      severity NOTE;
+    assert (b1 = TRUE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01922 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01922arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd
new file mode 100644
index 0000000..baffde1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1923.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01923ent IS
+END c07s02b01x00p01n01i01923ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01923arch OF c07s02b01x00p01n01i01923ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 nand b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01923" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01923 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01923arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd
new file mode 100644
index 0000000..a6ed08a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1924.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01924ent IS
+END c07s02b01x00p01n01i01924ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01924arch OF c07s02b01x00p01n01i01924ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 xor b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01924"
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01924 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01924arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd
new file mode 100644
index 0000000..2185442
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1925.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01925ent IS
+END c07s02b01x00p01n01i01925ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01925arch OF c07s02b01x00p01n01i01925ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 nor b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01925" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01925 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01925arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd
new file mode 100644
index 0000000..1f27f2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1931.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01931ent IS
+END c07s02b01x00p01n02i01931ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01931arch OF c07s02b01x00p01n02i01931ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+--          Test operators on one-dimesioned arrays of BIT
+--
+    ASSERT ( B"1100" AND  B"1010" ) = B"1000" 
+      REPORT "ERROR: composite AND operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100"  OR  B"1010" ) = B"1110" 
+      REPORT "ERROR: composite  OR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" NAND B"1010" ) = B"0111" 
+      REPORT "ERROR: composite NAND operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" NOR  B"1010" ) = B"0001" 
+      REPORT "ERROR: composite NOR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" XOR  B"1010" ) = B"0110" 
+      REPORT "ERROR: composite XOR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT (         NOT  B"1100" ) = B"0011" 
+      REPORT "ERROR: composite NOT operator failed : BIT"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   (( B"1100" AND  B"1010" ) = B"1000")   and
+                  (( B"1100"  OR  B"1010" ) = B"1110")   and
+                  (( B"1100" NAND B"1010" ) = B"0111")   and
+                  (( B"1100" NOR  B"1010" ) = B"0001")   and
+                  (( B"1100" XOR  B"1010" ) = B"0110")   and
+                  ((         NOT  B"1100" ) = B"0011")   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01931"
+      severity NOTE;
+    assert (   (( B"1100" AND  B"1010" ) = B"1000")   and
+               (( B"1100"  OR  B"1010" ) = B"1110")   and
+               (( B"1100" NAND B"1010" ) = B"0111")   and
+               (( B"1100" NOR  B"1010" ) = B"0001")   and
+               (( B"1100" XOR  B"1010" ) = B"0110")   and
+               ((         NOT  B"1100" ) = B"0011")   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01931 - Logical operators should be valid for any one-dimensional array type whose element type is BIT."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01931arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd
new file mode 100644
index 0000000..5aa6a7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1932.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01932ent IS
+END c07s02b01x00p01n02i01932ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01932arch OF c07s02b01x00p01n02i01932ent IS
+  SUBTYPE bit_8 is bit_vector(0 to 7);
+  SUBTYPE bit_4 is bit_vector(0 to 3);
+BEGIN
+  TESTING: PROCESS
+    CONSTANT slice_8a : bit_8 := B"1010_0011";
+    VARIABLE slice_8b : bit_8 := B"1110_1001";
+    VARIABLE target_1 : bit_4;
+    VARIABLE target_2 : bit_4;
+    VARIABLE target_3 : bit_4;
+    VARIABLE target_4 : bit_4;
+    VARIABLE target_5 : bit_4;
+    VARIABLE target_6 : bit_4;
+  BEGIN
+    target_1 := slice_8a (3 to 6) AND slice_8b (4 to 7);
+
+    target_2 := slice_8a (3 to 6) OR slice_8b (4 to 7);
+
+    target_3 := slice_8a (3 to 6) NOR slice_8b (4 to 7);
+
+    target_4 := slice_8a (3 to 6) NAND slice_8b (4 to 7);
+
+    target_5 := slice_8a (3 to 6) XOR slice_8b (4 to 7);
+    
+    target_6 := NOT slice_8b (0 to 3);
+
+    assert NOT(
+      target_1 = B"0001"   and
+      target_2 = B"1001"   and
+      target_3 = B"0110"   and
+      target_4 = B"1110"   and
+      target_5 = B"1000"   and
+      target_6 = B"0001"   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01932" 
+      severity NOTE;
+    assert (
+      target_1 = B"0001"   and
+      target_2 = B"1001"   and
+      target_3 = B"0110"   and
+      target_4 = B"1110"   and
+      target_5 = B"1000"   and
+      target_6 = B"0001"   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01932 - Logical operators are valid for bit slice operations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd
new file mode 100644
index 0000000..36b1d25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc194.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s00b00x00p11n01i00194ent IS
+END c03s00b00x00p11n01i00194ent;
+
+ARCHITECTURE c03s00b00x00p11n01i00194arch OF c03s00b00x00p11n01i00194ent IS
+  type       T1 is array (0 to 31) of BIT;
+  subtype    T2 is integer range 2 to 20;
+  signal    S1 : T2 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 15 after 10 ns; -- no_failure_here
+    wait for 20 ns;
+    assert NOT(S1 = 15)
+      report "***PASSED TEST: c03s00b00x00p11n01i00194"
+      severity NOTE;
+    assert ( S1 = 15 )
+      report "***FAILED TEST: c03s00b00x00p11n01i00194 - The assignment operation to an object having a given subtype only assigns values that belong to the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s00b00x00p11n01i00194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd
new file mode 100644
index 0000000..669b3eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1942.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01942ent IS
+END c07s02b01x00p01n02i01942ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01942arch OF c07s02b01x00p01n02i01942ent IS
+  TYPE b4 IS ARRAY (1 TO 4) OF BOOLEAN;
+
+  CONSTANT T : BOOLEAN := TRUE;
+  CONSTANT F : BOOLEAN :=FALSE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+--          Test operators on one-dimesioned arrays of BOOLEAN
+--
+    ASSERT ( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ) 
+      REPORT "ERROR: composite AND operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ) 
+      REPORT "ERROR: composite  OR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ) 
+      REPORT "ERROR: composite NAND operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ) 
+      REPORT "ERROR: composite NOR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ) 
+      REPORT "ERROR: composite XOR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT (                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ) 
+      REPORT "ERROR: composite NOT operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   (( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ))   and
+                  (( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ))   and
+                  (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ))   and
+                  (( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ))   and
+                  (( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ))   and
+                  ((                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ))   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01942" 
+      severity NOTE;
+    assert (   (( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ))   and
+               (( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ))   and
+               (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ))   and
+               (( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ))   and
+               (( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ))   and
+               ((                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ))   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01942 - Logical operators should be valid for any one-dimensional array type whose element type is BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01942arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd
new file mode 100644
index 0000000..f2bf0bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1943.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n05i01943ent IS
+END c07s02b01x00p01n05i01943ent;
+
+ARCHITECTURE c07s02b01x00p01n05i01943arch OF c07s02b01x00p01n05i01943ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s02b01x00p01n05i01943"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s02b01x00p01n05i01943"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s02b01x00p01n05i01943arch;
+
+-- CONFIGURATION c07s02b01x00p01n05i01943cfg OF c07s02b01x00p01n05i01943ent IS
+--     FOR c07s02b01x00p01n05i01943arch
+--     END FOR;
+-- END c07s02b01x00p01n05i01943cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd
new file mode 100644
index 0000000..9515a28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1944.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01944ent IS
+END c07s02b01x00p01n04i01944ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01944arch OF c07s02b01x00p01n04i01944ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    variable B : bit_vector (32 downto 1);
+    constant AA : bit_vector (1 to 32) := x"0000ffff";
+    variable C : bit_vector (15 downto 0);
+    variable D, DD : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+    alias FF : bit_vector (47 downto 0) is F;
+  BEGIN
+    
+    A := x"0000ffff";
+    B := x"00ff00ff";
+
+    C := x"00ff";
+    D := x"0f0f";
+
+    E := x"000000ffffff";
+    F := x"000fff000fff";
+
+    assert NOT(    (A and B ) = x"000000ff"   and
+                   (A or  B ) = x"00ffffff"   and
+                   (A xor B ) = x"00ffff00"   and
+                   (A nand B) = x"ffffff00"   and
+                   (A nor B ) = x"ff000000"   and
+                   (not A   ) = x"ffff0000"   and
+                   (AA and B ) = x"000000ff"   and
+                   (AA or  B ) = x"00ffffff"   and
+                   (AA xor B ) = x"00ffff00"   and
+                   (AA nand B) = x"ffffff00"   and
+                   (AA nor B ) = x"ff000000"   and
+                   (not AA   ) = x"ffff0000"   and
+                   (C and D ) = x"000f"   and
+                   (C or  D ) = x"0fff"   and
+                   (C xor D ) = x"0ff0"   and
+                   (C nand D) = x"fff0"   and
+                   (C nor D ) = x"f000"   and
+                   (not C   ) = x"ff00"   and
+                   (E and F ) = x"000000000fff"   and
+                   (E or  F ) = x"000fffffffff"   and
+                   (E xor F ) = x"000ffffff000"   and
+                   (E nand F) = x"fffffffff000"   and
+                   (E nor F ) = x"fff000000000"   and
+                   (E and FF ) = x"000000000fff"   and
+                   (E or  FF ) = x"000fffffffff"   and
+                   (E xor FF ) = x"000ffffff000"   and
+                   (E nand FF) = x"fffffffff000"   and
+                   (E nor FF ) = x"fff000000000"   and
+                   (not E   ) = x"ffffff000000")
+      report "***PASSED TEST: c07s02b01x00p01n04i01944" 
+      severity NOTE;
+    assert (    (A and B ) = x"000000ff"   and
+                (A or  B ) = x"00ffffff"   and
+                (A xor B ) = x"00ffff00"   and
+                (A nand B) = x"ffffff00"   and
+                (A nor B ) = x"ff000000"   and
+                (not A   ) = x"ffff0000"   and
+                (AA and B ) = x"000000ff"   and
+                (AA or  B ) = x"00ffffff"   and
+                (AA xor B ) = x"00ffff00"   and
+                (AA nand B) = x"ffffff00"   and
+                (AA nor B ) = x"ff000000"   and
+                (not AA   ) = x"ffff0000"   and
+                (C and D ) = x"000f"   and
+                (C or  D ) = x"0fff"   and
+                (C xor D ) = x"0ff0"   and
+                (C nand D) = x"fff0"   and
+                (C nor D ) = x"f000"   and
+                (not C   ) = x"ff00"   and
+                (E and F ) = x"000000000fff"   and
+                (E or  F ) = x"000fffffffff"   and
+                (E xor F ) = x"000ffffff000"   and
+                (E nand F) = x"fffffffff000"   and
+                (E nor F ) = x"fff000000000"   and
+                (E and FF ) = x"000000000fff"   and
+                (E or  FF ) = x"000fffffffff"   and
+                (E xor FF ) = x"000ffffff000"   and
+                (E nand FF) = x"fffffffff000"   and
+                (E nor FF ) = x"fff000000000"   and
+                (not E   ) = x"ffffff000000")
+      report "***FAILED TEST: c07s02b01x00p01n04i01944 - One dimensional array type logical operation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01944arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd
new file mode 100644
index 0000000..206571b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd
@@ -0,0 +1,308 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01945pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- ----------------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01945pkg.all;
+ENTITY c07s02b01x00p01n02i01945ent IS
+END c07s02b01x00p01n02i01945ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT  AND_C_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+  CONSTANT  AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  AND_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+  CONSTANT  AND_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT  AND_C_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+  CONSTANT  AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  AND_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+  CONSTANT  AND_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  AND_S_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+  SIGNAL  AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  AND_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+  SIGNAL  AND_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  AND_S_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+  SIGNAL  AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  AND_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+  SIGNAL  AND_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  AND_V_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+    VARIABLE  AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  AND_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+    VARIABLE  AND_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  AND_V_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+    VARIABLE  AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  AND_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+    VARIABLE  AND_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+  BEGIN
+--
+--          Test AND operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test AND operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test AND operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1   and
+                  ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2   and
+                  ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3   and
+                  ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4   and
+                  ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1   and
+                  ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2   and
+                  ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3   and
+                  ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4   and
+                  ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1   and
+                  ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2   and
+                  ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3   and
+                  ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4   and
+                  ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1   and
+                  ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2   and
+                  ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3   and
+                  ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4   and
+                  ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1   and
+                  ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2   and
+                  ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3   and
+                  ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4   and
+                  ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1   and
+                  ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2   and
+                  ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3   and
+                  ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01945" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1   and
+               ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2   and
+               ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3   and
+               ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4   and
+               ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1   and
+               ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2   and
+               ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3   and
+               ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4   and
+               ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1   and
+               ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2   and
+               ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3   and
+               ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4   and
+               ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1   and
+               ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2   and
+               ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3   and
+               ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4   and
+               ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1   and
+               ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2   and
+               ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3   and
+               ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4   and
+               ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1   and
+               ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2   and
+               ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3   and
+               ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd
new file mode 100644
index 0000000..ef01428
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd
@@ -0,0 +1,309 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1946.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01946pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01946pkg.all;
+ENTITY c07s02b01x00p01n02i01946ent IS
+END c07s02b01x00p01n02i01946ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01946arch OF c07s02b01x00p01n02i01946ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT   OR_C_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+  CONSTANT   OR_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT   OR_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+  CONSTANT   OR_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT   OR_C_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+  CONSTANT   OR_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT   OR_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+  CONSTANT   OR_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL   OR_S_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+  SIGNAL   OR_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL   OR_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+  SIGNAL   OR_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL   OR_S_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+  SIGNAL   OR_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL   OR_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+  SIGNAL   OR_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE   OR_V_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+    VARIABLE   OR_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE   OR_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+    VARIABLE   OR_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE   OR_V_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+    VARIABLE   OR_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE   OR_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+    VARIABLE   OR_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+  BEGIN
+--
+--          Test OR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test OR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test OR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4   and   
+                  ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01946" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1   and
+               ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2   and
+               ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3   and
+               ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4   and
+               ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1   and
+               ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2   and
+               ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3   and
+               ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4   and   
+               ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1   and
+               ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2   and
+               ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3   and
+               ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4   and
+               ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1   and
+               ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2   and
+               ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3   and
+               ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4   and
+               ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1   and
+               ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2   and
+               ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3   and
+               ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4   and
+               ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1   and
+               ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2   and
+               ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3   and
+               ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01946 - Logical operator OR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01946arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd
new file mode 100644
index 0000000..f1923bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd
@@ -0,0 +1,309 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1947.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01947pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01947pkg.all;
+ENTITY c07s02b01x00p01n02i01947ent IS
+END c07s02b01x00p01n02i01947ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01947arch OF c07s02b01x00p01n02i01947ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT NAND_C_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+  CONSTANT NAND_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT NAND_C_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  CONSTANT NAND_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT NAND_C_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+  CONSTANT NAND_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT NAND_C_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  CONSTANT NAND_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL NAND_S_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+  SIGNAL NAND_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL NAND_S_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  SIGNAL NAND_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL NAND_S_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+  SIGNAL NAND_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL NAND_S_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  SIGNAL NAND_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE NAND_V_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+    VARIABLE NAND_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE NAND_V_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+    VARIABLE NAND_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE NAND_V_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+    VARIABLE NAND_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE NAND_V_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+    VARIABLE NAND_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+
+  BEGIN
+--
+--          Test NANDoperator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NANDoperator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NANDoperator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1   and
+                  ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2   and
+                  ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3   and
+                  ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4   and
+                  ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1   and
+                  ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2   and
+                  ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3   and
+                  ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4   and
+                  ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1   and
+                  ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2   and
+                  ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3   and
+                  ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4   and
+                  ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1   and
+                  ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2   and
+                  ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3   and
+                  ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4   and
+                  ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1   and
+                  ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2   and
+                  ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3   and
+                  ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4   and
+                  ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1   and
+                  ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2   and
+                  ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3   and
+                  ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01947" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1   and
+               ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2   and
+               ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3   and
+               ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4   and
+               ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1   and
+               ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2   and
+               ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3   and
+               ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4   and
+               ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1   and
+               ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2   and
+               ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3   and
+               ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4   and
+               ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1   and
+               ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2   and
+               ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3   and
+               ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4   and
+               ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1   and
+               ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2   and
+               ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3   and
+               ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4   and
+               ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1   and
+               ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2   and
+               ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3   and
+               ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01947 - Logical operator NAND for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01947arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd
new file mode 100644
index 0000000..70490e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd
@@ -0,0 +1,308 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1948.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01948pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01948pkg.all;
+ENTITY c07s02b01x00p01n02i01948ent IS
+END c07s02b01x00p01n02i01948ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01948arch OF c07s02b01x00p01n02i01948ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT  NOR_C_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+  CONSTANT  NOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  NOR_C_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+  CONSTANT  NOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT  NOR_C_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+  CONSTANT  NOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  NOR_C_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+  CONSTANT  NOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  NOR_S_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+  SIGNAL  NOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  NOR_S_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+  SIGNAL  NOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  NOR_S_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+  SIGNAL  NOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  NOR_S_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+  SIGNAL  NOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE );
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  NOR_V_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+    VARIABLE  NOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  NOR_V_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+    VARIABLE  NOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  NOR_V_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+    VARIABLE  NOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  NOR_V_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+    VARIABLE  NOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE ); 
+
+  BEGIN
+--
+--          Test NOR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4   and
+                  ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01948" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1   and
+               ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2   and
+               ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3   and
+               ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4   and
+               ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1   and
+               ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2   and
+               ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3   and
+               ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4   and
+               ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1   and
+               ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2   and
+               ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3   and
+               ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4   and
+               ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1   and
+               ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2   and
+               ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3   and
+               ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4   and
+               ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1   and
+               ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2   and
+               ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3   and
+               ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4   and
+               ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1   and
+               ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2   and
+               ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3   and
+               ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01948 - Logical operator NOR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01948arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd
new file mode 100644
index 0000000..0639833
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd
@@ -0,0 +1,307 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1949.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01949pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01949pkg.all;
+ENTITY c07s02b01x00p01n02i01949ent IS
+END c07s02b01x00p01n02i01949ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01949arch OF c07s02b01x00p01n02i01949ent IS
+--
+--          CONSTANT Declarations
+-- 
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' ); 
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' ); 
+  CONSTANT  XOR_C_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' ); 
+  CONSTANT  XOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  XOR_C_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+  CONSTANT  XOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' ); 
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' ); 
+  CONSTANT  XOR_C_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' ); 
+  CONSTANT  XOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  XOR_C_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+  CONSTANT  XOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+-- 
+--          SIGNAL Declarations
+-- 
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );   
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  XOR_S_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' );
+  SIGNAL  XOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  XOR_S_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+  SIGNAL  XOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  XOR_S_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' );
+  SIGNAL  XOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  XOR_S_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+  SIGNAL  XOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  XOR_V_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' );
+    VARIABLE  XOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  XOR_V_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+    VARIABLE  XOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  XOR_V_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' );
+    VARIABLE  XOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  XOR_V_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+    VARIABLE  XOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+  BEGIN
+--
+--          Test XOR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test XOR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test XOR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4   and
+                  ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4   )   
+      report "***PASSED TEST: c07s02b01x00p01n02i01949" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1   and
+               ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2   and
+               ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3   and
+               ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4   and
+               ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1   and
+               ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2   and
+               ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3   and
+               ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4   and
+               ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1   and
+               ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2   and
+               ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3   and
+               ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4   and
+               ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1   and
+               ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2   and
+               ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3   and
+               ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4   and
+               ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1   and
+               ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2   and
+               ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3   and
+               ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4   and
+               ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1   and
+               ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2   and
+               ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3   and
+               ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4   )   
+      report "***FAILED TEST: c07s02b01x00p01n02i01949 - Logical operator XOR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01949arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd
new file mode 100644
index 0000000..549ae9a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd
@@ -0,0 +1,283 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1950.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01950pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01950pkg.all;
+ENTITY c07s02b01x00p01n02i01950ent IS
+END c07s02b01x00p01n02i01950ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01950arch OF c07s02b01x00p01n02i01950ent IS
+-- 
+--          CONSTANT Declarations
+-- 
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT  NOT_C_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+  CONSTANT  NOT_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT  NOT_C_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+  CONSTANT  NOT_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT  NOT_C_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+  CONSTANT  NOT_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT  NOT_C_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+  CONSTANT  NOT_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL  NOT_S_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+  SIGNAL  NOT_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL  NOT_S_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+  SIGNAL  NOT_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL  NOT_S_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+  SIGNAL  NOT_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL  NOT_S_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+  SIGNAL  NOT_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+BEGIN
+  TESTING: PROCESS
+-- 
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE  NOT_V_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+    VARIABLE  NOT_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE  NOT_V_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+    VARIABLE  NOT_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE  NOT_V_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+    VARIABLE  NOT_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE  NOT_V_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+    VARIABLE  NOT_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+  BEGIN
+--
+--          Test AND operator on: CONSTANTs
+--
+    ASSERT ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOT operator on: SIGNALs
+--
+    ASSERT ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOT operator on: VARIABLEs
+--
+    ASSERT ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1   and
+                  ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2   and
+                  ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3   and
+                  ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4   and
+                  ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1   and
+                  ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2   and
+                  ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3   and
+                  ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4   and
+                  ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1   and
+                  ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2   and
+                  ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3   and
+                  ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4   and
+                  ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1   and
+                  ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2   and
+                  ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3   and
+                  ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4   and
+                  ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1   and
+                  ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2   and
+                  ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3   and
+                  ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4   and
+                  ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1   and
+                  ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2   and
+                  ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3   and
+                  ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01950" 
+      severity NOTE;
+    assert (   ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1   and
+               ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2   and
+               ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3   and
+               ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4   and
+               ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1   and
+               ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2   and
+               ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3   and
+               ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4   and
+               ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1   and
+               ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2   and
+               ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3   and
+               ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4   and
+               ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1   and
+               ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2   and
+               ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3   and
+               ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4   and
+               ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1   and
+               ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2   and
+               ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3   and
+               ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4   and
+               ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1   and
+               ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2   and
+               ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3   and
+               ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01950 - Logical operator NOT for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01950arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd
new file mode 100644
index 0000000..7e05325
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1952.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01952ent IS
+END c07s02b01x00p02n02i01952ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01952arch OF c07s02b01x00p02n02i01952ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01952"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01952 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01952arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd
new file mode 100644
index 0000000..68affd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1953.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01953ent IS
+END c07s02b01x00p02n02i01953ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01953arch OF c07s02b01x00p02n02i01953ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01953"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01953 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01953arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd
new file mode 100644
index 0000000..6441460
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1954.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01954ent IS
+END c07s02b01x00p02n02i01954ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01954arch OF c07s02b01x00p02n02i01954ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01954"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01954 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01954arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd
new file mode 100644
index 0000000..f3bccbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1955.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01955ent IS
+END c07s02b01x00p02n02i01955ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01955arch OF c07s02b01x00p02n02i01955ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01955"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01955 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd
new file mode 100644
index 0000000..3099d05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1956.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01956ent IS
+END c07s02b01x00p02n02i01956ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01956arch OF c07s02b01x00p02n02i01956ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01956"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01956 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01956arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd
new file mode 100644
index 0000000..772d8f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1957.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01957ent IS
+END c07s02b01x00p02n02i01957ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01957arch OF c07s02b01x00p02n02i01957ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01957"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01957 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01957arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd
new file mode 100644
index 0000000..2035fd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01958ent IS
+END c07s02b01x00p02n02i01958ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01958"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01958arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd
new file mode 100644
index 0000000..5682a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1959.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01959ent IS
+END c07s02b01x00p02n02i01959ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01959arch OF c07s02b01x00p02n02i01959ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01959"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01959 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01959arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd
new file mode 100644
index 0000000..a88f706
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01960ent IS
+END c07s02b01x00p02n02i01960ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01960"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01960arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd
new file mode 100644
index 0000000..215dac4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1961.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01961ent IS
+END c07s02b01x00p02n02i01961ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01961arch OF c07s02b01x00p02n02i01961ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01961"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01961 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01961arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd
new file mode 100644
index 0000000..74d097a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1962.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01962ent IS
+END c07s02b01x00p02n02i01962ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01962arch OF c07s02b01x00p02n02i01962ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01962"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01962 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
new file mode 100644
index 0000000..5f67ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1963.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01963ent IS
+END c07s02b01x00p02n02i01963ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01963arch OF c07s02b01x00p02n02i01963ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01963"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01963 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01963arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd
new file mode 100644
index 0000000..461ac4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1964.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01964ent IS
+END c07s02b01x00p02n02i01964ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01964arch OF c07s02b01x00p02n02i01964ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01964"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01964 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd
new file mode 100644
index 0000000..4f523ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1965.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01965ent IS
+END c07s02b01x00p02n02i01965ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01965arch OF c07s02b01x00p02n02i01965ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01965"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01965 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01965arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd
new file mode 100644
index 0000000..c811c31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1966.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01966ent IS
+END c07s02b01x00p02n02i01966ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01966arch OF c07s02b01x00p02n02i01966ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01966"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01966 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd
new file mode 100644
index 0000000..f338edd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1967.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01967ent IS
+END c07s02b01x00p02n02i01967ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01967arch OF c07s02b01x00p02n02i01967ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01967"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01967 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01967arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd
new file mode 100644
index 0000000..e37c97d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1968.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01968ent IS
+END c07s02b01x00p02n02i01968ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01968arch OF c07s02b01x00p02n02i01968ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01968"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01968 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd
new file mode 100644
index 0000000..06e036e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1969.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01969ent IS
+END c07s02b01x00p02n02i01969ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01969arch OF c07s02b01x00p02n02i01969ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01969"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01969 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd
new file mode 100644
index 0000000..d52642a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1970.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01970ent IS
+END c07s02b01x00p02n02i01970ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01970arch OF c07s02b01x00p02n02i01970ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01970"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01970 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01970arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd
new file mode 100644
index 0000000..15aecac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1971.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01971ent IS
+END c07s02b01x00p02n02i01971ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01971arch OF c07s02b01x00p02n02i01971ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01971"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01971 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01971arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd
new file mode 100644
index 0000000..7d27566
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1972.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01972ent IS
+END c07s02b01x00p02n02i01972ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01972arch OF c07s02b01x00p02n02i01972ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+  BEGIN
+    a := not a;   
+    assert NOT(a=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01972"
+      severity NOTE;
+    assert ( a=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01972 - Logical operation of 'NOT'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01972arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd
new file mode 100644
index 0000000..c6032f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1973.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01973ent IS
+END c07s02b01x00p02n02i01973ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01973arch OF c07s02b01x00p02n02i01973ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+  BEGIN
+    a := not a;   
+    assert NOT(a=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01973"
+      severity NOTE;
+    assert ( a=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01973 - Logical operation of 'NOT'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd
new file mode 100644
index 0000000..ee8ae7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1974.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01974ent IS
+END c07s02b01x00p02n02i01974ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01974arch OF c07s02b01x00p02n02i01974ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant L : BIT_VECTOR(1 to 4) := "0101";
+    constant R : BIT_VECTOR(1 to 4) := "0011";
+
+    constant N  : BIT_VECTOR(1 TO 4) := not L;
+    constant A  : BIT_VECTOR(1 TO 4) := L and R;
+    constant O  : BIT_VECTOR(1 TO 4) := L or R;
+    constant NA : BIT_VECTOR(1 TO 4) := L nand R;
+    constant NO : BIT_VECTOR(1 TO 4) := L nor R;
+    constant X  : BIT_VECTOR(1 TO 4) := L xor R;
+  BEGIN
+
+    assert N  = "1010"      report "FAIL: NOT";
+    assert A  = "0001"      report "FAIL: AND";
+    assert O  = "0111"      report "FAIL: OR";
+    assert NA = "1110"      report "FAIL: NAND";
+    assert NO = "1000"      report "FAIL: NOR";
+    assert X  = "0110"      report "FAIL: XOR";
+
+    assert N = not L        report "FAIL: NOT (composite check)";
+    assert A  = (L and R)   report "FAIL: AND (composite check)";
+    assert O  = (L or R)    report "FAIL: OR (composite check)";
+    assert NA = (L nand R)  report "FAIL: NAND (composite check)";
+    assert NO = (L nor R)   report "FAIL: NOR (composite check)";
+    assert X  = (L xor R)   report "FAIL: XOR (composite check)";
+    
+    for i in 1 to 4 loop
+      assert N(i)  = not L(i)             report "FAIL: NOT";
+      assert A(i)  = (L(i) and R(i))      report "FAIL: AND";
+      assert O(i)  = (L(i) or R(i))       report "FAIL: OR";
+      assert NA(i) = (L(i) nand R(i))     report "FAIL: NAND";
+      assert NO(i) = (L(i) nor R(i))      report "FAIL: NOR";
+      assert X(i)  = (L(i) xor R(i))      report "FAIL: XOR";
+    end loop;
+
+    assert NOT(    N  = "1010"         and 
+                   A  = "0001"         and 
+                   O  = "0111"         and
+                   NA = "1110"         and
+                   NO = "1000"         and
+                   X  = "0110"         and
+                   N  = not L           and 
+                   A  = (L and R)      and 
+                   O  = (L or R)       and 
+                   NA = (L nand R)     and 
+                   NO = (L nor R)      and 
+                   X  = (L xor R)      )
+      report "***PASSED TEST: c07s02b01x00p02n02i01974"
+      severity NOTE;
+    assert (    N  = "1010"         and 
+                A  = "0001"         and 
+                O  = "0111"         and
+                NA = "1110"         and
+                NO = "1000"         and
+                X  = "0110"         and
+                N  = not L           and 
+                A  = (L and R)      and 
+                O  = (L or R)       and 
+                NA = (L nand R)     and 
+                NO = (L nor R)      and 
+                X  = (L xor R)      )
+      report "***FAILED TEST: c07s02b01x00p02n02i01974 - BIT_VECTOR type truth table test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01974arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd
new file mode 100644
index 0000000..4bfd50e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1975.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01975ent IS
+  constant T:bit := '1';
+  constant F:bit := '0';
+END c07s02b01x00p02n02i01975ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01975arch OF c07s02b01x00p02n02i01975ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1 : bit := T;
+    variable A2 : bit := F;
+  BEGIN
+    assert NOT(    (A1 and A1) = '1'   and
+                   (A1 and A2) = '0'   and
+                   (A2 and A1) = '0'   and
+                   (A2 and A2) = '0'   and
+                   (A1 or A1) = '1'   and
+                   (A1 or A2) = '1'   and
+                   (A2 or A1) = '1'   and
+                   (A2 or A2) = '0'   and
+                   (A1 xor A1) = '0'   and
+                   (A1 xor A2) = '1'   and
+                   (A2 xor A1) = '1'   and
+                   (A2 xor A2) = '0'   and
+                   (A1 nand A1) = '0'   and
+                   (A1 nand A2) = '1'   and
+                   (A2 nand A1) = '1'   and
+                   (A2 nand A2) = '1'   and
+                   (A1 nor A1) = '0'   and
+                   (A1 nor A2) = '0'   and
+                   (A2 nor A1) = '0'   and
+                   (A2 nor A2) = '1'   and
+                   (not A1) = '0'      and
+                   (not A2) = '1')
+      report "***PASSED TEST: c07s02b01x00p02n02i01975"
+      severity NOTE;
+    assert (    (A1 and A1) = '1'   and
+                (A1 and A2) = '0'   and
+                (A2 and A1) = '0'   and
+                (A2 and A2) = '0'   and
+                (A1 or A1) = '1'   and
+                (A1 or A2) = '1'   and
+                (A2 or A1) = '1'   and
+                (A2 or A2) = '0'   and
+                (A1 xor A1) = '0'   and
+                (A1 xor A2) = '1'   and
+                (A2 xor A1) = '1'   and
+                (A2 xor A2) = '0'   and
+                (A1 nand A1) = '0'   and
+                (A1 nand A2) = '1'   and
+                (A2 nand A1) = '1'   and
+                (A2 nand A2) = '1'   and
+                (A1 nor A1) = '0'   and
+                (A1 nor A2) = '0'   and
+                (A2 nor A1) = '0'   and
+                (A2 nor A2) = '1'   and
+                (not A1) = '0'      and
+                (not A2) = '1')
+      report "***FAILED TEST: c07s02b01x00p02n02i01975 - BIT type truth table test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01975arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd
new file mode 100644
index 0000000..8514536
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p03n01i01976ent IS
+END c07s02b01x00p03n01i01976ent;
+
+ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
+  signal s : integer := 0;
+  function temp(s:integer) return boolean is
+  begin
+    assert FALSE
+      report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
+      severity ERROR;
+    return true;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable x : boolean := false;
+  BEGIN
+    if x and (temp(s)) then
+      NULL;
+    end if;
+    wait for 1 ns;
+    assert FALSE
+      report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p03n01i01976arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd
new file mode 100644
index 0000000..1c391cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1978.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n02i01978ent IS
+END c07s02b02x00p01n02i01978ent;
+
+ARCHITECTURE c07s02b02x00p01n02i01978arch OF c07s02b02x00p01n02i01978ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s02b02x00p01n02i01978"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s02b02x00p01n02i01978"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s02b02x00p01n02i01978arch;
+
+-- CONFIGURATION c07s02b02x00p01n02i01978cfg OF c07s02b02x00p01n02i01978ent IS
+--     FOR c07s02b02x00p01n02i01978arch
+--     END FOR;
+-- END c07s02b02x00p01n02i01978cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd
new file mode 100644
index 0000000..1804bdf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc198.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00198ent IS
+END c03s01b00x00p04n01i00198ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00198arch OF c03s01b00x00p04n01i00198ent IS
+  type t1 is range (1+1) to (10+2);
+BEGIN
+  TESTING: PROCESS
+    variable k : t1 := 6;
+  BEGIN
+    k := 5;   
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p04n01i00198" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p04n01i00198- The range must be either a range attribute name or two simple expressions combined with a direction operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd
new file mode 100644
index 0000000..d0634a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1981.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n03i01981ent IS
+END c07s02b02x00p01n03i01981ent;
+
+ARCHITECTURE c07s02b02x00p01n03i01981arch OF c07s02b02x00p01n03i01981ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i, j, k, l, m, n, o, p : integer := 1;
+  BEGIN
+    if (i<j or (i>= 0) ) then  -- No_failure_here    
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p01n03i01981"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p01n03i01981 - The result type of each relational operator is the predefined type BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n03i01981arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd
new file mode 100644
index 0000000..d8498c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1982.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n03i01982ent IS
+END c07s02b02x00p01n03i01982ent;
+
+ARCHITECTURE c07s02b02x00p01n03i01982arch OF c07s02b02x00p01n03i01982ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i, j, k, l, m, n, o, p : integer := 1;
+  BEGIN
+    if (m=n) then  -- No_failure_here    
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p01n03i01982"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p01n03i01982 - The result type of each relational operator is the predefined type BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n03i01982arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd
new file mode 100644
index 0000000..ab8a25c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01983ent IS
+  type color is (red, green, blue);
+  constant azure : color := blue;
+  constant first : color := color'low;
+END c07s02b02x00p02n01i01983ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1, A2   : color;
+    variable A3    : color := blue;
+    alias AA1 :color is A1;
+  BEGIN
+
+    AA1:= first;
+    A2 := color'succ(A1);
+
+    assert NOT(     A2 = green   and
+                    green = A2   and
+                    A2 > AA1   and
+                    red >= A1   and
+                    A1 >= red   and
+                    A3 <= blue   and
+                    blue <= A3   and
+                    A1 < green   and
+                    green < A3   and
+                    red < azure    )
+      report "***PASSED TEST: c07s02b02x00p02n01i01983"
+      severity NOTE;
+    assert (     A2 = green   and
+                 green = A2   and
+                 A2 > AA1   and
+                 red >= A1   and
+                 A1 >= red   and
+                 A3 <= blue   and
+                 blue <= A3   and
+                 A1 < green   and
+                 green < A3   and
+                 red < azure    )
+      report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01983arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd
new file mode 100644
index 0000000..167b16d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1984.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01984ent IS
+END c07s02b02x00p02n01i01984ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01984arch OF c07s02b02x00p02n01i01984ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable B1 : boolean := true;
+    variable B2 : boolean := false;
+    variable A1 : bit := '1';
+    variable A2 : bit := '0';
+  BEGIN
+
+    assert NOT(     A1 = '1'   and
+                    '1' = A1   and
+                    B2 = false   and
+                    false = B2   and
+                    A1 /= A2   and
+                    B1 /= B2   and
+                    A2 < A1   and
+                    B2 < B1   and
+                    A1 > A2   and
+                    B1 > B2   and
+                    A2 <= A1   and
+                    B2 <= B1   and
+                    A1 >= A2   and
+                    B1 >= B2   and
+                    A1 <= A1   and
+                    B1 <= B1   and
+                    B2 <= B2   and
+                    A2 <= A2   )   
+      report "***PASSED TEST: c07s02b02x00p02n01i01984"
+      severity NOTE;
+    assert (     A1 = '1'   and
+                 '1' = A1   and
+                 B2 = false   and
+                 false = B2   and
+                 A1 /= A2   and
+                 B1 /= B2   and
+                 A2 < A1   and
+                 B2 < B1   and
+                 A1 > A2   and
+                 B1 > B2   and
+                 A2 <= A1   and
+                 B2 <= B1   and
+                 A1 >= A2   and
+                 B1 >= B2   and
+                 A1 <= A1   and
+                 B1 <= B1   and
+                 B2 <= B2   and
+                 A2 <= A2   )   
+      report "***FAILED TEST: c07s02b02x00p02n01i01984 - Relational operators true table test for data type of BIT and BOOLEAN failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01984arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd
new file mode 100644
index 0000000..005daf6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd
@@ -0,0 +1,153 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01985ent IS
+END c07s02b02x00p02n01i01985ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant meg       : integer := 1000000;
+    variable bigpos    : integer := 2000 * meg;
+    variable bigneg    : integer := -2000 * meg;
+    variable smallpos    : integer := 2000;
+    variable smallneg    : integer := -2000;
+    variable zero       : integer := 0;
+  BEGIN
+
+    assert NOT(    ( bigneg < smallneg)   and
+                   ( bigneg < zero)   and
+                   ( bigneg < smallpos)   and
+                   ( bigneg < bigpos)   and
+                   ( smallneg < zero)   and
+                   ( smallneg < smallpos)   and
+                   ( smallneg < bigpos)   and
+                   ( zero < smallpos)   and
+                   ( zero < bigpos)   and
+                   ( smallpos < bigpos)   and
+                   ( not(bigneg >= smallneg))   and
+                   ( not(bigneg >= zero))      and
+                   ( not(bigneg >= smallpos))   and
+                   ( not(bigneg >= bigpos))   and
+                   ( not(smallneg >= zero))   and
+                   ( not(smallneg >= smallpos))   and
+                   ( not(smallneg >= bigpos))   and
+                   ( not(zero >= smallpos))   and
+                   ( not(zero >= bigpos))      and
+                   ( not(smallpos >= bigpos))   and
+                   ( bigneg <= smallneg)   and
+                   ( bigneg <= zero)   and
+                   ( bigneg <= smallpos)   and
+                   ( bigneg <= bigpos)   and
+                   ( smallneg <= zero)   and
+                   ( smallneg <= smallpos)   and
+                   ( smallneg <= bigpos)   and
+                   ( zero <= smallpos)   and
+                   ( zero <= bigpos)   and
+                   ( smallpos <= bigpos)   and
+                   ( bigneg <= bigneg)   and
+                   ( smallneg <= smallneg)   and
+                   ( zero <=  zero)   and
+                   ( smallpos <= smallpos)   and
+                   ( bigpos <= bigpos)   and
+                   ( not(bigneg > smallneg))   and
+                   ( not(bigneg > zero))      and
+                   ( not(bigneg > smallpos))   and
+                   ( not(bigneg > bigpos))      and
+                   ( not(smallneg > zero))      and
+                   ( not(smallneg > smallpos))   and
+                   ( not(smallneg > bigpos))   and
+                   ( not(zero > smallpos))      and
+                   ( not(zero > bigpos))      and
+                   ( not(smallpos > bigpos))   and
+                   ( not(bigneg > bigneg))      and
+                   ( not(smallneg > smallneg))   and
+                   ( not(zero >  zero))      and
+                   ( not(smallpos > smallpos))   and
+                   ( not(bigpos > bigpos))      ) 
+      report "***PASSED TEST: c07s02b02x00p02n01i01985"
+      severity NOTE;
+    assert (    ( bigneg < smallneg)   and
+                ( bigneg < zero)   and
+                ( bigneg < smallpos)   and
+                ( bigneg < bigpos)   and
+                ( smallneg < zero)   and
+                ( smallneg < smallpos)   and
+                ( smallneg < bigpos)   and
+                ( zero < smallpos)   and
+                ( zero < bigpos)   and
+                ( smallpos < bigpos)   and
+                ( not(bigneg >= smallneg))   and
+                ( not(bigneg >= zero))      and
+                ( not(bigneg >= smallpos))   and
+                ( not(bigneg >= bigpos))   and
+                ( not(smallneg >= zero))   and
+                ( not(smallneg >= smallpos))   and
+                ( not(smallneg >= bigpos))   and
+                ( not(zero >= smallpos))   and
+                ( not(zero >= bigpos))      and
+                ( not(smallpos >= bigpos))   and
+                ( bigneg <= smallneg)   and
+                ( bigneg <= zero)   and
+                ( bigneg <= smallpos)   and
+                ( bigneg <= bigpos)   and
+                ( smallneg <= zero)   and
+                ( smallneg <= smallpos)   and
+                ( smallneg <= bigpos)   and
+                ( zero <= smallpos)   and
+                ( zero <= bigpos)   and
+                ( smallpos <= bigpos)   and
+                ( bigneg <= bigneg)   and
+                ( smallneg <= smallneg)   and
+                ( zero <=  zero)   and
+                ( smallpos <= smallpos)   and
+                ( bigpos <= bigpos)   and
+                ( not(bigneg > smallneg))   and
+                ( not(bigneg > zero))      and
+                ( not(bigneg > smallpos))   and
+                ( not(bigneg > bigpos))      and
+                ( not(smallneg > zero))      and
+                ( not(smallneg > smallpos))   and
+                ( not(smallneg > bigpos))   and
+                ( not(zero > smallpos))      and
+                ( not(zero > bigpos))      and
+                ( not(smallpos > bigpos))   and
+                ( not(bigneg > bigneg))      and
+                ( not(smallneg > smallneg))   and
+                ( not(zero >  zero))      and
+                ( not(smallpos > smallpos))   and
+                ( not(bigpos > bigpos))      ) 
+      report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01985arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd
new file mode 100644
index 0000000..b7fcb45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd
@@ -0,0 +1,149 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1986.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01986ent IS
+  type omega is range (-100) to 100
+    units
+      o1;
+      o2  = 5 o1;
+      o3  = 10 o1;
+    end units;
+END c07s02b02x00p02n01i01986ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01986arch OF c07s02b02x00p02n01i01986ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable om1, om2, om3 : omega;
+
+    --alias in A of variable in A of E physical type
+    
+    alias al1 : omega is om1;
+    alias al2 : omega is om2;
+    alias al3 : omega is om3;
+  BEGIN
+    om1 := 4 o1;
+    om2 := 5 o1;
+    om3 := 6 o1;
+
+    assert NOT(     5 o1 = 5 o1      and
+                    5 o1 = abs(5 o1)   and
+                    5 o1 = abs(-5 o1)   and
+                    4 o1 /= 5 o1      and
+                    4 o1 /= abs(5 o1)   and
+                    4 o1 /= abs(-5 o1)   and
+                    4 o1 <= 5 o1      and
+                    4 o1 <= abs(5 o1)   and
+                    4 o1 <= abs(-5 o1)   and
+                    5 o1 <= abs(-5 o1)   and
+                    4 o1 < 5 o1      and
+                    4 o1 < abs(5 o1)   and
+                    4 o1 < abs(-5 o1)   and
+                    6 o1 >= 5 o1      and
+                    6 o1 >= abs(5 o1)   and
+                    6 o1 >= abs(-5 o1)   and
+                    5 o1 >= abs(-5 o1)   and
+                    6 o1 > 5 o1      and
+                    6 o1 > abs(5 o1)   and
+                    6 o1 > abs(-5 o1)   and
+                    
+--relation operators with variables
+                    
+                    om1 = om1      and
+                    om2 = abs(om2)      and
+                    om2 = abs(-om2)   and
+                    om1 /= om2      and
+                    om1 /= abs(om2)   and
+                    om1 /= abs(-om2)   and
+                    om1 <= om2      and
+                    om1 <= abs(om2)   and
+                    om1 <= abs(-om2)   and
+                    om2 <= abs(-om2)   and
+                    om1 < om2      and
+                    om1 < abs(om2)      and
+                    om1 < abs(-om2)   and
+                    om2 >= om1      and
+                    om2 >= abs(om1)   and
+                    om2 >= abs(-om1)   and
+                    om2 >= abs(-om1)   and
+                    om2 > om1      and
+                    om2 > abs(om1)      and
+                    om2 > abs(-om1)   )
+      report "***PASSED TEST: c07s02b02x00p02n01i01986"
+      severity NOTE;
+    assert (     5 o1 = 5 o1      and
+                 5 o1 = abs(5 o1)   and
+                 5 o1 = abs(-5 o1)   and
+                 4 o1 /= 5 o1      and
+                 4 o1 /= abs(5 o1)   and
+                 4 o1 /= abs(-5 o1)   and
+                 4 o1 <= 5 o1      and
+                 4 o1 <= abs(5 o1)   and
+                 4 o1 <= abs(-5 o1)   and
+                 5 o1 <= abs(-5 o1)   and
+                 4 o1 < 5 o1      and
+                 4 o1 < abs(5 o1)   and
+                 4 o1 < abs(-5 o1)   and
+                 6 o1 >= 5 o1      and
+                 6 o1 >= abs(5 o1)   and
+                 6 o1 >= abs(-5 o1)   and
+                 5 o1 >= abs(-5 o1)   and
+                 6 o1 > 5 o1      and
+                 6 o1 > abs(5 o1)   and
+                 6 o1 > abs(-5 o1)   and
+                 
+--relation operators with variables
+                 
+                 om1 = om1      and
+                 om2 = abs(om2)      and
+                 om2 = abs(-om2)   and
+                 om1 /= om2      and
+                 om1 /= abs(om2)   and
+                 om1 /= abs(-om2)   and
+                 om1 <= om2      and
+                 om1 <= abs(om2)   and
+                 om1 <= abs(-om2)   and
+                 om2 <= abs(-om2)   and
+                 om1 < om2      and
+                 om1 < abs(om2)      and
+                 om1 < abs(-om2)   and
+                 om2 >= om1      and
+                 om2 >= abs(om1)   and
+                 om2 >= abs(-om1)   and
+                 om2 >= abs(-om1)   and
+                 om2 > om1      and
+                 om2 > abs(om1)      and
+                 om2 > abs(-om1)   )
+      report "***FAILED TEST: c07s02b02x00p02n01i01986 - Relational operators truth table test for data type of Physical failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01986arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd
new file mode 100644
index 0000000..a8d01ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01987ent IS
+END c07s02b02x00p02n01i01987ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1, r2, r3, r4 : real;
+  BEGIN
+
+    r1 := 69.0;
+    r2 := 50.0;
+    r3 := (-69.0);
+    r4 := (-50.0);
+
+    assert NOT(     real'high > real'low   and
+                    real'high >= real'low   and
+                    real'high > 0.0   and
+                    real'high >= 0.0   and
+                    real'low < 0.0      and
+                    real'low <= 0.0   and
+                    real'high /= real'low   and
+
+                    r1 > r2   and
+                    r1 >= r2   and
+                    r1 > 0.0   and
+                    r1 /= r2   and
+                    r2 < r1   and
+                    r2 <= r1   and
+                    
+                    r4 > r3   and
+                    r4 >= r3   and
+                    r4 < 0.0   and
+                    r4 /= r3   and
+                    r3 < r4   and
+                    r3 <= r4   and
+                    
+                    r1 > r3   and
+                    r2 >= r4   and
+                    r4 < r1   and
+                    r1 /= r3   and
+                    r2 /= r4   and
+                    r3 < r1   and
+                    r4 <= r2   and
+                    
+                    3.14E1 > 3.10E1   and
+                    5.7E-9 < 5.7E+9 )
+      report "***PASSED TEST: c07s02b02x00p02n01i01987"
+      severity NOTE;
+    assert (     real'high > real'low   and
+                 real'high >= real'low   and
+                 real'high > 0.0   and
+                 real'high >= 0.0   and
+                 real'low < 0.0      and
+                 real'low <= 0.0   and
+                 real'high /= real'low   and
+
+                 r1 > r2   and
+                 r1 >= r2   and
+                 r1 > 0.0   and
+                 r1 /= r2   and
+                 r2 < r1   and
+                 r2 <= r1   and
+                 
+                 r4 > r3   and
+                 r4 >= r3   and
+                 r4 < 0.0   and
+                 r4 /= r3   and
+                 r3 < r4   and
+                 r3 <= r4   and
+                 
+                 r1 > r3   and
+                 r2 >= r4   and
+                 r4 < r1   and
+                 r1 /= r3   and
+                 r2 /= r4   and
+                 r3 < r1   and
+                 r4 <= r2   and
+                 
+                 3.14E1 > 3.10E1   and
+                 5.7E-9 < 5.7E+9 )
+      report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd
new file mode 100644
index 0000000..45e875d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd
@@ -0,0 +1,204 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1988.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01988ent IS
+END c07s02b02x00p02n01i01988ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01988arch OF c07s02b02x00p02n01i01988ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    variable B : bit_vector (32 downto 1);
+    variable C : bit_vector (15 downto 0);
+    variable D : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+  BEGIN
+
+    A := x"ffffffff";
+    B := x"00000000";
+    C := x"ffff";
+    D := x"0000";
+    E := x"ffffffffffff";
+    F := x"000000000000";
+
+    assert NOT(    A = A      and
+                   A /= B      and
+                   A /= C      and
+                   A /= D      and
+                   A /= E      and
+                   A /= F      and
+                   B /= A      and
+                   B = B      and
+                   B /= C      and
+                   B /= D      and
+                   B /= E      and
+                   B /= F      and
+                   C /= A      and
+                   C /= B      and
+                   C = C      and
+                   C /= D      and
+                   C /= E      and
+                   C /= F      and
+                   D /= A      and
+                   D /= B      and
+                   D /= C      and
+                   D = D      and
+                   D /= E      and
+                   D /= F      and
+                   E /= A      and
+                   E /= B      and
+                   E /= C      and
+                   E /= D      and
+                   E = E      and
+                   E /= F      and
+                   F /= A      and
+                   F /= B      and
+                   F /= C      and
+                   F /= D      and
+                   F /= E      and
+                   F = F      and
+                   A <= A      and
+                   A > B      and
+                   A > C      and
+                   A > D      and
+                   A < E      and
+                   A > F      and
+                   B < A      and
+                   B <= B      and
+                   B < C      and
+                   B > D      and
+                   B < E      and
+                   B < F      and
+                   C < A      and
+                   C > B      and
+                   C <= C      and
+                   C > D      and
+                   C < E      and
+                   C > F      and
+                   D < A      and
+                   D < B      and
+                   D < C      and
+                   D <= D      and
+                   D < E      and
+                   D < F      and
+                   E > A      and
+                   E > B      and
+                   E > C      and
+                   E > D      and
+                   E <= E      and
+                   E > F      and
+                   F < A      and
+                   F > B      and
+                   F < C      and
+                   F > D      and
+                   F < E      and
+                   F <= F)
+      report "***PASSED TEST: c07s02b02x00p02n01i01988"
+      severity NOTE;
+    assert (    A = A      and
+                A /= B      and
+                A /= C      and
+                A /= D      and
+                A /= E      and
+                A /= F      and
+                B /= A      and
+                B = B      and
+                B /= C      and
+                B /= D      and
+                B /= E      and
+                B /= F      and
+                C /= A      and
+                C /= B      and
+                C = C      and
+                C /= D      and
+                C /= E      and
+                C /= F      and
+                D /= A      and
+                D /= B      and
+                D /= C      and
+                D = D      and
+                D /= E      and
+                D /= F      and
+                E /= A      and
+                E /= B      and
+                E /= C      and
+                E /= D      and
+                E = E      and
+                E /= F      and
+                F /= A      and
+                F /= B      and
+                F /= C      and
+                F /= D      and
+                F /= E      and
+                F = F      and
+                A <= A      and
+                A > B      and
+                A > C      and
+                A > D      and
+                A < E      and
+                A > F      and
+                B < A      and
+                B <= B      and
+                B < C      and
+                B > D      and
+                B < E      and
+                B < F      and
+                C < A      and
+                C > B      and
+                C <= C      and
+                C > D      and
+                C < E      and
+                C > F      and
+                D < A      and
+                D < B      and
+                D < C      and
+                D <= D      and
+                D < E      and
+                D < F      and
+                E > A      and
+                E > B      and
+                E > C      and
+                E > D      and
+                E <= E      and
+                E > F      and
+                F < A      and
+                F > B      and
+                F < C      and
+                F > D      and
+                F < E      and
+                F <= F)
+      report "***FAILED TEST: c07s02b02x00p02n01i01988 - Relational operators truth table test for data type of Bit_vector failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd
new file mode 100644
index 0000000..17952c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1991.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01991ent IS
+END c07s02b02x00p07n01i01991ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01991arch OF c07s02b02x00p07n01i01991ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type   ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
+    variable k : integer := 0;
+  BEGIN
+    if (ONE /= TWO) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01991" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01991 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01991arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd
new file mode 100644
index 0000000..6efeae5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1992.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01992ent IS
+END c07s02b02x00p07n01i01992ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01992arch OF c07s02b02x00p07n01i01992ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 6;
+  BEGIN
+    if (m /= 5) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01992"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01992 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01992arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd
new file mode 100644
index 0000000..1a9d15e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01993ent IS
+END c07s02b02x00p07n01i01993ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : real    := 5.5;
+  BEGIN
+    if (m /= 4.5) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01993" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01993arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd
new file mode 100644
index 0000000..bc3c073
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1994.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01994ent IS
+END c07s02b02x00p07n01i01994ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01994arch OF c07s02b02x00p07n01i01994ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CHAR_RECORD is record
+                          C1, C2, C3 : CHARACTER;
+                        end record;
+    variable k : integer     := 0;
+    variable m : CHAR_RECORD := ('a','b','c');
+  BEGIN
+    if (m /= ('a','b','b')) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01994" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01994 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01994arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd
new file mode 100644
index 0000000..4494382
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1995.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01995ent IS
+END c07s02b02x00p07n01i01995ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01995arch OF c07s02b02x00p07n01i01995ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 260
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+      end units;
+    variable k : integer    := 0;
+    variable m : PHYS    := 10 A; 
+  BEGIN
+    if (m /= 2 B) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01995"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01995 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01995arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd
new file mode 100644
index 0000000..5e75162
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1996.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01996ent IS
+END c07s02b02x00p07n02i01996ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01996arch OF c07s02b02x00p07n02i01996ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
+    variable k : integer := 0;
+  BEGIN
+    if (ONE = ONE) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01996"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01996 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01996arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd
new file mode 100644
index 0000000..6b7e2c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1997.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01997ent IS
+END c07s02b02x00p07n02i01997ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01997arch OF c07s02b02x00p07n02i01997ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    if (m = 5) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01997"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01997 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01997arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd
new file mode 100644
index 0000000..ab5c00a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1998.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01998ent IS
+END c07s02b02x00p07n02i01998ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01998arch OF c07s02b02x00p07n02i01998ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : real    := 5.5;
+  BEGIN
+    if (m = 5.5) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01998"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01998 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01998arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd
new file mode 100644
index 0000000..66cd6f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1999.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01999ent IS
+END c07s02b02x00p07n02i01999ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01999arch OF c07s02b02x00p07n02i01999ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+      end units;
+    variable k : integer := 0;
+    variable m : PHYS    := 10 A;
+  BEGIN
+    if (m = 1 B) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01999"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01999 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01999arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd
new file mode 100644
index 0000000..d968b30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2000.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i02000ent IS
+END c07s02b02x00p07n02i02000ent;
+
+ARCHITECTURE c07s02b02x00p07n02i02000arch OF c07s02b02x00p07n02i02000ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ENUM       is ( ONE, TWO, THREE, FOUR, FIVE );
+    type    NEW_INTEGER     is range integer'left to integer'right;
+    type    UN_INT_ARRAY    is array ( ENUM range <>) of NEW_INTEGER;
+    subtype INT_ARRAY       is UN_INT_ARRAY( ONE to TWO );
+    variable k : integer  := 0;
+    variable m : INT_ARRAY:= (1,2);
+  BEGIN
+    if (m = INT_ARRAY'(1,2)) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i02000"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i02000 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i02000arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd
new file mode 100644
index 0000000..10188b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i02001ent IS
+END c07s02b02x00p07n02i02001ent;
+
+ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CHAR_RECORD is record
+                          C1, C2, C3 : CHARACTER;
+                        end record;
+    variable k : integer  := 0;
+    variable m : CHAR_RECORD := ('a','b','c');
+  BEGIN
+    if (m = CHAR_RECORD'('a','b','c')) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i02001"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i02001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd
new file mode 100644
index 0000000..e3a1189
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2004.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02004ent IS
+END c07s02b02x00p08n02i02004ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02004arch OF c07s02b02x00p08n02i02004ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    array_x    is array (positive range <>) of integer;
+    subtype    array_three    is array_x (1 to 6) ;
+    subtype    array_four     is array_x (6 downto 1) ;
+    variable    x : array_four  := (1,2,3,4,5,6);
+    variable    y : array_three := (1,2,3,4,5,6);
+  BEGIN
+    assert NOT(x=y)
+      report "***PASSED TEST: c07s02b02x00p08n02i02004"
+      severity NOTE;
+    assert ( x=y )
+      report "***FAILED TEST: c07s02b02x00p08n02i02004 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02004arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd
new file mode 100644
index 0000000..f487125
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2005.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02005ent IS
+END c07s02b02x00p08n02i02005ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02005arch OF c07s02b02x00p08n02i02005ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : array_type;
+                end record;
+    variable x : rec := (1,1.2,true,(1,2,3,4,5,6,7,8,9,0));
+    variable y : rec := (1,1.2,true,(0,1,2,3,4,5,6,7,8,9));
+  BEGIN
+    assert NOT(x/=y)
+      report "***PASSED TEST: c07s02b02x00p08n02i02005"
+      severity NOTE;
+    assert ( x/=y )
+      report "***FAILED TEST: c07s02b02x00p08n02i02005 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd
new file mode 100644
index 0000000..e62e192
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2006.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02006ent IS
+END c07s02b02x00p08n02i02006ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02006arch OF c07s02b02x00p08n02i02006ent IS
+
+  TYPE    real_vector is array (integer range <>) of REAL;
+  SUBTYPE real_8 is real_vector(0 to 7);
+  SUBTYPE real_4 is real_vector(0 to 3);
+
+BEGIN
+  TESTING: PROCESS
+
+    CONSTANT slice_8a : real_8 := (1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0);
+    VARIABLE slice_8b : real_8 := (1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0);
+    VARIABLE target_1 : boolean;
+    VARIABLE target_2 : boolean;
+
+  BEGIN
+    target_1 := slice_8a (3 to 3)  = slice_8b (3 to 3);
+    target_2 := slice_8a (3 to 3) /= slice_8b (4 to 4);
+
+    assert NOT(target_1 and target_2) 
+      report "***PASSED TEST: c07s02b02x00p08n02i02006"
+      severity NOTE;
+    assert (target_1 and target_2) 
+      report "***FAILED TEST: c07s02b02x00p08n02i02006 - Two single element REAL slices are operable over the set of relational operations." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02006arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd
new file mode 100644
index 0000000..61261ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2007.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n03i02007ent IS
+END c07s02b02x00p08n03i02007ent;
+
+ARCHITECTURE c07s02b02x00p08n03i02007arch OF c07s02b02x00p08n03i02007ent IS
+  signal Q : BIT_VECTOR(0 downto 7);
+  signal S : BIT_VECTOR(7 to 0) ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S=Q)
+      report "***PASSED TEST: c07s02b02x00p08n03i02007"
+      severity NOTE;
+    assert ( S=Q )
+      report "***FAILED TEST: c07s02b02x00p08n03i02007 - Two null arrays of the same type are always equal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n03i02007arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd
new file mode 100644
index 0000000..532b757
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2008.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n04i02008ent IS
+END c07s02b02x00p08n04i02008ent;
+
+ARCHITECTURE c07s02b02x00p08n04i02008arch OF c07s02b02x00p08n04i02008ent IS
+  type ARR is access BIT_VECTOR ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : ARR := null ;
+    variable V2 : ARR := null ;
+  BEGIN
+    assert NOT( V1=V2 )
+      report "***PASSED TEST: c07s02b02x00p08n04i02008"
+      severity NOTE;
+    assert ( V1=V2 )
+      report "***FAILED TEST: c07s02b02x00p08n04i02008 - Two values of an access type are equal if both are equal to the null value of the access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n04i02008arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd
new file mode 100644
index 0000000..6443b8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc201.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00201ent IS
+END c03s01b00x00p04n01i00201ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00201arch OF c03s01b00x00p04n01i00201ent IS
+  type a is range (1+1) to 10;
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p04n01i00201" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p04n01i00201 -The range must be either a range attribute name or two simple expressions combined with a direction operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd
new file mode 100644
index 0000000..883aaea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02010ent IS
+END c07s02b02x00p10n01i02010ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type a1 is array (1 to 5) of integer;
+    variable a : a1 := (1,2,3,4,5);
+    variable b : a1 := (2,3,4,5,6);
+    variable k : integer := 0;
+  BEGIN
+    if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
+      -- No_failure_here
+      k := 5;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p10n01i02010" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd
new file mode 100644
index 0000000..80a1baa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02011ent IS
+END c07s02b02x00p10n01i02011ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
+
+  TYPE    int_vector is array (integer range <>) of INTEGER;
+  SUBTYPE int_8 is int_vector(0 to 7);
+  SUBTYPE int_4 is int_vector(0 to 3);
+
+BEGIN
+  TESTING: PROCESS
+    CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
+    VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
+    VARIABLE target_1 : boolean;
+    VARIABLE target_2 : boolean;
+    VARIABLE target_3 : boolean;
+    VARIABLE target_4 : boolean;
+  BEGIN
+
+    target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
+    
+    target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
+    
+    target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
+    
+    target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
+
+    wait for 5 ns;
+    assert NOT(   target_1 and
+                  target_2 and
+                  target_3 and
+                  target_4 )
+      report "***PASSED TEST: c07s02b02x00p10n01i02011" 
+      severity NOTE;
+    assert (   target_1 and
+               target_2 and
+               target_3 and
+               target_4 )
+      report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd
new file mode 100644
index 0000000..9ccadd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd
@@ -0,0 +1,251 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02012ent IS
+END c07s02b02x00p10n01i02012ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - for unconstrained types
+--           other composite type declarations are in package "COMPOSITE"
+--
+    CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
+    CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
+
+    CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+--
+--          Composite VARIABLE declarations
+--
+    VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
+    VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
+    VARIABLE V0_csa1_1 : t_csa1_1 ;
+    VARIABLE V0_csa1_3 : t_csa1_3 ;
+
+    VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+    VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
+    VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
+--
+--          Arrays of the same type, element values, different length
+--
+    VARIABLE V3_usa1_1 : t_usa1_1 ( 1  TO  7  ) ;
+    VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
+--
+    CONSTANT msg1 : STRING := "ERROR: less than operator failure: ";
+    CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: ";
+  BEGIN
+--
+--          Check less than operator - CONSTANTS (from package 'composite')
+    --
+    ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - VARIABLES
+--
+    ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - same type, element values : diff array length
+--
+    ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES
+--
+    ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - same type, element values : diff array length
+--
+    ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES
+--
+    ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE;
+    assert NOT(   C0_usa1_1 < C2_usa1_1   and
+                  C0_usa1_3 < C2_usa1_3   and
+                  C0_csa1_1 < C2_csa1_1   and
+                  C0_csa1_3 < C2_csa1_3   and
+                  V0_usa1_1 < V2_usa1_1   and
+                  V0_usa1_3 < V2_usa1_3   and
+                  V0_csa1_1 < V2_csa1_1   and
+                  V0_csa1_3 < V2_csa1_3   and
+                  V0_usa1_1 < C2_usa1_1   and
+                  V0_usa1_3 < C2_usa1_3   and
+                  V0_csa1_1 < C2_csa1_1   and
+                  V0_csa1_3 < C2_csa1_3   and
+                  V3_usa1_1 < V2_usa1_1   and
+                  V3_usa1_3 < V2_usa1_3   and
+                  C0_usa1_1 <= C2_usa1_1   and
+                  C0_usa1_3 <= C2_usa1_3   and
+                  C0_csa1_1 <= C2_csa1_1   and
+                  C0_csa1_3 <= C2_csa1_3   and
+                  V0_usa1_1 <= V2_usa1_1   and
+                  V0_usa1_3 <= V2_usa1_3   and
+                  V0_csa1_1 <= V2_csa1_1   and
+                  V0_csa1_3 <= V2_csa1_3   and
+                  V0_usa1_1 <= C2_usa1_1   and
+                  V0_usa1_3 <= C2_usa1_3   and
+                  V0_csa1_1 <= C2_csa1_1   and
+                  V0_csa1_3 <= C2_csa1_3   and
+                  V3_usa1_1 <= V2_usa1_1   and
+                  V3_usa1_3 <= V2_usa1_3   and
+                  C2_usa1_1 <= C2_usa1_1   and
+                  C2_usa1_3 <= C2_usa1_3   and
+                  C2_csa1_1 <= C2_csa1_1   and
+                  C2_csa1_3 <= C2_csa1_3   and
+                  V2_usa1_1 <= V2_usa1_1   and
+                  V2_usa1_3 <= V2_usa1_3   and
+                  V2_csa1_1 <= V2_csa1_1   and
+                  V2_csa1_3 <= V2_csa1_3   and
+                  V2_usa1_1 <= C2_usa1_1   and
+                  V2_usa1_3 <= C2_usa1_3   and
+                  V2_csa1_1 <= C2_csa1_1   and
+                  V2_csa1_3 <= C2_csa1_3   )
+      report "***PASSED TEST: c07s02b02x00p10n01i02012" 
+      severity NOTE;
+    assert (   C0_usa1_1 < C2_usa1_1   and
+               C0_usa1_3 < C2_usa1_3   and
+               C0_csa1_1 < C2_csa1_1   and
+               C0_csa1_3 < C2_csa1_3   and
+               V0_usa1_1 < V2_usa1_1   and
+               V0_usa1_3 < V2_usa1_3   and
+               V0_csa1_1 < V2_csa1_1   and
+               V0_csa1_3 < V2_csa1_3   and
+               V0_usa1_1 < C2_usa1_1   and
+               V0_usa1_3 < C2_usa1_3   and
+               V0_csa1_1 < C2_csa1_1   and
+               V0_csa1_3 < C2_csa1_3   and
+               V3_usa1_1 < V2_usa1_1   and
+               V3_usa1_3 < V2_usa1_3   and
+               C0_usa1_1 <= C2_usa1_1   and
+               C0_usa1_3 <= C2_usa1_3   and
+               C0_csa1_1 <= C2_csa1_1   and
+               C0_csa1_3 <= C2_csa1_3   and
+               V0_usa1_1 <= V2_usa1_1   and
+               V0_usa1_3 <= V2_usa1_3   and
+               V0_csa1_1 <= V2_csa1_1   and
+               V0_csa1_3 <= V2_csa1_3   and
+               V0_usa1_1 <= C2_usa1_1   and
+               V0_usa1_3 <= C2_usa1_3   and
+               V0_csa1_1 <= C2_csa1_1   and
+               V0_csa1_3 <= C2_csa1_3   and
+               V3_usa1_1 <= V2_usa1_1   and
+               V3_usa1_3 <= V2_usa1_3   and
+               C2_usa1_1 <= C2_usa1_1   and
+               C2_usa1_3 <= C2_usa1_3   and
+               C2_csa1_1 <= C2_csa1_1   and
+               C2_csa1_3 <= C2_csa1_3   and
+               V2_usa1_1 <= V2_usa1_1   and
+               V2_usa1_3 <= V2_usa1_3   and
+               V2_csa1_1 <= V2_csa1_1   and
+               V2_csa1_3 <= V2_csa1_3   and
+               V2_usa1_1 <= C2_usa1_1   and
+               V2_usa1_3 <= C2_usa1_3   and
+               V2_csa1_1 <= C2_csa1_1   and
+               V2_csa1_3 <= C2_csa1_3   )
+      report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd
new file mode 100644
index 0000000..4d43b28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd
@@ -0,0 +1,252 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2013.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02013ent IS
+END c07s02b02x00p10n01i02013ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02013arch OF c07s02b02x00p10n01i02013ent IS
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - for unconstrained types
+--           other composite type declarations are in package "COMPOSITE"
+--
+    CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
+    CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
+
+    CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+--
+--          Composite VARIABLE declarations
+--
+    VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
+    VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
+    VARIABLE V0_csa1_1 : t_csa1_1 ;
+    VARIABLE V0_csa1_3 : t_csa1_3 ;
+
+    VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+    VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
+    VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
+--
+--          Arrays of the same type, element values, different length
+--
+    VARIABLE V3_usa1_1 : t_usa1_1 ( 1  TO  7  ) ;
+    VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
+--
+    CONSTANT msg1 : STRING := "ERROR: greater than operator failure: ";
+    CONSTANT msg2 : STRING := "ERROR: greater than or equal operator failure: ";
+  BEGIN
+--
+--          Check greater than operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 > C0_usa1_1 REPORT msg1 & "C2>C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 > C0_usa1_3 REPORT msg1 & "C2>C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 > C0_csa1_1 REPORT msg1 & "C2>C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 > C0_csa1_3 REPORT msg1 & "C2>C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - VARIABLES
+--
+    ASSERT V2_usa1_1 > V0_usa1_1 REPORT msg1 & "V2>V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > V0_usa1_3 REPORT msg1 & "V2>V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 > V0_csa1_1 REPORT msg1 & "V2>V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 > V0_csa1_3 REPORT msg1 & "V2>V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 > C0_usa1_1 REPORT msg1 & "V2>C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > C0_usa1_3 REPORT msg1 & "V2>C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 > C0_csa1_1 REPORT msg1 & "V2>C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 > C0_csa1_3 REPORT msg1 & "V2>C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - same type, element values : diff array length
+--
+    ASSERT V2_usa1_1 > V3_usa1_1 REPORT msg1 & "V2>V3_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > V3_usa1_3 REPORT msg1 & "V2>V3_usa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 >= C0_usa1_1 REPORT msg2 & "C2>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 >= C0_usa1_3 REPORT msg2 & "C2>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 >= C0_csa1_1 REPORT msg2 & "C2>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 >= C0_csa1_3 REPORT msg2 & "C2>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES
+--
+    ASSERT V2_usa1_1 >= V0_usa1_1 REPORT msg2 & "V2>=V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= V0_usa1_3 REPORT msg2 & "V2>=V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 >= V0_csa1_1 REPORT msg2 & "V2>=V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 >= V0_csa1_3 REPORT msg2 & "V2>=V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 >= C0_usa1_1 REPORT msg2 & "V2>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= C0_usa1_3 REPORT msg2 & "V2>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 >= C0_csa1_1 REPORT msg2 & "V2>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 >= C0_csa1_3 REPORT msg2 & "V2>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - same type, element values : diff array length
+--
+    ASSERT V2_usa1_1 >= V3_usa1_1 REPORT msg2 & "V2>=V3_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= V3_usa1_3 REPORT msg2 & "V2>=V3_usa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C0_usa1_1 >= C0_usa1_1 REPORT msg2 & "C0>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 >= C0_usa1_3 REPORT msg2 & "C0>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 >= C0_csa1_1 REPORT msg2 & "C0>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 >= C0_csa1_3 REPORT msg2 & "C0>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES
+--
+    ASSERT V0_usa1_1 >= V0_usa1_1 REPORT msg2 & "V0>=V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 >= V0_usa1_3 REPORT msg2 & "V0>=V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 >= V0_csa1_1 REPORT msg2 & "V0>=V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 >= V0_csa1_3 REPORT msg2 & "V0>=V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 >= C0_usa1_1 REPORT msg2 & "V0>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 >= C0_usa1_3 REPORT msg2 & "V0>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 >= C0_csa1_1 REPORT msg2 & "V0>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 >= C0_csa1_3 REPORT msg2 & "V0>=C0_csa1_3" SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   C2_usa1_1 > C0_usa1_1   and
+                  C2_usa1_3 > C0_usa1_3   and
+                  C2_csa1_1 > C0_csa1_1   and
+                  C2_csa1_3 > C0_csa1_3   and
+                  V2_usa1_1 > V0_usa1_1   and
+                  V2_usa1_3 > V0_usa1_3   and
+                  V2_csa1_1 > V0_csa1_1   and
+                  V2_csa1_3 > V0_csa1_3   and
+                  V2_usa1_1 > C0_usa1_1   and
+                  V2_usa1_3 > C0_usa1_3   and
+                  V2_csa1_1 > C0_csa1_1   and
+                  V2_csa1_3 > C0_csa1_3   and
+                  V2_usa1_1 > V3_usa1_1   and
+                  V2_usa1_3 > V3_usa1_3   and
+                  C2_usa1_1 >= C0_usa1_1   and
+                  C2_usa1_3 >= C0_usa1_3   and
+                  C2_csa1_1 >= C0_csa1_1   and
+                  C2_csa1_3 >= C0_csa1_3   and
+                  V2_usa1_1 >= V0_usa1_1   and
+                  V2_usa1_3 >= V0_usa1_3   and
+                  V2_csa1_1 >= V0_csa1_1   and
+                  V2_csa1_3 >= V0_csa1_3   and
+                  V2_usa1_1 >= C0_usa1_1   and
+                  V2_usa1_3 >= C0_usa1_3   and
+                  V2_csa1_1 >= C0_csa1_1   and   
+                  V2_csa1_3 >= C0_csa1_3   and
+                  V2_usa1_1 >= V3_usa1_1   and
+                  V2_usa1_3 >= V3_usa1_3   and
+                  C0_usa1_1 >= C0_usa1_1   and
+                  C0_usa1_3 >= C0_usa1_3   and
+                  C0_csa1_1 >= C0_csa1_1   and
+                  C0_csa1_1 >= C0_csa1_1   and
+                  V0_usa1_1 >= V0_usa1_1   and
+                  V0_usa1_3 >= V0_usa1_3   and
+                  V0_csa1_1 >= V0_csa1_1   and
+                  V0_csa1_3 >= V0_csa1_3   and
+                  V0_usa1_1 >= C0_usa1_1   and
+                  V0_usa1_3 >= C0_usa1_3   and
+                  V0_csa1_1 >= C0_csa1_1   and
+                  V0_csa1_3 >= C0_csa1_3   )
+      report "***PASSED TEST: c07s02b02x00p10n01i02013" 
+      severity NOTE;
+    assert (   C2_usa1_1 > C0_usa1_1   and
+               C2_usa1_3 > C0_usa1_3   and
+               C2_csa1_1 > C0_csa1_1   and
+               C2_csa1_3 > C0_csa1_3   and
+               V2_usa1_1 > V0_usa1_1   and
+               V2_usa1_3 > V0_usa1_3   and
+               V2_csa1_1 > V0_csa1_1   and
+               V2_csa1_3 > V0_csa1_3   and
+               V2_usa1_1 > C0_usa1_1   and
+               V2_usa1_3 > C0_usa1_3   and
+               V2_csa1_1 > C0_csa1_1   and
+               V2_csa1_3 > C0_csa1_3   and
+               V2_usa1_1 > V3_usa1_1   and
+               V2_usa1_3 > V3_usa1_3   and
+               C2_usa1_1 >= C0_usa1_1   and
+               C2_usa1_3 >= C0_usa1_3   and
+               C2_csa1_1 >= C0_csa1_1   and
+               C2_csa1_3 >= C0_csa1_3   and
+               V2_usa1_1 >= V0_usa1_1   and
+               V2_usa1_3 >= V0_usa1_3   and
+               V2_csa1_1 >= V0_csa1_1   and
+               V2_csa1_3 >= V0_csa1_3   and
+               V2_usa1_1 >= C0_usa1_1   and
+               V2_usa1_3 >= C0_usa1_3   and
+               V2_csa1_1 >= C0_csa1_1   and   
+               V2_csa1_3 >= C0_csa1_3   and
+               V2_usa1_1 >= V3_usa1_1   and
+               V2_usa1_3 >= V3_usa1_3   and
+               C0_usa1_1 >= C0_usa1_1   and
+               C0_usa1_3 >= C0_usa1_3   and
+               C0_csa1_1 >= C0_csa1_1   and
+               C0_csa1_1 >= C0_csa1_1   and
+               V0_usa1_1 >= V0_usa1_1   and
+               V0_usa1_3 >= V0_usa1_3   and
+               V0_csa1_1 >= V0_csa1_1   and
+               V0_csa1_3 >= V0_csa1_3   and
+               V0_usa1_1 >= C0_usa1_1   and
+               V0_usa1_3 >= C0_usa1_3   and
+               V0_csa1_1 >= C0_csa1_1   and
+               V0_csa1_3 >= C0_csa1_3   )
+      report "***FAILED TEST: c07s02b02x00p10n01i02013 - Ordering operators >, >= for composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02013arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd
new file mode 100644
index 0000000..38de4b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p11n02i02014ent IS
+END c07s02b02x00p11n02i02014ent;
+
+ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
+  signal S1 : BIT_VECTOR(0 downto 7);
+  signal S2 : BIT_VECTOR(0 to 7) := "10101010"; 
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if (S1 < S2) then
+      k := 5;
+    end if;
+    wait for 1 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p11n02i02014"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p11n02i02014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd
new file mode 100644
index 0000000..0d2f943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p11n02i02015ent IS
+END c07s02b02x00p11n02i02015ent;
+
+ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable array_1 : array_three := (6,5,4,3,2,1);
+    variable array_2 : array_three := (6,5,4,4,3,2);
+    variable k       : integer;
+  BEGIN
+    if array_1 < array_2 then  -- No_failure_here
+      k := 5;
+    end if;
+    wait for 5 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p11n02i02015"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p11n02i02015arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd
new file mode 100644
index 0000000..95fa31c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2016.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p16n02i02016ent IS
+END c07s02b02x00p16n02i02016ent;
+
+ARCHITECTURE c07s02b02x00p16n02i02016arch OF c07s02b02x00p16n02i02016ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable array_1 : array_three := (6,5,4,3,2,1);
+    variable array_2 : array_three := (6,5,4,1,2,3);
+    variable k : integer := 0;
+  BEGIN
+    if array_1 > array_2 then
+      k := 5;
+    end if;
+    wait for 5 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p16n02i02016"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p16n02i02016 - The relations > (greater than) and >= (greater than or equal) are defined to be the complements of the <= and < operators respectively for the same two operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p16n02i02016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd
new file mode 100644
index 0000000..f9a4051
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2017.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02017ent IS
+END c07s02b04x00p01n01i02017ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02017arch OF c07s02b04x00p01n01i02017ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := k + 5 + 7;
+    assert NOT(k=12)
+      report "***PASSED TEST: c07s02b04x00p01n01i02017"
+      severity NOTE;
+    assert ( k=12 )
+      report "***FAILED TEST: c07s02b04x00p01n01i02017 - The adding operator + has its conventional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd
new file mode 100644
index 0000000..3778b21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2021.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02021ent IS
+END c07s02b04x00p01n01i02021ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02021arch OF c07s02b04x00p01n01i02021ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable w : real := 3.0 + 2.0;   -- No_failure_here
+                                          -- w should be 5.0
+  BEGIN
+    assert NOT(w=5.0) 
+      report "***PASSED TEST: c07s02b04x00p01n01i02021" 
+      severity NOTE;
+    assert (w=5.0) 
+      report "***FAILED TEST: c07s02b04x00p01n01i02021 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02021arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd
new file mode 100644
index 0000000..fd9e937
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2022.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02022ent IS
+END c07s02b04x00p01n01i02022ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02022arch OF c07s02b04x00p01n01i02022ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable w : real := 3.0 - 2.0;   -- No_failure_here
+                                          -- w should be 1.0
+  BEGIN
+    assert NOT(w=1.0) 
+      report "***PASSED TEST: c07s02b04x00p01n01i02022"
+      severity NOTE;
+    assert (w=1.0) 
+      report "***FAILED TEST: c07s02b04x00p01n01i02022 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd
new file mode 100644
index 0000000..137255d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p07n01i00203ent IS
+END c03s01b00x00p07n01i00203ent;
+
+ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    loop1:
+    for J in 1 downto 30 loop
+      k := k + J;
+    end loop LOOP1;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c03s01b00x00p07n01i00203"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p07n01i00203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd
new file mode 100644
index 0000000..0c15890
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc204.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p07n02i00204ent IS
+END c03s01b00x00p07n02i00204ent;
+
+ARCHITECTURE c03s01b00x00p07n02i00204arch OF c03s01b00x00p07n02i00204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for I in 5 downto 50 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c03s01b00x00p07n02i00204"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c03s01b00x00p07n02i00204 - In the case of L downto R, if L < R then the range is a null range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p07n02i00204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd
new file mode 100644
index 0000000..792c812
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc205.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p08n01i00205ent IS
+END c03s01b00x00p08n01i00205ent;
+
+ARCHITECTURE c03s01b00x00p08n01i00205arch OF c03s01b00x00p08n01i00205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k:bit;
+  BEGIN
+    k := bit'leftof('1');
+    assert NOT( k='0' )
+      report "***PASSED TEST: c03s01b00x00p08n01i00205"      severity NOTE;
+    assert ( k='0' )
+      report "***FAILED TEST: c03s01b00x00p08n01i00205 - Left of the value testing failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p08n01i00205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd
new file mode 100644
index 0000000..421f834
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc206.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p08n01i00206ent IS
+  type i is range 3 downto 1;
+END c03s01b00x00p08n01i00206ent;
+
+ARCHITECTURE c03s01b00x00p08n01i00206arch OF c03s01b00x00p08n01i00206ent IS
+  constant r:i:=2;
+BEGIN
+  TESTING: PROCESS
+    variable m:i;
+  BEGIN
+    m := i'leftof(r);
+    assert NOT( m=3 ) 
+      report "***PASSED TEST: c03s01b00x00p08n01i00206"
+      severity NOTE;
+    assert ( m=3 ) 
+      report "***FAILED TEST: c03s01b00x00p08n01i00206 - Left of the value testing failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p08n01i00206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd
new file mode 100644
index 0000000..1451f8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02061ent IS
+END c07s02b04x00p01n02i02061ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
+  signal S1 : Integer;
+  signal S2 : Integer;
+  signal S3 : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+    variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
+  BEGIN
+    S1 <= V1 + V2;
+    wait for 1 ns;
+    assert NOT(S1 = 20) 
+      report "***PASSED TEST: c07s02b04x00p01n02i02061" 
+      severity NOTE;
+    assert (S1 = 20) 
+      report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd
new file mode 100644
index 0000000..e2c53fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2062.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02062ent IS
+END c07s02b04x00p01n02i02062ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02062arch OF c07s02b04x00p01n02i02062ent IS
+  signal S2 : Integer;
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+  BEGIN
+    S2 <= V1 - V2;
+    wait for 1 ns;
+    assert NOT(S2 = 0) 
+      report "***PASSED TEST: c07s02b04x00p01n02i02062"
+      severity NOTE;
+    assert (S2 = 0) 
+      report "***FAILED TEST: c07s02b04x00p01n02i02062 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd
new file mode 100644
index 0000000..5b18f04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2063.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02063ent IS
+END c07s02b04x00p01n02i02063ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02063arch OF c07s02b04x00p01n02i02063ent IS
+  signal S1 : Integer;
+  signal S2 : Integer;
+  signal S3 : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+    variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
+  BEGIN
+    S3 <= V3&V4;
+    wait for 1 ns;
+    assert NOT(S3 = "01010101") 
+      report "***PASSED TEST: c07s02b04x00p01n02i02063" 
+      severity NOTE;
+    assert (S3 = "01010101") 
+      report "***FAILED TEST: c07s02b04x00p01n02i02063 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd
new file mode 100644
index 0000000..d5abd4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd
@@ -0,0 +1,169 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2077.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02077ent IS
+END c07s02b04x00p01n02i02077ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02077arch OF c07s02b04x00p01n02i02077ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    constant AA : bit_vector (1 to 32) := x"0000ffff";
+    variable B : bit_vector (32 downto 1);
+    variable C : bit_vector (15 downto 0);
+    variable D, DD : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+    alias FF : bit_vector (47 downto 0) is F;
+    variable Q, R : bit;
+  BEGIN
+
+    A := x"ffffffff";
+    B := x"00000000";
+    C := x"ffff";
+    D := x"0000";
+    E := x"ffffffffffff";
+    FF := x"000000000000";
+    Q := '1';
+    R := '0';
+
+    assert NOT(   ( C & Q = b"11111111111111111")   and
+                  ( C & R = b"11111111111111110")   and
+                  ( D & Q = b"00000000000000001")   and
+                  ( D & R = b"00000000000000000")   and
+                  ( Q & C = b"11111111111111111")   and
+                  ( R & C = b"01111111111111111")   and
+                  ( Q & D = b"10000000000000000")   and
+                  ( R & D = b"00000000000000000")   and
+                  ( A & Q = Q & A)   and
+                  ( B & R = R & B)   and
+                  ( A & R = C & (C & R))   and
+                  ( R & A = (R & C) & C)   and
+                  ( R & R & R & R  & C = x"0ffff")   and
+                  ( C & R & R & R & R = x"ffff0")      and
+                  ( E & Q = Q & E)   and
+                  ( F & Q = not (E & R))   and
+                  ( A & A = x"ffffffffffffffff")   and
+                  ( A & B = x"ffffffff00000000")   and
+                  ( A & C = x"ffffffffffff")   and
+                  ( A & D = x"ffffffff0000")   and
+                  ( A & E = x"ffffffffffffffffffff")   and
+                  ( A & F = x"ffffffff000000000000")   and
+                  ( B & A = x"00000000ffffffff")   and
+                  ( B & B = x"0000000000000000")   and
+                  ( B & C = x"00000000ffff")   and
+                  ( B & D = x"000000000000")   and
+                  ( B & E = x"00000000ffffffffffff")   and
+                  ( B & F = x"00000000000000000000")   and
+                  ( C & A = x"ffffffffffff")   and
+                  ( C & B = x"ffff00000000")   and
+                  ( C & C = x"ffffffff")      and
+                  ( C & D = x"ffff0000")      and
+                  ( C & E = x"ffffffffffffffff")   and
+                  ( C & F = x"ffff000000000000")   and
+                  ( D & A = x"0000ffffffff")   and
+                  ( D & B = x"000000000000")   and
+                  ( D & C = x"0000ffff")      and
+                  ( D & D = x"00000000")      and
+                  ( D & E = x"0000ffffffffffff")   and
+                  ( D & F = x"0000000000000000")   and
+                  ( E & A = x"ffffffffffffffffffff")   and
+                  ( E & B = x"ffffffffffff00000000")   and
+                  ( E & C = x"ffffffffffffffff")      and
+                  ( E & D = x"ffffffffffff0000")      and
+                  ( E & E = x"ffffffffffffffffffffffff")   and
+                  ( E & F = x"ffffffffffff000000000000")   and
+                  ( F & A = x"000000000000ffffffff")   and
+                  ( F & B = x"00000000000000000000")   and
+                  ( F & C = x"000000000000ffff")      and
+                  ( F & D = x"0000000000000000")      and
+                  ( F & E = x"000000000000ffffffffffff")   and
+                  ( F & F = x"000000000000000000000000")   )    
+      report "***PASSED TEST: c07s02b04x00p01n02i02077" 
+      severity NOTE;
+    assert (   ( C & Q = b"11111111111111111")   and
+               ( C & R = b"11111111111111110")   and
+               ( D & Q = b"00000000000000001")   and
+               ( D & R = b"00000000000000000")   and
+               ( Q & C = b"11111111111111111")   and
+               ( R & C = b"01111111111111111")   and
+               ( Q & D = b"10000000000000000")   and
+               ( R & D = b"00000000000000000")   and
+               ( A & Q = Q & A)   and
+               ( B & R = R & B)   and
+               ( A & R = C & (C & R))   and
+               ( R & A = (R & C) & C)   and
+               ( R & R & R & R  & C = x"0ffff")   and
+               ( C & R & R & R & R = x"ffff0")      and
+               ( E & Q = Q & E)   and
+               ( F & Q = not (E & R))   and
+               ( A & A = x"ffffffffffffffff")   and
+               ( A & B = x"ffffffff00000000")   and
+               ( A & C = x"ffffffffffff")   and
+               ( A & D = x"ffffffff0000")   and
+               ( A & E = x"ffffffffffffffffffff")   and
+               ( A & F = x"ffffffff000000000000")   and
+               ( B & A = x"00000000ffffffff")   and
+               ( B & B = x"0000000000000000")   and
+               ( B & C = x"00000000ffff")   and
+               ( B & D = x"000000000000")   and
+               ( B & E = x"00000000ffffffffffff")   and
+               ( B & F = x"00000000000000000000")   and
+               ( C & A = x"ffffffffffff")   and
+               ( C & B = x"ffff00000000")   and
+               ( C & C = x"ffffffff")      and
+               ( C & D = x"ffff0000")      and
+               ( C & E = x"ffffffffffffffff")   and
+               ( C & F = x"ffff000000000000")   and
+               ( D & A = x"0000ffffffff")   and
+               ( D & B = x"000000000000")   and
+               ( D & C = x"0000ffff")      and
+               ( D & D = x"00000000")      and
+               ( D & E = x"0000ffffffffffff")   and
+               ( D & F = x"0000000000000000")   and
+               ( E & A = x"ffffffffffffffffffff")   and
+               ( E & B = x"ffffffffffff00000000")   and
+               ( E & C = x"ffffffffffffffff")      and
+               ( E & D = x"ffffffffffff0000")      and
+               ( E & E = x"ffffffffffffffffffffffff")   and
+               ( E & F = x"ffffffffffff000000000000")   and
+               ( F & A = x"000000000000ffffffff")   and
+               ( F & B = x"00000000000000000000")   and
+               ( F & C = x"000000000000ffff")      and
+               ( F & D = x"0000000000000000")      and
+               ( F & E = x"000000000000ffffffffffff")   and
+               ( F & F = x"000000000000000000000000")   )    
+      report "***FAILED TEST: c07s02b04x00p01n02i02077 - The operation of operator & test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd
new file mode 100644
index 0000000..466ec4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2078.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02078ent IS
+END c07s02b04x00p20n01i02078ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02078arch OF c07s02b04x00p20n01i02078ent IS
+
+  procedure CheckConcat(
+    result       : STRING;
+    reference    : STRING;
+    left, right    : INTEGER
+    ) is
+    variable match : BOOLEAN;
+  begin
+    if result'LENGTH /= reference'LENGTH then
+      assert FALSE report "FAIL: length does not match";
+    elsif result'LEFT /= left then
+      assert FALSE report "FAIL: 'LEFT is wrong";
+    elsif result'RIGHT /= right then
+      assert FALSE report "FAIL: 'RIGHT is wrong";
+    elsif result /= reference then
+      assert FALSE report "FAIL: value is wrong";
+    else
+      assert result = reference report "FAIL: value is wrong";
+    end if;
+    assert NOT(   result'LENGTH = reference'LENGTH   and
+                  result'LEFT = left         and
+                  result'RIGHT = right         and
+                  result = reference         )
+      report "***PASSED TEST: c07s02b04x00p20n01i02078"
+      severity NOTE;
+    assert (   result'LENGTH = reference'LENGTH   and
+               result'LEFT = left         and
+               result'RIGHT = right         and
+               result = reference         )
+      report "***FAILED TEST: c07s02b04x00p20n01i02078 - Concatenation of string in function call test failed."
+      severity ERROR;
+  end;
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    CheckConcat("1" & "2", "12", 1, 2);
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd
new file mode 100644
index 0000000..54f4648
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2079.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02079ent IS
+END c07s02b04x00p20n01i02079ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02079arch OF c07s02b04x00p20n01i02079ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (positive range <>) of integer;
+    -- No_failure_here
+    constant a : array_type (1 to 3) := (1, 2, 3);
+    constant b : array_type (1 to 5) := (1, 2, 3, 4, 5);
+    constant x : array_type := a & b;
+  BEGIN
+    assert NOT(x=(1,2,3,1,2,3,4,5))
+      report "***PASSED TEST: c07s02b04x00p20n01i02079"
+      severity NOTE;
+    assert (x=(1,2,3,1,2,3,4,5))
+      report "***FAILED TEST: c07s02b04x00p20n01i02079 - The result of the concatenation of two one-dimensional arrays is a one-dimensional array whose length is the sum of the lengths of its operands, and whose elements consist of the elements of the left operand (in left to right order) followed by the elements of the right operand (in left to right order)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd
new file mode 100644
index 0000000..360dc89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc208.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00208ent IS
+END c03s01b00x00p09n01i00208ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00208arch OF c03s01b00x00p09n01i00208ent IS
+  type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
+  subtype weekend is integer range 5 to 6;
+BEGIN
+  TESTING: PROCESS
+    variable k : weekend := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00208" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00208 - Constraints for the subtype declaration must match the base type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd
new file mode 100644
index 0000000..122941e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2080.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02080ent IS
+END c07s02b04x00p20n01i02080ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02080arch OF c07s02b04x00p20n01i02080ent IS
+  TYPE real_vector is array (INTEGER range <>) of REAL;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : real_vector (1 to 10) ;
+    VARIABLE slice_1 : real_vector (1 to 4)  := (1.0,2.0,3.0,4.0);
+    VARIABLE slice_2 : real_vector (-2 to 4) :=
+      (5.0,6.0,7.0,8.0,9.0,10.0,11.0);
+  BEGIN
+
+    target (2 to 8):= slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target(2 to 8) = (1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***PASSED TEST: c07s02b04x00p20n01i02080"
+      severity NOTE;
+    assert (target(2 to 8) = (1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***FAILED TEST: c07s02b04x00p20n01i02080 - One dimensional array of REAL type concatenation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd
new file mode 100644
index 0000000..d76d8c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2081.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02081ent IS
+END c07s02b04x00p20n01i02081ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02081arch OF c07s02b04x00p20n01i02081ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : string (1 to 10) ;
+    VARIABLE slice_1 : string (1 to 10) := "0123456789";
+    VARIABLE slice_2 : string (1 to 10) := "abcdefghji";
+  BEGIN
+
+    target (2 to 8 ):= slice_1 ( 1 to 3 ) & slice_2 ( 4 to 7 );
+
+    assert NOT(target(2 to 8) = "012defg") 
+      report "***PASSED TEST: c07s02b04x00p20n01i02081"
+      severity NOTE;
+    assert (target(2 to 8) = "012defg") 
+      report "***FAILED TEST: c07s02b04x00p20n01i02081 - One dimensional array of STRING type concatenation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd
new file mode 100644
index 0000000..a2d4d90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02082ent IS
+END c07s02b04x00p20n01i02082ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
+  TYPE real_vector is array (INTEGER range <>) of REAL;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : real_vector (1 to 7) ;
+    VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
+    VARIABLE slice_2 : real_vector (-2 to 4) :=
+      (5.0,6.0,7.0,8.0,9.0,10.0,11.0);
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***PASSED TEST: c07s02b04x00p20n01i02082"
+      severity NOTE;
+    assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd
new file mode 100644
index 0000000..a9ee963
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2083.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02083ent IS
+END c07s02b04x00p20n01i02083ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02083arch OF c07s02b04x00p20n01i02083ent IS
+  TYPE int_vector is array (INTEGER range <>) of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : int_vector (1 to 7) ;
+    VARIABLE slice_1 : int_vector (1 to 4) := (1,2,3,4);
+    VARIABLE slice_2 : int_vector (-2 to 4) := (5,6,7,8,9,10,11);
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target=(1,2,3,6,7,8,9))
+      report "***PASSED TEST: c07s02b04x00p20n01i02083"
+      severity NOTE;
+    assert (target=(1,2,3,6,7,8,9))
+      report "***FAILED TEST: c07s02b04x00p20n01i02083 - One dimensional array of INTEGER type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd
new file mode 100644
index 0000000..6e40233
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2084.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02084ent IS
+END c07s02b04x00p20n01i02084ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02084arch OF c07s02b04x00p20n01i02084ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : string (1 to 7) ;
+    VARIABLE slice_1 : string (1 to 10) := "0123456789";
+    VARIABLE slice_2 : string (1 to 10) := "abcdefghji";
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( 4 to 7 );
+
+    assert NOT(target="012defg")
+      report "***PASSED TEST: c07s02b04x00p20n01i02084"
+      severity NOTE;
+    assert (target="012defg")
+      report "***FAILED TEST: c07s02b04x00p20n01i02084 - One dimensional array of STRING type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd
new file mode 100644
index 0000000..e689b8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2085.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02085ent IS
+END c07s02b04x00p20n01i02085ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02085arch OF c07s02b04x00p20n01i02085ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+  SUBTYPE     boolean_8_dwn     is boolean_v (4 downto -3);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : boolean_4_up := (true, true, false, false);
+    variable l_operand : boolean_4_dwn:= (false, false, true, true);
+    variable result    : boolean_8_dwn;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+    assert ( result (0)  = true )
+      report  "result (0) /= true" severity FAILURE;
+    assert ( result (-3)  = false )
+      report  "result (-3) /= false" severity FAILURE;
+
+    assert NOT((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02085"
+      severity NOTE;
+    assert ((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02085 - Concatenated array is descending and that the left bound is that of the first operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd
new file mode 100644
index 0000000..4d789e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2086.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02086ent IS
+END c07s02b04x00p20n01i02086ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02086arch OF c07s02b04x00p20n01i02086ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_4_null  is boolean_v (4 to 3);
+  SUBTYPE     boolean_8_up     is boolean_v (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_null ;
+    variable r_operand : boolean_4_up   := (false, false, true, true);
+    variable result    : boolean_4_up;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (1)  = false )
+      report  "result (1) /= false" severity FAILURE;
+    assert ( result (4)  = true )
+      report  "result (4) /= true" severity FAILURE;
+
+    assert NOT((result(1)=false) and (result=(false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02086"
+      severity NOTE;
+    assert ((result(1)=false) and (result=(false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02086 - The left bound of the concatenated array is that of the second operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd
new file mode 100644
index 0000000..14d62b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2087.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02087ent IS
+END c07s02b04x00p20n01i02087ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02087arch OF c07s02b04x00p20n01i02087ent IS
+
+  TYPE        boolean_v is array    (integer range <>) of boolean;
+  SUBTYPE     boolean_4 is boolean_v    (1 to 4);
+  SUBTYPE     boolean_8 is boolean_v    (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_8;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02087"
+      severity NOTE;
+    assert ((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02087 - Concatenation of two BOOLEAN arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd
new file mode 100644
index 0000000..e3893c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2088.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02088ent IS
+END c07s02b04x00p20n01i02088ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02088arch OF c07s02b04x00p20n01i02088ent IS
+
+  TYPE     boolean_v    is array    (integer range <>) of boolean;
+  SUBTYPE     boolean_4    is boolean_v    (1 to 4);
+  SUBTYPE     boolean_null    is boolean_v    (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_4;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false,true,false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02088"
+      severity NOTE;
+    assert ((result = (true,false,true,false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02088 - Concatenation of null and BOOLEAN arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd
new file mode 100644
index 0000000..19b89ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2089.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02089ent IS
+END c07s02b04x00p20n01i02089ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02089arch OF c07s02b04x00p20n01i02089ent IS
+
+  TYPE     bit_v       is array (integer range <>) of bit;
+  SUBTYPE     bit_4       is bit_v (1 to 4);
+  SUBTYPE     bit_null    is bit_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_4;
+    variable l_operand : bit_4    := ('1','0','1','0');
+    variable r_operand : bit_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('1','0','1','0')) and (result(1) = '1'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02089"
+      severity NOTE;
+    assert ((result = ('1','0','1','0')) and (result(1) = '1'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02089 - Concatenation of null and BIT array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd
new file mode 100644
index 0000000..26b0354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc209.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00209ent IS
+END c03s01b00x00p09n01i00209ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00209arch OF c03s01b00x00p09n01i00209ent IS
+  type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
+  constant x: CLSI := Jasmine;
+  constant y: CLSI := Saurin;
+  subtype People is CLSI range y downto x; 
+BEGIN
+  TESTING: PROCESS
+    variable k : People;
+  BEGIN
+    k := Jim;
+    assert NOT(k=Jim) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00209" 
+      severity NOTE;
+    assert (k=Jim) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00209 - Constraints for the subtype declaration must match the base type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00209arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd
new file mode 100644
index 0000000..ac46403
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2090.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02090ent IS
+END c07s02b04x00p20n01i02090ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02090arch OF c07s02b04x00p20n01i02090ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_8 is boolean_v (1 to 8);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_4;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+    alias    l_alias   : boolean_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : boolean_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT((result = (false,true,true,true)) and (result(1) = false))
+      report "***PASSED TEST: c07s02b04x00p20n01i02090"
+      severity NOTE;
+    assert ((result = (false,true,true,true)) and (result(1) = false))
+      report "***FAILED TEST: c07s02b04x00p20n01i02090 - Concatenation of two BOOLEAN aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd
new file mode 100644
index 0000000..f6b002a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2091.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02091ent IS
+END c07s02b04x00p20n01i02091ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02091arch OF c07s02b04x00p20n01i02091ent IS
+
+  TYPE     bit_v is array (integer range <>) of bit;
+  SUBTYPE     bit_8 is bit_v (1 to 8);
+  SUBTYPE     bit_4 is bit_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_4;
+    variable l_operand : bit_4 := ('1','0','1','0');
+    variable r_operand : bit_4 := ('0','0','1','1');
+    alias    l_alias   : bit_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : bit_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT((result = ('0','1','1','1')) and (result(1) = '0'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02091"
+      severity NOTE;
+    assert ((result = ('0','1','1','1')) and (result(1) = '0'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02091 - Concatenation of two BOOLEAITses failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd
new file mode 100644
index 0000000..189e802
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02092ent IS
+END c07s02b04x00p20n01i02092ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_8_up     is boolean_v (1 to 8);
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_up := (true, true, false, false);
+    variable r_operand : boolean_4_dwn:= (false, false, true, true); 
+    variable result    : boolean_8_up;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (5)  = false )
+      report  "result (5) /= false" severity FAILURE;
+    assert ( result (8)  = true )
+      report  "result (8) /= true" severity FAILURE;
+
+    assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02092"
+      severity NOTE;
+    assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd
new file mode 100644
index 0000000..0f7d461
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2093.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02093ent IS
+END c07s02b04x00p20n01i02093ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02093arch OF c07s02b04x00p20n01i02093ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+  SUBTYPE     boolean_4_null  is boolean_v (4 downto 5);
+  SUBTYPE     boolean_8_dwn     is boolean_v (8 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_null ;
+    variable r_operand : boolean_4_dwn  := (false, false, true, true);
+    variable result    : boolean_4_dwn;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+
+    assert NOT((result(4)=false) and (result=(false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02093"
+      severity NOTE;
+    assert ((result(4)=false) and (result=(false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02093 - The left bound of the concatenated array is that of the second operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02093arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd
new file mode 100644
index 0000000..981c61c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2094.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02094ent IS
+END c07s02b04x00p20n01i02094ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02094arch OF c07s02b04x00p20n01i02094ent IS
+
+  TYPE  boolean_v is array (integer range <>) of boolean;
+  SUBTYPE boolean_4  is boolean_v (1 to 4);
+  SUBTYPE boolean_8  is boolean_v (1 to 8);
+
+  FUNCTION return_array RETURN boolean_4 is
+    constant l_operand : boolean_4 := (true,false,true,false);
+  begin
+    RETURN l_operand;
+  end return_array;
+
+BEGIN
+  l : block
+    generic ( info : boolean_8 );
+    generic map ( return_array & return_array );
+  begin
+    assert NOT(info = (true,false,true,false,true,false,true,false))
+      report "***PASSED TEST: c07s02b04x00p20n01i02094"
+      severity NOTE;
+    assert (info = (true,false,true,false,true,false,true,false))
+      report "***FAILED TEST: c07s02b04x00p20n01i02094 - Function array concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02094arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd
new file mode 100644
index 0000000..eeae6c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2095.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02095ent IS
+END c07s02b04x00p20n01i02095ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02095arch OF c07s02b04x00p20n01i02095ent IS
+
+BEGIN
+  l : block
+    generic ( info : string );
+    generic map ( "VHDL" & " Technology" & " Group" );
+  begin
+    assert NOT(info = "VHDL Technology Group")
+      report "***PASSED TEST: c07s02b04x00p20n01i02095"
+      severity NOTE;
+    assert (info = "VHDL Technology Group")
+      report "***FAILED TEST: c07s02b04x00p20n01i02095 - Literal concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02095arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd
new file mode 100644
index 0000000..93aa9f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2096.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02096ent IS
+END c07s02b04x00p20n01i02096ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02096arch OF c07s02b04x00p20n01i02096ent IS
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+  constant l_operand : boolean_4 := (true,false,true,false);
+  constant r_operand : boolean_4 := (false,false,true,true);
+BEGIN
+  l : block
+    generic ( info : boolean_8 );
+    generic map ( l_operand & r_operand );
+  begin
+    assert NOT(info = (true,false,true,false,false,false,true,true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02096"
+      severity NOTE;
+    assert (info = (true,false,true,false,false,false,true,true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02096 - Constant concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02096arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd
new file mode 100644
index 0000000..5b75f0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2097.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02097ent IS
+END c07s02b04x00p20n01i02097ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02097arch OF c07s02b04x00p20n01i02097ent IS
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : boolean_8;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = (true,false,true,false,false,false,true,true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02097"
+      severity NOTE;
+    assert (result = (true,false,true,false,false,false,true,true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02097 - Variable concatenation did not succeed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02097arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd
new file mode 100644
index 0000000..b7eb7b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2098.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02098ent IS
+END c07s02b04x00p20n01i02098ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02098arch OF c07s02b04x00p20n01i02098ent IS
+
+  TYPE   boolean_v   is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+  signal result    : boolean_8;
+  signal l_operand : boolean_4 := (true,false,true,false);
+  signal r_operand : boolean_4 := (false,false,true,true);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    result <= l_operand & r_operand after 10 ns;
+    wait for 20 ns;
+    assert NOT(result = (true,false,true,false,false,false,true,true)) 
+      report "***PASSED TEST: c07s02b04x00p20n01i02098"
+      severity NOTE;
+    assert (result = (true,false,true,false,false,false,true,true)) 
+      report "***FAILED TEST: c07s02b04x00p20n01i02098- Signals concatenation did not succeed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd
new file mode 100644
index 0000000..31a25c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2099.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02099ent IS
+END c07s02b04x00p20n01i02099ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02099arch OF c07s02b04x00p20n01i02099ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_8 is record_v (1 to 8);
+  SUBTYPE     record_4 is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_4 := ( (12,34) , (56,78) , (12,34) , (56,78) );
+    variable r_operand : record_4 := ( (56,78) , (56,78) , (12,34) , (12,34) );
+    alias    l_alias   : record_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : record_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02099"
+      severity NOTE;
+    assert (result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02099 - Concatenation of two RECORD aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd
new file mode 100644
index 0000000..adcbda4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2100.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02100ent IS
+END c07s02b04x00p20n01i02100ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02100arch OF c07s02b04x00p20n01i02100ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_null    is record_v (1 to 0);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+    variable r_operand : record_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02100"
+      severity NOTE;
+    assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02100 - Concatenation of null and RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd
new file mode 100644
index 0000000..4aadc84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2101.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02101ent IS
+END c07s02b04x00p20n01i02101ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02101arch OF c07s02b04x00p20n01i02101ent IS
+
+  TYPE  simple_record is record
+                           data_1 : integer;
+                           data_2 : integer;
+                         end record;
+  TYPE     record_v    is array (integer range <>) of simple_record;
+  SUBTYPE     record_null    is record_v (1 to 0);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_null;
+    variable r_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02101"
+      severity NOTE;
+    assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02101 - Concatenation of null and RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd
new file mode 100644
index 0000000..7223c95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2102.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02102ent IS
+END c07s02b04x00p20n01i02102ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02102arch OF c07s02b04x00p20n01i02102ent IS
+
+  TYPE  simple_record is record
+                           data_1 : integer;
+                           data_2 : integer;
+                         end record;
+  TYPE     record_v    is array (integer range <>) of simple_record;
+  SUBTYPE     record_8    is record_v (1 to 8);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_8;
+    variable l_operand : record_4 := ( (12,34) , (56,78) , (12,34) , (56,78) );
+    variable r_operand : record_4 := ( (56,78) , (56,78) , (12,34) , (12,34) );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ((12,34),(56,78),(12,34),(56,78),(56,78),(56,78),(12,34),(12,34)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02102"
+      severity NOTE;
+    assert (result = ((12,34),(56,78),(12,34),(56,78),(56,78),(56,78),(12,34),(12,34)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02102 - Concatenation of two RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd
new file mode 100644
index 0000000..0195e22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2103.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02103ent IS
+END c07s02b04x00p20n01i02103ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02103arch OF c07s02b04x00p20n01i02103ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_8 is positive_v (1 to 8);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
+    alias    l_alias   : positive_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : positive_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( 89 , 1 , 1 , 1 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02103"
+      severity NOTE;
+    assert (result = ( 89 , 1 , 1 , 1 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02103 - Concatenation of two RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd
new file mode 100644
index 0000000..751ba25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2104.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02104ent IS
+END c07s02b04x00p20n01i02104ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02104arch OF c07s02b04x00p20n01i02104ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_8    is positive_v (1 to 8);
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_8;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02104"
+      severity NOTE;
+    assert (result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02104 - Concatenation of two POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd
new file mode 100644
index 0000000..d8dae27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2105.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02105ent IS
+END c07s02b04x00p20n01i02105ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02105arch OF c07s02b04x00p20n01i02105ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_null;
+    variable r_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 1 , 89 , 1 , 89 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02105"
+      severity NOTE;
+    assert (result = ( 1 , 89 , 1 , 89 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02105 - Concatenation of null and POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02105arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd
new file mode 100644
index 0000000..5d17705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2106.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02106ent IS
+END c07s02b04x00p20n01i02106ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02106arch OF c07s02b04x00p20n01i02106ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_8 is natural_v (1 to 8);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_4 := ( 23 , 23 , 0 , 0 );
+    alias    l_alias   : natural_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : natural_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( 23, 0, 0, 0 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02106"
+      severity NOTE;
+    assert (result = ( 23, 0, 0, 0 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02106 - Concatenation of two NATURAL alias failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02106arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd
new file mode 100644
index 0000000..5562356
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2107.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02107ent IS
+END c07s02b04x00p20n01i02107ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02107arch OF c07s02b04x00p20n01i02107ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_4    is natural_v (1 to 4);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02107"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02107 - Concatenation of null and NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02107arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd
new file mode 100644
index 0000000..c3d1718
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2108.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02108ent IS
+END c07s02b04x00p20n01i02108ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02108arch OF c07s02b04x00p20n01i02108ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_4    is natural_v (1 to 4);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_null;
+    variable r_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02108"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02108 - Concatenation of null and NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02108arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd
new file mode 100644
index 0000000..0bd6f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2109.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02109ent IS
+END c07s02b04x00p20n01i02109ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02109arch OF c07s02b04x00p20n01i02109ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_8 is natural_v (1 to 8);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_8;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_4 := ( 23 , 23 , 0 , 0 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 , 23 , 23 , 0 , 0 )) 
+      report "***PASSED TEST: c07s02b04x00p20n01i02109"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 , 23 , 23 , 0 , 0 )) 
+      report "***FAILED TEST: c07s02b04x00p20n01i02109 - Concatenation of two NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd
new file mode 100644
index 0000000..382896c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc211.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00211ent IS
+END c03s01b00x00p09n01i00211ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00211arch OF c03s01b00x00p09n01i00211ent IS
+  type ascending_range is range 0 to 10 ;
+  type descending_range is range 10 downto 0 ;
+  subtype ascending_subrange is descending_range range 2 to 5 ;
+  subtype descending_subrange is ascending_range range 5 downto 2 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2)) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00211" 
+      severity NOTE;
+    assert ((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2)) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00211 - The type of expression is not the same as the base type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00211arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd
new file mode 100644
index 0000000..595e334
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2110.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02110ent IS
+END c07s02b04x00p20n01i02110ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02110arch OF c07s02b04x00p20n01i02110ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_8 is time_v (1 to 8);
+  SUBTYPE     time_4 is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_4 := ( 23 ns , 23 ns , 78 ns , 78 ns );
+    alias    l_alias   : time_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : time_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ( 23 ns, 78 ns, 78 ns, 78 ns )) and (result(1) = 23 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02110"
+      severity NOTE;
+    assert ((result = ( 23 ns, 78 ns, 78 ns, 78 ns )) and (result(1) = 23 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02110 - Concatenation of two TIME aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd
new file mode 100644
index 0000000..1413e7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02111ent IS
+END c07s02b04x00p20n01i02111ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_null    is time_v (1 to 0);
+  SUBTYPE     time_4       is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02111"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd
new file mode 100644
index 0000000..431983e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2112.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02112ent IS
+END c07s02b04x00p20n01i02112ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02112arch OF c07s02b04x00p20n01i02112ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_null    is time_v (1 to 0);
+  SUBTYPE     time_4       is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_null;
+    variable r_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02112"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02112 - Concatenation of null and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02112arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd
new file mode 100644
index 0000000..ca5c3dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2113.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02113ent IS
+END c07s02b04x00p20n01i02113ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02113arch OF c07s02b04x00p20n01i02113ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_4       is time_v (1 to 4);
+  SUBTYPE     time_8       is time_v (1 to 8);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_8;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_4 := ( 23 ns , 23 ns , 78 ns , 78 ns );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns, 23 ns, 23 ns, 78 ns, 78 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02113"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns, 23 ns, 23 ns, 78 ns, 78 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02113 - Concatenation of two TIME arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02113arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd
new file mode 100644
index 0000000..3987029
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02114ent IS
+END c07s02b04x00p20n01i02114ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_8 is real_v (1 to 8);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_4;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
+    alias    l_alias   : real_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : real_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
+      report "***PASSED TEST:c07s02b04x00p20n01i02114"
+      severity NOTE;
+    assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
+      report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02114arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd
new file mode 100644
index 0000000..ddd9a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2115.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02115ent IS
+END c07s02b04x00p20n01i02115ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02115arch OF c07s02b04x00p20n01i02115ent IS
+
+  TYPE     real_v       is array (integer range <>) of real;
+  SUBTYPE     real_4       is real_v (1 to 4);
+  SUBTYPE     real_null    is real_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_4;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (12.345, -67.890,12.345, -67.890)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p20n01i02115"
+      severity NOTE;
+    assert ((result = (12.345, -67.890,12.345, -67.890)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p20n01i02115 - Concatenation of null and REAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02115arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd
new file mode 100644
index 0000000..0017fd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02116ent IS
+END c07s02b04x00p20n01i02116ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_8 is real_v (1 to 8);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_8;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p20n01i02116"
+      severity NOTE;
+    assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02116arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd
new file mode 100644
index 0000000..db929b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2117.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02117ent IS
+END c07s02b04x00p20n01i02117ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02117arch OF c07s02b04x00p20n01i02117ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_8 is integer_v (1 to 8);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_4 := (789,789,123,123);
+    alias    l_alias   : integer_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : integer_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = (789,123,123,123)) and (result(1) = 789))
+      report "***PASSED TEST: c07s02b04x00p20n01i02117"
+      severity NOTE;
+    assert ((result = (789,123,123,123)) and (result(1) = 789))
+      report "***FAILED TEST: c07s02b04x00p20n01i02117 - Concatenation of two INTEGER aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd
new file mode 100644
index 0000000..e12baec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2118.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02118ent IS
+END c07s02b04x00p20n01i02118ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02118arch OF c07s02b04x00p20n01i02118ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4    is integer_v (1 to 4);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02118"
+      severity NOTE;
+    assert ((result = (123,789,123,789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02118 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02118arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd
new file mode 100644
index 0000000..7f38400
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2119.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02119ent IS
+END c07s02b04x00p20n01i02119ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02119arch OF c07s02b04x00p20n01i02119ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4    is integer_v (1 to 4);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_null;
+    variable r_operand : integer_4 := (123,789,123,789);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02119"
+      severity NOTE;
+    assert ((result = (123,789,123,789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02119 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd
new file mode 100644
index 0000000..db7b4fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2120.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02120ent IS
+END c07s02b04x00p20n01i02120ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02120arch OF c07s02b04x00p20n01i02120ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_8 is integer_v (1 to 8);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_8;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_4 := (789,789,123,123);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789,789,789,123,123)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02120"
+      severity NOTE;
+    assert ((result = (123,789,123,789,789,789,123,123)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02120 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02120arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd
new file mode 100644
index 0000000..1481f44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2121.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02121ent IS
+END c07s02b04x00p20n01i02121ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02121arch OF c07s02b04x00p20n01i02121ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_8 is character_v (1 to 8);
+  SUBTYPE     character_4 is character_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : character_4;
+    variable l_operand : character_4 := ('A','z','A','z');
+    variable r_operand : character_4 := ('z','z','A','A');
+    alias    l_alias   : character_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : character_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ('z','A','A','A')) and (result(1)='z'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02121"
+      severity NOTE;
+    assert ((result = ('z','A','A','A')) and (result(1)='z'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02121 - Concatenation of two CHARACTER aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02121arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd
new file mode 100644
index 0000000..78ed21c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2122.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02122ent IS
+END c07s02b04x00p20n01i02122ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02122arch OF c07s02b04x00p20n01i02122ent IS
+
+  TYPE        severity_level_v    is array (integer range <>) of severity_level;
+  SUBTYPE     severity_level_4    is severity_level_v (1 to 4);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_null;
+    variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p20n01i02122"
+      severity NOTE;
+    assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p20n01i02122 - Concatenation of null and SEVERITY_LEVEL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02122arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd
new file mode 100644
index 0000000..4f68425
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2123.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02123ent IS
+END c07s02b04x00p20n01i02123ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02123arch OF c07s02b04x00p20n01i02123ent IS
+
+  TYPE        severity_level_v    is array (integer range <>) of severity_level;
+  SUBTYPE     severity_level_4    is severity_level_v (1 to 4);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+    variable r_operand : severity_level_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p20n01i02123"
+      severity NOTE;
+    assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p20n01i02123 - Concatenation of null and SEVERITY_LEVEL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02123arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd
new file mode 100644
index 0000000..4ea3db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2124.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02124ent IS
+END c07s02b04x00p20n01i02124ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02124arch OF c07s02b04x00p20n01i02124ent IS
+
+  procedure CheckConcat(
+    result       : STRING;
+    reference    : STRING;
+    left, right    : INTEGER
+    ) is
+    variable match : BOOLEAN;
+  begin
+    if result'LENGTH /= reference'LENGTH then
+      assert FALSE report "FAIL: length does not match";
+    elsif result'LEFT /= left then
+      assert FALSE report "FAIL: 'LEFT is wrong";
+    elsif result'RIGHT /= right then
+      assert FALSE report "FAIL: 'RIGHT is wrong";
+    elsif result /= reference then
+      assert FALSE report "FAIL: value is wrong";
+    else
+      assert result = reference report "FAIL: value is wrong";
+    end if;
+    assert NOT(   result'LENGTH = reference'LENGTH   and
+                  result'LEFT = left         and
+                  result'RIGHT = right         and
+                  result = reference         )
+      report "***PASSED TEST: c07s02b04x00p20n01i02124"
+      severity NOTE;
+    assert (   result'LENGTH = reference'LENGTH   and
+               result'LEFT = left         and
+               result'RIGHT = right         and
+               result = reference         )
+      report "***FAILED TEST: c07s02b04x00p20n01i02124 - Concatenation of string in function call test failed."
+      severity ERROR;
+  end;
+
+BEGIN
+  TESTING : PROCESS
+    subtype String3to3 is STRING(3 to 3);
+  BEGIN
+    CheckConcat(String3to3'("9") & "A", "9A", 3, 4);
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02124arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd
new file mode 100644
index 0000000..b436717
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2125.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02125ent IS
+END c07s02b04x00p20n01i02125ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02125arch OF c07s02b04x00p20n01i02125ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean_4    := (true, false, true, false);
+    variable r_operand : boolean    :=  true;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, false, true, false, true)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02125"
+      severity NOTE;
+    assert ((result = (true, false, true, false, true)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02125 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02125arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd
new file mode 100644
index 0000000..0c15786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02126ent IS
+END c07s02b04x00p20n01i02126ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
+
+  TYPE    integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4     is integer_v (1 to 4);
+  SUBTYPE     integer_8     is integer_v (1 to 8);
+  SUBTYPE     integer_8_dwn     is integer_v (8 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : integer_4 := ( 5,6,7,8 );
+    variable l_operand1: integer := 1;
+    variable l_operand2: integer := 2;
+    variable l_operand3: integer := 3;
+    variable l_operand4: integer := 4;
+    variable result    : integer_8;
+    variable result_dwn: integer_8_dwn;
+  BEGIN
+    result_dwn := l_operand1 &
+                  l_operand2 &
+                  l_operand3 &
+                  l_operand4 &
+                  l_operand2 &
+                  l_operand3 &
+                  l_operand2 &
+                  l_operand3;
+    
+    assert (result_dwn = (1,2,3,4,2,3,2,3))
+      report "integer implicit array concatenation failed"
+      severity FAILURE;
+
+    assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
+      report "***PASSED TEST: c07s02b04x00p20n01i02126"
+      severity NOTE;
+    assert (result_dwn = (1,2,3,4,2,3,2,3))
+      report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02126arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd
new file mode 100644
index 0000000..c9000b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2127.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02127ent IS
+END c07s02b04x00p20n01i02127ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02127arch OF c07s02b04x00p20n01i02127ent IS
+
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_1    is boolean_v (1 to 1);
+  SUBTYPE     boolean_null    is boolean_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_1;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = true )
+      report "***PASSED TEST: c07s02b04x00p20n01i02127"
+      severity NOTE;
+    assert ( result(1) = true )
+      report "***FAILED TEST: c07s02b04x00p20n01i02127 - Concatenation of null and BOOLEAN element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02127arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd
new file mode 100644
index 0000000..cc3d39b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2128.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02128ent IS
+END c07s02b04x00p20n01i02128ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02128arch OF c07s02b04x00p20n01i02128ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_4    := (true, false, true, false);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02128"
+      severity NOTE;
+    assert ((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02128 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02128arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd
new file mode 100644
index 0000000..232433c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2129.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02129ent IS
+END c07s02b04x00p20n01i02129ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02129arch OF c07s02b04x00p20n01i02129ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_4    := (true, false, true, false);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02129"
+      severity NOTE;
+    assert ((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02129 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02129arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd
new file mode 100644
index 0000000..bf34caf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc213.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p03n01i00213ent IS
+END c03s01b01x00p03n01i00213ent;
+
+ARCHITECTURE c03s01b01x00p03n01i00213arch OF c03s01b01x00p03n01i00213ent IS
+  type pqr is (foo, swath, a, 'a');  -- No_failure_here
+  signal dude1 : pqr := foo;
+  signal dude2 : pqr;      
+  signal dude3 : pqr := a;
+  signal dude4 : pqr := 'a';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(dude1 = foo and dude2 = foo and dude3 = a and dude4 = 'a')
+      report "***PASSED TEST: c03s01b01x00p03n01i00213"
+      severity NOTE;
+    assert (dude1 = foo and dude2 = foo and dude3 = a and dude4 = 'a' )
+      report "***FAILED TEST: c03s01b01x00p03n01i00213 - When an enumeration type is being declared, that both identifiers and literals may be contained in the list of elements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p03n01i00213arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd
new file mode 100644
index 0000000..0db9fe3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2130.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02130ent IS
+END c07s02b04x00p21n01i02130ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02130arch OF c07s02b04x00p21n01i02130ent IS
+
+  TYPE     character_v    is array (integer range <>) of character;
+  SUBTYPE     character_1    is character_v (1 to 1);
+  SUBTYPE     character_null    is character_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_1;
+    variable l_operand : character_null;
+    variable r_operand : character := 'A';
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 'A' )
+      report "***PASSED TEST: c07s02b04x00p21n01i02130"
+      severity NOTE;
+    assert ( result(1) = 'A' )
+      report "***FAILED TEST: c07s02b04x00p21n01i02130 - Concatenation of null array and character element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02130arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd
new file mode 100644
index 0000000..9f9c272
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2131.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02131ent IS
+END c07s02b04x00p20n01i02131ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02131arch OF c07s02b04x00p20n01i02131ent IS
+
+  TYPE    integer_v  is array (integer range <>) of integer;
+  SUBTYPE     integer_4  is integer_v (1 to 4);
+  SUBTYPE     integer_8  is integer_v (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : integer_4 := ( 5,6,7,8 );
+    variable l_operand1: integer := 1;
+    variable l_operand2: integer := 2;
+    variable l_operand3: integer := 3;
+    variable l_operand4: integer := 4;
+    variable result    : integer_8;
+  BEGIN
+    result := l_operand1 &
+              l_operand2 &
+              l_operand3 &
+              l_operand4 &
+              r_operand;
+    assert (result = (1,2,3,4,5,6,7,8))
+      report "integer implicit array concatenation failed"
+      severity FAILURE;
+    assert NOT(result = (1,2,3,4,5,6,7,8))
+      report "***PASSED TEST: c07s02b04x00p20n01i02131"
+      severity NOTE;
+    assert (result = (1,2,3,4,5,6,7,8))
+      report "***FAILED TEST: c07s02b04x00p20n01i02131 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02131arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd
new file mode 100644
index 0000000..9b8ee5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2132.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02132ent IS
+END c07s02b04x00p21n01i02132ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02132arch OF c07s02b04x00p21n01i02132ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_5 is record_v (1 to 5);
+  SUBTYPE     record_4 is record_v (1 to 4);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_5;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : record_4 := ((12,34), (56,78), (12,34), (56,78));
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
+      report "***PASSED TEST: c07s02b04x00p21n01i02132"
+      severity NOTE;
+    assert ( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
+      report "***FAILED TEST:c07s02b04x00p21n01i02132 - Concatenation of element and RECORD array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02132arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd
new file mode 100644
index 0000000..c267ac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2133.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02133ent IS
+END c07s02b04x00p21n01i02133ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02133arch OF c07s02b04x00p21n01i02133ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_5 is record_v (1 to 5);
+  SUBTYPE     record_4 is record_v (1 to 4);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_5;
+    variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+    variable r_operand : simple_record :=  (12,34);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02133"
+      severity NOTE;
+    assert ( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02133 - Concatenation of element and RECORD array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02133arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd
new file mode 100644
index 0000000..c504b8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2134.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02134ent IS
+END c07s02b04x00p21n01i02134ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02134arch OF c07s02b04x00p21n01i02134ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE  record_null is record_v (1 to 0);
+  SUBTYPE  record_1    is record_v (1 to 1);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_1;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : record_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = (12,34) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02134"
+      severity NOTE;
+    assert ( result(1) = (12,34) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02134 - Concatenation of null and RECORD element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02134arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd
new file mode 100644
index 0000000..0fe47c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2135.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02135ent IS
+END c07s02b04x00p21n01i02135ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02135arch OF c07s02b04x00p21n01i02135ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE  record_null is record_v (1 to 0);
+  SUBTYPE  record_1    is record_v (1 to 1);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_1;
+    variable l_operand : record_null;
+    variable r_operand : simple_record :=  (12,34);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = (12,34) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02135"
+      severity NOTE;
+    assert ( result(1) = (12,34) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02135 - Concatenation of null and RECORD element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02135arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd
new file mode 100644
index 0000000..f860e73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2136.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02136ent IS
+END c07s02b04x00p21n01i02136ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02136arch OF c07s02b04x00p21n01i02136ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_5 is positive_v (1 to 5);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_5;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive_4 := ( 1 ,  89 ,  1 ,  89  );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 1 ,  1 ,  89 ,  1 ,  89 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02136"
+      severity NOTE;
+    assert ( result = ( 1 ,  1 ,  89 ,  1 ,  89 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02136 - Concatenation of element and POSITIVE array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02136arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd
new file mode 100644
index 0000000..49f8c50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2137.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02137ent IS
+END c07s02b04x00p21n01i02137ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02137arch OF c07s02b04x00p21n01i02137ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_5 is positive_v (1 to 5);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_5;
+    variable l_operand : positive_4 := ( 12,  56,  12,  56 );
+    variable r_operand : positive    :=  12;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 12, 56, 12, 56, 12 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02137"
+      severity NOTE;
+    assert ( result = ( 12, 56, 12, 56, 12 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02137 - Concatenation of element and POSITIVE array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd
new file mode 100644
index 0000000..17dfe04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02138ent IS
+END c07s02b04x00p21n01i02138ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_1    is positive_v (1 to 1);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_1;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 1 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02138"
+      severity NOTE;
+    assert ( result(1) = 1 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd
new file mode 100644
index 0000000..382eb4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2139.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02139ent IS
+END c07s02b04x00p21n01i02139ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02139arch OF c07s02b04x00p21n01i02139ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_1    is positive_v (1 to 1);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_1;
+    variable l_operand : positive_null;
+    variable r_operand : positive :=  1 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 1 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02139"
+      severity NOTE;
+    assert ( result(1) = 1 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02139 - Concatenation of null and POSITIVE element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd
new file mode 100644
index 0000000..0b1b233
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2140.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02140ent IS
+END c07s02b04x00p21n01i02140ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02140arch OF c07s02b04x00p21n01i02140ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 1, 89, 1, 89 ) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02140"
+      severity NOTE;
+    assert ( result = ( 1, 89, 1, 89 ) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02140 - Concatenation of null and POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02140arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd
new file mode 100644
index 0000000..b18f6b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2141.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02141ent IS
+END c07s02b04x00p21n01i02141ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02141arch OF c07s02b04x00p21n01i02141ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_5 is natural_v (1 to 5);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_5;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural_4 := ( 0 ,  23 ,  0 ,  23  );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 0 ,  0 ,  23 ,  0 ,  23 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02141"
+      severity NOTE;
+    assert ( result = ( 0 ,  0 ,  23 ,  0 ,  23 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02141 - Concatenation of element and NATURAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02141arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd
new file mode 100644
index 0000000..967cd18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2142.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02142ent IS
+END c07s02b04x00p21n01i02142ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02142arch OF c07s02b04x00p21n01i02142ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_5 is natural_v (1 to 5);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_5;
+    variable l_operand : natural_4    := ( 12 ,  56 ,  12 ,  56  );
+    variable r_operand : natural    :=  12 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 12 ,  56 ,  12 ,  56 ,  12 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02142"
+      severity NOTE;
+    assert ( result = ( 12 ,  56 ,  12 ,  56 ,  12 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02142 - Concatenation of element and NATURAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02142arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd
new file mode 100644
index 0000000..79591fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2143.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02143ent IS
+END c07s02b04x00p21n01i02143ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02143arch OF c07s02b04x00p21n01i02143ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_1    is natural_v (1 to 1);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_1;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 0 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02143"
+      severity NOTE;
+    assert ( result(1) = 0 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02143 - Concatenation of null and NATURAL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02143arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd
new file mode 100644
index 0000000..d5b4927
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2144.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02144ent IS
+END c07s02b04x00p21n01i02144ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02144arch OF c07s02b04x00p21n01i02144ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_1    is natural_v (1 to 1);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_1;
+    variable l_operand : natural_null;
+    variable r_operand : natural := 0;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 0 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02144"
+      severity NOTE;
+    assert ( result(1) = 0 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02144 - Concatenation of null and NATURAL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02144arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd
new file mode 100644
index 0000000..e8c6477
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2145.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02145ent IS
+END c07s02b04x00p21n01i02145ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02145arch OF c07s02b04x00p21n01i02145ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_4 is time_v (1 to 4);
+  SUBTYPE     time_5 is time_v (1 to 5);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_5;
+    variable l_operand : time    :=  78 ns ;
+    variable r_operand : time_4    := ( 78 ns, 23 ns, 78 ns, 23 ns);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (78 ns, 78 ns, 23 ns, 78 ns, 23 ns)) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p21n01i02145"
+      severity NOTE;
+    assert ((result = (78 ns, 78 ns, 23 ns, 78 ns, 23 ns)) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p21n01i02145 - Concatenation of element and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02145arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd
new file mode 100644
index 0000000..bf914ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2146.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02146ent IS
+END c07s02b04x00p21n01i02146ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02146arch OF c07s02b04x00p21n01i02146ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_4 is time_v (1 to 4);
+  SUBTYPE     time_5 is time_v (1 to 5);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_5;
+    variable l_operand : time_4    := ( 12 ns,  56 ns,  12 ns,  56 ns );
+    variable r_operand : time    :=  12 ns;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12 ns,  56 ns,  12 ns,  56 ns,  12 ns)) and (result(1) = 12 ns))
+      report "***PASSED TEST: c07s02b04x00p21n01i02146"
+      severity NOTE;
+    assert ((result = (12 ns,  56 ns,  12 ns,  56 ns,  12 ns)) and (result(1) = 12 ns))
+      report "***FAILED TEST: c07s02b04x00p21n01i02146 - Concatenation of element and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02146arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd
new file mode 100644
index 0000000..c9f1c8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2147.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02147ent IS
+END c07s02b04x00p21n01i02147ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02147arch OF c07s02b04x00p21n01i02147ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_1       is time_v (1 to 1);
+  SUBTYPE     time_null    is time_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_1;
+    variable l_operand : time    :=  78 ns ;
+    variable r_operand : time_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 78 ns) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02147"
+      severity NOTE;
+    assert (result(1) = 78 ns) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02147 - Concatenation of null and TIME element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd
new file mode 100644
index 0000000..a387d65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2148.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02148ent IS
+END c07s02b04x00p21n01i02148ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02148arch OF c07s02b04x00p21n01i02148ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_1       is time_v (1 to 1);
+  SUBTYPE     time_null    is time_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_1;
+    variable l_operand : time_null;
+    variable r_operand : time :=  78 ns ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 78 ns) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02148"
+      severity NOTE;
+    assert (result(1) = 78 ns) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02148 - Concatenation of null and TIME element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02148arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd
new file mode 100644
index 0000000..56ed0a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2149.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02149ent IS
+END c07s02b04x00p21n01i02149ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02149arch OF c07s02b04x00p21n01i02149ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_5 is real_v (1 to 5);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_5;
+    variable l_operand : real    := 12.345;
+    variable r_operand : real_4    := (12.345, -67.890, 12.345, -67.890);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p21n01i02149"
+      severity NOTE;
+    assert ((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p21n01i02149 - Concatenation of element and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd
new file mode 100644
index 0000000..18994c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02150ent IS
+END c07s02b04x00p21n01i02150ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_5 is real_v (1 to 5);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_5;
+    variable l_operand : real_4    := ( 12.34,  56.78,  12.34,  56.78 );
+    variable r_operand : real    :=  12.34;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12.34,  56.78,  12.34,  56.78,  12.34)) and (result(1) = 12.34))
+      report "***PASSED TEST: c07s02b04x00p21n01i02150"
+      severity NOTE;
+    assert ((result = (12.34,  56.78,  12.34,  56.78,  12.34)) and (result(1) = 12.34))
+      report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02150arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd
new file mode 100644
index 0000000..38fc528
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2151.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02151ent IS
+END c07s02b04x00p21n01i02151ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02151arch OF c07s02b04x00p21n01i02151ent IS
+
+  TYPE     real_v       is array (integer range <>) of real;
+  SUBTYPE     real_1       is real_v (1 to 1);
+  SUBTYPE     real_null    is real_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_1;
+    variable l_operand : real_null;
+    variable r_operand : real := 12.345;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 12.345)
+      report "***PASSED TEST: c07s02b04x00p21n01i02151"
+      severity NOTE;
+    assert (result(1) = 12.345)
+      report "***FAILED TEST: c07s02b04x00p21n01i02151 - Concatenation of null and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02151arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd
new file mode 100644
index 0000000..6f575d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2152.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02152ent IS
+END c07s02b04x00p21n01i02152ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02152arch OF c07s02b04x00p21n01i02152ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_5 is integer_v (1 to 5);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_5;
+    variable l_operand : integer := 123;
+    variable r_operand : integer_4 := (123, 789, 123, 789 );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (123, 123, 789, 123, 789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p21n01i02152"
+      severity NOTE;
+    assert ((result = (123, 123, 789, 123, 789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p21n01i02152 - Concatenation of element and INTEGER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02152arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd
new file mode 100644
index 0000000..6e4ba35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2153.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02153ent IS
+END c07s02b04x00p21n01i02153ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02153arch OF c07s02b04x00p21n01i02153ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_5 is integer_v (1 to 5);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_5;
+    variable l_operand : integer_4    := (123, 789, 123, 789 );
+    variable r_operand : integer    := 123;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (123, 789, 123, 789, 123)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p21n01i02153"
+      severity NOTE;
+    assert ((result = (123, 789, 123, 789, 123)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p21n01i02153 - Concatenation of element and INTEGER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd
new file mode 100644
index 0000000..41f4915
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2154.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02154ent IS
+END c07s02b04x00p21n01i02154ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02154arch OF c07s02b04x00p21n01i02154ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_1    is integer_v (1 to 1);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_1;
+    variable l_operand : integer    := 123;
+    variable r_operand : integer_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=123)
+      report "***PASSED TEST: c07s02b04x00p21n01i02154"
+      severity NOTE;
+    assert (result(1)=123)
+      report "***FAILED TEST: c07s02b04x00p21n01i02154 - Concatenation of null and INTEGER element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd
new file mode 100644
index 0000000..2b2fed2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2155.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02155ent IS
+END c07s02b04x00p21n01i02155ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02155arch OF c07s02b04x00p21n01i02155ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_1    is integer_v (1 to 1);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_1;
+    variable l_operand : integer_null;
+    variable r_operand : integer := 123;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=123)
+      report "***PASSED TEST: c07s02b04x00p21n01i02155"
+      severity NOTE;
+    assert (result(1)=123)
+      report "***FAILED TEST: c07s02b04x00p21n01i02155 - Concatenation of null and INTEGER element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd
new file mode 100644
index 0000000..3eb69ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2156.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02156ent IS
+END c07s02b04x00p21n01i02156ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02156arch OF c07s02b04x00p21n01i02156ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_5 is character_v (1 to 5);
+  SUBTYPE     character_4 is character_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_5;
+    variable l_operand : character_4    := ('A', 'z', 'A', 'z' );
+    variable r_operand : character       := 'A';
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result=('A', 'z', 'A', 'z', 'A'))
+      report "***PASSED TEST: c07s02b04x00p21n01i02156"
+      severity NOTE;
+    assert (result=('A', 'z', 'A', 'z', 'A'))
+      report "***FAILED TEST: c07s02b04x00p21n01i02156 - Concatenation of CHARACTER element and CHARACTER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd
new file mode 100644
index 0000000..28cd93b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02157ent IS
+END c07s02b04x00p21n01i02157ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
+
+  TYPE     severity_level_v    is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_1    is severity_level_v (1 to 1);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_1;
+    variable l_operand : severity_level_null;
+    variable r_operand : severity_level :=  NOTE ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=NOTE)
+      report "***PASSED TEST: c07s02b04x00p21n01i02157"
+      severity NOTE;
+    assert (result(1)=NOTE)
+      report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd
new file mode 100644
index 0000000..08122e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02158ent IS
+END c07s02b04x00p21n01i02158ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
+
+  TYPE     severity_level_v    is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_1    is severity_level_v (1 to 1);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_1;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=NOTE)
+      report "***PASSED TEST: c07s02b04x00p21n01i02158"
+      severity NOTE;
+    assert (result(1)=NOTE)
+      report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd
new file mode 100644
index 0000000..1516218
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02159ent IS
+END c07s02b04x00p21n01i02159ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE  severity_level_5 is severity_level_v (1 to 5);
+  SUBTYPE  severity_level_4 is severity_level_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_5;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level_4 := ( NOTE ,  FAILURE ,  NOTE ,  FAILURE  );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p21n01i02159"
+      severity NOTE;
+    assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
new file mode 100644
index 0000000..be0ac22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2160.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02160ent IS
+END c07s02b04x00p22n01i02160ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02160arch OF c07s02b04x00p22n01i02160ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_2 is boolean_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_2;
+    variable l_operand : boolean := true;
+    variable r_operand : boolean := false;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p22n01i02160"
+      severity NOTE;
+    assert ((result = (true,false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p22n01i02160 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd
new file mode 100644
index 0000000..d08ca3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2161.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02161ent IS
+END c07s02b04x00p22n01i02161ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02161arch OF c07s02b04x00p22n01i02161ent IS
+
+  TYPE     bit_v is array (integer range <>) of bit;
+  SUBTYPE     bit_2 is bit_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_2;
+    variable l_operand : bit := '1';
+    variable r_operand : bit := '0';
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('1','0')) and (result(1) = '1'))
+      report "***PASSED TEST: c07s02b04x00p22n01i02161"
+      severity NOTE;
+    assert ((result = ('1','0')) and (result(1) = '1'))
+      report "***FAILED TEST: c07s02b04x00p22n01i02161 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02161arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd
new file mode 100644
index 0000000..0a04430
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2162.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02162ent IS
+END c07s02b04x00p22n01i02162ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02162arch OF c07s02b04x00p22n01i02162ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_2 is record_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_2;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : simple_record :=  (56,78) ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( (12,34), (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02162"
+      severity NOTE;
+    assert (result = ( (12,34), (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02162 - Concatenation of record element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd
new file mode 100644
index 0000000..59ad661
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2163.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02163ent IS
+END c07s02b04x00p22n01i02163ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02163arch OF c07s02b04x00p22n01i02163ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_2 is positive_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_2;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive :=  89 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 1, 89 )) 
+      report "***PASSED TEST: c07s02b04x00p22n01i02163"
+      severity NOTE;
+    assert (result = ( 1, 89 )) 
+      report "***FAILED TEST: c07s02b04x00p22n01i02163 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd
new file mode 100644
index 0000000..558940c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2164.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02164ent IS
+END c07s02b04x00p22n01i02164ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02164arch OF c07s02b04x00p22n01i02164ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_2 is natural_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_2;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural :=  23 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 0, 23 ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02164"
+      severity NOTE;
+    assert (result = ( 0, 23 ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02164 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd
new file mode 100644
index 0000000..cd12114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2165.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02165ent IS
+END c07s02b04x00p22n01i02165ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02165arch OF c07s02b04x00p22n01i02165ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_2 is time_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_2;
+    variable l_operand : time :=  78 ns ;
+    variable r_operand : time :=  23 ns ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 78 ns, 23 ns ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02165"
+      severity NOTE;
+    assert (result = ( 78 ns, 23 ns ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02165 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd
new file mode 100644
index 0000000..9c9d2a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02166ent IS
+END c07s02b04x00p22n01i02166ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_2 is real_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_2;
+    variable l_operand : real := 12.345;
+    variable r_operand : real :=  -67.890;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ( 12.345,  -67.890 )) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p22n01i02166"
+      severity NOTE;
+    assert ((result = ( 12.345,  -67.890 )) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd
new file mode 100644
index 0000000..97e648a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02167ent IS
+END c07s02b04x00p22n01i02167ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_2 is character_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_2;
+    variable l_operand : character := 'A';
+    variable r_operand : character := 'z';
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('A', 'z')) and (result(1)='A'))
+      report "***PASSED TEST: c07s02b04x00p22n01i02167"
+      severity NOTE;
+    assert ((result = ('A', 'z')) and (result(1)='A'))
+      report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd
new file mode 100644
index 0000000..8518523
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2168.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02168ent IS
+END c07s02b04x00p22n01i02168ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02168arch OF c07s02b04x00p22n01i02168ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_2 is severity_level_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_2;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level :=  FAILURE ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(( result = (NOTE,FAILURE)) and (result(1) = NOTE))
+      report "***PASSED TEST: c07s02b04x00p22n01i02168"
+      severity NOTE;
+    assert (( result = (NOTE,FAILURE)) and (result(1) = NOTE))
+      report "***FAILED TEST: c07s02b04x00p22n01i02168 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd
new file mode 100644
index 0000000..35f91ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2169.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02169ent IS
+END c07s02b04x00p22n01i02169ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02169arch OF c07s02b04x00p22n01i02169ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE  severity_level_8 is severity_level_v (1 to 8);
+  SUBTYPE  severity_level_4 is severity_level_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+    variable r_operand : severity_level_4 := ( FAILURE , FAILURE , NOTE , NOTE );
+    alias    l_alias   : severity_level_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : severity_level_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT(( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) =  FAILURE  ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02169"
+      severity NOTE;
+    assert (( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) =  FAILURE  ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02169 - Concatenation of two SEVERITY_LEVEL aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd
new file mode 100644
index 0000000..dac01fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd
@@ -0,0 +1,328 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc217.vhd,v 1.2 2005-03-21 17:33:22 dmartin Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n02i00217ent IS
+END c03s01b01x00p06n02i00217ent;
+
+ARCHITECTURE c03s01b01x00p06n02i00217arch OF c03s01b01x00p06n02i00217ent IS
+
+BEGIN
+   TESTING: PROCESS
+   BEGIN
+   assert NOT ((character'pos(NUL) =   0) and
+                    (character'pos(SOH) =   1) and
+                    (character'pos(STX) =   2) and
+                    (character'pos(ETX) =   3) and
+                    (character'pos(EOT) =   4) and
+                    (character'pos(ENQ) =   5) and
+                    (character'pos(ACK) =   6) and
+                    (character'pos(BEL) =   7) and
+                    (character'pos(BS ) =   8) and
+                    (character'pos(HT ) =   9) and
+                    (character'pos(LF ) =  10) and
+                    (character'pos(VT ) =  11) and
+                    (character'pos(FF ) =  12) and
+                    (character'pos(CR ) =  13) and
+                    (character'pos(SO ) =  14) and
+                    (character'pos(SI ) =  15) and
+                    (character'pos(DLE) =  16) and
+                    (character'pos(DC1) =  17) and
+                    (character'pos(DC2) =  18) and
+                    (character'pos(DC3) =  19) and
+                    (character'pos(DC4) =  20) and
+                    (character'pos(NAK) =  21) and
+                    (character'pos(SYN) =  22) and
+                    (character'pos(ETB) =  23) and
+                    (character'pos(CAN) =  24) and
+                    (character'pos(EM ) =  25) and
+                    (character'pos(SUB) =  26) and
+                    (character'pos(ESC) =  27) and
+                    (character'pos(FSP) =  28) and
+                    (character'pos(GSP) =  29) and
+                    (character'pos(RSP) =  30) and
+                    (character'pos(USP) =  31) and
+                    (character'pos(' ') =  32) and
+                    (character'pos('!') =  33) and
+                    (character'pos('"') =  34) and
+                    (character'pos('#') =  35) and
+                    (character'pos('$') =  36) and
+                    (character'pos('%') =  37) and
+                    (character'pos('&') =  38) and
+                    (character'pos(''') =  39) and
+                    (character'pos('(') =  40) and
+                    (character'pos(')') =  41) and
+                    (character'pos('*') =  42) and
+                    (character'pos('+') =  43) and
+                    (character'pos(',') =  44) and
+                    (character'pos('-') =  45) and
+                    (character'pos('.') =  46) and
+                    (character'pos('/') =  47) and
+                    (character'pos('0') =  48) and
+                    (character'pos('1') =  49) and
+                    (character'pos('2') =  50) and
+                    (character'pos('3') =  51) and
+                    (character'pos('4') =  52) and
+                    (character'pos('5') =  53) and
+                    (character'pos('6') =  54) and
+                    (character'pos('7') =  55) and
+                    (character'pos('8') =  56) and
+                    (character'pos('9') =  57) and
+                    (character'pos(':') =  58) and
+                    (character'pos(';') =  59) and
+                    (character'pos('<') =  60) and
+                    (character'pos('=') =  61) and
+                    (character'pos('>') =  62) and
+                    (character'pos('?') =  63) and
+          (character'pos('@') =  64) and
+                    (character'pos('A') =  65) and
+                    (character'pos('B') =  66) and
+                    (character'pos('C') =  67) and
+                    (character'pos('D') =  68) and
+                    (character'pos('E') =  69) and
+                    (character'pos('F') =  70) and
+                    (character'pos('G') =  71) and
+                    (character'pos('H') =  72) and
+                    (character'pos('I') =  73) and
+                    (character'pos('J') =  74) and
+                    (character'pos('K') =  75) and
+                    (character'pos('L') =  76) and
+                    (character'pos('M') =  77) and
+                    (character'pos('N') =  78) and
+                    (character'pos('O') =  79) and
+                    (character'pos('P') =  80) and
+                    (character'pos('Q') =  81) and
+                    (character'pos('R') =  82) and
+                    (character'pos('S') =  83) and
+                    (character'pos('T') =  84) and
+                    (character'pos('U') =  85) and
+                    (character'pos('V') =  86) and
+                    (character'pos('W') =  87) and
+                    (character'pos('X') =  88) and
+                    (character'pos('Y') =  89) and
+                    (character'pos('Z') =  90) and
+                    (character'pos('[') =  91) and
+                    (character'pos('\') =  92) and
+                    (character'pos(']') =  93) and
+                    (character'pos('^') =  94) and
+                    (character'pos('_') =  95) and
+                    (character'pos('`') =  96) and
+                    (character'pos('a') =  97) and
+                    (character'pos('b') =  98) and
+                    (character'pos('c') =  99) and
+                    (character'pos('d') = 100) and
+                    (character'pos('e') = 101) and
+                    (character'pos('f') = 102) and
+                    (character'pos('g') = 103) and
+                    (character'pos('h') = 104) and
+                    (character'pos('i') = 105) and
+                    (character'pos('j') = 106) and
+                    (character'pos('k') = 107) and
+                    (character'pos('l') = 108) and
+                    (character'pos('m') = 109) and
+                    (character'pos('n') = 110) and
+                    (character'pos('o') = 111) and
+                    (character'pos('p') = 112) and
+                    (character'pos('q') = 113) and
+                    (character'pos('r') = 114) and
+                    (character'pos('s') = 115) and
+                    (character'pos('t') = 116) and
+                    (character'pos('u') = 117) and
+                    (character'pos('v') = 118) and
+                    (character'pos('w') = 119) and
+                    (character'pos('x') = 120) and
+                    (character'pos('y') = 121) and
+                    (character'pos('z') = 122) and
+                    (character'pos('{') = 123) and
+                    (character'pos('|') = 124) and
+                    (character'pos('}') = 125) and
+                    (character'pos('~') = 126) and
+                    (character'pos(DEL) = 127) and
+          (character'pos(character'right) = 127) and 
+                    (bit'pos('0') = 0) and
+                    (bit'pos('1') = 1) and
+                    (bit'pos(bit'right) = 1) and
+                    (boolean'pos(false) = 0) and
+                    (boolean'pos(true)  = 1) and
+                    (boolean'pos(boolean'right) = 1) and
+                    (severity_level'pos(NOTE)    = 0) and
+                    (severity_level'pos(WARNING) = 1) and
+                    (severity_level'pos(ERROR)   = 2) and
+                    (severity_level'pos(FAILURE) = 3) and
+                    (severity_level'pos(severity_level'right)
+= 3))
+      report "***PASSED TEST: c03s01b01x00p06n02i00217"
+      severity NOTE;
+   assert (    (character'pos(NUL) =   0) and
+                    (character'pos(SOH) =   1) and
+                    (character'pos(STX) =   2) and
+                    (character'pos(ETX) =   3) and
+                    (character'pos(EOT) =   4) and
+                    (character'pos(ENQ) =   5) and
+                    (character'pos(ACK) =   6) and
+                    (character'pos(BEL) =   7) and
+                    (character'pos(BS ) =   8) and
+                    (character'pos(HT ) =   9) and
+                    (character'pos(LF ) =  10) and
+                    (character'pos(VT ) =  11) and
+                    (character'pos(FF ) =  12) and
+                    (character'pos(CR ) =  13) and
+                    (character'pos(SO ) =  14) and
+                    (character'pos(SI ) =  15) and
+                    (character'pos(DLE) =  16) and
+                    (character'pos(DC1) =  17) and
+                    (character'pos(DC2) =  18) and
+                    (character'pos(DC3) =  19) and
+                    (character'pos(DC4) =  20) and
+                    (character'pos(NAK) =  21) and
+                    (character'pos(SYN) =  22) and
+                    (character'pos(ETB) =  23) and
+                    (character'pos(CAN) =  24) and
+                    (character'pos(EM ) =  25) and
+                    (character'pos(SUB) =  26) and
+                    (character'pos(ESC) =  27) and
+                    (character'pos(FSP) =  28) and
+                    (character'pos(GSP) =  29) and
+                    (character'pos(RSP) =  30) and
+                    (character'pos(USP) =  31) and
+                    (character'pos(' ') =  32) and
+                    (character'pos('!') =  33) and
+                    (character'pos('"') =  34) and
+                    (character'pos('#') =  35) and
+                    (character'pos('$') =  36) and
+                    (character'pos('%') =  37) and
+                    (character'pos('&') =  38) and
+                    (character'pos(''') =  39) and
+                    (character'pos('(') =  40) and
+                    (character'pos(')') =  41) and
+                    (character'pos('*') =  42) and
+                    (character'pos('+') =  43) and
+                    (character'pos(',') =  44) and
+                    (character'pos('-') =  45) and
+                    (character'pos('.') =  46) and
+                    (character'pos('/') =  47) and
+                    (character'pos('0') =  48) and
+                    (character'pos('1') =  49) and
+                    (character'pos('2') =  50) and
+                    (character'pos('3') =  51) and
+                    (character'pos('4') =  52) and
+                    (character'pos('5') =  53) and
+                    (character'pos('6') =  54) and
+                    (character'pos('7') =  55) and
+          (character'pos('8') =  56) and
+                    (character'pos('9') =  57) and
+                    (character'pos(':') =  58) and
+                    (character'pos(';') =  59) and
+                    (character'pos('<') =  60) and
+                    (character'pos('=') =  61) and
+                    (character'pos('>') =  62) and
+                    (character'pos('?') =  63) and
+                    (character'pos('@') =  64) and
+                    (character'pos('A') =  65) and
+                    (character'pos('B') =  66) and
+                    (character'pos('C') =  67) and
+                    (character'pos('D') =  68) and
+                    (character'pos('E') =  69) and
+                    (character'pos('F') =  70) and
+                    (character'pos('G') =  71) and
+                    (character'pos('H') =  72) and
+                    (character'pos('I') =  73) and
+                    (character'pos('J') =  74) and
+                    (character'pos('K') =  75) and
+                    (character'pos('L') =  76) and
+                    (character'pos('M') =  77) and
+                    (character'pos('N') =  78) and
+                    (character'pos('O') =  79) and
+                    (character'pos('P') =  80) and
+                    (character'pos('Q') =  81) and
+                    (character'pos('R') =  82) and
+                    (character'pos('S') =  83) and
+                    (character'pos('T') =  84) and
+                    (character'pos('U') =  85) and
+                    (character'pos('V') =  86) and
+                    (character'pos('W') =  87) and
+                    (character'pos('X') =  88) and
+                    (character'pos('Y') =  89) and
+                    (character'pos('Z') =  90) and
+                    (character'pos('[') =  91) and
+                    (character'pos('\') =  92) and
+                    (character'pos(']') =  93) and
+                    (character'pos('^') =  94) and
+                    (character'pos('_') =  95) and
+                    (character'pos('`') =  96) and
+                    (character'pos('a') =  97) and
+                    (character'pos('b') =  98) and
+                    (character'pos('c') =  99) and
+                    (character'pos('d') = 100) and
+                    (character'pos('e') = 101) and
+                    (character'pos('f') = 102) and
+                    (character'pos('g') = 103) and
+                    (character'pos('h') = 104) and
+                    (character'pos('i') = 105) and
+                    (character'pos('j') = 106) and
+                    (character'pos('k') = 107) and
+                    (character'pos('l') = 108) and
+                    (character'pos('m') = 109) and
+                    (character'pos('n') = 110) and
+                    (character'pos('o') = 111) and
+                    (character'pos('p') = 112) and
+                    (character'pos('q') = 113) and
+                    (character'pos('r') = 114) and
+                    (character'pos('s') = 115) and
+                    (character'pos('t') = 116) and
+                    (character'pos('u') = 117) and
+                    (character'pos('v') = 118) and
+                    (character'pos('w') = 119) and
+          (character'pos('x') = 120) and
+                    (character'pos('y') = 121) and
+                    (character'pos('z') = 122) and
+                    (character'pos('{') = 123) and
+                    (character'pos('|') = 124) and
+                    (character'pos('}') = 125) and
+                    (character'pos('~') = 126) and
+                    (character'pos(DEL) = 127) and
+                    (character'pos(character'right) = 255) and  
+                    (bit'pos('0') = 0) and
+                    (bit'pos('1') = 1) and
+                    (bit'pos(bit'right) = 1) and
+                    (boolean'pos(false) = 0) and
+                    (boolean'pos(true)  = 1) and
+                    (boolean'pos(boolean'right) = 1) and
+                    (severity_level'pos(NOTE)    = 0) and
+                    (severity_level'pos(WARNING) = 1) and
+                    (severity_level'pos(ERROR)   = 2) and
+                    (severity_level'pos(FAILURE) = 3) and
+                    (severity_level'pos(severity_level'right)
+= 3))
+      report "***FAILED TEST: c03s01b01x00p06n02i00217 - The predefined order relations between enumeration values follow the order of corresponding position number."
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c03s01b01x00p06n02i00217arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd
new file mode 100644
index 0000000..d922d46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2172.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02172ent IS
+END c07s02b05x00p01n01i02172ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02172arch OF c07s02b05x00p01n01i02172ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: integer := + 10;
+  BEGIN
+    assert NOT(x1=10) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02172" 
+      severity NOTE;
+    assert (x1=10) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02172 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd
new file mode 100644
index 0000000..8f91207
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02173ent IS
+END c07s02b05x00p01n01i02173ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: integer := - 10;
+  BEGIN
+    assert NOT(x1=-10) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02173" 
+      severity NOTE;
+    assert (x1=-10) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd
new file mode 100644
index 0000000..3af500a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2174.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02174ent IS
+END c07s02b05x00p01n01i02174ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02174arch OF c07s02b05x00p01n01i02174ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: real := - 10.0;
+  BEGIN
+    assert NOT(x1=-10.0) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02174" 
+      severity NOTE;
+    assert (x1=-10.0) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02174 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd
new file mode 100644
index 0000000..93f27a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2175.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02175ent IS
+END c07s02b05x00p01n01i02175ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02175arch OF c07s02b05x00p01n01i02175ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: real := + 10.0;
+  BEGIN
+    assert NOT(x1=+10.0) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02175" 
+      severity NOTE;
+    assert (x1=+10.0) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02175 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd
new file mode 100644
index 0000000..c0d8655
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2176.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02176ent IS
+END c07s02b05x00p01n01i02176ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02176arch OF c07s02b05x00p01n01i02176ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5  p2;
+      end units;
+    constant a : phys := - p2;
+  BEGIN
+    assert NOT(a = - 10 p1)
+      report "***PASSED TEST: c07s02b05x00p01n01i02176" 
+      severity NOTE;
+    assert (a = - 10 p1)
+      report "***FAILED TEST: c07s02b05x00p01n01i02176 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd
new file mode 100644
index 0000000..2d15aba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2177.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02177ent IS
+END c07s02b05x00p01n01i02177ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02177arch OF c07s02b05x00p01n01i02177ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5  p2;
+      end units;
+    constant a : phys := + p2;
+  BEGIN
+    assert NOT(a =  10 p1)
+      report "***PASSED TEST: c07s02b05x00p01n01i02177"
+      severity NOTE;
+    assert (a =  10 p1)
+      report "***FAILED TEST: c07s02b05x00p01n01i02177 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd
new file mode 100644
index 0000000..6886309
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2178.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02178ent IS
+END c07s02b05x00p01n02i02178ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02178arch OF c07s02b05x00p01n02i02178ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := + m;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02178"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02178 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd
new file mode 100644
index 0000000..f4a00fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2179.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02179ent IS
+END c07s02b05x00p01n02i02179ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02179arch OF c07s02b05x00p01n02i02179ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := - m;
+    assert NOT( k = - 5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02179"
+      severity NOTE;
+    assert ( k = - 5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02179 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd
new file mode 100644
index 0000000..aa88f2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc218.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00218ent IS
+END c03s01b01x00p06n03i00218ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00218arch OF c03s01b01x00p06n03i00218ent IS
+  subtype BTRUE is BOOLEAN range TRUE to TRUE;
+  type ENUM1 is (ZERO, ONE, TWO, THREE);
+  type ENUM2 is (TRUE, FALSE);
+  type ENUM3 is ('1', '0');
+  type ENUM4 is ('Z', 'Y', 'X');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((ENUM1'POS(ZERO) = 0)
+               and (ENUM1'POS(ONE) = 1)
+               and (ENUM1'POS(TWO) = 2)
+               and (ENUM1'POS(THREE) = 3)
+               and (ENUM2'POS(TRUE) = 0)
+               and (ENUM2'POS(FALSE) = 1)
+               and (ENUM3'POS('1') = 0)
+               and (ENUM3'POS('0') = 1)
+               and (ENUM4'POS('Z') = 0)
+               and (ENUM4'POS('Y') = 1)
+               and (ENUM4'POS('X') = 2) )
+      report "***PASSED TEST: c03s01b01x00p06n03i00218"
+      severity NOTE;
+    assert ( (ENUM1'POS(ZERO) = 0)
+             and (ENUM1'POS(ONE) = 1)
+             and (ENUM1'POS(TWO) = 2)
+             and (ENUM1'POS(THREE) = 3)
+             and (ENUM2'POS(TRUE) = 0)
+             and (ENUM2'POS(FALSE) = 1)
+             and (ENUM3'POS('1') = 0)
+             and (ENUM3'POS('0') = 1)
+             and (ENUM4'POS('Z') = 0)
+             and (ENUM4'POS('Y') = 1)
+             and (ENUM4'POS('X') = 2))
+      report "***FAILED TEST: c03s01b01x00p06n03i00218 - The position value of the nth listed enumeration literal is n-1."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00218arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd
new file mode 100644
index 0000000..28f4ddf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02180ent IS
+END c07s02b05x00p01n02i02180ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := abs m;
+    assert NOT( k =  5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02180"
+      severity NOTE;
+    assert ( k =  5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd
new file mode 100644
index 0000000..f55fb91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2181.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02181ent IS
+END c07s02b05x00p01n02i02181ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02181arch OF c07s02b05x00p01n02i02181ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := abs (-m);
+    assert NOT( k =  5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02181"
+      severity NOTE;
+    assert ( k =  5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02181 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd
new file mode 100644
index 0000000..67349ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2182.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02182ent IS
+END c07s02b05x00p01n02i02182ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02182arch OF c07s02b05x00p01n02i02182ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := - m;
+    assert NOT( k =  - 5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02182"
+      severity NOTE;
+    assert ( k =  - 5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02182 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd
new file mode 100644
index 0000000..51150bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2183.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02183ent IS
+END c07s02b05x00p01n02i02183ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02183arch OF c07s02b05x00p01n02i02183ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := + m;
+    assert NOT( k =  5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02183"
+      severity NOTE;
+    assert ( k =  5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02183 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd
new file mode 100644
index 0000000..6157997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2184.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02184ent IS
+END c07s02b05x00p01n02i02184ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02184arch OF c07s02b05x00p01n02i02184ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := + m;
+    assert NOT( k =  5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02184"
+      severity NOTE;
+    assert ( k =  5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02184 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd
new file mode 100644
index 0000000..c3748ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2185.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02185ent IS
+END c07s02b05x00p01n02i02185ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02185arch OF c07s02b05x00p01n02i02185ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range -1000 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := - m;
+    assert NOT( k = - 5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02185"
+      severity NOTE;
+    assert ( k =  - 5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02185 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd
new file mode 100644
index 0000000..c6c1c2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2186.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02186ent IS
+END c07s02b05x00p01n02i02186ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02186arch OF c07s02b05x00p01n02i02186ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := abs m;
+    assert NOT( k = 5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02186"
+      severity NOTE;
+    assert ( k = 5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02186 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd
new file mode 100644
index 0000000..6e271ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2187.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02187ent IS
+END c07s02b05x00p01n01i02187ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02187arch OF c07s02b05x00p01n01i02187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV1   : INTEGER      := 0;
+    variable INTV2   : INTEGER      := 0;
+    variable TIMEV1  : TIME         := 1 ns;
+    variable TIMEV2  : TIME         := 1 ns;
+    variable REALV1  : REAL         := 0.0;
+    variable REALV2  : REAL         := 0.0;
+  BEGIN
+    -- Test negation of simple integers.
+    INTV1 := 14;
+    assert (-INTV1 = -14)
+      report "Negation of simple integers does not work.";
+    INTV2 := INTEGER'HIGH;
+    assert (-INTV2 = -INTEGER'HIGH)
+      report "Negation of simple integers does not work.";
+
+    -- Test identity of simple integers.
+    assert (+14 = 14)
+      report "Identity of simple integers does not work.";
+
+    -- Test negation of "TIME".
+    TIMEV1 := 1 ns;
+    assert (-TIMEV1 = -1 ns)
+      report "Negation of TIME values does not work.";
+    TIMEV2 := TIME'HIGH;
+    assert (-TIMEV2 = -TIME'HIGH)
+      report "Negation of TIME values does not work.";
+    
+    -- Test identify of "TIME".
+    assert (+14 ps = 14 ps)
+      report "Identity of TIME values does not work.";
+    
+    -- Test negation of simple floating point numbers.
+    REALV1 := 14.0;
+    assert (-REALV1 = -14.0)
+      report "Negation of simple integers does not work.";
+    REALV2 := REAL'HIGH;
+    assert (-REALV2 = -REAL'HIGH)
+      report "Negation of simple integers does not work.";
+    
+    -- Test identity of simple floating point numbers.
+    assert (+14.0 = 14.0)
+      report "Identity of simple integers does not work.";
+    wait for 5 fs;
+    assert NOT(   (-INTV1 = -14)         and
+                  (-INTV2 = -INTEGER'HIGH)   and
+                  (+14 = 14)         and
+                  (-TIMEV1 = -1 ns)      and
+                  (-TIMEV2 = -TIME'HIGH)      and
+                  (+14 ps = 14 ps)      and
+                  (-REALV1 = -14.0)      and
+                  (-REALV2 = -REAL'HIGH)      and
+                  (+14.0 = 14.0)         )
+      report "***PASSED TEST: c07s02b05x00p01n01i02187" 
+      severity NOTE;
+    assert (   (-INTV1 = -14)         and
+               (-INTV2 = -INTEGER'HIGH)   and
+               (+14 = 14)         and
+               (-TIMEV1 = -1 ns)      and
+               (-TIMEV2 = -TIME'HIGH)      and
+               (+14 ps = 14 ps)      and
+               (-REALV1 = -14.0)      and
+               (-REALV2 = -REAL'HIGH)      and
+               (+14.0 = 14.0)         )
+      report "***FAILED TEST: c07s02b05x00p01n01i02187 - Identity and nefation function did not work correctly for all numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd
new file mode 100644
index 0000000..0eb52bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00219ent IS
+  type e is (EMIN,ETYP,EMAX);
+END c03s01b01x00p06n03i00219ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable e1:integer;
+  BEGIN
+    e1 := e'pos(EMIN);
+    assert NOT(e1=0)
+      report "***PASSED TEST: c03s01b01x00p06n03i00219"
+      severity NOTE;
+    assert (e1=0)
+      report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00219arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd
new file mode 100644
index 0000000..4672d83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2199.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02199ent IS
+END c07s02b06x00p01n01i02199ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02199arch OF c07s02b06x00p01n01i02199ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable y : real := -9.0 * (-3.0); -- y should be 27.0
+  BEGIN
+    assert NOT(y=27.0)
+      report "***PASSED TEST: c07s02b06x00p01n01i02199"
+      severity NOTE;
+    assert ( y=27.0 )
+      report "***FAILED TEST: c07s02b06x00p01n01i02199 - The  operators * and / are predefined for any integer type and any floating point type and have their convertional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd
new file mode 100644
index 0000000..2a8bbc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00220ent IS
+  type e is (EMIN,ETYP,EMAX);
+END c03s01b01x00p06n03i00220ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(e'pos(ETYP) < e'pos(EMAX))
+      report "***PASSED TEST: c03s01b01x00p06n03i00220"
+      severity NOTE;
+    assert (e'pos(ETYP) < e'pos(EMAX))
+      report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00220arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd
new file mode 100644
index 0000000..7aa992c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2200.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02200ent IS
+END c07s02b06x00p01n01i02200ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02200arch OF c07s02b06x00p01n01i02200ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable z : real := -0.01 / (1.0); -- z should be -0.01
+  BEGIN
+    assert NOT(z=-0.01)
+      report "***PASSED TEST: c07s02b06x00p01n01i02200"
+      severity NOTE;
+    assert ( z=-0.01 )
+      report "***FAILED TEST: c07s02b06x00p01n01i02200 - The  operators * and / are predefined for any integer type and any floating point type and have their convertional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd
new file mode 100644
index 0000000..2d1b8f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2203.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02203ent IS
+END c07s02b06x00p01n01i02203ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02203arch OF c07s02b06x00p01n01i02203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : integer := 10 * 12;    -- a should be 120
+  BEGIN
+    assert NOT(a = 120) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02203" 
+      severity NOTE;
+    assert (a = 120) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02203 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd
new file mode 100644
index 0000000..f9e3f09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2204.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02204ent IS
+END c07s02b06x00p01n01i02204ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02204arch OF c07s02b06x00p01n01i02204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : integer := 10 / 2;   
+  BEGIN
+    assert NOT(a = 5) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02204" 
+      severity NOTE;
+    assert (a = 5) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02204 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd
new file mode 100644
index 0000000..841b6c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2205.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02205ent IS
+END c07s02b06x00p01n01i02205ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02205arch OF c07s02b06x00p01n01i02205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : real := 10.0 * 2.0;   
+  BEGIN
+    assert NOT(a = 20.0) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02205" 
+      severity NOTE;
+    assert (a = 20.0) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02205 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd
new file mode 100644
index 0000000..0b07dd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2206.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02206ent IS
+END c07s02b06x00p01n01i02206ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02206arch OF c07s02b06x00p01n01i02206ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : real := 10.0 / 2.0;   
+  BEGIN
+    assert NOT(a = 5.0) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02206" 
+      severity NOTE;
+    assert (a = 5.0) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02206 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd
new file mode 100644
index 0000000..6977af0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2208.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02208ent IS
+END c07s02b06x00p01n01i02208ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02208arch OF c07s02b06x00p01n01i02208ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : integer := 15;
+    constant y : integer := 9;
+    variable z : integer;
+  BEGIN
+    z := x mod y;  -- No_failure_here
+    assert NOT(z=6) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02208" 
+      severity NOTE;
+    assert (z=6) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02208 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd
new file mode 100644
index 0000000..edd65cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2257.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02257ent IS
+END c07s02b06x00p05n01i02257ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02257arch OF c07s02b06x00p05n01i02257ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant div11 : integer := (1 - 4) / (1 - 4);
+    constant div12 : integer := (1 - 4) / (2 - 4);
+    constant div13 : integer := (1 - 4) / (3 - 4);
+    constant div15 : integer := (1 - 4) / (5 - 4);
+    constant div16 : integer := (1 - 4) / (6 - 4);
+    constant div17 : integer := (1 - 4) / (7 - 4);
+    constant div18 : integer := (1 - 4) / (8 - 4);
+    constant div19 : integer := (1 - 4) / (9 - 4);
+    constant div41 : integer := (4 - 4) / (1 - 4);
+    constant div42 : integer := (4 - 4) / (2 - 4);
+    constant div43 : integer := (4 - 4) / (3 - 4);
+    constant div45 : integer := (4 - 4) / (5 - 4);
+    constant div46 : integer := (4 - 4) / (6 - 4);
+    constant div47 : integer := (4 - 4) / (7 - 4);
+    constant div48 : integer := (4 - 4) / (8 - 4);
+    constant div49 : integer := (4 - 4) / (9 - 4);
+    constant div61 : integer := (6 - 4) / (1 - 4);
+    constant div62 : integer := (6 - 4) / (2 - 4);
+    constant div63 : integer := (6 - 4) / (3 - 4);
+    constant div65 : integer := (6 - 4) / (5 - 4);
+    constant div66 : integer := (6 - 4) / (6 - 4);
+    constant div67 : integer := (6 - 4) / (7 - 4);
+    constant div68 : integer := (6 - 4) / (8 - 4);
+    constant div69 : integer := (6 - 4) / (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+
+    assert div11 = (1 - four) / (1 - four);
+    assert div12 = (1 - four) / (2 - four);
+    assert div13 = (1 - four) / (3 - four);
+    assert div15 = (1 - four) / (5 - four);
+    assert div16 = (1 - four) / (6 - four);
+    assert div17 = (1 - four) / (7 - four);
+    assert div18 = (1 - four) / (8 - four);
+    assert div19 = (1 - four) / (9 - four);
+    assert div41 = (4 - four) / (1 - four);
+    assert div42 = (4 - four) / (2 - four);
+    assert div43 = (4 - four) / (3 - four);
+    assert div45 = (4 - four) / (5 - four);
+    assert div46 = (4 - four) / (6 - four);
+    assert div47 = (4 - four) / (7 - four);
+    assert div48 = (4 - four) / (8 - four);
+    assert div49 = (4 - four) / (9 - four);
+    assert div61 = (6 - four) / (1 - four);
+    assert div62 = (6 - four) / (2 - four);
+    assert div63 = (6 - four) / (3 - four);
+    assert div65 = (6 - four) / (5 - four);
+    assert div66 = (6 - four) / (6 - four);
+    assert div67 = (6 - four) / (7 - four);
+    assert div68 = (6 - four) / (8 - four);
+    assert div69 = (6 - four) / (9 - four);
+
+    assert NOT((div11 = (1 - four) / (1 - four))   and
+               ( div12 = (1 - four) / (2 - four))   and
+               ( div13 = (1 - four) / (3 - four))   and
+               ( div15 = (1 - four) / (5 - four))   and
+               ( div16 = (1 - four) / (6 - four))   and
+               ( div17 = (1 - four) / (7 - four))   and
+               ( div18 = (1 - four) / (8 - four))   and
+               ( div19 = (1 - four) / (9 - four))   and
+               ( div41 = (4 - four) / (1 - four))   and
+               ( div42 = (4 - four) / (2 - four))   and
+               ( div43 = (4 - four) / (3 - four))   and
+               ( div45 = (4 - four) / (5 - four))   and
+               ( div46 = (4 - four) / (6 - four))   and
+               ( div47 = (4 - four) / (7 - four))   and
+               ( div48 = (4 - four) / (8 - four))   and
+               ( div49 = (4 - four) / (9 - four))   and
+               ( div61 = (6 - four) / (1 - four))   and
+               ( div62 = (6 - four) / (2 - four))   and
+               ( div63 = (6 - four) / (3 - four))   and
+               ( div65 = (6 - four) / (5 - four))   and
+               ( div66 = (6 - four) / (6 - four))   and
+               ( div67 = (6 - four) / (7 - four))   and
+               ( div68 = (6 - four) / (8 - four))   and
+               ( div69 = (6 - four) / (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02257"
+      severity NOTE;
+    assert (( div11 = (1 - four) / (1 - four))   and
+            ( div12 = (1 - four) / (2 - four))   and
+            ( div13 = (1 - four) / (3 - four))   and
+            ( div15 = (1 - four) / (5 - four))   and
+            ( div16 = (1 - four) / (6 - four))   and
+            ( div17 = (1 - four) / (7 - four))   and
+            ( div18 = (1 - four) / (8 - four))   and
+            ( div19 = (1 - four) / (9 - four))   and
+            ( div41 = (4 - four) / (1 - four))   and
+            ( div42 = (4 - four) / (2 - four))   and
+            ( div43 = (4 - four) / (3 - four))   and
+            ( div45 = (4 - four) / (5 - four))   and
+            ( div46 = (4 - four) / (6 - four))   and
+            ( div47 = (4 - four) / (7 - four))   and
+            ( div48 = (4 - four) / (8 - four))   and
+            ( div49 = (4 - four) / (9 - four))   and
+            ( div61 = (6 - four) / (1 - four))   and
+            ( div62 = (6 - four) / (2 - four))   and
+            ( div63 = (6 - four) / (3 - four))   and
+            ( div65 = (6 - four) / (5 - four))   and
+            ( div66 = (6 - four) / (6 - four))   and
+            ( div67 = (6 - four) / (7 - four))   and
+            ( div68 = (6 - four) / (8 - four))   and
+            ( div69 = (6 - four) / (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02257 - Constant integer type division test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02257arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd
new file mode 100644
index 0000000..c111322
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd
@@ -0,0 +1,159 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2258.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02258ent IS
+END c07s02b06x00p05n01i02258ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02258arch OF c07s02b06x00p05n01i02258ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant mul11 : integer := (1 - 4) * (1 - 4);
+    constant mul12 : integer := (1 - 4) * (2 - 4);
+    constant mul13 : integer := (1 - 4) * (3 - 4);
+    constant mul14 : integer := (1 - 4) * (4 - 4);
+    constant mul15 : integer := (1 - 4) * (5 - 4);
+    constant mul16 : integer := (1 - 4) * (6 - 4);
+    constant mul17 : integer := (1 - 4) * (7 - 4);
+    constant mul18 : integer := (1 - 4) * (8 - 4);
+    constant mul19 : integer := (1 - 4) * (9 - 4);
+    constant mul41 : integer := (4 - 4) * (1 - 4);
+    constant mul42 : integer := (4 - 4) * (2 - 4);
+    constant mul43 : integer := (4 - 4) * (3 - 4);
+    constant mul44 : integer := (4 - 4) * (4 - 4);
+    constant mul45 : integer := (4 - 4) * (5 - 4);
+    constant mul46 : integer := (4 - 4) * (6 - 4);
+    constant mul47 : integer := (4 - 4) * (7 - 4);
+    constant mul48 : integer := (4 - 4) * (8 - 4);
+    constant mul49 : integer := (4 - 4) * (9 - 4);
+    constant mul61 : integer := (6 - 4) * (1 - 4);
+    constant mul62 : integer := (6 - 4) * (2 - 4);
+    constant mul63 : integer := (6 - 4) * (3 - 4);
+    constant mul64 : integer := (6 - 4) * (4 - 4);
+    constant mul65 : integer := (6 - 4) * (5 - 4);
+    constant mul66 : integer := (6 - 4) * (6 - 4);
+    constant mul67 : integer := (6 - 4) * (7 - 4);
+    constant mul68 : integer := (6 - 4) * (8 - 4);
+    constant mul69 : integer := (6 - 4) * (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+
+    assert mul11 = (1 - four) * (1 - four);
+    assert mul12 = (1 - four) * (2 - four);
+    assert mul13 = (1 - four) * (3 - four);
+    assert mul14 = (1 - four) * (4 - four);
+    assert mul15 = (1 - four) * (5 - four);
+    assert mul16 = (1 - four) * (6 - four);
+    assert mul17 = (1 - four) * (7 - four);
+    assert mul18 = (1 - four) * (8 - four);
+    assert mul19 = (1 - four) * (9 - four);
+    assert mul41 = (4 - four) * (1 - four);
+    assert mul42 = (4 - four) * (2 - four);
+    assert mul43 = (4 - four) * (3 - four);
+    assert mul44 = (4 - four) * (4 - four);
+    assert mul45 = (4 - four) * (5 - four);
+    assert mul46 = (4 - four) * (6 - four);
+    assert mul47 = (4 - four) * (7 - four);
+    assert mul48 = (4 - four) * (8 - four);
+    assert mul49 = (4 - four) * (9 - four);
+    assert mul61 = (6 - four) * (1 - four);
+    assert mul62 = (6 - four) * (2 - four);
+    assert mul63 = (6 - four) * (3 - four);
+    assert mul64 = (6 - four) * (4 - four);
+    assert mul65 = (6 - four) * (5 - four);
+    assert mul66 = (6 - four) * (6 - four);
+    assert mul67 = (6 - four) * (7 - four);
+    assert mul68 = (6 - four) * (8 - four);
+    assert mul69 = (6 - four) * (9 - four);
+
+    assert NOT(( mul11 = (1 - four) * (1 - four))   and
+               ( mul12 = (1 - four) * (2 - four))   and
+               ( mul13 = (1 - four) * (3 - four))   and
+               ( mul14 = (1 - four) * (4 - four))   and
+               ( mul15 = (1 - four) * (5 - four))   and
+               ( mul16 = (1 - four) * (6 - four))   and
+               ( mul17 = (1 - four) * (7 - four))   and
+               ( mul18 = (1 - four) * (8 - four))   and
+               ( mul19 = (1 - four) * (9 - four))   and
+               ( mul41 = (4 - four) * (1 - four))   and
+               ( mul42 = (4 - four) * (2 - four))   and
+               ( mul43 = (4 - four) * (3 - four))   and
+               ( mul44 = (4 - four) * (4 - four))   and
+               ( mul45 = (4 - four) * (5 - four))   and
+               ( mul46 = (4 - four) * (6 - four))   and
+               ( mul47 = (4 - four) * (7 - four))   and
+               ( mul48 = (4 - four) * (8 - four))   and
+               ( mul49 = (4 - four) * (9 - four))   and
+               ( mul61 = (6 - four) * (1 - four))   and
+               ( mul62 = (6 - four) * (2 - four))   and
+               ( mul63 = (6 - four) * (3 - four))   and
+               ( mul64 = (6 - four) * (4 - four))   and
+               ( mul65 = (6 - four) * (5 - four))   and
+               ( mul66 = (6 - four) * (6 - four))   and
+               ( mul67 = (6 - four) * (7 - four))   and
+               ( mul68 = (6 - four) * (8 - four))   and
+               ( mul69 = (6 - four) * (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02258"
+      severity NOTE;
+    assert (( mul11 = (1 - four) * (1 - four))   and
+            ( mul12 = (1 - four) * (2 - four))   and
+            ( mul13 = (1 - four) * (3 - four))   and
+            ( mul14 = (1 - four) * (4 - four))   and
+            ( mul15 = (1 - four) * (5 - four))   and
+            ( mul16 = (1 - four) * (6 - four))   and
+            ( mul17 = (1 - four) * (7 - four))   and
+            ( mul18 = (1 - four) * (8 - four))   and
+            ( mul19 = (1 - four) * (9 - four))   and
+            ( mul41 = (4 - four) * (1 - four))   and
+            ( mul42 = (4 - four) * (2 - four))   and
+            ( mul43 = (4 - four) * (3 - four))   and
+            ( mul44 = (4 - four) * (4 - four))   and
+            ( mul45 = (4 - four) * (5 - four))   and
+            ( mul46 = (4 - four) * (6 - four))   and
+            ( mul47 = (4 - four) * (7 - four))   and
+            ( mul48 = (4 - four) * (8 - four))   and
+            ( mul49 = (4 - four) * (9 - four))   and
+            ( mul61 = (6 - four) * (1 - four))   and
+            ( mul62 = (6 - four) * (2 - four))   and
+            ( mul63 = (6 - four) * (3 - four))   and
+            ( mul64 = (6 - four) * (4 - four))   and
+            ( mul65 = (6 - four) * (5 - four))   and
+            ( mul66 = (6 - four) * (6 - four))   and
+            ( mul67 = (6 - four) * (7 - four))   and
+            ( mul68 = (6 - four) * (8 - four))   and
+            ( mul69 = (6 - four) * (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02258 - Constant integer type multiplication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd
new file mode 100644
index 0000000..cd8fcce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2259.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02259ent IS
+END c07s02b06x00p05n01i02259ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02259arch OF c07s02b06x00p05n01i02259ent IS
+BEGIN
+  TESTING: PROCESS
+    constant mod11 : integer := (1 - 4) mod (1 - 4);
+    constant mod12 : integer := (1 - 4) mod (2 - 4);
+    constant mod13 : integer := (1 - 4) mod (3 - 4);
+    constant mod15 : integer := (1 - 4) mod (5 - 4);
+    constant mod16 : integer := (1 - 4) mod (6 - 4);
+    constant mod17 : integer := (1 - 4) mod (7 - 4);
+    constant mod18 : integer := (1 - 4) mod (8 - 4);
+    constant mod19 : integer := (1 - 4) mod (9 - 4);
+    constant mod41 : integer := (4 - 4) mod (1 - 4);
+    constant mod42 : integer := (4 - 4) mod (2 - 4);
+    constant mod43 : integer := (4 - 4) mod (3 - 4);
+    constant mod45 : integer := (4 - 4) mod (5 - 4);
+    constant mod46 : integer := (4 - 4) mod (6 - 4);
+    constant mod47 : integer := (4 - 4) mod (7 - 4);
+    constant mod48 : integer := (4 - 4) mod (8 - 4);
+    constant mod49 : integer := (4 - 4) mod (9 - 4);
+    constant mod61 : integer := (6 - 4) mod (1 - 4);
+    constant mod62 : integer := (6 - 4) mod (2 - 4);
+    constant mod63 : integer := (6 - 4) mod (3 - 4);
+    constant mod65 : integer := (6 - 4) mod (5 - 4);
+    constant mod66 : integer := (6 - 4) mod (6 - 4);
+    constant mod67 : integer := (6 - 4) mod (7 - 4);
+    constant mod68 : integer := (6 - 4) mod (8 - 4);
+    constant mod69 : integer := (6 - 4) mod (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+    assert mod11 = (1 - four) mod (1 - four);
+    assert mod12 = (1 - four) mod (2 - four);
+    assert mod13 = (1 - four) mod (3 - four);
+    assert mod15 = (1 - four) mod (5 - four);
+    assert mod16 = (1 - four) mod (6 - four);
+    assert mod17 = (1 - four) mod (7 - four);
+    assert mod18 = (1 - four) mod (8 - four);
+    assert mod19 = (1 - four) mod (9 - four);
+    assert mod41 = (4 - four) mod (1 - four);
+    assert mod42 = (4 - four) mod (2 - four);
+    assert mod43 = (4 - four) mod (3 - four);
+    assert mod45 = (4 - four) mod (5 - four);
+    assert mod46 = (4 - four) mod (6 - four);
+    assert mod47 = (4 - four) mod (7 - four);
+    assert mod48 = (4 - four) mod (8 - four);
+    assert mod49 = (4 - four) mod (9 - four);
+    assert mod61 = (6 - four) mod (1 - four);
+    assert mod62 = (6 - four) mod (2 - four);
+    assert mod63 = (6 - four) mod (3 - four);
+    assert mod65 = (6 - four) mod (5 - four);
+    assert mod66 = (6 - four) mod (6 - four);
+    assert mod67 = (6 - four) mod (7 - four);
+    assert mod68 = (6 - four) mod (8 - four);
+    assert mod69 = (6 - four) mod (9 - four);
+
+    assert NOT((mod11 = (1 - four) mod (1 - four))   and
+               ( mod12 = (1 - four) mod (2 - four))   and
+               ( mod13 = (1 - four) mod (3 - four))   and
+               ( mod15 = (1 - four) mod (5 - four))   and
+               ( mod16 = (1 - four) mod (6 - four))   and
+               ( mod17 = (1 - four) mod (7 - four))   and
+               ( mod18 = (1 - four) mod (8 - four))   and
+               ( mod19 = (1 - four) mod (9 - four))   and
+               ( mod41 = (4 - four) mod (1 - four))   and
+               ( mod42 = (4 - four) mod (2 - four))   and
+               ( mod43 = (4 - four) mod (3 - four))   and
+               ( mod45 = (4 - four) mod (5 - four))   and
+               ( mod46 = (4 - four) mod (6 - four))   and
+               ( mod47 = (4 - four) mod (7 - four))   and
+               ( mod48 = (4 - four) mod (8 - four))   and
+               ( mod49 = (4 - four) mod (9 - four))   and
+               ( mod61 = (6 - four) mod (1 - four))   and
+               ( mod62 = (6 - four) mod (2 - four))   and
+               ( mod63 = (6 - four) mod (3 - four))   and
+               ( mod65 = (6 - four) mod (5 - four))   and
+               ( mod66 = (6 - four) mod (6 - four))   and
+               ( mod67 = (6 - four) mod (7 - four))   and
+               ( mod68 = (6 - four) mod (8 - four))   and
+               ( mod69 = (6 - four) mod (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02259"
+      severity NOTE;
+    assert (( mod11 = (1 - four) mod (1 - four))   and
+            ( mod12 = (1 - four) mod (2 - four))   and
+            ( mod13 = (1 - four) mod (3 - four))   and
+            ( mod15 = (1 - four) mod (5 - four))   and
+            ( mod16 = (1 - four) mod (6 - four))   and
+            ( mod17 = (1 - four) mod (7 - four))   and
+            ( mod18 = (1 - four) mod (8 - four))   and
+            ( mod19 = (1 - four) mod (9 - four))   and
+            ( mod41 = (4 - four) mod (1 - four))   and
+            ( mod42 = (4 - four) mod (2 - four))   and
+            ( mod43 = (4 - four) mod (3 - four))   and
+            ( mod45 = (4 - four) mod (5 - four))   and
+            ( mod46 = (4 - four) mod (6 - four))   and
+            ( mod47 = (4 - four) mod (7 - four))   and
+            ( mod48 = (4 - four) mod (8 - four))   and
+            ( mod49 = (4 - four) mod (9 - four))   and
+            ( mod61 = (6 - four) mod (1 - four))   and
+            ( mod62 = (6 - four) mod (2 - four))   and
+            ( mod63 = (6 - four) mod (3 - four))   and
+            ( mod65 = (6 - four) mod (5 - four))   and
+            ( mod66 = (6 - four) mod (6 - four))   and
+            ( mod67 = (6 - four) mod (7 - four))   and
+            ( mod68 = (6 - four) mod (8 - four))   and
+            ( mod69 = (6 - four) mod (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02259 - Constant integer type mod test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02259arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd
new file mode 100644
index 0000000..166f289
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02260ent IS
+END c07s02b06x00p05n01i02260ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant rem11 : integer := (1 - 4) rem (1 - 4);
+    constant rem12 : integer := (1 - 4) rem (2 - 4);
+    constant rem13 : integer := (1 - 4) rem (3 - 4);
+    constant rem15 : integer := (1 - 4) rem (5 - 4);
+    constant rem16 : integer := (1 - 4) rem (6 - 4);
+    constant rem17 : integer := (1 - 4) rem (7 - 4);
+    constant rem18 : integer := (1 - 4) rem (8 - 4);
+    constant rem19 : integer := (1 - 4) rem (9 - 4);
+    constant rem41 : integer := (4 - 4) rem (1 - 4);
+    constant rem42 : integer := (4 - 4) rem (2 - 4);
+    constant rem43 : integer := (4 - 4) rem (3 - 4);
+    constant rem45 : integer := (4 - 4) rem (5 - 4);
+    constant rem46 : integer := (4 - 4) rem (6 - 4);
+    constant rem47 : integer := (4 - 4) rem (7 - 4);
+    constant rem48 : integer := (4 - 4) rem (8 - 4);
+    constant rem49 : integer := (4 - 4) rem (9 - 4);
+    constant rem61 : integer := (6 - 4) rem (1 - 4);
+    constant rem62 : integer := (6 - 4) rem (2 - 4);
+    constant rem63 : integer := (6 - 4) rem (3 - 4);
+    constant rem65 : integer := (6 - 4) rem (5 - 4);
+    constant rem66 : integer := (6 - 4) rem (6 - 4);
+    constant rem67 : integer := (6 - 4) rem (7 - 4);
+    constant rem68 : integer := (6 - 4) rem (8 - 4);
+    constant rem69 : integer := (6 - 4) rem (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+    assert rem11 = (1 - four) rem (1 - four);
+    assert rem12 = (1 - four) rem (2 - four);
+    assert rem13 = (1 - four) rem (3 - four);
+    assert rem15 = (1 - four) rem (5 - four);
+    assert rem16 = (1 - four) rem (6 - four);
+    assert rem17 = (1 - four) rem (7 - four);
+    assert rem18 = (1 - four) rem (8 - four);
+    assert rem19 = (1 - four) rem (9 - four);
+    assert rem41 = (4 - four) rem (1 - four);
+    assert rem42 = (4 - four) rem (2 - four);
+    assert rem43 = (4 - four) rem (3 - four);
+    assert rem45 = (4 - four) rem (5 - four);
+    assert rem46 = (4 - four) rem (6 - four);
+    assert rem47 = (4 - four) rem (7 - four);
+    assert rem48 = (4 - four) rem (8 - four);
+    assert rem49 = (4 - four) rem (9 - four);
+    assert rem61 = (6 - four) rem (1 - four);
+    assert rem62 = (6 - four) rem (2 - four);
+    assert rem63 = (6 - four) rem (3 - four);
+    assert rem65 = (6 - four) rem (5 - four);
+    assert rem66 = (6 - four) rem (6 - four);
+    assert rem67 = (6 - four) rem (7 - four);
+    assert rem68 = (6 - four) rem (8 - four);
+    assert rem69 = (6 - four) rem (9 - four);
+
+    assert NOT((rem11 = (1 - four) rem (1 - four))   and
+               ( rem12 = (1 - four) rem (2 - four))   and
+               ( rem13 = (1 - four) rem (3 - four))   and
+               ( rem15 = (1 - four) rem (5 - four))   and
+               ( rem16 = (1 - four) rem (6 - four))   and
+               ( rem17 = (1 - four) rem (7 - four))   and
+               ( rem18 = (1 - four) rem (8 - four))   and
+               ( rem19 = (1 - four) rem (9 - four))   and
+               ( rem41 = (4 - four) rem (1 - four))   and
+               ( rem42 = (4 - four) rem (2 - four))   and
+               ( rem43 = (4 - four) rem (3 - four))   and
+               ( rem45 = (4 - four) rem (5 - four))   and
+               ( rem46 = (4 - four) rem (6 - four))   and
+               ( rem47 = (4 - four) rem (7 - four))   and
+               ( rem48 = (4 - four) rem (8 - four))   and
+               ( rem49 = (4 - four) rem (9 - four))   and
+               ( rem61 = (6 - four) rem (1 - four))   and
+               ( rem62 = (6 - four) rem (2 - four))   and
+               ( rem63 = (6 - four) rem (3 - four))   and
+               ( rem65 = (6 - four) rem (5 - four))   and
+               ( rem66 = (6 - four) rem (6 - four))   and
+               ( rem67 = (6 - four) rem (7 - four))   and
+               ( rem68 = (6 - four) rem (8 - four))   and
+               ( rem69 = (6 - four) rem (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02260"
+      severity NOTE;
+    assert (( rem11 = (1 - four) rem (1 - four))   and
+            ( rem12 = (1 - four) rem (2 - four))   and
+            ( rem13 = (1 - four) rem (3 - four))   and
+            ( rem15 = (1 - four) rem (5 - four))   and
+            ( rem16 = (1 - four) rem (6 - four))   and
+            ( rem17 = (1 - four) rem (7 - four))   and
+            ( rem18 = (1 - four) rem (8 - four))   and
+            ( rem19 = (1 - four) rem (9 - four))   and
+            ( rem41 = (4 - four) rem (1 - four))   and
+            ( rem42 = (4 - four) rem (2 - four))   and
+            ( rem43 = (4 - four) rem (3 - four))   and
+            ( rem45 = (4 - four) rem (5 - four))   and
+            ( rem46 = (4 - four) rem (6 - four))   and
+            ( rem47 = (4 - four) rem (7 - four))   and
+            ( rem48 = (4 - four) rem (8 - four))   and
+            ( rem49 = (4 - four) rem (9 - four))   and
+            ( rem61 = (6 - four) rem (1 - four))   and
+            ( rem62 = (6 - four) rem (2 - four))   and
+            ( rem63 = (6 - four) rem (3 - four))   and
+            ( rem65 = (6 - four) rem (5 - four))   and
+            ( rem66 = (6 - four) rem (6 - four))   and
+            ( rem67 = (6 - four) rem (7 - four))   and
+            ( rem68 = (6 - four) rem (8 - four))   and
+            ( rem69 = (6 - four) rem (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02260arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd
new file mode 100644
index 0000000..631bbf4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2261.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02261ent IS
+END c07s02b06x00p05n01i02261ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02261arch OF c07s02b06x00p05n01i02261ent IS
+  
+  constant s4p : real := 4.0;
+  constant s4n : real := (-4.0);
+  constant s5p : real := 5.0;
+  constant s5n : real := (-5.0);
+  
+BEGIN
+  TESTING: PROCESS
+    variable m1 : real :=   4.0  *   5.0 ;
+    variable m2 : real :=   4.0  * (-5.0);
+    variable m3 : real := (-4.0) *   5.0 ;
+    variable m4 : real := (-4.0) * (-5.0);
+    
+    variable d1 : real :=   4.0  /   5.0 ;
+    variable d2 : real :=   4.0  / (-5.0);
+    variable d3 : real := (-4.0) /   5.0 ;
+    variable d4 : real := (-4.0) / (-5.0);
+    
+    variable Em1 : real :=  s4p  *  s5p;
+    variable Em2 : real :=  s4p  *  s5n;
+    variable Em3 : real :=  s4n  *  s5p;
+    variable Em4 : real :=  s4n  *  s5n;
+    
+    variable Ed1 : real :=  s4p  /  s5p;
+    variable Ed2 : real :=  s4p  /  s5n;
+    variable Ed3 : real :=  s4n  /  s5p;
+    variable Ed4 : real :=  s4n  /  s5n;
+  BEGIN
+    assert m1 = Em1;
+    assert m2 = Em2;
+    assert m3 = Em3;
+    assert m4 = Em4;
+    
+    assert d1 = Ed1;
+    assert d2 = Ed2;
+    assert d3 = Ed3;
+    assert d4 = Ed4;
+
+    assert NOT((m1 = Em1)   and
+               ( m2 = Em2)   and
+               ( m3 = Em3)   and
+               ( m4 = Em4)   and
+               ( d1 = Ed1)   and
+               ( d2 = Ed2)   and
+               ( d3 = Ed3)   and
+               ( d4 = Ed4)   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02261"
+      severity NOTE;
+    assert (( m1 = Em1)   and
+            ( m2 = Em2)   and
+            ( m3 = Em3)   and
+            ( m4 = Em4)   and
+            ( d1 = Ed1)   and
+            ( d2 = Ed2)   and
+            ( d3 = Ed3)   and
+            ( d4 = Ed4)   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02261 - Constant real type multiplication and division test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02261arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd
new file mode 100644
index 0000000..d3074ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2262.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02262ent IS
+END c07s02b06x00p11n01i02262ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02262arch OF c07s02b06x00p11n01i02262ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := 10 rem (-3);
+    assert NOT(k=1)
+      report "***PASSED TEST: c07s02b06x00p11n01i02262"
+      severity NOTE;
+    assert ( k=1 )
+      report "***FAILED TEST: c07s02b06x00p11n01i02262 - Integer division and remainder are deined by the following relation : A = (A/B)*B + (A rem B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02262arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd
new file mode 100644
index 0000000..07cded6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2263.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02263ent IS
+END c07s02b06x00p11n01i02263ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02263arch OF c07s02b06x00p11n01i02263ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := (-A)/B ;
+    V2 := -(A/B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02263"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02263 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02263arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd
new file mode 100644
index 0000000..186aaa5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2264.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02264ent IS
+END c07s02b06x00p11n01i02264ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02264arch OF c07s02b06x00p11n01i02264ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := (-A)/B ;
+    V2 := A/(-B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02264"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02264 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02264arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd
new file mode 100644
index 0000000..176b09b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02265ent IS
+END c07s02b06x00p11n01i02265ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := -(A/B) ;
+    V2 := A/(-B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02265"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd
new file mode 100644
index 0000000..60c04e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2266.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02266ent IS
+END c07s02b06x00p11n01i02266ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02266arch OF c07s02b06x00p11n01i02266ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER   := 0;
+  BEGIN
+    -- Test integer division.
+    -- 1. Both positive.
+    for A in 0 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 0 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    wait for 5 ns;
+
+    assert NOT(OKtest = 0)
+      report "***PASSED TEST: c07s02b06x00p11n01i02266"
+      severity NOTE;
+    assert (OKtest = 0)
+      report "***FAILED TEST: c07s02b06x00p11n01i02266 - Integer division should satisfy the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02266arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd
new file mode 100644
index 0000000..eaea8bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2267.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02267ent IS
+END c07s02b06x00p11n01i02267ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02267arch OF c07s02b06x00p11n01i02267ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER   := 0;
+  BEGIN
+    -- Test integer rem operations.
+    -- 1. Both positive.
+    for A in 1 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 1 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+
+    wait for 5 ns;
+
+    assert NOT(OKtest = 0)
+      report "***PASSED TEST: c07s02b06x00p11n01i02267"
+      severity NOTE;
+    assert (OKtest = 0)
+      report "***FAILED TEST: c07s02b06x00p11n01i02267 - Integer division should satisfy the following identity: A = (A/B)*B + (A rem B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02267arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd
new file mode 100644
index 0000000..faa11da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2268.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p12n01i02268ent IS
+END c07s02b06x00p12n01i02268ent;
+
+ARCHITECTURE c07s02b06x00p12n01i02268arch OF c07s02b06x00p12n01i02268ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := 10 mod (-3);
+    assert NOT(k = -2)
+      report "***PASSED TEST: c07s02b06x00p12n01i02268"
+      severity NOTE;
+    assert (k = -2)
+      report "***FAILED TEST: c07s02b06x00p12n01i02268 - The result of the modulus operation satisfy the relation :A = B*N + (A mod B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p12n01i02268arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd
new file mode 100644
index 0000000..5ebc3aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2269.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p12n01i02269ent IS
+END c07s02b06x00p12n01i02269ent;
+
+ARCHITECTURE c07s02b06x00p12n01i02269arch OF c07s02b06x00p12n01i02269ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER := 0;
+  BEGIN
+    -- Test integer mod operations.
+    -- 1. Both positive.
+    for A in 0 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 0 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    wait for 5 ns;
+    assert NOT(OKtest=0)
+      report "***PASSED TEST: c07s02b06x00p12n01i02269"
+      severity NOTE;
+    assert (OKtest=0)
+      report "***FAILED TEST: c07s02b06x00p12n01i02269 - The result of the modulus operation satisfy the relation :A = B*N + (A mod B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p12n01i02269arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd
new file mode 100644
index 0000000..2081cf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02270ent IS
+END c07s02b06x00p14n01i02270ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    variable k : phys := 10 p2;
+  BEGIN
+    assert NOT(k = 2 p3)
+      report "***PASSED TEST: c07s02b06x00p14n01i02270"
+      severity NOTE;
+    assert (k = 2 p3)
+      report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02270arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd
new file mode 100644
index 0000000..f49b502
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2271.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02271ent IS
+END c07s02b06x00p14n01i02271ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02271arch OF c07s02b06x00p14n01i02271ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : time := 2 * 10 ns;
+  BEGIN
+    assert NOT(k = 20 ns)
+      report "***PASSED TEST: c07s02b06x00p14n01i02271"
+      severity NOTE;
+    assert (k = 20 ns)
+      report "***FAILED TEST: c07s02b06x00p14n01i02271 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02271arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd
new file mode 100644
index 0000000..0a30df9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2272.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02272ent IS
+END c07s02b06x00p14n01i02272ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02272arch OF c07s02b06x00p14n01i02272ent IS
+  signal SS : TIME;
+BEGIN
+  TESTING: PROCESS
+    variable A : TIME    := 3 * 11 ns;
+    variable R : REAL    := 7.9999;
+    variable S : INTEGER    := 1;
+  BEGIN
+    SS <= R * ( S * A );            -- context 4
+    wait for 10 ns;
+    assert NOT((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
+      report "***PASSED TEST: c07s02b06x00p14n01i02272"
+      severity NOTE;
+    assert ((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
+      report "***FAILED TEST: c07s02b06x00p14n01i02272 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02272arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd
new file mode 100644
index 0000000..37f9331
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00228ent IS
+END c03s01b01x00p07n01i00228ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL1 is ('0', '1', 'Z', 'X') ;
+  signal S1 : MVL ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= '1' after 10 ns,
+          '0' after 20 ns,
+          'Z' after 50 ns; 
+    wait for 60 ns;
+    assert NOT( S1 = 'Z' )
+      report "***PASSED TEST: c03s01b01x00p07n01i00228"
+      severity NOTE;
+    assert ( S1 = 'Z' )
+      report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00228arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd
new file mode 100644
index 0000000..e89ca13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2283.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02283ent IS
+END c07s02b06x00p14n01i02283ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02283arch OF c07s02b06x00p14n01i02283ent IS
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 80000
+      units
+        PHYS1;
+        PHYS2 = 2 PHYS1;
+        PHYS10 = 10 PHYS1;
+        PHYS100 = 10 PHYS10;
+      end units;
+    function G ( A : PHYS; B : INTEGER; C : REAL ) return PHYS is
+    begin
+      return A / B * C;       
+    end G;
+    variable B : PHYS := 11 PHYS1;
+    variable R : REAL := 7.9999;
+  BEGIN
+    B := G(B,4,1.3) / 4 * 0.0 ;
+    assert NOT(B = 0 PHYS1) 
+      report "***PASSED TEST: c07s02b06x00p14n01i02283" 
+      severity NOTE;
+    assert (B = 0 PHYS1) 
+      report "***FAILED TEST: c07s02b06x00p14n01i02283 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02283arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd
new file mode 100644
index 0000000..a3a6d12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2285.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02285ent IS
+END c07s02b06x00p14n01i02285ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02285arch OF c07s02b06x00p14n01i02285ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    constant a : phys := 2 p3;
+    constant b : phys := 10 p2;
+    constant d : integer := a / b;
+  BEGIN
+    assert NOT(d = 1)
+      report "***PASSED TEST: c07s02b06x00p14n01i02285" 
+      severity NOTE;
+    assert (d = 1)
+      report "***FAILED TEST: c07s02b06x00p14n01i02285 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02285arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd
new file mode 100644
index 0000000..05b89d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02286ent IS
+END c07s02b06x00p14n01i02286ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 100000
+      units
+        A;
+        B = 100 A;
+        C = 100 B;
+      end units;
+    function F_PHYS ( A : PHYS ) return PHYS is
+    begin   
+      return A;       
+    end F_PHYS;
+    variable P : PHYS    := 1 B;
+    variable Z : integer := time'(1 min) / time'(27 sec);
+  BEGIN
+    Z  := P / F_PHYS(1 A);
+    assert NOT(Z = 100)
+      report "***PASSED TEST: c07s02b06x00p14n01i02286" 
+      severity NOTE;
+    assert (Z = 100)
+      report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02286arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd
new file mode 100644
index 0000000..5f9310c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2287.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02287ent IS
+END c07s02b06x00p32n01i02287ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02287arch OF c07s02b06x00p32n01i02287ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 fs;
+    assert NOT(    ((1 fs * 1000) = 1 ps)    and   
+                   ((1 ps * 1000) = 1 ns)   and
+                   ((1 ns * 1000) = 1 us)   and
+                   ((1000 * 1 fs) = 1 ps)   and
+                   ((1000 * 1 ps) = 1 ns)   and
+                   ((1000 * 1 ns) = 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02287"
+      severity NOTE;
+    assert (    ((1 fs * 1000) = 1 ps)    and   
+                ((1 ps * 1000) = 1 ns)   and
+                ((1 ns * 1000) = 1 us)   and
+                ((1000 * 1 fs) = 1 ps)   and
+                ((1000 * 1 ps) = 1 ns)   and
+                ((1000 * 1 ns) = 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02287 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02287arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd
new file mode 100644
index 0000000..4750ae6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2288.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02288ent IS
+END c07s02b06x00p32n01i02288ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02288arch OF c07s02b06x00p32n01i02288ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    ((1 A  * 10)    = 1 nm)   and
+                   ((1 nm * 1000)    = 1 um)   and
+                   ((1 um * 1000)    = 1 mm)   and
+                   ((1 mm * 10)    = 1 cm)   and
+                   ((10   * 1 A)    = 1 nm)   and
+                   ((1000 * 1 nm)    = 1 um)   and
+                   ((1000 * 1 um)    = 1 mm)   and
+                   ((10   * 1 mm)    = 1 cm)   and
+                   ((1 A * 254000) = 1 mil)and
+                   ((1 mil * 1000) = 1 inch)and
+                   ((254000 * 1 A) = 1 mil)and
+                   ((1000 * 1 mil) = 1 inch))
+      report "***PASSED TEST: c07s02b06x00p32n01i02288"
+      severity NOTE;
+    assert (    ((1 A  * 10)    = 1 nm)   and
+                ((1 nm * 1000)    = 1 um)   and
+                ((1 um * 1000)    = 1 mm)   and
+                ((1 mm * 10)    = 1 cm)   and
+                ((10   * 1 A)    = 1 nm)   and
+                ((1000 * 1 nm)    = 1 um)   and
+                ((1000 * 1 um)    = 1 mm)   and
+                ((10   * 1 mm)    = 1 cm)   and
+                ((1 A * 254000) = 1 mil)and
+                ((1 mil * 1000) = 1 inch)and
+                ((254000 * 1 A) = 1 mil)and
+                ((1000 * 1 mil) = 1 inch))
+      report "***FAILED TEST: c07s02b06x00p32n01i02288 - Multiplication of a physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02288arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd
new file mode 100644
index 0000000..4a2bbf1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2289.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02289ent IS
+END c07s02b06x00p32n01i02289ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02289arch OF c07s02b06x00p32n01i02289ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    ((1 ns * 1000) = 1 us)   and   
+                   ((1 us * 1000) = 1 ms)   and
+                   ((1 ms * 1000) = 1 sec)   and
+                   ((1000 * 1 ns) = 1 us)   and
+                   ((1000 * 1 us) = 1 ms)   and
+                   ((1000 * 1 ms) = 1 sec)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02289"
+      severity NOTE;
+    assert (    ((1 ns * 1000) = 1 us)   and   
+                ((1 us * 1000) = 1 ms)   and
+                ((1 ms * 1000) = 1 sec)   and
+                ((1000 * 1 ns) = 1 us)   and
+                ((1000 * 1 us) = 1 ms)   and
+                ((1000 * 1 ms) = 1 sec)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02289 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02289arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd
new file mode 100644
index 0000000..dfcdb4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc229.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00229ent IS
+  type big    is (a,b,c,d,e,f,g);
+  type small    is (f,g,h,i);
+END c03s01b01x00p07n01i00229ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00229arch OF c03s01b01x00p07n01i00229ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bigf   : big;
+    variable smallf   : small;
+    variable i,l   : integer;
+  BEGIN
+    bigf    := f;
+    smallf    := f;
+    i    := big'pos(f);
+    l    := small'pos(f);
+    assert NOT(i > l) 
+      report "***PASSED TEST: c03s01b01x00p07n01i00229"
+      severity NOTE;
+    assert (i > l) 
+      report "***FAILED TEST: c03s01b01x00p07n01i00229 - The type of an overloaded enumeration literal is determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00229arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd
new file mode 100644
index 0000000..43de405
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2290.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02290ent IS
+END c07s02b06x00p32n01i02290ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02290arch OF c07s02b06x00p32n01i02290ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ms;
+    assert NOT(    ((1 ms * 1000) = 1 sec)   and
+                   ((1 sec * 60)  = 1 min)   and
+                   ((1 min * 60)  = 1 hr)   and
+                   ((1000 * 1 ms) = 1 sec)   and
+                   ((60 * 1 sec)  = 1 min)   and
+                   ((60 * 1 min)  = 1 hr))
+      report "***PASSED TEST: c07s02b06x00p32n01i02290"
+      severity NOTE;
+    assert (    ((1 ms * 1000) = 1 sec)   and
+                ((1 sec * 60)  = 1 min)   and
+                ((1 min * 60)  = 1 hr)   and
+                ((1000 * 1 ms) = 1 sec)   and
+                ((60 * 1 sec)  = 1 min)   and
+                ((60 * 1 min)  = 1 hr))
+      report "***FAILED TEST: c07s02b06x00p32n01i02290 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02290arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd
new file mode 100644
index 0000000..d30c13b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2291.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02291ent IS
+END c07s02b06x00p32n01i02291ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02291arch OF c07s02b06x00p32n01i02291ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 fs * 1000.0) > 1 fs)
+      report "Assertion error.(28)";
+    assert ((1 ps * 1000.0) > 1 ps)
+      report "Assertion error.(29)";
+    assert ((1 ns * 1000.0) > 1 ns)
+      report "Assertion error.(30)";
+    wait for 5 fs;
+    assert NOT(    ((1 fs * 1000.0) > 1 fs)   and
+                   ((1 ps * 1000.0) > 1 ps)   and
+                   ((1 ns * 1000.0) > 1 ns)   and
+                   ((1000.0 * 1 fs) > 1 fs)   and
+                   ((1000.0 * 1 ps) > 1 ps)   and
+                   ((1000.0 * 1 ns) > 1 ns)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02291"
+      severity NOTE;
+    assert (    ((1 fs * 1000.0) > 1 fs)   and
+                ((1 ps * 1000.0) > 1 ps)   and
+                ((1 ns * 1000.0) > 1 ns)   and
+                ((1000.0 * 1 fs) > 1 fs)   and
+                ((1000.0 * 1 ps) > 1 ps)   and
+                ((1000.0 * 1 ns) > 1 ns)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02291 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02291arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd
new file mode 100644
index 0000000..952ac12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02292ent IS
+END c07s02b06x00p32n01i02292ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert ((1 A  * 10.0) > 1 A)
+      report "Assertion error.(1)";
+    assert ((1 nm * 1000.0) > 1 nm)
+      report "Assertion error.(2)";
+    assert ((1 um * 1000.0) > 1 um)
+      report "Assertion error.(3)";
+    assert ((1 mm * 10.0) > 1 mm)
+      report "Assertion error.(4)";
+    assert ((10.0  * 1 A) > 1 A)
+      report "Assertion error.(6)";
+    assert ((1000.0 * 1 nm) > 1 nm)
+      report "Assertion error.(7)";
+    assert ((1000.0 * 1 um) > 1 um)
+      report "Assertion error.(8)";
+    assert ((10.0 * 1 mm) > 1 mm)
+      report "Assertion error.(9)";
+    assert ((1 A * 254000.0) > 1 A)
+      report "Assertion error.(16)";
+    assert ((1 mil * 1000.0) > 1 mil)
+      report "Assertion error.(17)";
+    assert ((254000.0 * 1 A) > 1 A)
+      report "Assertion error.(20)";
+    assert ((1000.0 * 1 mil) > 1 mil)
+      report "Assertion error.(21)";
+    assert NOT(    ((1 A  * 10.0) > 1 A)   and
+                   ((1 nm * 1000.0) > 1 nm)and
+                   ((1 um * 1000.0) > 1 um)and
+                   ((1 mm * 10.0) > 1 mm)   and
+                   ((10.0  * 1 A) > 1 A)   and
+                   ((1000.0 * 1 nm) > 1 nm)and
+                   ((1000.0 * 1 um) > 1 um)and
+                   ((10.0 * 1 mm) > 1 mm)   and
+                   ((1 A * 254000.0) > 1 A)   and
+                   ((1 mil * 1000.0) > 1 mil)   and
+                   ((254000.0 * 1 A) > 1 A)   and
+                   ((1000.0 * 1 mil) > 1 mil)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02292"
+      severity NOTE;
+    assert (    ((1 A  * 10.0) > 1 A)   and
+                ((1 nm * 1000.0) > 1 nm)and
+                ((1 um * 1000.0) > 1 um)and
+                ((1 mm * 10.0) > 1 mm)   and
+                ((10.0  * 1 A) > 1 A)   and
+                ((1000.0 * 1 nm) > 1 nm)and
+                ((1000.0 * 1 um) > 1 um)and
+                ((10.0 * 1 mm) > 1 mm)   and
+                ((1 A * 254000.0) > 1 A)   and
+                ((1 mil * 1000.0) > 1 mil)   and
+                ((254000.0 * 1 A) > 1 A)   and
+                ((1000.0 * 1 mil) > 1 mil)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd
new file mode 100644
index 0000000..375e703
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2293.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02293ent IS
+END c07s02b06x00p32n01i02293ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02293arch OF c07s02b06x00p32n01i02293ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 us * 1000.0) > 1 us)
+      report "Assertion error.(31)";
+    assert ((1 ms * 1000.0) > 1 ms)
+      report "Assertion error.(32)";
+    assert ((1 sec * 60.0)  > 1 sec)
+      report "Assertion error.(33)";
+    wait for 5 us;
+    assert NOT(    ((1 us * 1000.0) > 1 us)   and
+                   ((1 ms * 1000.0) > 1 ms)   and
+                   ((1 sec * 60.0)  > 1 sec)   and
+                   ((1000.0 * 1 us) > 1 us)   and
+                   ((1000.0 * 1 ms) > 1 ms)   and
+                   ((60.0 * 1 sec)  > 1 sec)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02293"
+      severity NOTE;
+    assert (    ((1 us * 1000.0) > 1 us)   and
+                ((1 ms * 1000.0) > 1 ms)   and
+                ((1 sec * 60.0)  > 1 sec)   and
+                ((1000.0 * 1 us) > 1 us)   and
+                ((1000.0 * 1 ms) > 1 ms)   and
+                ((60.0 * 1 sec)  > 1 sec)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02293 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02293arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd
new file mode 100644
index 0000000..6847fa6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2294.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02294ent IS
+END c07s02b06x00p32n01i02294ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02294arch OF c07s02b06x00p32n01i02294ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 min * 60.0)  > 1 min)
+      report "Assertion error.(34)";
+    assert ((60.0 * 1 min)  > 1 min)
+      report "Assertion error.(41)";
+    wait for 5 ms;
+    assert NOT(    ((1 min * 60.0)  > 1 min)   and
+                   ((60.0 * 1 min)  > 1 min)   ) 
+      report "***PASSED TEST: c07s02b06x00p32n01i02294"
+      severity NOTE;
+    assert (    ((1 min * 60.0)  > 1 min)   and
+                ((60.0 * 1 min)  > 1 min)   ) 
+      report "***FAILED TEST: c07s02b06x00p32n01i02294 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd
new file mode 100644
index 0000000..2ef64fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2295.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02295ent IS
+END c07s02b06x00p33n01i02295ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02295arch OF c07s02b06x00p33n01i02295ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 us / 1000) = 1 ns);
+    assert ((1 ns / 1000) = 1 ps);
+    assert ((1 ps / 1000) = 1 fs);
+    wait for 5 fs;
+    assert NOT(    ((1 us / 1000) = 1 ns)   and
+                   ((1 ns / 1000) = 1 ps)   and
+                   ((1 ps / 1000) = 1 fs)   )
+      report "***PASSED TEST: c07s02b06x00p33n01i02295"
+      severity NOTE;
+    assert (    ((1 us / 1000) = 1 ns)   and
+                ((1 ns / 1000) = 1 ps)   and
+                ((1 ps / 1000) = 1 fs)   )
+      report "***FAILED TEST: c07s02b06x00p33n01i02295 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02295arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd
new file mode 100644
index 0000000..d9948ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2296.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02296ent IS
+END c07s02b06x00p33n01i02296ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02296arch OF c07s02b06x00p33n01i02296ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert NOT(   ((1 cm / 10) = 1 mm)   and
+                  ((1 mm / 1000) = 1 um)   and
+                  ((1 um / 1000) = 1 nm)   and
+                  ((1 nm / 10) = 1 A))
+      report "***PASSED TEST: c07s02b06x00p33n01i02296"
+      severity NOTE;
+    assert (   ((1 cm / 10) = 1 mm)   and
+               ((1 mm / 1000) = 1 um)   and
+               ((1 um / 1000) = 1 nm)   and
+               ((1 nm / 10) = 1 A))
+      report "***FAILED TEST: c07s02b06x00p33n01i02296 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02296arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd
new file mode 100644
index 0000000..f1fd555
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2297.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02297ent IS
+END c07s02b06x00p33n01i02297ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02297arch OF c07s02b06x00p33n01i02297ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 min / 60)    = 1 sec);
+    assert ((1 sec / 1000)    = 1 ms);
+    assert ((1 ms / 1000)    = 1 us);
+    wait for 5 us;
+    assert NOT(   ((1 min / 60)    = 1 sec)   and
+                  ((1 sec / 1000) = 1 ms)      and
+                  ((1 ms / 1000)    = 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p33n01i02297"
+      severity NOTE;
+    assert (   ((1 min / 60)    = 1 sec)   and
+               ((1 sec / 1000) = 1 ms)      and
+               ((1 ms / 1000)    = 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p33n01i02297 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02297arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd
new file mode 100644
index 0000000..3520ee0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02298ent IS
+END c07s02b06x00p35n01i02298ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 ns / 1000.0) < 1 ns);
+    assert ((1 ps / 1000.0) < 1 ps);
+    assert ((1 fs / 1000.0) < 1 fs);
+    wait for 5 fs;
+    assert NOT(    ((1 ns / 1000.0) < 1 ns)   and
+                   ((1 ps / 1000.0) < 1 ps)   and
+                   ((1 fs / 1000.0) < 1 fs))   
+      report "***PASSED TEST: c07s02b06x00p35n01i02298"
+      severity NOTE;
+    assert (    ((1 ns / 1000.0) < 1 ns)   and
+                ((1 ps / 1000.0) < 1 ps)   and
+                ((1 fs / 1000.0) < 1 fs))   
+      report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02298arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd
new file mode 100644
index 0000000..a828124
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02299ent IS
+END c07s02b06x00p35n01i02299ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+
+  BEGIN
+    -- Test simple user-defined physical type * integer expressions.
+    assert ((1 cm / 10.0) < 1 cm);
+    assert ((1 mm / 1000.0) < 1 mm);
+    assert ((1 um / 1000.0) < 1 um);
+    assert ((1 nm / 10.0) < 1 nm);
+    wait for 5 ns;
+    assert NOT(    ((1 cm / 10.0) < 1 cm)   and
+                   ((1 mm / 1000.0) < 1 mm)and
+                   ((1 um / 1000.0) < 1 um)and
+                   ((1 nm / 10.0) < 1 nm)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02299"
+      severity NOTE;
+    assert (    ((1 cm / 10.0) < 1 cm)   and
+                ((1 mm / 1000.0) < 1 mm)and
+                ((1 um / 1000.0) < 1 um)and
+                ((1 nm / 10.0) < 1 nm)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd
new file mode 100644
index 0000000..61b2a53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc23.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00023ent IS
+END c04s02b00x00p09n03i00023ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00023arch OF c04s02b00x00p09n03i00023ent IS
+  type    T1 is     range 0  to 100;
+  subtype T2 is T1 range 20 to 80 ;
+  subtype T3 is T2 range 40 to 60 ;  -- No_failure_here
+  subtype T4 is T3 range 50 to 50 ;
+BEGIN
+  TESTING: PROCESS
+    variable k : T4 := 50;
+  BEGIN
+    assert NOT(k=50) 
+      report "***PASSED TEST: c04s02b00x00p09n03i00023"
+      severity NOTE;
+    assert (k=50) 
+      report "***FAILED TEST: c04s02b00x00p09n03i00023 - Range constraints for the subtype declarations contradict the range of the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n03i00023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd
new file mode 100644
index 0000000..966021b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00230ent IS
+END c03s01b02x00p02n01i00230ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
+  type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 11;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00230" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00230arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd
new file mode 100644
index 0000000..808e2e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2300.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02300ent IS
+END c07s02b06x00p35n01i02300ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02300arch OF c07s02b06x00p35n01i02300ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 sec / 1000.0) < 1 sec);
+    assert ((1 ms / 1000.0) < 1 ms);
+    assert ((1 us / 1000.0) < 1 us);
+    wait for 5 us;
+    assert NOT(    ((1 sec / 1000.0) < 1 sec)   and
+                   ((1 ms / 1000.0) < 1 ms)   and
+                   ((1 us / 1000.0) < 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02300"
+      severity NOTE;
+    assert (    ((1 sec / 1000.0) < 1 sec)   and
+                ((1 ms / 1000.0) < 1 ms)   and
+                ((1 us / 1000.0) < 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02300 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02300arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd
new file mode 100644
index 0000000..3f9f088
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2301.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02301ent IS
+END c07s02b06x00p35n01i02301ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02301arch OF c07s02b06x00p35n01i02301ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 hr / 60.0) < 1 hr);
+    assert ((1 min / 60.0) < 1 min);
+    wait for 5 ms;
+    assert NOT(    ((1 hr / 60.0) < 1 hr)      and
+                   ((1 min / 60.0) < 1 min)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02301"
+      severity NOTE;
+    assert (    ((1 hr / 60.0) < 1 hr)      and
+                ((1 min / 60.0) < 1 min)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02301 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02301arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd
new file mode 100644
index 0000000..773a0ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2302.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02302ent IS
+END c07s02b06x00p37n01i02302ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02302arch OF c07s02b06x00p37n01i02302ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 us / 1 ns) = 1000);
+    assert ((1 ns / 1 ps) = 1000);
+    assert ((1 ps / 1 fs) = 1000);
+    wait for 5 fs;
+    assert NOT(    ((1 us / 1 ns) = 1000)   and
+                   ((1 ns / 1 ps) = 1000)   and
+                   ((1 ps / 1 fs) = 1000)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02302"
+      severity NOTE;
+    assert (    ((1 us / 1 ns) = 1000)   and
+                ((1 ns / 1 ps) = 1000)   and
+                ((1 ps / 1 fs) = 1000)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02302 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02302arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd
new file mode 100644
index 0000000..811f3f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02303ent IS
+END c07s02b06x00p37n01i02303ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    -- Test dividing user-defined physical type values.
+    assert ((1 cm / 1 mm) = 10);
+    assert ((1 mm / 1 um) = 1000);
+    assert ((1 um / 1 nm) = 1000);
+    assert ((1 nm / 1 A) = 10);
+    wait for 5 ns;
+    assert NOT(    ((1 cm / 1 mm) = 10)   and
+                   ((1 mm / 1 um) = 1000)   and
+                   ((1 um / 1 nm) = 1000)   and
+                   ((1 nm / 1 A) = 10)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02303"
+      severity NOTE;
+    assert (    ((1 cm / 1 mm) = 10)   and
+                ((1 mm / 1 um) = 1000)   and
+                ((1 um / 1 nm) = 1000)   and
+                ((1 nm / 1 A) = 10)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02303arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd
new file mode 100644
index 0000000..0370861
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2304.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02304ent IS
+END c07s02b06x00p37n01i02304ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02304arch OF c07s02b06x00p37n01i02304ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 min / 1 sec) = 60);
+    assert ((1 sec / 1 ms) = 1000);
+    assert ((1 ms / 1 us) = 1000);
+    wait for 5 us;
+    assert NOT(    ((1 min / 1 sec) = 60)   and   
+                   ((1 sec / 1 ms) = 1000)   and
+                   ((1 ms / 1 us) = 1000)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02304"
+      severity NOTE;
+    assert (    ((1 min / 1 sec) = 60)   and   
+                ((1 sec / 1 ms) = 1000)   and
+                ((1 ms / 1 us) = 1000)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02304 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02304arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd
new file mode 100644
index 0000000..4baba80
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2305.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02305ent IS
+END c07s02b06x00p37n01i02305ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02305arch OF c07s02b06x00p37n01i02305ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 hr / 1 min) = 60);
+    assert ((1 min / 1 sec) = 60);
+    wait for 5 sec;
+    assert NOT(    ((1 hr / 1 min) = 60)   and
+                   ((1 min / 1 sec) = 60)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02305"
+      severity NOTE;
+    assert (    ((1 hr / 1 min) = 60)   and
+                ((1 min / 1 sec) = 60)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02305 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02305arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd
new file mode 100644
index 0000000..da8b698
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2307.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02307ent IS
+END c07s02b07x00p01n01i02307ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02307arch OF c07s02b07x00p01n01i02307ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : integer := abs 10;
+  BEGIN
+    assert NOT(x = 10) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02307" 
+      severity NOTE;
+    assert (x = 10) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02307 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02307arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd
new file mode 100644
index 0000000..ae72cf5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2308.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02308ent IS
+END c07s02b07x00p01n01i02308ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02308arch OF c07s02b07x00p01n01i02308ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : real := abs 10.5;
+  BEGIN
+    assert NOT(x = 10.5) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02308" 
+      severity NOTE;
+    assert (x = 10.5) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02308 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02308arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd
new file mode 100644
index 0000000..cc07ae9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2309.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02309ent IS
+END c07s02b07x00p01n01i02309ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02309arch OF c07s02b07x00p01n01i02309ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    constant b : phys := abs (10 p2);
+  BEGIN
+    assert NOT(b = 100 p1) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02309" 
+      severity NOTE;
+    assert (b = 100 p1) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02309 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd
new file mode 100644
index 0000000..8c48162
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd
@@ -0,0 +1,175 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02324ent IS
+END c07s02b07x00p01n01i02324ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV1    : INTEGER;
+    variable INTV2    : INTEGER;
+    variable INTV3    : INTEGER;
+    variable INTV4    : INTEGER;
+    variable INTV5    : INTEGER;
+    variable INTV6    : INTEGER;
+    variable INTV7    : INTEGER;
+    variable INTV8    : INTEGER;
+    variable REALV1   : REAL;
+    variable REALV2   : REAL;
+    variable REALV3   : REAL;
+    variable REALV4   : REAL;
+    variable REALV5   : REAL;
+    variable REALV6   : REAL;
+    variable REALV7   : REAL;
+    variable REALV8   : REAL;
+  BEGIN
+    -- Test absolute value of integer literals and variables.
+    INTV1 := abs (-5);
+    assert (INTV1 = 5)
+      report "Assertion Violation(1)";
+    INTV2 := abs 5;
+    assert (INTV2 = 5)
+      report "Assertion Violation(2)";
+    INTV3 := abs 0;
+    assert (INTV3 = 0)
+      report "Assertion Violation(3)";
+    INTV4 := abs INTEGER'HIGH;
+    assert (INTV4 = INTEGER'HIGH)
+      report "Assertion Violation(4)";
+    
+    INTV5 := -5;
+    INTV5 := abs INTV5;
+    assert (INTV5 = 5)
+      report "Assertion Violation(5)";
+    INTV6 := 5;
+    INTV6 := abs 5;
+    assert (INTV6 = 5)
+      report "Assertion Violation(6)";
+    INTV7 := 0;
+    INTV7 := abs 0;
+    assert (INTV7 = 0)
+      report "Assertion Violation(7)";
+    INTV8 := INTEGER'HIGH;
+    INTV8 := abs INTEGER'HIGH;
+    assert (INTV8 = INTEGER'HIGH)
+      report "Assertion Violation(8)";
+    
+    -- Do the same for the predefined physical type TIME.
+    assert (abs (-5 ns) = 5 ns)
+      report "Assertion Violation(9)";
+    assert (abs 5 ns = 5 ns)
+      report "Assertion Violation(10)";
+    assert (abs 0 fs = 0 fs)
+      report "Assertion Violation(11)";
+    assert (abs TIME'HIGH = TIME'HIGH)
+      report "Assertion Violation(12)";
+    
+    -- Test absolute value of real literals and variables.
+    REALV1 := abs (-5.0);
+    assert (REALV1 = 5.0)
+      report "Assertion Violation(13)";
+    REALV2 := abs 5.0;
+    assert (REALV2 = 5.0)
+      report "Assertion Violation(14)";
+    REALV3 := abs 0.0;
+    assert (REALV3 = 0.0)
+      report "Assertion Violation(15)";
+    REALV4 := abs REAL'HIGH;
+    assert (REALV4 = REAL'HIGH)
+      report "Assertion Violation(16)";
+
+    REALV5 := -5.0;
+    REALV5 := abs REALV5;
+    assert (REALV5 = 5.0)
+      report "Assertion Violation(17)";
+    REALV6 := 5.0;
+    REALV6 := abs 5.0;
+    assert (REALV6 = 5.0)
+      report "Assertion Violation(18)";
+    REALV7 := 0.0;
+    REALV7 := abs 0.0;
+    assert (REALV7 = 0.0)
+      report "Assertion Violation(19)";
+    REALV8 := REAL'HIGH;
+    REALV8 := abs REAL'HIGH;
+    assert (REALV8 = REAL'HIGH)
+      report "Assertion Violation(20)";
+    wait for 5 ns;
+    assert NOT(   (INTV1 = 5)      and
+                  (INTV2 = 5)      and
+                  (INTV3 = 0)      and
+                  (INTV4 = INTEGER'HIGH)   and
+                  (INTV5 = 5)      and
+                  (INTV6 = 5)      and
+                  (INTV7 = 0)      and
+                  (INTV8 = INTEGER'HIGH)   and
+                  (abs (-5 ns) = 5 ns)   and
+                  (abs 5 ns = 5 ns)   and
+                  (abs 0 fs = 0 fs)   and
+                  (abs TIME'HIGH = TIME'HIGH)   and
+                  (REALV1 = 5.0)      and
+                  (REALV2 = 5.0)      and
+                  (REALV3 = 0.0)      and
+                  (REALV4 = REAL'HIGH)   and
+                  (REALV5 = 5.0)      and
+                  (REALV6 = 5.0)      and
+                  (REALV7 = 0.0)      and
+                  (REALV8 = REAL'HIGH)   ) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02324" 
+      severity NOTE;
+    assert (   (INTV1 = 5)      and
+               (INTV2 = 5)      and
+               (INTV3 = 0)      and
+               (INTV4 = INTEGER'HIGH)   and
+               (INTV5 = 5)      and
+               (INTV6 = 5)      and
+               (INTV7 = 0)      and
+               (INTV8 = INTEGER'HIGH)   and
+               (abs (-5 ns) = 5 ns)   and
+               (abs 5 ns = 5 ns)   and
+               (abs 0 fs = 0 fs)   and
+               (abs TIME'HIGH = TIME'HIGH)   and
+               (REALV1 = 5.0)      and
+               (REALV2 = 5.0)      and
+               (REALV3 = 0.0)      and
+               (REALV4 = REAL'HIGH)   and
+               (REALV5 = 5.0)      and
+               (REALV6 = 5.0)      and
+               (REALV7 = 0.0)      and
+               (REALV8 = REAL'HIGH)   ) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02324arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd
new file mode 100644
index 0000000..ae13b74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2325.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i02325ent IS
+END c07s01b00x00p07n01i02325ent;
+
+ARCHITECTURE c07s01b00x00p07n01i02325arch OF c07s01b00x00p07n01i02325ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+  BEGIN
+    k := abs (-10.3);
+    assert NOT( k = 10.3 )
+      report "***PASSED TEST: c07s01b00x00p07n01i02325"
+      severity NOTE;
+    assert ( k = 10.3 )
+      report "***FAILED TEST: c07s01b00x00p07n01i02325 - The result of the 'abs' operation must be the absolute value of the operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i02325arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd
new file mode 100644
index 0000000..5a8e5cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2326.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i02326ent IS
+END c07s01b00x00p07n01i02326ent;
+
+ARCHITECTURE c07s01b00x00p07n01i02326arch OF c07s01b00x00p07n01i02326ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1, r2, r3, r4 : real;
+  BEGIN
+    
+    r1 := 69.0;
+    r2 := 50.0;
+    r3 := (-69.0);
+    r4 := (-50.0);
+    wait for 5 ns; 
+    assert NOT(   ( r1 = abs(r3))   and
+                  ( r2 = abs(r4))   and
+                  ( 50.0 = abs(-50.0))   and
+                  ( (-25.0) = (-abs(-25.0)))   and
+                  ( 3.14E-2 = abs(-3.14E-2))   and
+                  ( (-0.379) = (-abs(-0.379)))   ) 
+      report "***PASSED TEST: c07s01b00x00p07n01i02326"
+      severity NOTE;
+    assert (   ( r1 = abs(r3))   and
+               ( r2 = abs(r4))   and
+               ( 50.0 = abs(-50.0))   and
+               ( (-25.0) = (-abs(-25.0)))   and
+               ( 3.14E-2 = abs(-3.14E-2))   and
+               ( (-0.379) = (-abs(-0.379)))   ) 
+      report "***FAILED TEST: c07s01b00x00p07n01i02326 - The result of the 'abs' operation must be the absolute value of the operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i02326arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd
new file mode 100644
index 0000000..522af65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2329.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02329ent IS
+END c07s02b07x00p02n02i02329ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02329arch OF c07s02b07x00p02n02i02329ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    function L1 ( A : NEW_INT; B : integer ) return NEW_INT is
+    begin
+      return A ** B;  -- context 1
+    end L1;
+    variable k : NEW_INT := 0;
+  BEGIN
+    k := L1(2,2);
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02329"
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02329 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02329arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd
new file mode 100644
index 0000000..827fc46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02330ent IS
+END c07s02b07x00p02n02i02330ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    variable k : NEW_INT := 2 ** 5;
+  BEGIN
+    assert NOT(k=32) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02330" 
+      severity NOTE;
+    assert (k=32) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02330arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd
new file mode 100644
index 0000000..3121f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2331.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02331ent IS
+END c07s02b07x00p02n02i02331ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02331arch OF c07s02b07x00p02n02i02331ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    variable k : NEW_INT := 5;
+  BEGIN
+    k := 2 ** 2;
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02331" 
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02331 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02331arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd
new file mode 100644
index 0000000..b52012c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2332.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02332ent IS
+END c07s02b07x00p02n02i02332ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02332arch OF c07s02b07x00p02n02i02332ent IS
+  type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+  signal k : NEW_INT := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 2 ** 2;
+    wait for 1 ns;
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02332" 
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02332 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02332arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd
new file mode 100644
index 0000000..f81a5f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc234.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00234ent IS
+END c03s01b02x00p02n01i00234ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00234arch OF c03s01b02x00p02n01i00234ent IS
+  type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 11;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00234"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00234 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00234arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd
new file mode 100644
index 0000000..5d92f5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2359.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p06n01i02359ent IS
+END c07s02b07x00p06n01i02359ent;
+
+ARCHITECTURE c07s02b07x00p06n01i02359arch OF c07s02b07x00p06n01i02359ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1,r2,r3,r4,r5,r6   : real;
+    variable r7,r8,r9,r10      : real;
+    variable i1         : integer;
+  BEGIN
+
+    r2 := 2.0;
+    r3 := 10.0;
+    i1 := 10;
+    r1 := 2.0 ** 10;
+    r4 := r2 ** i1;
+    r5 := (-2.0)**10;
+    r6 := 0.0 ** i1;
+    r7 := 0.0 ** 5;
+    r8 := 2.0;
+    r9 := r8 ** 0;
+    r10:= r8 ** (-0);
+    wait for 5 ns;
+    assert NOT(    ( r1 = r4 )   and
+                   ( r1 = 1024.0)   and
+                   ( r1 = r5 )   and
+                   ( r6 = 0.0)   and
+                   ( r6 = r7 )   and
+                   ( r9 = 1.0 )   and
+                   ( r10= r9 )   )
+      report "***PASSED TEST: c07s02b07x00p06n01i02359"
+      severity NOTE;
+    assert (    ( r1 = r4 )   and
+                ( r1 = 1024.0)   and
+                ( r1 = r5 )   and
+                ( r6 = 0.0)   and
+                ( r6 = r7 )   and
+                ( r9 = 1.0 )   and
+                ( r10= r9 )   )
+      report "***FAILED TEST: c07s02b07x00p06n01i02359 - Unary operator exponentiation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p06n01i02359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd
new file mode 100644
index 0000000..ad765ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2360.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n01i02360ent IS
+END c07s02b07x00p10n01i02360ent;
+
+ARCHITECTURE c07s02b07x00p10n01i02360arch OF c07s02b07x00p10n01i02360ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+  BEGIN
+    k := 2.5**4;
+    wait for 5 ns;
+    assert NOT(k=39.0625)
+      report "***PASSED TEST: c07s02b07x00p10n01i02360"
+      severity NOTE;
+    assert (k=39.0625)
+      report "***FAILED TEST: c07s02b07x00p10n01i02360 - Exponentiation with an integer exponent is equivalent to repeated multiplication of the left operand by itself."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n01i02360arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd
new file mode 100644
index 0000000..94ca3ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2363.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n01i02363ent IS
+END c07s02b07x00p10n01i02363ent;
+
+ARCHITECTURE c07s02b07x00p10n01i02363arch OF c07s02b07x00p10n01i02363ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable INTV : INTEGER;
+    variable res  : real;
+  BEGIN
+    INTV := -2;
+    res  := 3.0 ** INTV;
+    wait for 5 ns;
+    assert NOT((0.1111111 < res) and (res < 0.1111112))
+      report "***PASSED TEST: c07s02b07x00p10n01i02363"
+      severity NOTE;
+    assert ((0.1111111 < res) and (res < 0.1111112))
+      report "***FAILED TEST: c07s02b07x00p10n01i02363 - Exponentiation of a real with a negative exponent test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n01i02363arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd
new file mode 100644
index 0000000..0cb2b28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2364.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02364ent IS
+END c07s03b01x00p01n01i02364ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02364arch OF c07s03b01x00p01n01i02364ent IS
+  signal S3 : Integer := 1111 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3 <= 5555;
+    wait for 1 ns;
+    assert NOT(S3 = 5555)
+      report "***PASSED TEST: c07s03b01x00p01n01i02364"
+      severity NOTE;
+    assert (S3 = 5555)
+      report "***FAILED TEST: c07s03b01x00p01n01i02364 - A literal is a numeric literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd
new file mode 100644
index 0000000..7206f95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2365.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02365ent IS
+END c07s03b01x00p01n01i02365ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02365arch OF c07s03b01x00p01n01i02365ent IS
+  type    MVL is ('0','1','X','Z') ;
+  signal    S2  : MVL := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= 'X';
+    wait for 1 ns;
+    assert NOT(S2 = 'X')
+      report "***PASSED TEST: c07s03b01x00p01n01i02365"
+      severity NOTE;
+    assert (S2 = 'X')
+      report "***FAILED TEST: c07s03b01x00p01n01i02365 - A literal is an enumeration literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd
new file mode 100644
index 0000000..d59b748
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2366.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02366ent IS
+END c07s03b01x00p01n01i02366ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02366arch OF c07s03b01x00p01n01i02366ent IS
+  constant C1 : STRING := "54LS271" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "54LS271" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02366"
+      severity NOTE;
+    assert ( C1 = "54LS271" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02366 - A literal is a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd
new file mode 100644
index 0000000..62381cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2367.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02367ent IS
+END c07s03b01x00p01n01i02367ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02367arch OF c07s03b01x00p01n01i02367ent IS
+  constant C1 : STRING := "" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02367"
+      severity NOTE;
+    assert ( C1 = "" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02367 - A literal is the literal null." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02367arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd
new file mode 100644
index 0000000..c104af7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2368.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02368ent IS
+END c07s03b01x00p01n01i02368ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02368arch OF c07s03b01x00p01n01i02368ent IS
+  constant C1 : bit_vector(0 to 7) := "01010101" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "01010101" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02368"
+      severity NOTE;
+    assert ( C1 = "01010101" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02368 - A literal is a bit string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02368arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd
new file mode 100644
index 0000000..6bcc22a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p06n02i02369ent IS
+END c07s03b01x00p06n02i02369ent;
+
+ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( O"4777" = B"100_111_111_111" )
+      report "***PASSED TEST: c07s03b01x00p06n02i02369"
+      severity NOTE;
+    assert ( O"4777" = B"100_111_111_111" )
+      report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p06n02i02369arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd
new file mode 100644
index 0000000..02cacea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2370.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p06n02i02370ent IS
+END c07s03b01x00p06n02i02370ent;
+
+ARCHITECTURE c07s03b01x00p06n02i02370arch OF c07s03b01x00p06n02i02370ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a new string type.
+    type KRING is array( natural range <> ) of CHARACTER;
+    variable K : KRING( 1 to 10 ) := "it is cold";
+  BEGIN
+    assert NOT( K = "it is cold" )
+      report "***PASSED TEST: c07s03b01x00p06n02i02370"
+      severity NOTE;
+    assert ( K = "it is cold" )
+      report "***FAILED TEST: c07s03b01x00p06n02i02370 - The type of the literal is determinable from the context in which it appears."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p06n02i02370arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd
new file mode 100644
index 0000000..3cde245
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2371.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p07n01i02371ent IS
+END c07s03b01x00p07n01i02371ent;
+
+ARCHITECTURE c07s03b01x00p07n01i02371arch OF c07s03b01x00p07n01i02371ent IS
+  constant S1 : BIT_VECTOR := B"111_111_110";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((S1'LEFT = 0) and (S1'RIGHT = 8))
+      report "***PASSED TEST: c07s03b01x00p07n01i02371"
+      severity NOTE;
+    assert ((S1'LEFT = 0) and (S1'RIGHT = 8))
+      report "***FAILED TEST: c07s03b01x00p07n01i02371 - The number of elements in the aggregate is equal to the length of the string or bit string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p07n01i02371arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd
new file mode 100644
index 0000000..3f2367b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2372.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p07n02i02372ent IS
+END c07s03b01x00p07n02i02372ent;
+
+ARCHITECTURE c07s03b01x00p07n02i02372arch OF c07s03b01x00p07n02i02372ent IS
+  constant S1 : BIT_VECTOR := B"111_111_110" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((S1'LEFT = 0) and (S1(0) = '1') and (S1'RIGHT = 8) and (S1(8) = '0')) 
+      report "***PASSED TEST: c07s03b01x00p07n02i02372"
+      severity NOTE;
+    assert ((S1'LEFT = 0) and (S1(0) = '1') and (S1'RIGHT = 8) and (S1(8) = '0')) 
+      report "***FAILED TEST: c07s03b01x00p07n02i02372 - Failure in string literal direction test."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p07n02i02372arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd
new file mode 100644
index 0000000..fe5703b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2373.vhd,v 1.1.1.1 2001-08-22 18:20:51 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p08n01i02373ent IS
+END c07s03b01x00p08n01i02373ent;
+
+ARCHITECTURE c07s03b01x00p08n01i02373arch OF c07s03b01x00p08n01i02373ent IS
+
+BEGIN
+   TESTING: PROCESS
+                        -- Redefine the type CHARACTER.
+                        type NEW_CHAR is (
+                            NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
+                            BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI,
+                            DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
+                            CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP,
+
+                            ' ', '!', '"', '#', '$', '%', '&', ''',
+                            '(', ')', '*', '+', ',', '-', '.', '/',
+                            '2', '3', '4', '5', '6', '7',
+                            '8', '9', ':', ';', '<', '=', '>', '?',
+
+                            '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
+                            'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+                            'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
+                            'X', 'Y', 'Z', '[', '\', ']', '^', '_' );
+
+                       -- Local declarations.
+                       variable S : STRING( 1 to 12 );
+                       variable B : BIT_VECTOR( 1 to 2 );
+   BEGIN
+                       -- Should be OK,  non-overloaded literals.
+                       S := "hello, world";
+                       B := B"11";
+         wait for 5 ns;
+   assert NOT(    S = "hello, world"   and
+          B = B"11"      )
+      report "***PASSED TEST: c07s03b01x00p08n01i02373"
+      severity NOTE;
+   assert (    S = "hello, world"   and
+          B = B"11"      )
+      report "***FAILED TEST: c07s03b01x00p08n01i02373 - The graphic characters contained within a string literal should be visible."
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c07s03b01x00p08n01i02373arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd
new file mode 100644
index 0000000..2430a73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2374.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p02n01i02374ent IS
+END c07s03b02x00p02n01i02374ent;
+
+ARCHITECTURE c07s03b02x00p02n01i02374arch OF c07s03b02x00p02n01i02374ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       x1 is array (1 to 2) of integer;
+    constant    v1 :  x1 := (0, 0);   -- Success_here
+  BEGIN
+    assert NOT(v1(1)=0 and v1(2)=0)
+      report "***PASSED TEST: c07s03b02x00p02n01i02374"
+      severity NOTE;
+    assert (v1(1)=0 and v1(2)=0)
+      report "***FAILED TEST: c07s03b02x00p02n01i02374 - The aggregate consists of one or more element associations seperated with commas(,) which are enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p02n01i02374arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd
new file mode 100644
index 0000000..66969a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2378.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p03n01i02378ent IS
+END c07s03b02x00p03n01i02378ent;
+
+ARCHITECTURE c07s03b02x00p03n01i02378arch OF c07s03b02x00p03n01i02378ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x1 is array (1 to 2) of integer;
+    constant v1: x1 := (1 => 0, 2 => 0);   -- Success_here
+  BEGIN
+    assert NOT(v1(1)=0 and v1(2)=0)
+      report "***PASSED TEST: c07s03b02x00p03n01i02378"
+      severity NOTE;
+    assert (v1(1)=0 and v1(2)=0)
+      report "***FAILED TEST: c07s03b02x00p03n01i02378 - The element association consists of (optionally) choices followed by an arrow operator (=>) and an expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p03n01i02378arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd
new file mode 100644
index 0000000..9df473a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2380.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p04n01i02380ent IS
+END c07s03b02x00p04n01i02380ent;
+
+ARCHITECTURE c07s03b02x00p04n01i02380arch OF c07s03b02x00p04n01i02380ent IS
+  type T1 is array (1 to 5) of integer;
+  constant C1 : T1 := (1|2 => 0, others => 4) ; -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
+      report "***PASSED TEST: c07s03b02x00p04n01i02380"
+      severity NOTE;
+    assert (C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
+      report "***FAILED TEST: c07s03b02x00p04n01i02380 - The choices must be one or more choices separated with vertical bars(|)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p04n01i02380arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd
new file mode 100644
index 0000000..388748b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2382.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n02i02382ent IS
+END c07s03b02x00p06n02i02382ent;
+
+ARCHITECTURE c07s03b02x00p06n02i02382arch OF c07s03b02x00p06n02i02382ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype    BYTE    is BIT_VECTOR( 0 to 7 );
+    type    NIBBLE    is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+    variable NIBV1  : NIBBLE;
+    variable NIBV2  : NIBBLE;
+  BEGIN
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV1 := BYTE'( 7 => '0', 6 | 5 | 4 | 3 | 2 | 1 | 0 => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '0' );
+    BYTEV2 := BYTE'( 7 => '1', 0 | 3 | 2 | 4 | 1 | 5 | 6  => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '1' );
+
+    -- 2. Descending next.
+    NIBV1 := NIBBLE'( 3 | 2 | 1 => '1', 0 downto 0 => '0' );
+    assert( NIBV1( 3 ) = '1' );
+    assert( NIBV1( 2 ) = '1' );
+    assert( NIBV1( 1 ) = '1' );
+    assert( NIBV1( 0 ) = '0' );
+    NIBV2 := NIBBLE'( 2 | 3 => '0', 0 downto 0 | 1 => '1' );
+    assert( NIBV2( 3 ) = '0' );
+    assert( NIBV2( 2 ) = '0' );
+    assert( NIBV2( 1 ) = '1' );
+    assert( NIBV2( 0 ) = '1' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV1( 0 ) = '1' )   and
+                   ( BYTEV1( 1 ) = '1' )   and
+                   ( BYTEV1( 2 ) = '1' )   and
+                   ( BYTEV1( 3 ) = '1' )   and
+                   ( BYTEV1( 4 ) = '1' )   and
+                   ( BYTEV1( 5 ) = '1' )   and
+                   ( BYTEV1( 6 ) = '1' )   and
+                   ( BYTEV1( 7 ) = '0' )   and
+                   ( BYTEV2( 0 ) = '0' )   and 
+                   ( BYTEV2( 1 ) = '0' )   and
+                   ( BYTEV2( 2 ) = '0' )   and
+                   ( BYTEV2( 3 ) = '0' )   and
+                   ( BYTEV2( 4 ) = '0' )   and
+                   ( BYTEV2( 5 ) = '0' )   and
+                   ( BYTEV2( 6 ) = '0' )   and
+                   ( BYTEV2( 7 ) = '1' )   and
+                   ( NIBV1( 3 ) = '1' )   and 
+                   ( NIBV1( 2 ) = '1' )   and
+                   ( NIBV1( 1 ) = '1' )   and
+                   ( NIBV1( 0 ) = '0' )   and
+                   ( NIBV2( 3 ) = '0' )   and
+                   ( NIBV2( 2 ) = '0' )   and
+                   ( NIBV2( 1 ) = '1' )   and
+                   ( NIBV2( 0 ) = '1' )   )
+      report "***PASSED TEST: c07s03b02x00p06n02i02382"
+      severity NOTE;
+    assert (    ( BYTEV1( 0 ) = '1' )   and
+                ( BYTEV1( 1 ) = '1' )   and
+                ( BYTEV1( 2 ) = '1' )   and
+                ( BYTEV1( 3 ) = '1' )   and
+                ( BYTEV1( 4 ) = '1' )   and
+                ( BYTEV1( 5 ) = '1' )   and
+                ( BYTEV1( 6 ) = '1' )   and
+                ( BYTEV1( 7 ) = '0' )   and
+                ( BYTEV2( 0 ) = '0' )   and 
+                ( BYTEV2( 1 ) = '0' )   and
+                ( BYTEV2( 2 ) = '0' )   and
+                ( BYTEV2( 3 ) = '0' )   and
+                ( BYTEV2( 4 ) = '0' )   and
+                ( BYTEV2( 5 ) = '0' )   and
+                ( BYTEV2( 6 ) = '0' )   and
+                ( BYTEV2( 7 ) = '1' )   and
+                ( NIBV1( 3 ) = '1' )   and 
+                ( NIBV1( 2 ) = '1' )   and
+                ( NIBV1( 1 ) = '1' )   and
+                ( NIBV1( 0 ) = '0' )   and
+                ( NIBV2( 3 ) = '0' )   and
+                ( NIBV2( 2 ) = '0' )   and
+                ( NIBV2( 1 ) = '1' )   and
+                ( NIBV2( 0 ) = '1' )   )
+      report "***FAILED TEST: c07s03b02x00p06n02i02382 - Named association assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n02i02382arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd
new file mode 100644
index 0000000..0d5e116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2383.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n02i02383ent IS
+END c07s03b02x00p06n02i02383ent;
+
+ARCHITECTURE c07s03b02x00p06n02i02383arch OF c07s03b02x00p06n02i02383ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype    BYTE    is BIT_VECTOR( 0 to 7 );
+    type    NIBBLE    is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+    variable NIBV1  : NIBBLE;
+    variable NIBV2  : NIBBLE;
+  BEGIN
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV1 := BYTE'( 7 => '0', others => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '0' );
+    BYTEV2 := BYTE'( 7 => '1', 0 to 6 => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '1' );
+
+    -- 2. Descending next.
+    NIBV1 := NIBBLE'( 3 downto 1 => '1', 0 downto 0 => '0' );
+    assert( NIBV1( 3 ) = '1' );
+    assert( NIBV1( 2 ) = '1' );
+    assert( NIBV1( 1 ) = '1' );
+    assert( NIBV1( 0 ) = '0' );
+    NIBV2 := NIBBLE'( 1 to 3 => '0', 0 downto 0 => '1' );
+    assert( NIBV2( 3 ) = '0' );
+    assert( NIBV2( 2 ) = '0' );
+    assert( NIBV2( 1 ) = '0' );
+    assert( NIBV2( 0 ) = '1' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV1( 0 ) = '1' )   and
+                   ( BYTEV1( 1 ) = '1' )   and
+                   ( BYTEV1( 2 ) = '1' )   and
+                   ( BYTEV1( 3 ) = '1' )   and
+                   ( BYTEV1( 4 ) = '1' )   and
+                   ( BYTEV1( 5 ) = '1' )   and
+                   ( BYTEV1( 6 ) = '1' )   and
+                   ( BYTEV1( 7 ) = '0' )   and
+                   ( BYTEV2( 0 ) = '0' )   and 
+                   ( BYTEV2( 1 ) = '0' )   and
+                   ( BYTEV2( 2 ) = '0' )   and
+                   ( BYTEV2( 3 ) = '0' )   and
+                   ( BYTEV2( 4 ) = '0' )   and
+                   ( BYTEV2( 5 ) = '0' )   and
+                   ( BYTEV2( 6 ) = '0' )   and
+                   ( BYTEV2( 7 ) = '1' )   and
+                   ( NIBV1( 3 ) = '1' )   and 
+                   ( NIBV1( 2 ) = '1' )   and
+                   ( NIBV1( 1 ) = '1' )   and
+                   ( NIBV1( 0 ) = '0' )   and
+                   ( NIBV2( 3 ) = '0' )   and
+                   ( NIBV2( 2 ) = '0' )   and
+                   ( NIBV2( 1 ) = '0' )   and
+                   ( NIBV2( 0 ) = '1' )   )
+      report "***PASSED TEST: c07s03b02x00p06n02i02383"
+      severity NOTE;
+    assert (    ( BYTEV1( 0 ) = '1' )   and
+                ( BYTEV1( 1 ) = '1' )   and
+                ( BYTEV1( 2 ) = '1' )   and
+                ( BYTEV1( 3 ) = '1' )   and
+                ( BYTEV1( 4 ) = '1' )   and
+                ( BYTEV1( 5 ) = '1' )   and
+                ( BYTEV1( 6 ) = '1' )   and
+                ( BYTEV1( 7 ) = '0' )   and
+                ( BYTEV2( 0 ) = '0' )   and 
+                ( BYTEV2( 1 ) = '0' )   and
+                ( BYTEV2( 2 ) = '0' )   and
+                ( BYTEV2( 3 ) = '0' )   and
+                ( BYTEV2( 4 ) = '0' )   and
+                ( BYTEV2( 5 ) = '0' )   and
+                ( BYTEV2( 6 ) = '0' )   and
+                ( BYTEV2( 7 ) = '1' )   and
+                ( NIBV1( 3 ) = '1' )   and 
+                ( NIBV1( 2 ) = '1' )   and
+                ( NIBV1( 1 ) = '1' )   and
+                ( NIBV1( 0 ) = '0' )   and
+                ( NIBV2( 3 ) = '0' )   and
+                ( NIBV2( 2 ) = '0' )   and
+                ( NIBV2( 1 ) = '0' )   and
+                ( NIBV2( 0 ) = '1' )   )
+      report "***FAILED TEST: c07s03b02x00p06n02i02383 - Named association assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n02i02383arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd
new file mode 100644
index 0000000..5a979a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2384.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n03i02384ent IS
+END c07s03b02x00p06n03i02384ent;
+
+ARCHITECTURE c07s03b02x00p06n03i02384arch OF c07s03b02x00p06n03i02384ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+    type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV : BYTE;
+    variable NIBV  : NIBBLE;
+  BEGIN
+    -- Verify that they were initialized properly.
+    for I in 0 to 7 loop
+      assert( BYTEV( I ) = '0' );
+    end loop;
+    for I in 3 downto 0 loop
+      assert( NIBV( I ) = '0' );
+    end loop;
+
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV := BYTE'( '1','1','1','1','1','1','1','0' );
+    assert( BYTEV( 0 ) = '1' );
+    assert( BYTEV( 1 ) = '1' );
+    assert( BYTEV( 2 ) = '1' );
+    assert( BYTEV( 3 ) = '1' );
+    assert( BYTEV( 4 ) = '1' );
+    assert( BYTEV( 5 ) = '1' );
+    assert( BYTEV( 6 ) = '1' );
+    assert( BYTEV( 7 ) = '0' );
+
+    -- 2. Descending next.
+    NIBV := NIBBLE'( '1','1','1','0' );
+    assert( NIBV( 1 ) = '1' );
+    assert( NIBV( 2 ) = '1' );
+    assert( NIBV( 3 ) = '1' );
+    assert( NIBV( 0 ) = '0' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV( 0 ) = '1' )   and 
+                   ( BYTEV( 1 ) = '1' )   and
+                   ( BYTEV( 2 ) = '1' )   and
+                   ( BYTEV( 3 ) = '1' )   and
+                   ( BYTEV( 4 ) = '1' )   and
+                   ( BYTEV( 5 ) = '1' )   and
+                   ( BYTEV( 6 ) = '1' )   and
+                   ( BYTEV( 7 ) = '0' )   and
+                   ( NIBV( 1 ) = '1' )   and 
+                   ( NIBV( 2 ) = '1' )   and
+                   ( NIBV( 3 ) = '1' )   and
+                   ( NIBV( 0 ) = '0' )   )
+      report "***PASSED TEST: c07s03b02x00p06n03i02384"
+      severity NOTE;
+    assert (    ( BYTEV( 0 ) = '1' )   and 
+                ( BYTEV( 1 ) = '1' )   and
+                ( BYTEV( 2 ) = '1' )   and
+                ( BYTEV( 3 ) = '1' )   and
+                ( BYTEV( 4 ) = '1' )   and
+                ( BYTEV( 5 ) = '1' )   and
+                ( BYTEV( 6 ) = '1' )   and
+                ( BYTEV( 7 ) = '0' )   and
+                ( NIBV( 1 ) = '1' )   and 
+                ( NIBV( 2 ) = '1' )   and
+                ( NIBV( 3 ) = '1' )   and
+                ( NIBV( 0 ) = '0' )   )
+      report "***FAILED TEST: c07s03b02x00p06n03i02384 - Element positional association test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n03i02384arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd
new file mode 100644
index 0000000..767e225
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2387.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02387ent IS
+END c07s03b02x00p07n01i02387ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02387arch OF c07s03b02x00p07n01i02387ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( FALSE, E2 => TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=FALSE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02387" 
+      severity NOTE;
+    assert (S2.E1=FALSE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02387 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd
new file mode 100644
index 0000000..a9fbbfc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2388.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02388ent IS
+END c07s03b02x00p07n01i02388ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02388arch OF c07s03b02x00p07n01i02388ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( TRUE, TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02388" 
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02388 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02388arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd
new file mode 100644
index 0000000..d7ebbaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2389.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02389ent IS
+END c07s03b02x00p07n01i02389ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02389arch OF c07s03b02x00p07n01i02389ent IS
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( E1=>TRUE, E2=>TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02389"
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02389 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02389arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd
new file mode 100644
index 0000000..34dc4b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc239.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00239ent IS
+END c03s01b02x00p04n01i00239ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00239arch OF c03s01b02x00p04n01i00239ent IS
+  type t3 is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1); 
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00239" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00239 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00239arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd
new file mode 100644
index 0000000..e01aad7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2390.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02390ent IS
+END c07s03b02x00p07n01i02390ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02390arch OF c07s03b02x00p07n01i02390ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( E1=>TRUE, E2=>TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02390" 
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02390 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02390arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd
new file mode 100644
index 0000000..600e531
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2391.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02391ent IS
+END c07s03b02x00p07n01i02391ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02391arch OF c07s03b02x00p07n01i02391ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2,E3,E4,E5 : BOOLEAN;
+                      end record;
+  signal S3 : ARRAY_TYPE(1 to 5);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3 <= ( 5 => TRUE, 4|2 downto 1 => TRUE, 3 => TRUE);
+    -- named associations may appear in any order.
+    wait for 1 ns;
+    assert NOT(S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02391" 
+      severity NOTE;
+    assert (S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02391 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02391arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd
new file mode 100644
index 0000000..b8d5d94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2392.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02392ent IS
+END c07s03b02x00p07n01i02392ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02392arch OF c07s03b02x00p07n01i02392ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2,E3,E4,E5 : BOOLEAN;
+                      end record;
+  signal S4 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S4 <= ( E5 => TRUE, E4|E2|E1 => TRUE, E3 => TRUE);
+    -- named associations may appear in any order.
+    wait for 1 ns;
+    assert NOT((S4.E1=TRUE) and (S4.E2=TRUE) and (S4.E3=TRUE) and (S4.E4=TRUE) and (S4.E5=TRUE)) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02392" 
+      severity NOTE;
+    assert ((S4.E1=TRUE) and (S4.E2=TRUE) and (S4.E3=TRUE) and (S4.E4=TRUE) and (S4.E5=TRUE)) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02392 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd
new file mode 100644
index 0000000..2eb7b0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n02i02394ent IS
+END c07s03b02x00p07n02i02394ent;
+
+ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t26 is record
+                  elem_1: integer;
+                end record;
+    variable v26 : t26;
+  BEGIN
+    v26 := (elem_1 => 26);
+    assert NOT(v26.elem_1=26) 
+      report "***PASSED TEST: c07s03b02x00p07n02i02394"
+      severity NOTE;
+    assert (v26.elem_1=26) 
+      report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n02i02394arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd
new file mode 100644
index 0000000..fcbcdaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2395.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n02i02395ent IS
+END c07s03b02x00p07n02i02395ent;
+
+ARCHITECTURE c07s03b02x00p07n02i02395arch OF c07s03b02x00p07n02i02395ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype ONE is BIT_VECTOR( 0 to 0);
+
+    -- Declare array variables of these types.
+    variable ONEV1 : ONE;
+    variable ONEV2 : ONE;
+  BEGIN
+    ONEV1 := ONE'( 0 => '0' );
+    assert( ONEV1( 0 ) = '0' );
+    ONEV2 := ONE'( 0 => '1' );
+    assert( ONEV2( 0 ) = '1' );
+    assert NOT(( ONEV1( 0 ) = '0' )   and ( ONEV2( 0 ) = '1' ))
+      report "***PASSED TEST: c07s03b02x00p07n02i02395" 
+      severity NOTE;
+    assert (( ONEV1( 0 ) = '0' )   and ( ONEV2( 0 ) = '1' ))
+      report "***FAILED TEST: c07s03b02x00p07n02i02395 - Aggregate specification should be using named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n02i02395arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd
new file mode 100644
index 0000000..96ddff3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02396ent IS
+END c07s03b02x00p07n01i02396ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+
+    -- Declare array variables of these types.
+    variable BYTEV : BYTE;
+  BEGIN
+    BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
+                    2 => '1', 0 => '1', 5 => '0',
+                    3 => '0', 1 => '0' );
+    assert( BYTEV( 1 ) = '0' );
+    assert( BYTEV( 3 ) = '0' );
+    assert( BYTEV( 5 ) = '0' );
+    assert( BYTEV( 7 ) = '0' );
+    assert( BYTEV( 0 ) = '1' );
+    assert( BYTEV( 2 ) = '1' );
+    assert( BYTEV( 4 ) = '1' );
+    assert( BYTEV( 6 ) = '1' );
+    wait for 1 ns;
+    assert NOT(   ( BYTEV( 1 ) = '0' )   and 
+                  ( BYTEV( 3 ) = '0' )   and 
+                  ( BYTEV( 5 ) = '0' )   and 
+                  ( BYTEV( 7 ) = '0' )   and 
+                  ( BYTEV( 0 ) = '1' )   and 
+                  ( BYTEV( 2 ) = '1' )   and 
+                  ( BYTEV( 4 ) = '1' )   and 
+                  ( BYTEV( 6 ) = '1' ))
+      report "***PASSED TEST: c07s03b02x00p07n01i02396" 
+      severity NOTE;
+    assert (   ( BYTEV( 1 ) = '0' )   and 
+               ( BYTEV( 3 ) = '0' )   and 
+               ( BYTEV( 5 ) = '0' )   and 
+               ( BYTEV( 7 ) = '0' )   and 
+               ( BYTEV( 0 ) = '1' )   and 
+               ( BYTEV( 2 ) = '1' )   and 
+               ( BYTEV( 4 ) = '1' )   and 
+               ( BYTEV( 6 ) = '1' ))
+      report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02396arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd
new file mode 100644
index 0000000..991b85a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n01i02399ent IS
+END c07s03b02x00p08n01i02399ent;
+
+ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_2 : real;
+                  ele_3 : boolean;
+                end record;
+    variable v23 : rec;
+  BEGIN
+    v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
+    assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE)) 
+      report "***PASSED TEST: c07s03b02x00p08n01i02399" 
+      severity NOTE;
+    assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE)) 
+      report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n01i02399arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd
new file mode 100644
index 0000000..ddbe215
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc24.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n01i00024ent IS
+END c04s02b00x00p10n01i00024ent;
+
+ARCHITECTURE c04s02b00x00p10n01i00024arch OF c04s02b00x00p10n01i00024ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    -- Define an ascending subtype.
+    subtype ASC is INTEGER range 0 to 1;
+
+    -- Define a descending subtype.
+    subtype DES is INTEGER range 1 to 0;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+    -- Test the direction of the ascending range.
+    PREV := -1;
+    for I in ASC loop
+      if (I > PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 2;
+    for I in DES loop
+      if (I < PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST:c04s02b00x00p10n01i00024"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n01i00024 - The direction of a discrete subtype indication is the same as the direction of the range constraint that appears as the constraint of the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n01i00024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd
new file mode 100644
index 0000000..de9f1b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2400.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n02i02400ent IS
+END c07s03b02x00p08n02i02400ent;
+
+ARCHITECTURE c07s03b02x00p08n02i02400arch OF c07s03b02x00p08n02i02400ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t18 is array (1 to 5) of integer;
+    variable v18 : t18;
+  BEGIN
+    v18 := (1 to 2 => 18, others => 0);  -- discrete range in an
+                                         -- array aggregate allowed.
+    assert NOT(v18(1)=18 and v18(2)=18 and v18(3)=0 and v18(4)=0 and v18(5)=0)
+      report "***PASSED TEST: c07s03b02x00p08n02i02400"
+      severity NOTE;
+    assert (v18(1)=18 and v18(2)=18 and v18(3)=0 and v18(4)=0 and v18(5)=0)
+      report "***FAILED TEST: c07s03b02x00p08n02i02400 - An element association with a choice that is a discrete range is allowed in an array aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n02i02400arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd
new file mode 100644
index 0000000..c3c1545
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2401.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n02i02401ent IS
+END c07s03b02x00p08n02i02401ent;
+
+ARCHITECTURE c07s03b02x00p08n02i02401arch OF c07s03b02x00p08n02i02401ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t18 is array (1 to 5) of integer;
+    variable v18 : t18;
+  BEGIN
+    v18 := (1+ 2 => 18, others => 0);  -- discrete range in an
+                                           -- array aggregate allowed.
+    assert NOT(v18(1)=0 and v18(2)=0 and v18(3)=18 and v18(4)=0 and v18(5)=0)
+      report "***PASSED TEST: c07s03b02x00p08n02i02401"
+      severity NOTE;
+    assert (v18(1)=0 and v18(2)=0 and v18(3)=18 and v18(4)=0 and v18(5)=0)
+      report "***FAILED TEST: c07s03b02x00p08n02i02401 - An element association with a choice that is a discrete range is allowed in an array aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n02i02401arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd
new file mode 100644
index 0000000..787aff9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2403.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02403ent IS
+END c07s03b02x00p08n05i02403ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02403arch OF c07s03b02x00p08n05i02403ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  a: integer;
+                  b: integer;
+                  c: integer;
+                  d: integer;
+                end record;
+    constant y: rec := (a => 12, others => 10);
+  BEGIN
+    assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
+      report "***PASSED TEST: c07s03b02x00p08n05i02403"
+      severity NOTE;
+    assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
+      report "***FAILED TEST: c07s03b02x00p08n05i02403 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd
new file mode 100644
index 0000000..59f8878
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2404.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02404ent IS
+END c07s03b02x00p08n05i02404ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02404arch OF c07s03b02x00p08n05i02404ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array (1 to 3) of integer;
+    constant y: arr := (1 => 12, others => 0);
+  BEGIN
+    assert NOT(y(1)=12 and y(2)=0 and y(3)=0)
+      report "***PASSED TEST: c07s03b02x00p08n05i02404"
+      severity NOTE;
+    assert (y(1)=12 and y(2)=0 and y(3)=0)
+      report "***FAILED TEST: c07s03b02x00p08n05i02404 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02404arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd
new file mode 100644
index 0000000..1e0b0d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2408.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02408ent IS
+END c07s03b02x00p08n05i02408ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02408arch OF c07s03b02x00p08n05i02408ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+  BEGIN
+    BYTEV1 := BYTE'( others => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '1' );
+    BYTEV2 := BYTE'( others => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '0' );
+    wait for 5 ns;
+    assert NOT(   ( BYTEV1( 0 ) = '1' )   and
+                  ( BYTEV1( 1 ) = '1' )   and
+                  ( BYTEV1( 2 ) = '1' )   and
+                  ( BYTEV1( 3 ) = '1' )   and
+                  ( BYTEV1( 4 ) = '1' )   and
+                  ( BYTEV1( 5 ) = '1' )   and
+                  ( BYTEV1( 6 ) = '1' )   and
+                  ( BYTEV1( 7 ) = '1' )   and
+                  ( BYTEV2( 0 ) = '0' )   and
+                  ( BYTEV2( 1 ) = '0' )   and
+                  ( BYTEV2( 2 ) = '0' )   and
+                  ( BYTEV2( 3 ) = '0' )   and
+                  ( BYTEV2( 4 ) = '0' )   and
+                  ( BYTEV2( 5 ) = '0' )   and
+                  ( BYTEV2( 6 ) = '0' )   and
+                  ( BYTEV2( 7 ) = '0' )   ) 
+      report "***PASSED TEST: c07s03b02x00p08n05i02408" 
+      severity NOTE;
+    assert (   ( BYTEV1( 0 ) = '1' )   and
+               ( BYTEV1( 1 ) = '1' )   and
+               ( BYTEV1( 2 ) = '1' )   and
+               ( BYTEV1( 3 ) = '1' )   and
+               ( BYTEV1( 4 ) = '1' )   and
+               ( BYTEV1( 5 ) = '1' )   and
+               ( BYTEV1( 6 ) = '1' )   and
+               ( BYTEV1( 7 ) = '1' )   and
+               ( BYTEV2( 0 ) = '0' )   and
+               ( BYTEV2( 1 ) = '0' )   and
+               ( BYTEV2( 2 ) = '0' )   and
+               ( BYTEV2( 3 ) = '0' )   and
+               ( BYTEV2( 4 ) = '0' )   and
+               ( BYTEV2( 5 ) = '0' )   and
+               ( BYTEV2( 6 ) = '0' )   and
+               ( BYTEV2( 7 ) = '0' )   ) 
+      report "***FAILED TEST: c07s03b02x00p08n05i02408 - Others should work well by itself."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02408arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd
new file mode 100644
index 0000000..d38159a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc241.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00241ent IS
+END c03s01b02x00p04n01i00241ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00241arch OF c03s01b02x00p04n01i00241ent IS
+  type a is range boolean'pos(1=2) to boolean'pos(2=2);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 1;
+  BEGIN
+    k := 1;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00241" 
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00241 - The bounds in the range constraint are not locally static expressions of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00241arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd
new file mode 100644
index 0000000..1938b1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p09n01i02412ent IS
+END c07s03b02x00p09n01i02412ent;
+
+ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
+  type T1 is array (1 to 5) of integer;
+  constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4) 
+      report "***PASSED TEST: c07s03b02x00p09n01i02412" 
+      severity NOTE;
+    assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4) 
+      report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p09n01i02412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd
new file mode 100644
index 0000000..7382d61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2415.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n01i02415ent IS
+END c07s03b02x00p10n01i02415ent;
+
+ARCHITECTURE c07s03b02x00p10n01i02415arch OF c07s03b02x00p10n01i02415ent IS
+  type sigrec1 is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : bit;
+    end record;
+  
+  signal S1 : bit;
+  signal S2 : integer;
+  signal S3 : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3) <= sigrec1'('0', 2, '1');
+    wait for 1 ns;
+    assert NOT(S1='0' and S2=2 and S3='1')
+      report "***PASSED TEST: c07s03b02x00p10n01i02415" 
+      severity NOTE;
+    assert (S1='0' and S2=2 and S3='1')
+      report "***FAILED TEST: c07s03b02x00p10n01i02415 - Type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n01i02415arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd
new file mode 100644
index 0000000..8b9c52b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2417.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n02i02417ent IS
+END c07s03b02x00p10n02i02417ent;
+
+ARCHITECTURE c07s03b02x00p10n02i02417arch OF c07s03b02x00p10n02i02417ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : character;
+                  ele_5 : bit;
+                  ele_6 : time;
+                  ele_7 : severity_level;
+                end record;
+    variable v24 : rec;
+  BEGIN
+    v24 := (ele_1=>23,ele_2=>1.4,ele_3=>True,ele_4=>'C',ele_5=>'1',ele_6=>1 ns,ele_7=>error);      
+    assert NOT(   v24.ele_1 = 23      and
+                  v24.ele_2 = 1.4      and
+                  v24.ele_3 = True   and
+                  v24.ele_4 = 'C'      and
+                  v24.ele_5 = '1'      and
+                  v24.ele_6 = 1 ns   and
+                  v24.ele_7 = error   )
+      report "***PASSED TEST: c07s03b02x00p10n02i02417"
+      severity NOTE;
+    assert (   v24.ele_1 = 23      and
+               v24.ele_2 = 1.4      and
+               v24.ele_3 = True   and
+               v24.ele_4 = 'C'      and
+               v24.ele_5 = '1'      and
+               v24.ele_6 = 1 ns   and
+               v24.ele_7 = error   )
+      report "***FAILED TEST: c07s03b02x00p10n02i02417 - Elements of an aggregate should have the same type as that determined by the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n02i02417arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd
new file mode 100644
index 0000000..04c6858
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n01i02421ent IS
+END c07s03b02x01p01n01i02421ent;
+
+ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  a: integer;
+                  b: real;
+                end record;
+    constant y: rec := (a => 12, b => 12.0);
+  BEGIN
+    assert NOT(y.a=12 and y.b=12.0) 
+      report "***PASSED TEST: c07s03b02x01p01n01i02421"
+      severity NOTE;
+    assert (y.a=12 and y.b=12.0) 
+      report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n01i02421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd
new file mode 100644
index 0000000..103e460
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n02i02425ent IS
+END c07s03b02x01p01n02i02425ent;
+
+ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
+  type rec is record
+                a: integer;
+                b: integer;
+                c: integer;
+                d: integer;
+              end record;
+  constant y: rec := (a => 12, others => 10); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10) 
+      report "***PASSED TEST: c07s03b02x01p01n02i02425" 
+      severity NOTE;
+    assert (y.a=12 and y.b=10 and y.c=10 and y.d=10) 
+      report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n02i02425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd
new file mode 100644
index 0000000..00e9c02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2428.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n03i02428ent IS
+END c07s03b02x01p01n03i02428ent;
+
+ARCHITECTURE c07s03b02x01p01n03i02428arch OF c07s03b02x01p01n03i02428ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : real;
+                  ele_2 : real;
+                end record;
+    constant p  :rec := (ele_1 | ele_2 => 4.5); -- No_failure_here
+  BEGIN
+    assert NOT(p.ele_1=4.5 and p.ele_2=4.5) 
+      report "***PASSED TEST: c07s03b02x01p01n03i02428" 
+      severity NOTE;
+    assert (p.ele_1=4.5 and p.ele_2=4.5) 
+      report "***FAILED TEST: c07s03b02x01p01n03i02428 - Element association with others choice should be used to represent elements of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n03i02428arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd
new file mode 100644
index 0000000..d53fd45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2430.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n04i02430ent IS
+END c07s03b02x01p01n04i02430ent;
+
+ARCHITECTURE c07s03b02x01p01n04i02430arch OF c07s03b02x01p01n04i02430ent IS
+  type sigrec1 is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : bit;
+    end record;
+  signal S1 : sigrec1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= (('0' and '1'), 2, '1');
+    wait for 1 ns;
+    assert NOT(S1.B1='0' and S1.B2=2 and S1.B3='1') 
+      report "***PASSED TEST: c07s03b02x01p01n04i02430" 
+      severity NOTE;
+    assert (S1.B1='0' and S1.B2=2 and S1.B3='1') 
+      report "***FAILED TEST: c07s03b02x01p01n04i02430 - Expression of an element association must have the same type as the associated record element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n04i02430arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd
new file mode 100644
index 0000000..f1bcd82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2432.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02432ent IS
+END c07s03b02x02p01n01i02432ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02432arch OF c07s03b02x02p01n01i02432ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array (1 to 3) of integer;
+    variable x: arr;
+  BEGIN
+    x := (1 => 1, 2 => 12, 3 => 24);  -- No_failure_here
+    assert NOT(x(1)=1 and x(2)=12 and x(3)=24) 
+      report "***PASSED TEST: c07s03b02x02p01n01i02432" 
+      severity NOTE;
+    assert (x(1)=1 and x(2)=12 and x(3)=24) 
+      report "***FAILED TEST: c07s03b02x02p01n01i02432 - Expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02432arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd
new file mode 100644
index 0000000..3d10ee1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2435.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02435ent IS
+END c07s03b02x02p01n02i02435ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02435arch OF c07s03b02x02p01n02i02435ent IS
+  type m1 is array (1 to 3) of integer;
+  type m2 is array (1 to 2) of m1;
+  constant c: m2 := ((1, 1, 2), (1, 2, 3));  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(c(1)=(1,1,2) and c(2)=(1,2,3))
+      report "***PASSED TEST: c07s03b02x02p01n02i02435"
+      severity NOTE;
+    assert (c(1)=(1,1,2) and c(2)=(1,2,3))
+      report "***FAILED TEST: c07s03b02x02p01n02i02435 - Multidimensional aggregates are allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02435arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd
new file mode 100644
index 0000000..fca10db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2436.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02436ent IS
+END c07s03b02x02p01n02i02436ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02436arch OF c07s03b02x02p01n02i02436ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BIT_VECTOR is array
+      (natural range <>, positive range <>) of BIT; 
+    variable NUM1 : BIT_VECTOR(0 to 7, 1 to 2) := (
+      ('0', '0'), ('1', '1'),      
+      ('0', '1'), ('1', '1'),      
+      ('0', '1'), ('0', '1'),      
+      ('1', '0'), ('1', '0')       
+      );
+                                        -- No_failure_here   
+  BEGIN
+    assert NOT( NUM1 =(('0', '0'), ('1', '1'),      
+                       ('0', '1'), ('1', '1'),       
+                       ('0', '1'), ('0', '1'),       
+                       ('1', '0'), ('1', '0')))
+      report "***PASSED TEST: c07s03b02x02p01n02i02436"
+      severity NOTE;
+    assert    ( NUM1 =(('0', '0'), ('1', '1'),      
+                       ('0', '1'), ('1', '1'),       
+                       ('0', '1'), ('0', '1'),       
+                       ('1', '0'), ('1', '0')))
+      report "***FAILED TEST: c07s03b02x02p01n02i02436 - Multidimensional aggregates are allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02436arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd
new file mode 100644
index 0000000..ed47707
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd
@@ -0,0 +1,193 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02439ent IS
+END c07s03b02x02p01n01i02439ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Range types are all predefined enumerated types.
+    type CHAR_ARR    is ARRAY( CHARACTER )       of BIT;
+    type BIT_ARR    is ARRAY( BIT )       of BIT;
+    type BOOL_ARR    is ARRAY( BOOLEAN )       of BIT;
+    type SEV_ARR    is ARRAY( SEVERITY_LEVEL )    of BIT;
+
+    -- Declare variables of these types.
+    variable CHARV : CHAR_ARR;
+    variable BITV  : BIT_ARR;
+    variable BOOLV : BOOL_ARR;
+    variable SEVV  : SEV_ARR;
+    variable OKtest: integer := 0;
+  BEGIN
+    -- Assign each of these arrays using aggregates.
+    -- 1. Individual aggregates.
+    CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
+                        'c' to DEL => '1' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( '0' => '0', '1' => '1' );
+    assert( BITV( '0' ) = '0' );
+    if NOT( BITV( '0' ) = '0' ) then
+      OKtest := 1;
+    end if;
+    assert( BITV( '1' ) = '1' );
+    if NOT( BITV( '1' ) = '1' ) then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE => '0', TRUE => '1' );
+    assert( BOOLV( FALSE ) = '0' );
+    if NOT( BOOLV( FALSE ) = '0' ) then
+      OKtest := 1;
+    end if;
+    assert( BOOLV( TRUE ) = '1' );
+    if NOT( BOOLV( TRUE ) = '1' ) then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
+                       FAILURE => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+    
+    -- 2. Groups of aggregates.
+    CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
+                        'c' to DEL => '0' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( '0' | '1' => '0' );
+    assert( BITV( '0' ) = '0' );
+    assert( BITV( '1' ) = '0' );
+    if NOT((BITV('0')='0') and (BITV('1')='0')) then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE | TRUE => '1' );
+    assert( BOOLV( FALSE ) = '1' );
+    assert( BOOLV( TRUE ) = '1' );
+    if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+
+    -- 3. Use of 'others' in these aggregates.
+    CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( others => '1' );
+    assert( BITV( '0' ) = '1' );
+    assert( BITV( '1' ) = '1' );
+    if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE => '1', others => '0' );
+    assert( BOOLV( FALSE ) = '1' );
+    assert( BOOLV( TRUE ) = '0' );
+    if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT(OKtest = 0) 
+      report "***PASSED TEST: c07s03b02x02p01n01i02439" 
+      severity NOTE;
+    assert (OKtest = 0) 
+      report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02439arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd
new file mode 100644
index 0000000..723d240
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2440.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02440ent IS
+END c07s03b02x02p01n01i02440ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02440arch OF c07s03b02x02p01n01i02440ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Range types are all predefined enumerated types.
+    type    CHAR_ARR    is ARRAY( CHARACTER range <> ) of BIT;
+    subtype    CHAR_PART    is CHAR_ARR( 'a' to 'z' );
+    subtype    CHAR_PART_DESC    is CHAR_ARR( 'z' downto 'a' );
+
+    type    BIT_ARR    is ARRAY( BIT range <> ) of BIT;
+    subtype    BIT_PART    is BIT_ARR( bit'('0') to bit'('0') );
+    subtype    BIT_PART_DESC    is BIT_ARR( bit'('1') downto bit'('0') );
+
+    type    BOOL_ARR    is ARRAY( BOOLEAN range <> ) of BIT;
+    subtype    BOOL_PART    is BOOL_ARR( TRUE to TRUE );
+    subtype    BOOL_PART_DESC    is BOOL_ARR( TRUE downto FALSE );
+
+    type    SEV_ARR    is ARRAY( SEVERITY_LEVEL range <> ) of BIT;
+    subtype    SEV_PART    is SEV_ARR( WARNING to FAILURE );
+    subtype    SEV_PART_DESC    is SEV_ARR( FAILURE downto WARNING );
+
+    -- Declare variables of these types.
+    variable CHARV : CHAR_PART;
+    variable BITV  : BIT_PART;
+    variable BOOLV : BOOL_PART;
+    variable SEVV  : SEV_PART;
+    variable OKtest: integer := 0;
+  BEGIN
+    -- Assign each of these arrays using aggregates.
+    -- 1. Individual aggregates.
+    CHARV := CHAR_PART'( 'a' => '1', 'b' => '0', 'c' to 'z' => '1' );                                    for C in 'a' to 'z' loop
+                                                                                                           if  (C = 'a') then
+                                                                                                             assert( CHARV( C ) = '1' );
+                                                                                                             if NOT( CHARV( C ) = '1' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           elsif (C = 'b') then
+                                                                                                             assert( CHARV( C ) = '0' );
+                                                                                                             if NOT( CHARV( C ) = '0' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           else
+                                                                                                             assert( CHARV( C ) = '1' );
+                                                                                                             if NOT( CHARV( C ) = '1' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           end if;
+  end loop;
+  BITV  := BIT_PART'( '0' => '0' );
+  assert( BITV( '0' ) = '0' );
+  if NOT( BITV( '0' ) = '0' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( TRUE => '1' );
+  assert( BOOLV( TRUE ) = '1' );
+  if NOT( BOOLV( TRUE ) = '1' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( WARNING => '1', ERROR => '0',
+                      FAILURE => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+  
+  -- 2. Groups of aggregates.
+  CHARV := CHAR_PART'( 'a' | 'b' => '1', 'c' to 'z' => '0' );
+  for C in 'a' to 'z' loop
+    if  (C = 'a') then
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    elsif (C = 'b') then
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    else
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    end if;
+  end loop;
+  BITV  := BIT_PART'( '0' to '0' => '0' );
+  assert( BITV( '0' ) = '0' );
+  if NOT( BITV( '0' ) = '0' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( TRUE to TRUE => '1' );
+  assert( BOOLV( TRUE ) = '1' );
+  if NOT( BOOLV( TRUE ) = '1' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( ERROR => '0', WARNING | FAILURE => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+
+  -- 3. Use of 'others' in these aggregates.
+  CHARV := CHAR_PART'( 'a' | 'b' => '0', others => '1' );
+  for C in 'a' to 'z' loop
+    if  (C = 'a') then
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    elsif (C = 'b') then
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    else
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    end if;
+  end loop;
+  BITV  := BIT_PART'( others => '1' );
+  assert( BITV( '0' ) = '1' );
+  if NOT( BITV( '0' ) = '1' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( others => '0' );
+  assert( BOOLV( TRUE ) = '0' );
+  if NOT( BOOLV( TRUE ) = '0' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( ERROR => '0', others => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+  wait for 5 ns;
+  assert NOT(OKtest = 0) 
+    report "***PASSED TEST: c07s03b02x02p01n01i02440" 
+    severity NOTE;
+  assert (OKtest = 0) 
+    report "***FAILED TEST: c07s03b02x02p01n01i02440 - Aggregates with different range types test failed."
+    severity ERROR;
+  wait;
+END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02440arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd
new file mode 100644
index 0000000..bd18a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2446.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n01i02446ent IS
+END c07s03b02x02p02n01i02446ent;
+
+ARCHITECTURE c07s03b02x02p02n01i02446arch OF c07s03b02x02p02n01i02446ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is array (1 to 10) of Integer;
+    constant C : T1 := (1 => 2, 2=>4, 3 =>6, 4 =>5, others =>10) ; -- No_failure_here
+  BEGIN
+    assert NOT(C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10) 
+      report "***PASSED TEST: c07s03b02x02p02n01i02446" 
+      severity NOTE;
+    assert (C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10) 
+      report "***FAILED TEST: c07s03b02x02p02n01i02446 - All element associations of an array aggregate must be either all positional or all named."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n01i02446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd
new file mode 100644
index 0000000..250965a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n02i02448ent IS
+END c07s03b02x02p02n02i02448ent;
+
+ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       t13 is array (bit'('0') to bit'('0')) of integer;
+    variable    v13 : t13;
+  BEGIN
+    v13 := (bit'('0') => 13);  -- No_failure_here
+    assert NOT(v13(bit'('0'))=13) 
+      report "***PASSED TEST: c07s03b02x02p02n02i02448" 
+      severity NOTE;
+    assert (v13(bit'('0'))=13) 
+      report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n02i02448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd
new file mode 100644
index 0000000..37da19e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02452ent IS
+END c07s03b02x02p03n02i02452ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY   is UNCONSTRAINED_ARRAY ( 1 to 5 );
+
+    function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
+    begin
+      return A;
+    end F;
+
+    function F2 return CONSTRAINED_ARRAY is
+    begin
+      return F( ( others => 'c' ) );
+      -- sole "others" choice is legal.
+    end F2;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F2;   
+    assert NOT(k="ccccc") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02452" 
+      severity NOTE;
+    assert (k="ccccc") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd
new file mode 100644
index 0000000..5b4fb26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2453.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02453ent IS
+END c07s03b02x02p03n02i02453ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02453arch OF c07s03b02x02p03n02i02453ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY   is UNCONSTRAINED_ARRAY ( 1 to 5 );
+
+    function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
+    begin
+      return A;
+    end F;
+    function F2 return CONSTRAINED_ARRAY is
+    begin
+      return F( ( 'a','b',others => 'c' ) );
+      -- sole "others" choice is legal.
+    end F2;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F2;   
+    assert NOT(k="abccc") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02453" 
+      severity NOTE;
+    assert (k="abccc") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02453 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02453arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd
new file mode 100644
index 0000000..108d1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2454.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b02x02p03n02i02454pkg is
+  type    UN_ARR    is array (integer range <>) of character;
+  subtype CON_ARR is UN_ARR( 1 to 5) ;
+end c07s03b02x02p03n02i02454pkg;
+
+use work.c07s03b02x02p03n02i02454pkg.all;
+
+ENTITY c07s03b02x02p03n02i02454ent IS
+  port     (P : in CON_ARR := (others => 'A'));  --- No_failure_here
+END c07s03b02x02p03n02i02454ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02454arch OF c07s03b02x02p03n02i02454ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
+      report "***PASSED TEST: c07s03b02x02p03n02i02454"
+      severity NOTE;
+    assert (P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
+      report "***FAILED TEST: c07s03b02x02p03n02i02454 - As the default expression defining the default initial value of a port declared to be of a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02454arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd
new file mode 100644
index 0000000..70ca4c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2455.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02455ent IS
+END c07s03b02x02p03n02i02455ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02455arch OF c07s03b02x02p03n02i02455ent IS
+
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of CHARACTER;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  function F return CONSTRAINED_ARRAY is
+  begin
+    return ( others => 'c'  );
+    -- sole "others" choice is legal.
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k(1)='c' and k(2)='c' and k(3)='c')
+      report "***PASSED TEST: c07s03b02x02p03n02i02455"
+      severity NOTE;
+    assert (k(1)='c' and k(2)='c' and k(3)='c')
+      report "***FAILED TEST: c07s03b02x02p03n02i02455 - The others choice should be allowed as the aggregate is the result expression of a function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02455arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd
new file mode 100644
index 0000000..2954f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2456.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02456ent IS
+END c07s03b02x02p03n02i02456ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02456arch OF c07s03b02x02p03n02i02456ent IS
+
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of CHARACTER;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  function F return CONSTRAINED_ARRAY is
+  begin
+    return ( 'a','b', others => 'c' );
+    -- "others" choice is legal.
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k(1)='a' and k(2)='b' and k(3)='c')
+      report "***PASSED TEST: c07s03b02x02p03n02i02456"
+      severity NOTE;
+    assert (k(1)='a' and k(2)='b' and k(3)='c')
+      report "***FAILED TEST: c07s03b02x02p03n02i02456 - The others choice should be allowed as the aggregate is the result expression of a function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd
new file mode 100644
index 0000000..37b9116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2457.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02457ent IS
+END c07s03b02x02p03n02i02457ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02457arch OF c07s03b02x02p03n02i02457ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+    variable V : CONSTRAINED_ARRAY ;
+    -- check in declaration of constrained array variable.
+  BEGIN
+    V := ( others => '$' );
+    -- check in variable assignment to constrained array object.
+    wait for 5 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02457"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02457 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd
new file mode 100644
index 0000000..8f8966a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2458.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02458ent IS
+END c07s03b02x02p03n02i02458ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02458arch OF c07s03b02x02p03n02i02458ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
+    variable V : CONSTRAINED_ARRAY ;
+    -- check in declaration of constrained array variable.
+  BEGIN
+
+    V := ( 'd','x',others => '$' );
+    -- check in variable assignment to constrained array object.
+    wait for 5 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02458"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02458 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd
new file mode 100644
index 0000000..1cf7b89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2459.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02459ent IS
+END c07s03b02x02p03n02i02459ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02459arch OF c07s03b02x02p03n02i02459ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  signal  V : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    V <= ( others => '$' );
+    wait for 1 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02459"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02459 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd
new file mode 100644
index 0000000..f1b3e21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2460.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02460ent IS
+END c07s03b02x02p03n02i02460ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02460arch OF c07s03b02x02p03n02i02460ent IS
+  type       UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype    CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  type       AGGREGATE_ARRAY    is array (1 to 2) of CONSTRAINED_ARRAY;
+  signal     V,W          : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (V,W) <= AGGREGATE_ARRAY' (('d', 'x', others => 'a'),  
+                               ('d', 'x', others => 'a')); 
+    wait for 1 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='a' ) 
+      report "***PASSED TEST: c07s03b02x02p03n02i02460"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='a' ) 
+      report "***FAILED TEST: c07s03b02x02p03n02i02460 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd
new file mode 100644
index 0000000..e9266b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2461.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02461ent IS
+END c07s03b02x02p03n02i02461ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02461arch OF c07s03b02x02p03n02i02461ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  signal  V : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    V <= ('d','x', others => '$' );
+    wait for 1 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='$' ) 
+      report "***PASSED TEST: c07s03b02x02p03n02i02461"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='$' ) 
+      report "***FAILED TEST: c07s03b02x02p03n02i02461 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd
new file mode 100644
index 0000000..3382831
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2462.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02462ent IS
+END c07s03b02x02p03n02i02462ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02462arch OF c07s03b02x02p03n02i02462ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  type    AGGREGATE_ARRAY    is array (1 to 2) of CONSTRAINED_ARRAY;
+  signal  V, W         :  CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (W,V) <= (AGGREGATE_ARRAY'((others => '$'),( others => '$' )));
+    wait for 1 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
+      report "***PASSED TEST: c07s03b02x02p03n02i02462"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
+      report "***FAILED TEST: c07s03b02x02p03n02i02462 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd
new file mode 100644
index 0000000..0dad7cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02463ent IS
+END c07s03b02x02p03n02i02463ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
+  subtype    BV1 is BIT_VECTOR (2 downto 1);
+  constant    c   : BV1 := ('1', others => '0');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02463"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd
new file mode 100644
index 0000000..8be786d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02464ent IS
+END c07s03b02x02p03n02i02464ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
+
+  subtype BV1 is BIT_VECTOR (2 downto 1);
+  constant c : BV1 := (1 => '0', others => '1');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02464"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02464arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd
new file mode 100644
index 0000000..356fc58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2465.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02465ent IS
+END c07s03b02x02p03n02i02465ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02465arch OF c07s03b02x02p03n02i02465ent IS
+  subtype    BV1 is BIT_VECTOR (2 downto 1);
+  constant    c   : BV1 := (2 => '1', others => '0');   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02465"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02465 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02465arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd
new file mode 100644
index 0000000..9f0171c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02466ent IS
+END c07s03b02x02p03n02i02466ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS
+  type    UN_ARR is array (integer range <>) of character;
+  subtype CON_ARR is UN_ARR( 1 to 5 ) ;
+  signal  S : CON_ARR := ('A','Z', others => 'C');     -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
+      report "***PASSED TEST: c07s03b02x02p03n02i02466"
+      severity NOTE;
+    assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
+      report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02466arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd
new file mode 100644
index 0000000..a38a8dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2467.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02467ent IS
+END c07s03b02x02p03n02i02467ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02467arch OF c07s03b02x02p03n02i02467ent IS
+  type      UN_ARR  is array (integer range <>) of character;
+  subtype   CON_ARR is UN_ARR( 1 to 5 );
+  attribute LOCN : CON_ARR ;
+  signal    S    : Integer ;
+  attribute LOCN of S : signal is ('A', others => 'Z'); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02467"
+      severity NOTE;
+    assert ( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02467 - An array aggregate with an others choice may appear as the expression defining the value of an attribute in an attribute specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02467arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd
new file mode 100644
index 0000000..b7f9023
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2471.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02471ent IS
+END c07s03b02x02p03n02i02471ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02471arch OF c07s03b02x02p03n02i02471ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype  CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
+    function F return CONSTRAINED_ARRAY is
+    begin
+      return CONSTRAINED_ARRAY'(others => '7');
+      -- check in function return statement.
+    end F;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    wait for 5 ns;
+    assert NOT(k = "7777") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02471" 
+      severity NOTE;
+    assert (k = "7777") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02471 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02471arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd
new file mode 100644
index 0000000..c6cd94b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2472.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02472ent IS
+END c07s03b02x02p03n02i02472ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02472arch OF c07s03b02x02p03n02i02472ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype  CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
+    function F return CONSTRAINED_ARRAY is
+    begin
+      return CONSTRAINED_ARRAY'(2 => 'h', others => '7');
+      -- check in function return statement.
+    end F;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k = "7h77") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02472" 
+      severity NOTE;
+    assert (k = "7h77") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02472 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02472arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd
new file mode 100644
index 0000000..a6106a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2474.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n02i02474ent IS
+END c07s03b02x02p13n02i02474ent;
+
+ARCHITECTURE c07s03b02x02p13n02i02474arch OF c07s03b02x02p13n02i02474ent IS
+  type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype  CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+    variable k : CA_DOWN;
+  BEGIN
+    k := CA_DOWN'((10 downto 1 => 'B'));   
+    assert NOT(k="BBBBBBBBBB") 
+      report "***PASSED TEST: c07s03b02x02p13n02i02474"
+      severity NOTE;
+    assert (k="BBBBBBBBBB") 
+      report "***FAILED TEST: c07s03b02x02p13n02i02474 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n02i02474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd
new file mode 100644
index 0000000..e26ee60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2475.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n02i02475ent IS
+END c07s03b02x02p13n02i02475ent;
+
+ARCHITECTURE c07s03b02x02p13n02i02475arch OF c07s03b02x02p13n02i02475ent IS
+  type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_UP is UNCONSTRAINED_ARRAY ( 1 to 10 );
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+    variable k : CA_UP;
+  BEGIN
+    k := CA_DOWN'((1 to 10 => 'B'));   
+    assert NOT(k="BBBBBBBBBB") 
+      report "***PASSED TEST: c07s03b02x02p13n02i02475" 
+      severity NOTE;
+    assert (k="BBBBBBBBBB") 
+      report "***FAILED TEST: c07s03b02x02p13n02i02475 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n02i02475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd
new file mode 100644
index 0000000..c65a292
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2477.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02477ent IS
+END c07s03b02x02p13n04i02477ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02477arch OF c07s03b02x02p13n04i02477ent IS
+  type    index_values is (one, two, three);
+  type    ucarr is array (index_values range <>) of Boolean;      
+  subtype carr  is ucarr (index_values'low to index_values'high);
+  function f2 (i : integer) return carr is
+  begin
+    return (True, True, False);  
+  end f2;
+BEGIN
+  TESTING: PROCESS
+    variable k : carr;
+  BEGIN
+    k := f2(1);
+    assert NOT(k=(True,True,False)) 
+      report "***PASSED TEST: c07s03b02x02p13n04i02477" 
+      severity NOTE;
+    assert (k=(True,True,False)) 
+      report "***FAILED TEST: c07s03b02x02p13n04i02477 - The leftmost bound is determined by the applicable index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02477arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd
new file mode 100644
index 0000000..d7595a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2478.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02478ent IS
+END c07s03b02x02p13n04i02478ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02478arch OF c07s03b02x02p13n04i02478ent IS
+  type    index_values is (one, two, three);
+  type    ucarr is array (index_values range <>) of Boolean;      
+  subtype carr  is ucarr (index_values'low to index_values'high);
+  function f2 (i : integer) return carr is
+  begin
+    return (index_values'LOW => TRUE, others => False);
+  end f2;
+BEGIN
+  TESTING: PROCESS
+    variable k : carr;
+  BEGIN
+    k := f2(1);
+    assert NOT(k=(True,False,False)) 
+      report "***PASSED TEST: c07s03b02x02p13n04i02478"
+      severity NOTE;
+    assert (k=(True,False,False)) 
+      report "***FAILED TEST: c07s03b02x02p13n04i02478 - The leftmost bound is determined by the applicable index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02478arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd
new file mode 100644
index 0000000..d819686
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2479.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02479ent IS
+END c07s03b02x02p13n04i02479ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02479arch OF c07s03b02x02p13n04i02479ent IS
+  type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(CA_DOWN'LEFT = 10)
+      report "***PASSED TEST: c07s03b02x02p13n04i02479"
+      severity NOTE;
+    assert (CA_DOWN'LEFT = 10)
+      report "***FAILED TEST: c07s03b02x02p13n04i02479 - S'LEFT did not return the correct value." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02479arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd
new file mode 100644
index 0000000..d0da580
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2480.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02480ent IS
+END c07s03b02x02p13n04i02480ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02480arch OF c07s03b02x02p13n04i02480ent IS
+  type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_UP   is UNCONSTRAINED_ARRAY (1 to 10);
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
+      report "***PASSED TEST: c07s03b02x02p13n04i02480" 
+      severity NOTE;
+    assert ((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
+      report "***FAILED TEST: c07s03b02x02p13n04i02480 - Rightmost bounds INCORRECT for positional aggregates." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02480arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd
new file mode 100644
index 0000000..87dbef2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2481.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n02i02481ent IS
+END c07s03b03x00p01n02i02481ent;
+
+ARCHITECTURE c07s03b03x00p01n02i02481arch OF c07s03b03x00p01n02i02481ent IS
+  function f(a, b : INTEGER) return INTEGER is
+  begin
+    return a + b;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable v : INTEGER := 0;
+  BEGIN
+    v := f(1, 2);
+    wait for 5 ns;
+    assert NOT( v=3 )
+      report "***PASSED TEST: c07s03b03x00p01n02i02481"
+      severity NOTE;
+    assert ( v=3 )
+      report "***FAILED TEST: c07s03b03x00p01n02i02481 - Function call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n02i02481arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd
new file mode 100644
index 0000000..550baa6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2483.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n01i02483ent IS
+END c07s03b03x00p01n01i02483ent;
+
+ARCHITECTURE c07s03b03x00p01n01i02483arch OF c07s03b03x00p01n01i02483ent IS
+
+  function CreateN(constant size : in INTEGER) return STRING is
+  begin
+    return "This is a test return value";
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert False 
+      report CreateN(1) 
+      severity NOTE;
+                                        -- should be string above
+    assert FALSE
+      report "***PASSED TEST: c07s03b03x00p01n01i02483 - This test needs manual check to see that 'This is a test return value' assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n01i02483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd
new file mode 100644
index 0000000..4f8b2a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2484.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n02i02484ent IS
+END c07s03b03x00p01n02i02484ent;
+
+ARCHITECTURE c07s03b03x00p01n02i02484arch OF c07s03b03x00p01n02i02484ent IS
+  signal t1, t2, t3, t4 : INTEGER := -1;
+BEGIN
+  TESTING: PROCESS
+    constant ref    : INTEGER := 123;
+
+    function FuncN1 return INTEGER is
+      function FuncN2 return INTEGER is
+        function FuncN3 return INTEGER is
+          function FuncN4 return INTEGER is
+            function FuncN5 return INTEGER is
+              function FuncN6 return INTEGER is
+                function FuncN7 return INTEGER is
+                  function FuncN8 return INTEGER is
+                    function FuncN9 return INTEGER is
+                      function FuncN10 return INTEGER is
+                        function FuncN11 return INTEGER is
+                        begin
+                          return ref;
+                        end FuncN11;
+                      begin
+                        return FuncN11;
+                      end FuncN10;
+                    begin
+                      return FuncN10;
+                    end FuncN9;
+                  begin
+                    return FuncN9;
+                  end FuncN8;
+                begin
+                  return FuncN8;
+                end FuncN7;
+              begin
+                return FuncN7;
+              end FuncN6;
+            begin
+              return FuncN6;
+            end FuncN5;
+          begin
+            return FuncN5;
+          end FuncN4;
+        begin
+          return FuncN4;
+        end FuncN3;
+      begin
+        return FuncN3;
+      end FuncN2;
+    begin
+      return FuncN2;
+    end FuncN1;
+    
+    
+    function Func1 return INTEGER is
+    begin
+      return 1;
+    end Func1;
+
+    function Func2(selector : BOOLEAN) return INTEGER is
+    begin
+      if selector then
+        return 11;
+      else
+        return 13;
+      end if;
+    end Func2;
+
+  BEGIN
+    t1 <= func1;
+    t2 <= func2(TRUE);
+    t3 <= func2(FALSE);
+    t4 <= funcN1;
+    wait for 5 ns;
+    assert NOT( t1=1 and t2=11 and t3=13 and t4=123 )
+      report "***PASSED TEST: c07s03b03x00p01n02i02484"
+      severity NOTE;
+    assert ( t1=1 and t2=11 and t3=13 and t4=123 )
+      report "***FAILED TEST: c07s03b03x00p01n02i02484 - Function call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n02i02484arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd
new file mode 100644
index 0000000..51d0d6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2485.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02485ent IS
+END c07s03b03x00p02n01i02485ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02485arch OF c07s03b03x00p02n01i02485ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z:real) return boolean is
+    begin
+      if y then
+        return true;
+      end if;
+      return false;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable r: real;
+    variable q1: boolean;
+  BEGIN
+    q1 := check (p,q,r);
+    assert NOT(q1=true)
+      report "***PASSED TEST: c07s03b03x00p02n01i02485"
+      severity NOTE;
+    assert (q1=true)
+      report "***FAILED TEST: c07s03b03x00p02n01i02485 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd
new file mode 100644
index 0000000..ac37a57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2486.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02486ent IS
+END c07s03b03x00p02n01i02486ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02486arch OF c07s03b03x00p02n01i02486ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check  return boolean is
+    begin
+      return false;
+    end;
+    variable q: boolean ;
+  BEGIN
+    q := check;
+    assert NOT(q=FALSE) 
+      report "***PASSED TEST: c07s03b03x00p02n01i02486" 
+      severity NOTE;
+    assert (q=FALSE) 
+      report "***FAILED TEST: c07s03b03x00p02n01i02486 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd
new file mode 100644
index 0000000..897a057
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2487.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02487ent IS
+END c07s03b03x00p02n01i02487ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02487arch OF c07s03b03x00p02n01i02487ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function typeconv (a1 : real) return integer is
+    begin
+      return 1;
+    end;
+    function func1    (a2 : integer) return integer is
+    begin
+      return 5;
+    end func1;
+    variable x: real := 1.2;
+    variable y: integer;
+  BEGIN
+    y := func1 (typeconv (x));
+    assert NOT(y=5)
+      report "***PASSED TEST: c07s03b03x00p02n01i02487" 
+      severity NOTE;
+    assert (y=5)
+      report "***FAILED TEST: c07s03b03x00p02n01i02487 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd
new file mode 100644
index 0000000..34037fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02494ent IS
+END c07s03b03x00p04n02i02494ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x : integer) return integer is
+    begin
+      return (10 * x);
+    end;
+    variable q1: integer := 12;
+    variable q2: integer ;
+  BEGIN
+    q2 := check (q1) + 24 - check (2);
+    assert NOT( q2 = 124 )
+      report "***PASSED TEST: c07s03b03x00p04n02i02494"
+      severity NOTE;
+    assert ( q2=124 )
+      report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02494arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd
new file mode 100644
index 0000000..f4adba4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2495.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02495ent IS
+END c07s03b03x00p04n02i02495ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02495arch OF c07s03b03x00p04n02i02495ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z1:real; z2:real:= 1.3)
+      return boolean is    
+    begin
+      if y then
+        return true;
+      end if;
+      return false;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable s: boolean;
+    variable r: real;
+  BEGIN
+    s := check (p, q, r);  -- No_failure_here
+    assert NOT( s=true ) 
+      report "***PASSED TEST: c07s03b03x00p04n02i02495"
+      severity NOTE;
+    assert ( s=true ) 
+      report "***FAILED TEST: c07s03b03x00p04n02i02495 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd
new file mode 100644
index 0000000..f2ae45d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2496.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02496ent IS
+END c07s03b03x00p04n02i02496ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02496arch OF c07s03b03x00p04n02i02496ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function func1 (a1 : real; b1 : integer:= 12) return integer is 
+    begin
+      return 5;
+    end;
+    variable x: real := 1.2;
+    variable y: integer ;
+  BEGIN
+    y := func1 (x);
+    assert NOT( y=5 )
+      report "***PASSED TEST: c07s03b03x00p04n02i02496"
+      severity NOTE;
+    assert ( y=5 )
+      report "***FAILED TEST: c07s03b03x00p04n02i02496 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd
new file mode 100644
index 0000000..41274df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2499.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p05n01i02499ent IS
+END c07s03b03x00p05n01i02499ent;
+
+ARCHITECTURE c07s03b03x00p05n01i02499arch OF c07s03b03x00p05n01i02499ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x : boolean) return boolean is
+    begin
+      return false;
+    end;
+    variable q1: boolean := true;
+    variable q2: boolean ;
+  BEGIN
+    q2 := check (check (q1)); -- q2 should be false
+    assert NOT(q2=FALSE) 
+      report "***PASSED TEST: c07s03b03x00p05n01i02499" 
+      severity NOTE;
+    assert (q2=FALSE) 
+      report "***FAILED TEST: c07s03b03x00p05n01i02499 - Actual parameter must belong to the subtype of the associated formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p05n01i02499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd
new file mode 100644
index 0000000..5c059f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc25.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n02i00025ent IS
+END c04s02b00x00p10n02i00025ent;
+
+ARCHITECTURE c04s02b00x00p10n02i00025arch OF c04s02b00x00p10n02i00025ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define an ascending subtype.
+    subtype ASC_B is INTEGER range 0 to 1;
+    subtype ASC is ASC_B;
+
+    -- Define a descending subtype.
+    subtype DES_B is INTEGER range 1 to 0;
+    subtype DES is DES_B;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+
+    -- Test the direction of the ascending range.
+    PREV := -1;
+    for I in ASC loop
+      if (I > PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 2;
+    for I in DES loop
+      if (I < PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST:c04s02b00x00p10n02i00025"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n02i00025 - The direction of a discrete subtype indication is the same as that of the denoted subtype in the absence of an explicit type constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n02i00025arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd
new file mode 100644
index 0000000..167c685
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p05n01i02500ent IS
+END c07s03b03x00p05n01i02500ent;
+
+ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1(constant p : in STRING) return INTEGER is
+    begin
+      return P'LENGTH;
+    end;
+
+    constant C : STRING := "Testing";
+  BEGIN
+    wait for 5 ns;
+    assert NOT(f1(c) = c'LENGTH)
+      report "***PASSED TEST: c07s03b03x00p05n01i02500"
+      severity NOTE;
+    assert (f1(c) = c'LENGTH)
+      report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p05n01i02500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd
new file mode 100644
index 0000000..7c00acb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2501.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p02n01i02501ent IS
+END c07s03b04x00p02n01i02501ent;
+
+ARCHITECTURE c07s03b04x00p02n01i02501arch OF c07s03b04x00p02n01i02501ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type bit_vctor is array (bit'('0') to bit'('1') ) of integer;
+    variable k : bit_vctor;
+  BEGIN
+    k := (5,6);
+    assert NOT( k=(5,6) )
+      report "***PASSED TEST: c07s03b04x00p02n01i02501"
+      severity NOTE;
+    assert ( k=(5,6) )
+      report "***FAILED TEST: c07s03b04x00p02n01i02501 - The qualified expression must either consist of a type mark, an apostrophe ('), and an expression enclosed with parentheses or consist of a type mark, an apostrophe ('), and an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p02n01i02501arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd
new file mode 100644
index 0000000..443df49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2502.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p02n01i02502ent IS
+END c07s03b04x00p02n01i02502ent;
+
+ARCHITECTURE c07s03b04x00p02n01i02502arch OF c07s03b04x00p02n01i02502ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S :rec_type;
+  BEGIN
+    S   := rec_type'(bit'('0'), 1, true);
+    assert NOT(S.x='0' and S.y=1 and S.z=true) 
+      report "***PASSED TEST: c07s03b04x00p02n01i02502"
+      severity NOTE;
+    assert (S.x='0' and S.y=1 and S.z=true) 
+      report "***FAILED TEST: c07s03b04x00p02n01i02502 - The qualified expression must either consist of a type mark, an apostrophe ('), and an expression enclosed with parentheses or consist of a type mark, an apostrophe ('), and an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p02n01i02502arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd
new file mode 100644
index 0000000..2a2d52c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02506ent IS
+END c07s03b04x00p03n01i02506ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable S1 :rec_type;
+  BEGIN
+    S1   := rec_type'(bit'('0'), 1, true)  ;-- No_Failure_here
+    assert NOT(S1.x='0' and S1.y=1 and S1.z=true) 
+      report "***PASSED TEST: c07s03b04x00p03n01i02506" 
+      severity NOTE;
+    assert (S1.x='0' and S1.y=1 and S1.z=true) 
+      report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02506arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd
new file mode 100644
index 0000000..23300a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00251ent IS
+END c03s01b02x00p04n01i00251ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
+  type I1 is range 1 to 10;
+  type I2 is range 11 to 20;
+  constant V1: I1 := 1;
+  constant V2: I2 := 20;
+  type I5 is range V1 to V2;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00251" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00251arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd
new file mode 100644
index 0000000..f991006
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2511.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n03i02511ent IS
+END c07s03b04x00p03n03i02511ent;
+
+ARCHITECTURE c07s03b04x00p03n03i02511arch OF c07s03b04x00p03n03i02511ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1 return integer is
+    begin 
+      return 2; 
+    end;
+    variable k : integer := 0;
+  BEGIN
+    k := integer'(f1/f1);
+    assert NOT( k=1 )
+      report "***PASSED TEST: c07s03b04x00p03n03i02511"
+      severity NOTE;
+    assert ( k=1 )
+      report "***FAILED TEST: c07s03b04x00p03n03i02511 - The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n03i02511arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd
new file mode 100644
index 0000000..d5171cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2513.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p02n01i02513ent IS
+END c07s03b05x00p02n01i02513ent;
+
+ARCHITECTURE c07s03b05x00p02n01i02513arch OF c07s03b05x00p02n01i02513ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k1 : integer    := 65;
+    variable k2 : real   := 1.2;
+  BEGIN
+    k1 := integer(k2);
+    wait for 1 ns;
+    assert NOT(k1 = 1) 
+      report "***PASSED TEST: c07s03b05x00p02n01i02513" 
+      severity NOTE;
+    assert (k1 = 1) 
+      report "***FAILED TEST: c07s03b05x00p02n01i02513 - Missing expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p02n01i02513arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd
new file mode 100644
index 0000000..f04846f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2515.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n02i02515ent IS
+END c07s03b05x00p03n02i02515ent;
+
+ARCHITECTURE c07s03b05x00p03n02i02515arch OF c07s03b05x00p03n02i02515ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    
+    function f(a:century) return century is
+    begin 
+      return century'(1); 
+    end;
+    
+    type millenia is ('1', '2', '3', '4', '5');
+    
+    function f (a:millenia) return millenia is
+    begin 
+      return millenia'('2'); 
+    end;
+    
+    variable hundreds : century  ;
+  BEGIN
+    hundreds := century (f(hundreds));
+    assert NOT(hundreds = 1) 
+      report "***PASSED TEST: c07s03b05x00p03n02i02515" 
+      severity NOTE;
+    assert (hundreds = 1) 
+      report "***FAILED TEST: c07s03b05x00p03n02i02515 - Type of operand must be determinable independent of the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n02i02515arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd
new file mode 100644
index 0000000..4dd38db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2519.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n04i02519ent IS
+END c07s03b05x00p03n04i02519ent;
+
+ARCHITECTURE c07s03b05x00p03n04i02519arch OF c07s03b05x00p03n04i02519ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    variable hundreds : century  ;
+    type millenia is range 1 to 10;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    assert NOT( thousand = 1 )
+      report "***PASSED TEST: c07s03b05x00p03n04i02519"
+      severity NOTE;
+    assert ( thousand = 1 )
+      report "***FAILED TEST: c07s03b05x00p03n04i02519 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n04i02519arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd
new file mode 100644
index 0000000..4bae3f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2520.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n04i02520ent IS
+END c07s03b05x00p03n04i02520ent;
+
+ARCHITECTURE c07s03b05x00p03n04i02520arch OF c07s03b05x00p03n04i02520ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    function f return century is
+    begin 
+      return (century'(3)); 
+    end;
+    variable hundreds : century  ;
+    type millenia is range 1 to 10;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (f);
+    assert NOT( thousand = 3 )
+      report "***PASSED TEST: c07s03b05x00p03n04i02520"
+      severity NOTE;
+    assert ( thousand = 3 )
+      report "***FAILED TEST: c07s03b05x00p03n04i02520 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n04i02520arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd
new file mode 100644
index 0000000..66743ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2522.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p04n01i02522ent IS
+END c07s03b05x00p04n01i02522ent;
+
+ARCHITECTURE c07s03b05x00p04n01i02522arch OF c07s03b05x00p04n01i02522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples;
+    variable Seville   : Oranges := 5;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    Seville  :=  Oranges (Macintosh) ;    -- No_Failure_here
+    wait for 1 ns;
+    assert NOT( Seville = 5 )
+      report "***PASSED TEST: c07s03b05x00p04n01i02522"
+      severity NOTE;
+    assert ( Seville = 5 )
+      report "***FAILED TEST: c07s03b05x00p04n01i02522 - Conversion consists of conversion to the target type followed by a check that the result of the conversion belongs to the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p04n01i02522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd
new file mode 100644
index 0000000..5872a1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2524.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p05n02i02524ent IS
+END c07s03b05x00p05n02i02524ent;
+
+ARCHITECTURE c07s03b05x00p05n02i02524arch OF c07s03b05x00p05n02i02524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Grapes is (Sweet, Sour);
+    variable Green : Grapes;
+  BEGIN
+    Green := Grapes (Sweet);
+    assert NOT( Green = Sweet )
+      report "***PASSED TEST: c07s03b05x00p05n02i02524"
+      severity NOTE;
+    assert ( Green = Sweet )
+      report "***FAILED TEST: c07s03b05x00p05n02i02524 - Conversion of an operand of a given type to the type itself is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p05n02i02524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd
new file mode 100644
index 0000000..a75f2b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2525.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02525ent IS
+END c07s03b05x00p06n02i02525ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02525arch OF c07s03b05x00p06n02i02525ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples   := 7;
+    variable Seville   : Oranges    := 5;
+  BEGIN
+    Macintosh := Apples (Seville);
+    assert NOT( Macintosh=5 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02525"
+      severity NOTE;
+    assert ( Macintosh=5 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02525 - The operand can be of any integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02525arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd
new file mode 100644
index 0000000..2372ff5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2527.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02527ent IS
+END c07s03b05x00p06n04i02527ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02527arch OF c07s03b05x00p06n04i02527ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.2);
+    assert NOT( V1 = 10 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02527"
+      severity NOTE;
+    assert ( V1 = 10 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02527 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02527arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd
new file mode 100644
index 0000000..9c6d815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2528.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02528ent IS
+END c07s03b05x00p06n04i02528ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02528arch OF c07s03b05x00p06n04i02528ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.7);
+    assert NOT( V1 = 11 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02528"
+      severity NOTE;
+    assert ( V1 = 11 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02528 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02528arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd
new file mode 100644
index 0000000..8773c71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02529ent IS
+END c07s03b05x00p06n04i02529ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.5);
+    assert NOT((V1 = 10) or ( V1 = 11 ))
+      report "***PASSED TEST: c07s03b05x00p06n04i02529"
+      severity NOTE;
+    assert ((V1 = 10) or ( V1 = 11 ))
+      report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd
new file mode 100644
index 0000000..ca1c915
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2530.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02530ent IS
+END c07s03b05x00p06n04i02530ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02530arch OF c07s03b05x00p06n04i02530ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (-3.2147483647);
+    assert NOT( V1 = -3 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02530"
+      severity NOTE;
+    assert ( V1 = -3 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02530 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd
new file mode 100644
index 0000000..c84e756
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2531.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02531ent IS
+END c07s03b05x00p06n02i02531ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02531arch OF c07s03b05x00p06n02i02531ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k1 : integer    := 5;
+    variable k2 : real    := 1.1;
+  BEGIN
+    k2 := real (k1);
+    assert NOT( k2=5.0 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02531"
+      severity NOTE;
+    assert ( k2=5.0 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02531 - The type conversion from integer to real failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd
new file mode 100644
index 0000000..e135cf3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2532.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02532ent IS
+END c07s03b05x00p06n02i02532ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02532arch OF c07s03b05x00p06n02i02532ent IS
+  signal R1 : REAL    := 10.0;
+  signal I2 : INTEGER    := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    I2 <= INTEGER(R1);
+    wait for 5 ns;
+    assert NOT( I2=10 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02532"
+      severity NOTE;
+    assert ( I2=10 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02532 - The type conversion from real to integer type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02532arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd
new file mode 100644
index 0000000..af67db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2533.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p10n01i02533ent IS
+END c07s03b05x00p10n01i02533ent;
+
+ARCHITECTURE c07s03b05x00p10n01i02533arch OF c07s03b05x00p10n01i02533ent IS
+  type Memory is array (Integer range <>) of Integer;
+  subtype T1 is Memory (1 to 6) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T1 := (2,3,4,2,5,6) ;
+  BEGIN
+    V1 := Memory (V2) ;    -- No_Failure_her
+    assert NOT(V1=(2,3,4,2,5,6))
+      report "***PASSED TEST: c07s03b05x00p10n01i02533"
+      severity NOTE;
+    assert (V1=(2,3,4,2,5,6))
+      report "***FAILED TEST: c07s03b05x00p10n01i02533 - The bounds of the operand are converted to the corresponding index type of the target type when the type mark is an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p10n01i02533arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd
new file mode 100644
index 0000000..6b3277a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2535.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p13n03i02535ent IS
+END c07s03b05x00p13n03i02535ent;
+
+ARCHITECTURE c07s03b05x00p13n03i02535arch OF c07s03b05x00p13n03i02535ent IS
+  type Memory is array (Integer range <>) of Integer;
+  subtype T1 is Memory (1 to 6) ;
+  subtype T2 is Memory (1 to 6) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T1 := (2,3,6,3,4,5) ;
+  BEGIN
+    V1 := T2 (V2) ;    -- No_Failure_here
+    wait for 1 ns;
+    assert NOT(V1 = (2,3,6,3,4,5)) 
+      report "***PASSED TEST: c07s03b05x00p13n03i02535" 
+      severity NOTE;
+    assert (V1 = (2,3,6,3,4,5)) 
+      report "***FAILED TEST: c07s03b05x00p13n03i02535 - A check is made that for each element of the operand there is a matching element of the target subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p13n03i02535arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd
new file mode 100644
index 0000000..c09161d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc254.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p06n01i00254ent IS
+END c03s01b02x00p06n01i00254ent;
+
+ARCHITECTURE c03s01b02x00p06n01i00254arch OF c03s01b02x00p06n01i00254ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer;
+  BEGIN
+    k := integer'POS(2);
+    assert NOT( k=2 )
+      report "***PASSED TEST: c03s01b02x00p06n01i00254"
+      severity NOTE;
+    assert ( k=2 )
+      report "***FAILED TEST: c03s01b02x00p06n01i00254 - The position number of an integer value is the corresponding value of the type universal_integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p06n01i00254arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd
new file mode 100644
index 0000000..d29cddc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2546.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02546ent IS
+END c07s03b05x00p14n01i02546ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02546arch OF c07s03b05x00p14n01i02546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer;
+  BEGIN
+    i := 100 ns / 20 ns;     -- no_failure_here
+    assert NOT(i=5) 
+      report "***PASSED TEST: c07s03b05x00p14n01i02546" 
+      severity NOTE;
+    assert (i=5) 
+      report "***FAILED TEST: c07s03b05x00p14n01i02546 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd
new file mode 100644
index 0000000..d85a1f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2547.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02547ent IS
+END c07s03b05x00p14n01i02547ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02547arch OF c07s03b05x00p14n01i02547ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : real;
+  BEGIN
+    i := 100.5 * 0.5;     -- no_failure_here
+    assert NOT(i=50.25) 
+      report "***PASSED TEST: c07s03b05x00p14n01i02547" 
+      severity NOTE;
+    assert (i=50.25) 
+      report "***FAILED TEST: c07s03b05x00p14n01i02547 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02547arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd
new file mode 100644
index 0000000..37e6322
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2550.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p08n01i02550ent IS
+END c07s03b05x00p08n01i02550ent;
+
+ARCHITECTURE c07s03b05x00p08n01i02550arch OF c07s03b05x00p08n01i02550ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is  array (1 to 5) of integer ;
+    type millenia is array (5 downto 1) of integer;
+    variable hundreds : century  := (1,1,1,1,1);
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    assert NOT(thousand = (1,1,1,1,1)) 
+      report "***PASSED TEST: c07s03b05x00p08n01i02550" 
+      severity NOTE;
+    assert (thousand = (1,1,1,1,1)) 
+      report "***FAILED TEST: c07s03b05x00p08n01i02550 - Operand and the target type should have the same index type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p08n01i02550arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd
new file mode 100644
index 0000000..f07a68f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2551.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02551ent IS
+END c07s03b06x00p02n01i02551ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02551arch OF c07s03b06x00p02n01i02551ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T is
+      record
+        a:integer;
+        b:integer;
+      end record;
+    type A is access T;
+    variable B1, B2: A := new T'(0, 0);
+    variable C : T;
+  BEGIN
+    C  := B1.all;
+    assert NOT(C.a = 0 and C.b = 0 )
+      report "***PASSED TEST: c07s03b06x00p02n01i02551"
+      severity NOTE;
+    assert (C.a = 0 and C.b = 0 )
+      report "***FAILED TEST: c07s03b06x00p02n01i02551 - The allocator must either consist of the reserved word new and a subtype indication or consist of the reserved word new and a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02551arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd
new file mode 100644
index 0000000..99ea00a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2558.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p03n02i02558ent IS
+END c07s03b06x00p03n02i02558ent;
+
+ARCHITECTURE c07s03b06x00p03n02i02558arch OF c07s03b06x00p03n02i02558ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Bit;
+        SUCC  : Bit;
+      end record;
+    variable HEAD : LINK :=  new CELL ;
+  BEGIN
+    assert NOT(HEAD.VALUE='0')
+      report "***PASSED TEST: c07s03b06x00p03n02i02558"
+      severity NOTE;
+    assert (HEAD.VALUE='0')
+      report "***FAILED TEST: c07s03b06x00p03n02i02558 - The initial value of the created object is the same as the default initial value for an explicitly declared variable of the designated subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p03n02i02558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd
new file mode 100644
index 0000000..13e0af9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2559.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p05n01i02559ent IS
+END c07s03b06x00p05n01i02559ent;
+
+ARCHITECTURE c07s03b06x00p05n01i02559arch OF c07s03b06x00p05n01i02559ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Bit;
+        SUCC  : Bit;
+      end record;
+    type T1 is access BIT_VECTOR ;
+    variable HEAD : LINK := new CELL'('1','0') ;
+    variable V2   : T1   := new BIT_VECTOR(0 to 7) ;     --- No_failure_here
+  BEGIN
+    assert NOT((V2.all="00000000") and (HEAD.VALUE='1') and (HEAD.SUCC='0'))
+      report "***PASSED TEST: c07s03b06x00p05n01i02559"
+      severity NOTE;
+    assert ((V2.all="00000000") and (HEAD.VALUE='1') and (HEAD.SUCC='0'))
+      report "***FAILED TEST: c07s03b06x00p05n01i02559 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p05n01i02559arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd
new file mode 100644
index 0000000..4a108f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2562.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p06n02i02562ent IS
+END c07s03b06x00p06n02i02562ent;
+
+ARCHITECTURE c07s03b06x00p06n02i02562arch OF c07s03b06x00p06n02i02562ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEM is array (Integer range <>) of Integer;
+    subtype T1 is MEM (1 to 6) ;
+    type LINK is access T1;
+    variable HEAD : LINK :=  new T1 ;
+  BEGIN
+    assert NOT(HEAD'LOW = 1)
+      report "***PASSED TEST: c07s03b06x00p06n02i02562"
+      severity NOTE;
+    assert (HEAD'LOW = 1)
+      report "***FAILED TEST: c07s03b06x00p06n02i02562 - The created object is constrained by the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p06n02i02562arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd
new file mode 100644
index 0000000..e208770
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2563.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p06n03i02563ent IS
+END c07s03b06x00p06n03i02563ent;
+
+ARCHITECTURE c07s03b06x00p06n03i02563arch OF c07s03b06x00p06n03i02563ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEM is array (Integer range <>) of Integer;
+    subtype T1 is MEM (1 to 6) ;
+    type LINK is access BIT_VECTOR;
+    variable HEAD : LINK :=  new BIT_VECTOR'("00110110") ;
+  BEGIN
+    assert NOT(HEAD'HIGH=7)
+      report "***PASSED TEST: c07s03b06x00p06n03i02563"
+      severity NOTE;
+    assert (HEAD'HIGH=7)
+      report "***FAILED TEST: c07s03b06x00p06n03i02563 - The created object is con strained by the bounds of the initial value defined by that expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p06n03i02563arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd
new file mode 100644
index 0000000..85b75b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2564.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p08n01i02564ent IS
+END c07s03b06x00p08n01i02564ent;
+
+ARCHITECTURE c07s03b06x00p08n01i02564arch OF c07s03b06x00p08n01i02564ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       LINK is access BIT_VECTOR;
+    variable    HEAD : LINK :=  new BIT_VECTOR'("00110110") ;
+    variable    TAIL : LINK;
+  BEGIN
+    TAIL := HEAD;
+    wait for 1 ns;
+    assert NOT( TAIL(3) = '1' )
+      report "***PASSED TEST: c07s03b06x00p08n01i02564"
+      severity NOTE;
+    assert ( TAIL(3) = '1' )
+      report "***FAILED TEST: c07s03b06x00p08n01i02564 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p08n01i02564arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd
new file mode 100644
index 0000000..7848d44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2565.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s04b01x00p08n01i02565ent IS
+END c07s04b01x00p08n01i02565ent;
+
+ARCHITECTURE c07s04b01x00p08n01i02565arch OF c07s04b01x00p08n01i02565ent IS
+  SUBTYPE s10 IS STRING (1 TO 4);
+
+  ATTRIBUTE attr1 : INTEGER;
+--
+  ATTRIBUTE attr1 OF s10 : SUBTYPE IS 4;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE v : s10;
+  BEGIN
+--
+--      The expressions in a named assocition list of more than 1 element
+--      must be locally static.
+--
+    v := (1 | s10'attr1 => 'a', OTHERS => 'b' );
+    wait for 5 ns;
+    assert NOT( v="abba" )
+      report "***PASSED TEST: c07s04b01x00p08n01i02565"
+      severity NOTE;
+    assert ( v="abba" )
+      report "***FAILED TEST: c07s04b01x00p08n01i02565 - Bad value for named aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s04b01x00p08n01i02565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd
new file mode 100644
index 0000000..94ba289
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s04b02x00p15n01i02566ent_a IS
+  GENERIC ( gen_prm : INTEGER );
+END c07s04b02x00p15n01i02566ent_a;
+
+ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
+  SIGNAL s : BIT;
+
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
+--
+--      Usage of user-defined attribute as a globally-static expression
+--
+  CONSTANT c0 : INTEGER := s'attr1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c0 = gen_prm )
+      report "***PASSED TEST: c07s04b02x00p15n01i02566"
+      severity NOTE;
+    assert ( c0 = gen_prm )
+      report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s04b02x00p15n01i02566arch_a;
+
+
+
+ENTITY c07s04b02x00p15n01i02566ent IS
+END c07s04b02x00p15n01i02566ent;
+
+ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
+
+  COMPONENT c07s04b02x00p15n01i02566ent_a
+    GENERIC ( gen_prm : INTEGER );
+  END COMPONENT;
+
+  for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
+
+BEGIN
+
+  cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
+END c07s04b02x00p15n01i02566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd
new file mode 100644
index 0000000..51d8306
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2567.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p02n01i02567ent IS
+END c07s05b00x00p02n01i02567ent;
+
+ARCHITECTURE c07s05b00x00p02n01i02567arch OF c07s05b00x00p02n01i02567ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2E6 = (2E3*1E3))
+      report "***PASSED TEST: c07s05b00x00p02n01i02567"
+      severity NOTE;
+    assert (2E6 = (2E3*1E3))
+      report "***FAILED TEST: c07s05b00x00p02n01i02567 - The same operations are defined for the type universal_integer as for any integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p02n01i02567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd
new file mode 100644
index 0000000..86460b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2569.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n02i02569ent IS
+END c07s05b00x00p16n02i02569ent;
+
+ARCHITECTURE c07s05b00x00p16n02i02569arch OF c07s05b00x00p16n02i02569ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2E6 = (2E3*1E3))
+      report "***PASSED TEST: c07s05b00x00p16n02i02569"
+      severity NOTE;
+    assert ( 2E6 = (2E3*1E3) )
+      report "***FAILED TEST: c07s05b00x00p16n02i02569 - The values of the operands and the result lie within the range of the integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n02i02569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd
new file mode 100644
index 0000000..c85b28e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2570.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n02i02570ent IS
+END c07s05b00x00p16n02i02570ent;
+
+ARCHITECTURE c07s05b00x00p16n02i02570arch OF c07s05b00x00p16n02i02570ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2.12E6 = (1.06E3*2.0E3))
+      report "***PASSED TEST: c07s05b00x00p16n02i02570"
+      severity NOTE;
+    assert ( 2.12E6 = (1.06E3*2.0E3) ) 
+      report "***FAILED TEST: c07s05b00x00p16n02i02570 - The values of the operands and the result lie within the range of the floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n02i02570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd
new file mode 100644
index 0000000..5f41d55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2573.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p02n01i02573ent IS
+  type ONE    is range 10#1#    to 1;
+  type TWO    is range 2    to 2;
+  type THREE    is range 3    to 3;
+  type FOUR    is range 4    to 4;
+  type A1    is array(FOUR range<>)of FOUR;
+  type FIVE    is range 1    to 5;
+  type U1    is range 1    to 200
+    units
+      SINGLE;
+      EVEN   =2 SINGLE;
+      DOUBLE   =10#1#E1 EVEN;
+      QUAD   =2E1 EVEN;
+    end units;
+END c13s02b00x00p02n01i02573ent;
+
+ARCHITECTURE c13s02b00x00p02n01i02573arch OF c13s02b00x00p02n01i02573ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s02b00x00p02n01i02573"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p02n01i02573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd
new file mode 100644
index 0000000..adeca5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2575.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p02n02i02575ent IS
+END c13s02b00x00p02n02i02575ent;
+
+ARCHITECTURE c13s02b00x00p02n02i02575arch OF c13s02b00x00p02n02i02575ent IS
+  type MEM is range 4 to 5;     -- Space is a separator except in this comment section
+  type M1  is range 2 to 4;     -- End of line is a separator between the
+  -- earlier comment section and this type.
+BEGIN
+  TESTING: PROCESS
+    variable j : MEM := 4;
+    variable n : M1  := 2;
+  BEGIN
+    assert NOT(j=4 and n=2) 
+      report "***PASSED TEST: c13s02b00x00p02n02i02575"
+      severity NOTE;
+    assert (j=4 and n=2) 
+      report "***FAILED TEST: c13s02b00x00p02n02i02575 - Lexical test failed."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p02n02i02575arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd
new file mode 100644
index 0000000..628008b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2578.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p05n01i02578ent IS
+END c13s02b00x00p05n01i02578ent;
+
+ARCHITECTURE c13s02b00x00p05n01i02578arch OF c13s02b00x00p05n01i02578ent IS
+  constant c1: character :='A';   -- NO_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(c1 = 'A') 
+      report "***PASSED TEST: c13s02b00x00p05n01i02578" 
+      severity NOTE;
+    assert (c1 = 'A') 
+      report "***FAILED TEST: c13s02b00x00p05n01i02578 - Lexical delimiter test failed." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p05n01i02578arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd
new file mode 100644
index 0000000..282dd2a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc258.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00258ent IS
+END c03s01b02x00p08n01i00258ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00258arch OF c03s01b02x00p08n01i00258ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V1 : integer := -2147483647;  -- No_failure_here
+    variable V2 : integer := +2147483647;  -- No_failure_here
+  BEGIN
+    assert NOT( V1 = -2147483647 and V2 = +2147483647 ) 
+      report "***PASSED TEST: c03s01b02x00p08n01i00258" 
+      severity NOTE;
+    assert ( V1 = -2147483647 and V2 = +2147483647 ) 
+      report "***FAILED TEST: c03s01b02x00p08n01i00258 - Integer declared outside bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd
new file mode 100644
index 0000000..c959df3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc26.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n02i00026ent IS
+END c04s02b00x00p10n02i00026ent;
+
+ARCHITECTURE c04s02b00x00p10n02i00026arch OF c04s02b00x00p10n02i00026ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define an ascending subtype.
+    subtype ASC_B is INTEGER range 0 to 1;
+    subtype ASC is ASC_B;
+
+    -- Define a descending subtype.
+    subtype DES_B is INTEGER range 1 downto 0;
+    subtype DES is DES_B;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+
+    -- Test the direction of the ascending range.
+    PREV := 0;
+    for I in ASC loop
+      if (I >= PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 1;
+    for I in DES loop
+      if (I <= PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST: c04s02b00x00p10n02i00026"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n02i00026 - The direction of a discrete subtype indication is the same as that of the denoted subtype in the absence of an explicit type constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n02i00026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd
new file mode 100644
index 0000000..ecc3acb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2642.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTI is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTIT is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTITY is
+end;
+
+entity This_Entity_Name_Is_Not_Long is
+end;
+
+architecture This_Arch_Name_Is_Not_Long of This_Entity_Name_Is_Not_Long is
+begin
+end;
+
+ENTITY c13s03b01x00p02n01i02642ent IS
+END c13s03b01x00p02n01i02642ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02642arch OF c13s03b01x00p02n01i02642ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p02n01i02642" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd
new file mode 100644
index 0000000..fccf425
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2643.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTI is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTIT is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTITY is
+end;
+
+entity This_Entity_Name_Is_Not_Long is
+end;
+
+architecture This_Arch_Name_Is_Not_Long of This_Entity_Name_Is_Not_Long is
+begin
+end;
+
+ENTITY c13s03b01x00p02n01i02643ent IS
+END c13s03b01x00p02n01i02643ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02643arch OF c13s03b01x00p02n01i02643ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p02n01i02643" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd
new file mode 100644
index 0000000..9f489b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p02n01i00265ent IS
+END c03s01b03x00p02n01i00265ent;
+
+ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
+  type J is           -- physical type decl
+    range 0 to 1000
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+  type J1 is access J;   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : J; 
+  BEGIN
+    k := 10 C;
+    assert NOT( k=100 B )
+      report "***PASSED TEST: c03s01b03x00p02n01i00265"
+      severity NOTE;
+    assert ( k=100 B)
+      report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p02n01i00265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd
new file mode 100644
index 0000000..8f28517
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p04n01i02675ent IS
+END c13s03b01x00p04n01i02675ent;
+
+ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
+  constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( Qwerty_tyur_RT_456T = 10 )
+      report "***PASSED TEST: c13s03b01x00p04n01i02675"
+      severity NOTE;
+    assert ( Qwerty_tyur_RT_456T = 10 )
+      report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p04n01i02675arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd
new file mode 100644
index 0000000..00cf372
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p05n01i02676ent IS
+END c13s03b01x00p05n01i02676ent;
+
+ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
+  constant   a234567_10_234567_20_234567a : integer := 2;
+  constant   a234567_10_234567_20_234567b : integer := 7;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
+      report "***PASSED TEST: c13s03b01x00p05n01i02676"
+      severity NOTE;
+    assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
+      report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n01i02676arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd
new file mode 100644
index 0000000..945287b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2677.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p05n01i02677ent IS
+END c13s03b01x00p05n01i02677ent;
+
+ARCHITECTURE c13s03b01x00p05n01i02677arch OF c13s03b01x00p05n01i02677ent IS
+  constant   a234567_aa : integer := 2;
+  constant   a234567aa  : integer := 7;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a234567_aa /= a234567aa )
+      report "***PASSED TEST: c13s03b01x00p05n01i02677"
+      severity NOTE;
+    assert ( a234567_aa /= a234567aa )
+      report "***FAILED TEST: c13s03b01x00p05n01i02677 - All characters of an identifier are significant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n01i02677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd
new file mode 100644
index 0000000..fde19bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2679.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c13s03b01x00p05n02i02679pkg is
+  fUnction F rEturn BooLEAN;
+end c13s03b01x00p05n02i02679pkg ;
+
+package body c13s03b01x00p05n02i02679pkg is
+  fUnction F rEturn BooLEAN is
+    tYpe TyP_1 is ranGe 1 to 10;
+    suBtyPe STYp_1 is TYP_1 range 1 to 5;
+    type ReC_1 is rEcorD
+                    RV_1: BOOlean;
+                    RV_2: intEGER;
+                    RV_3: REal;
+                  end RECord;
+    VariabLe V1: STYP_1;
+  beGin
+    v1 := 4;
+    rETurn FalSe;
+  enD f;
+end c13s03b01x00p05n02i02679pkg ;
+
+ENTITY c13s03b01x00p05n02i02679ent IS
+END c13s03b01x00p05n02i02679ent;
+
+ARCHITECTURE c13s03b01x00p05n02i02679arch OF c13s03b01x00p05n02i02679ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p05n02i02679"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n02i02679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd
new file mode 100644
index 0000000..eef9bff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2690.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02690ent IS
+  constant TIP_OFTHEICE    : Integer := 10 ;
+  constant TIPOFTHEICE     : Real    := 0.546 ;
+  constant T1       : Real := 3.14159_26 ;
+  constant T2       : Real := 1.0E+6 ; --- No_failure_here
+END c13s04b01x00p02n01i02690ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02690arch OF c13s04b01x00p02n01i02690ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   TIP_OFTHEICE = 10   and
+                  TIPOFTHEICE  = 0.546   and
+                  T1        =3.14159_26   and
+                  T2        = 1.0E+6   )
+      report "***PASSED TEST: c13s04b01x00p02n01i02690"
+      severity NOTE;
+    assert (   TIP_OFTHEICE = 10   and
+               TIPOFTHEICE  = 0.546   and
+               T1        =3.14159_26   and
+               T2        = 1.0E+6   )
+      report "***FAILED TEST: c13s04b01x00p02n01i02690 - Correct decimal literal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd
new file mode 100644
index 0000000..86984f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02697ent IS
+END c13s04b01x00p05n01i02697ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
+  constant   a : real := 2.34;
+  constant   b : real := 2.3_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02697"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02697arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd
new file mode 100644
index 0000000..03194cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2698.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02698ent IS
+END c13s04b01x00p05n01i02698ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02698arch OF c13s04b01x00p05n01i02698ent IS
+  constant   a : real := 234.1;
+  constant   b : real := 23_4.1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02698"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02698 - The underline character inserted between adjacent digits of a decimal literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd
new file mode 100644
index 0000000..713efd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2699.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02699ent IS
+END c13s04b01x00p05n01i02699ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02699arch OF c13s04b01x00p05n01i02699ent IS
+  constant   a : integer := 234;
+  constant   b : integer := 2_3_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02699"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02699 - The underline character inserted between adjacent digits of an integer literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02699arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd
new file mode 100644
index 0000000..a11725b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n04i00027ent IS
+END c04s02b00x00p10n04i00027ent;
+
+ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
+
+  subtype s1 is integer range 1  to 10;      -- No_failure_here
+  subtype s2 is integer range 10 downto 1;   -- No_failure_here
+
+  -- the following are null ranges
+  subtype s3 is integer range 1  downto 10;  -- No_failure_here
+  subtype s4 is integer range 10 to 1;       -- No_failure_here
+  
+BEGIN
+  TESTING: PROCESS
+    variable k1 : s1 := 1;
+    variable k2 : s2 := 10;
+    variable k  : integer := 0;
+  BEGIN
+    for i in s1 loop
+      if (i /= k1) then
+        k := 1;
+      end if;
+      if (k1 < 10) then
+        k1 := k1 + 1;
+      end if;
+    end loop;
+    for i in s2 loop
+      if (i /= k2) then
+        k := 1;
+      end if;
+      if (k2 > 1) then
+        k2 := k2 - 1;
+      end if;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c04s02b00x00p10n04i00027"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n04i00027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd
new file mode 100644
index 0000000..7886fbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2700.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02700ent IS
+END c13s04b01x00p05n02i02700ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02700arch OF c13s04b01x00p05n02i02700ent IS
+  constant   i : real := 12.3E6;
+  constant   e : real := 12.3e6;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(i = e)
+      report "***PASSED TEST: c13s04b01x00p05n02i02700"
+      severity NOTE;
+    assert ( i= e )
+      report "***FAILED TEST: c13s04b01x00p05n02i02700 - The letter E of the exponent of the real can be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02700arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd
new file mode 100644
index 0000000..9af2db7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2701.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02701ent IS
+END c13s04b01x00p05n02i02701ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02701arch OF c13s04b01x00p05n02i02701ent IS
+  constant   i : integer := 12E6;
+  constant   e : integer := 12e6;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(i = e)
+      report "***PASSED TEST: c13s04b01x00p05n02i02701"
+      severity NOTE;
+    assert ( i= e )
+      report "***FAILED TEST: c13s04b01x00p05n02i02701 - The letter E of the exponent of the integer can be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02701arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd
new file mode 100644
index 0000000..3791815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2702.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02702ent IS
+END c13s04b01x00p05n02i02702ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02702arch OF c13s04b01x00p05n02i02702ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (1e2 = 1E2)
+                     and    (1.2e1 = 1.2E1)
+                     and    (1.2e-1 = 1.2E-1)
+                     and    (16#F#e1 = 16#F#E1)
+                     and    (16#F.F#e1 = 16#F.F#E1))
+      report "***PASSED TEST: c13s04b01x00p05n02i02702"
+      severity NOTE;
+    assert (      (1e2 = 1E2)
+                  and    (1.2e1 = 1.2E1)
+                  and    (1.2e-1 = 1.2E-1)
+                  and    (16#F#e1 = 16#F#E1)
+                  and    (16#F.F#e1 = 16#F.F#E1))
+      report "***FAILED TEST: c13s04b01x00p05n02i02702 - Upper case and lower case E that used to indicate exponent in both integer and real literals test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02702arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd
new file mode 100644
index 0000000..2429f6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2703.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02703ent IS
+END c13s04b01x00p06n01i02703ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02703arch OF c13s04b01x00p06n01i02703ent IS
+  constant   i : real := 12.3;
+  constant   m : real := 1.23e1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=m )
+      report "***PASSED TEST: c13s04b01x00p06n01i02703"
+      severity NOTE;
+    assert ( i=m )
+      report "***FAILED TEST: c13s04b01x00p06n01i02703 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd
new file mode 100644
index 0000000..b64f41d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2704.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02704ent IS
+END c13s04b01x00p06n01i02704ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02704arch OF c13s04b01x00p06n01i02704ent IS
+  constant   i : integer := 12300;
+  constant   m : integer := 123e2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=m )
+      report "***PASSED TEST: c13s04b01x00p06n01i02704"
+      severity NOTE;
+    assert ( i=m )
+      report "***FAILED TEST: c13s04b01x00p06n01i02704 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd
new file mode 100644
index 0000000..66d3355
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2705.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02705ent IS
+END c13s04b01x00p06n01i02705ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02705arch OF c13s04b01x00p06n01i02705ent IS
+  constant   i : real := 0.12;
+  constant   m : real := 1.2e-1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( abs(i-m) < 0.00000000001 )
+      report "***PASSED TEST: c13s04b01x00p06n01i02705"
+      severity NOTE;
+    assert ( abs(i-m) < 0.00000000001 )
+      report "***FAILED TEST: c13s04b01x00p06n01i02705 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd
new file mode 100644
index 0000000..9d5d313
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2707.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02707ent IS
+END c13s04b01x00p11n01i02707ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02707arch OF c13s04b01x00p11n01i02707ent IS
+  constant   i : integer := 003;
+  constant   k : integer :=   3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=k )
+      report "***PASSED TEST: c13s04b01x00p11n01i02707"
+      severity NOTE;
+    assert ( i=k )
+      report "***FAILED TEST: c13s04b01x00p11n01i02707 - Leading zeros should be allowed for an integer literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02707arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd
new file mode 100644
index 0000000..95bc8c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2708.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02708ent IS
+END c13s04b01x00p11n01i02708ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02708arch OF c13s04b01x00p11n01i02708ent IS
+  constant   i : real := 00567.8;
+  constant   k : real :=   567.8;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=k )
+      report "***PASSED TEST: c13s04b01x00p11n01i02708"
+      severity NOTE;
+    assert ( i=k )
+      report "***FAILED TEST: c13s04b01x00p11n01i02708 - Leading zeros should be allowed for an real literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02708arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd
new file mode 100644
index 0000000..a026f2a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2709.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p13n01i02709ent IS
+END c13s04b01x00p13n01i02709ent;
+
+ARCHITECTURE c13s04b01x00p13n01i02709arch OF c13s04b01x00p13n01i02709ent IS
+  constant   k : integer := 3E0;
+  constant   i : integer := 3  ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( k=i )
+      report "***PASSED TEST: c13s04b01x00p13n01i02709"
+      severity NOTE;
+    assert ( k=i )
+      report "***FAILED TEST: c13s04b01x00p13n01i02709 - A zero exponent should be allowed for an integer liiteral."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p13n01i02709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd
new file mode 100644
index 0000000..e8b694d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2710.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02710ent IS
+END c13s04b01x00p11n01i02710ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02710arch OF c13s04b01x00p11n01i02710ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(       (5 = 000005)
+                      and (10#030# = 10#30#)
+                      and (1E004 = 1E4)
+                      and (10#01_2#E1 = 0010#1_2#E1)) 
+      report "***PASSED TEST: c13s04b01x00p11n01i02710"
+      severity NOTE;
+    assert (       (5 = 000005)
+                   and (10#030# = 10#30#)
+                   and (1E004 = 1E4)
+                   and (10#01_2#E1 = 0010#1_2#E1)) 
+      report "***FAILED TEST: c13s04b01x00p11n01i02710 - Leading zeros should be allowed in integral parts of integer literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02710arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd
new file mode 100644
index 0000000..d5125a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2711.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02711ent IS
+END c13s04b02x00p01n01i02711ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02711arch OF c13s04b02x00p01n01i02711ent IS
+  constant   two   : integer := 2#1111_1111#;
+  constant   sixteen   : integer := 16#FF#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( two=sixteen )
+      report "***PASSED TEST: c13s04b02x00p01n01i02711"
+      severity NOTE;
+    assert ( two=sixteen )
+      report "***FAILED TEST: c13s04b02x00p01n01i02711 - Integer 255 in the base of 2 and 16 should be equal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd
new file mode 100644
index 0000000..2a3924a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02712ent IS
+END c13s04b02x00p01n01i02712ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (2#11#=3)
+                     and    (7#66#=48)
+                     and    (12#BB#=143)
+                     and    (16#FF#=255)) 
+      report "***PASSED TEST: c13s04b02x00p01n01i02712"
+      severity NOTE;
+    assert (      (2#11#=3)
+                  and    (7#66#=48)
+                  and    (12#BB#=143)
+                  and    (16#FF#=255)) 
+      report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02712arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd
new file mode 100644
index 0000000..f6b7987
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2713.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02713ent IS
+END c13s04b02x00p01n01i02713ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02713arch OF c13s04b02x00p01n01i02713ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   16#F.FF#E+2 = 2#1.1111_1111_111#E11   and
+                  16#F.FF#E+2 = 4095.0   ) 
+      report "***PASSED TEST: c13s04b02x00p01n01i02713"
+      severity NOTE;
+    assert (   16#F.FF#E+2 = 2#1.1111_1111_111#E11   and
+               16#F.FF#E+2 = 4095.0   ) 
+      report "***FAILED TEST: c13s04b02x00p01n01i02713 - Base literals expressed in two and sixteen test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02713arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd
new file mode 100644
index 0000000..89905c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2718.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p02n01i02718ent IS
+END c13s04b02x00p02n01i02718ent;
+
+ARCHITECTURE c13s04b02x00p02n01i02718arch OF c13s04b02x00p02n01i02718ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real := 5#1234.4321#E-10;   --No_failure_here
+  BEGIN
+    wait for 5 ns;
+    assert NOT( total_time = 5#1234.4321#E-10 )
+      report "***PASSED TEST: c13s04b02x00p02n01i02718"
+      severity NOTE;
+    assert ( total_time = 5#1234.4321#E-10 )
+      report "***FAILED TEST: c13s04b02x00p02n01i02718 - Based literal literal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p02n01i02718arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd
new file mode 100644
index 0000000..eda6823
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2719.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p03n01i02719ent IS
+END c13s04b02x00p03n01i02719ent;
+
+ARCHITECTURE c13s04b02x00p03n01i02719arch OF c13s04b02x00p03n01i02719ent IS
+  constant T1 : Integer := 16#E#E1;
+  constant T2 : Real    := 5#1234.4321#; --- No_Failure_here
+
+  constant T3 : Integer := 2#1111_1111#;
+  constant T4 : Integer := 16#FF#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   T1 = 16#E#E1      and
+                  T2 = 5#1234.4321#   and
+                  T3 = 2#1111_1111#   and
+                  T4 = 16#FF#      )   
+      report "***PASSED TEST: c13s04b02x00p03n01i02719" 
+      severity NOTE;
+    assert (   T1 = 16#E#E1      and
+               T2 = 5#1234.4321#   and
+               T3 = 2#1111_1111#   and
+               T4 = 16#FF#      )   
+      report "***FAILED TEST: c13s04b02x00p03n01i02719 - Base literal as an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p03n01i02719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd
new file mode 100644
index 0000000..5d1289c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc272.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p06n01i00272ent IS
+END c03s01b03x00p06n01i00272ent;
+
+ARCHITECTURE c03s01b03x00p06n01i00272arch OF c03s01b03x00p06n01i00272ent IS
+  type small is range 0 to 2_000_000_000      --   < 2**31-1
+    units
+      lu;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable   smaller : small;
+  BEGIN
+    smaller := 2000000000 lu;
+    wait for 5 ns;
+    assert NOT( smaller = 2000000000 lu ) 
+      report "***PASSED TEST: c03s01b03x00p06n01i00272" 
+      severity NOTE;
+    assert ( smaller = 2000000000 lu ) 
+      report "***FAILED TEST: c03s01b03x00p06n01i00272 - Large physical type declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p06n01i00272arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd
new file mode 100644
index 0000000..e8f06bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2722.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n01i02722ent IS
+END c13s04b02x00p06n01i02722ent;
+
+ARCHITECTURE c13s04b02x00p06n01i02722arch OF c13s04b02x00p06n01i02722ent IS
+  constant a1:integer   :=16#987_654#;
+  constant b1:integer   :=16#987654#;
+  constant a2:integer   :=16#A_B#;
+  constant b2:integer   :=16#AB#;
+  constant a3:integer   :=10#7_8#;
+  constant b3:integer   :=10#78#;
+  constant a4:integer   :=2#11_11#;
+  constant b4:integer   :=2#1111#;
+  constant a5:real   :=16#C.C_D#;
+  constant b5:real   :=16#C.CD#;
+  constant a6:real   :=10#8.9_7#;
+  constant b6:real   :=10#8.97#;
+  constant a7:real   :=2#11_11.11_11#;
+  constant b7:real   :=2#1111.1111#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert (a1=b1) report "Underline affects the value of a based literal" severity failure;
+    assert (a2=b2) report "Underline affects the value of a based literal" severity failure;
+    assert (a3=b3) report "Underline affects the value of a based literal" severity failure;
+    assert (a4=b4) report "Underline affects the value of a based literal" severity failure;
+    assert (a5=b5) report "Underline affects the value of a based literal" severity failure;
+    assert (a6=b6) report "Underline affects the value of a based literal" severity failure;
+    assert (a7=b7) report "Underline affects the value of a based literal" severity failure;
+    assert NOT(   a1=b1   and
+                  a2=b2   and
+                  a3=b3   and
+                  a4=b4   and
+                  a5=b5   and
+                  a6=b6   and
+                  a7=b7   )
+      report "***PASSED TEST: c13s04b02x00p06n01i02722"
+      severity NOTE;
+    assert (   a1=b1   and
+               a2=b2   and
+               a3=b3   and
+               a4=b4   and
+               a5=b5   and
+               a6=b6   and
+               a7=b7   )
+      report "***FAILED TEST: c13s04b02x00p06n01i02722 - An underline character inserted between adjacent digits of a based literal does not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n01i02722arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd
new file mode 100644
index 0000000..ff4075e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2724.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n04i02724ent IS
+END c13s04b02x00p06n04i02724ent;
+
+ARCHITECTURE c13s04b02x00p06n04i02724arch OF c13s04b02x00p06n04i02724ent IS
+  constant a1   :integer:=16#A#;
+  constant b1   :integer:=16#a#;
+  constant a2   :integer:=16#B#;
+  constant b2   :integer:=16#b#;
+  constant a3   :integer:=16#C#;
+  constant b3   :integer:=16#c#;
+  constant a4   :integer:=16#D#;
+  constant b4   :integer:=16#d#;
+  constant a5   :integer:=16#E#;
+  constant b5   :integer:=16#e#;
+  constant a6   :integer:=16#F#;
+  constant b6   :integer:=16#f#;
+
+  constant a7   :real:=16#A.A#;
+  constant b7   :real:=16#a.a#;
+  constant a8   :real:=16#B.B#;
+  constant b8   :real:=16#b.b#;
+  constant a9   :real:=16#C.C#;
+  constant b9   :real:=16#c.c#;
+  constant a10   :real:=16#D.D#;
+  constant b10   :real:=16#d.d#;
+  constant a11   :real:=16#E.E#;
+  constant b11   :real:=16#e.e#;
+  constant a12   :real:=16#F.F#;
+  constant b12   :real:=16#f.f#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert (a1=b1) report "A & a not the same for an extended digit in an integer based literal" severity failure;
+    assert (a2=b2) report "B & b not the same for an extended digit in an integer based literal" severity failure;
+    assert (a3=b3) report "C & c not the same for an extended digit in an integer based literal" severity failure;
+    assert (a4=b4) report "D & d not the same for an extended digit in an integer based literal" severity failure;
+    assert (a5=b5) report "E & e not the same for an extended digit in an integer based literal" severity failure;
+    assert (a6=b6) report "F & f not the same for an extended digit in an integer based literal" severity failure;
+    
+    assert (a7=b7) report "A & a not the same for an extended digit in a real based literal" severity failure;
+    assert (a8=b8) report "B & b not the same for an extended digit in a real based literal" severity failure;
+    assert (a9=b9) report "C & c not the same for an extended digit in a real based literal" severity failure;
+    assert (a10=b10) report "D & d not the same for an extended digit in a real based literal" severity failure;
+    assert (a11=b11) report "E & e not the same for an extended digit in a real based literal" severity failure;
+    assert (a12=b12) report "F & f not the same for an extended digit in a real based literal" severity failure;
+    assert NOT(    a1   = b1    and
+                   a2   = b2   and
+                   a3   = b3   and
+                   a4   = b4   and
+                   a5   = b5   and
+                   a6   = b6   and
+                   a7   = b7   and
+                   a8   = b8   and
+                   a9   = b9   and
+                   a10   = b10   and
+                   a11   = b11   and
+                   a12   = b12   )
+      report "***PASSED TEST: c13s04b02x00p06n04i02724"
+      severity NOTE;
+    assert (    a1   = b1    and
+                a2   = b2   and
+                a3   = b3   and
+                a4   = b4   and
+                a5   = b5   and
+                a6   = b6   and
+                a7   = b7   and
+                a8   = b8   and
+                a9   = b9   and
+                a10   = b10   and
+                a11   = b11   and
+                a12   = b12   )
+      report "***FAILED TEST: c13s04b02x00p06n04i02724 - Upper and lower case should be allowed for a letter in integer and real based literal with the came meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n04i02724arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd
new file mode 100644
index 0000000..ed50cc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2725.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n03i02725ent IS
+END c13s04b02x00p06n03i02725ent;
+
+ARCHITECTURE c13s04b02x00p06n03i02725arch OF c13s04b02x00p06n03i02725ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(       (16#ABCDEF#=16#abcdef#)
+                      and    (16#abcd.EF#=16#ABCD.ef#))
+      report "***PASSED TEST: c13s04b02x00p06n03i02725"
+      severity NOTE;
+    assert (       (16#ABCDEF#=16#abcdef#)
+                   and    (16#abcd.EF#=16#ABCD.ef#))
+      report "***FAILED TEST: c13s04b02x00p06n03i02725d - The only letters allowed as extended digits are the letters A through F."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n03i02725arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd
new file mode 100644
index 0000000..33ef3e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2726.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p07n02i02726ent IS
+END c13s04b02x00p07n02i02726ent;
+
+ARCHITECTURE c13s04b02x00p07n02i02726arch OF c13s04b02x00p07n02i02726ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( 16#E#E1 = 224 )
+      report "***PASSED TEST: c13s04b02x00p07n02i02726"
+      severity NOTE;
+    assert ( 16#E#E1 = 224 )
+      report "***FAILED TEST: c13s04b02x00p07n02i02726 - Value of a based literal with the exponent test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p07n02i02726arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd
new file mode 100644
index 0000000..89bb05c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2733.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02733ent IS
+END c13s05b00x00p01n01i02733ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02733arch OF c13s05b00x00p01n01i02733ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      grph is array (1 to 95) of character;
+    variable   k : grph;
+  BEGIN
+    k(1) := 'A';
+    k(2) := 'B';
+    assert NOT(   k(1) = 'A'   and
+                  k(2) = 'B'   ) 
+      report "***PASSED TEST: c13s05b00x00p01n01i02733"
+      severity NOTE;
+    assert (   k(1) = 'A'   and
+               k(2) = 'B'   ) 
+      report "***FAILED TEST: c13s05b00x00p01n01i02733 - Graphic charcters be used as a character literal test fail." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02733arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd
new file mode 100644
index 0000000..7b1dead
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd
@@ -0,0 +1,333 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2734.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02734ent IS
+END c13s05b00x00p01n01i02734ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02734arch OF c13s05b00x00p01n01i02734ent IS
+
+BEGIN
+   TESTING: PROCESS
+    type      grph is array (1 to 95) of character;
+    variable   k : grph;
+   BEGIN
+      k(1)  := 'A';
+      k(2)  := 'B';
+      k(3)  := 'C';
+      k(4)  := 'D';
+      k(5)  := 'E';
+      k(6)  := 'F';
+      k(7)  := 'G';
+      k(8)  := 'H';
+      k(9)  := 'I';
+      k(10) := 'J';
+      k(11) := 'K';
+      k(12) := 'L';
+      k(13) := 'M';
+      k(14) := 'N';
+      k(15) := 'O';
+      k(16) := 'P';
+      k(17) := 'Q';
+      k(18) := 'R';
+      k(19) := 'S';
+      k(20) := 'T';
+      k(21) := 'U';
+      k(22) := 'V';
+      k(23) := 'W';
+      k(24) := 'X';
+      k(25) := 'Y';
+      k(26) := 'Z';
+      k(27) := '0';
+      k(28) := '1';
+      k(29) := '2';
+      k(30) := '3';
+      k(31) := '4';
+      k(32) := '5';
+      k(33) := '6';
+      k(34) := '7';
+      k(35) := '8';
+      k(36) := '9';
+      k(37) := '"';
+      k(38) := '#';
+      k(39) := '&';
+      k(40) := ''';
+      k(41) := '(';
+      k(42) := ')';
+      k(43) := '*';
+      k(44) := '+';
+      k(45) := ',';
+      k(46) := '-';
+      k(47) := '.';
+      k(48) := '/';
+      k(49) := ':';
+      k(50) := ';';
+      k(51) := '<';
+      k(52) := '=';
+      k(53) := '>';
+      k(54) := '_';
+      k(55) := '|';
+      k(56) := ' ';
+      k(57) := 'a';
+      k(58) := 'b';
+      k(59) := 'c';
+      k(60) := 'd';
+      k(61) := 'e';
+      k(62) := 'f';
+      k(63) := 'g';
+      k(64) := 'h';
+      k(65) := 'i';
+      k(66) := 'j';
+      k(67) := 'k';
+      k(68) := 'l';
+      k(69) := 'm';
+      k(70) := 'n';
+      k(71) := 'o';
+      k(72) := 'p';
+      k(73) := 'q';
+      k(74) := 'r';
+      k(75) := 's';
+      k(76) := 't';
+      k(77) := 'u';
+      k(78) := 'v';
+      k(79) := 'w';
+      k(80) := 'x';
+      k(81) := 'y';
+      k(82) := 'z';
+      k(83) := '!';
+      k(84) := '$';
+      k(85) := '%';
+      k(86) := '@';
+      k(87) := '?';
+      k(88) := '[';
+      k(89) := '\';
+      k(90) := ']';
+      k(91) := '^';
+      k(92) := '`';
+      k(93) := '{';
+      k(94) := '}';
+      k(95) := '~';
+   assert NOT(   k(1)  = 'A'   and
+         k(2)  = 'B'   and 
+         k(3)  = 'C'   and
+         k(4)  = 'D'   and
+         k(5)  = 'E'   and
+         k(6)  = 'F'   and
+         k(7)  = 'G'   and
+         k(8)  = 'H'   and
+         k(9)  = 'I'   and
+         k(10) = 'J'   and
+         k(11) = 'K'   and
+         k(12) = 'L'   and
+         k(13) = 'M'   and
+         k(14) = 'N'   and
+         k(15) = 'O'   and
+         k(16) = 'P'   and
+         k(17) = 'Q'   and
+         k(18) = 'R'   and
+         k(19) = 'S'   and
+         k(20) = 'T'   and
+         k(21) = 'U'   and
+         k(22) = 'V'   and
+         k(23) = 'W'   and
+         k(24) = 'X'   and
+         k(25) = 'Y'   and
+         k(26) = 'Z'   and
+         k(27) = '0'   and
+         k(28) = '1'   and
+         k(29) = '2'   and
+         k(30) = '3'   and
+         k(31) = '4'   and
+         k(32) = '5'   and
+         k(33) = '6'   and
+         k(34) = '7'   and
+         k(35) = '8'   and
+         k(36) = '9'   and
+         k(37) = '"'   and
+         k(38) = '#'   and
+         k(39) = '&'   and
+         k(40) = '''   and
+         k(41) = '('   and
+         k(42) = ')'   and
+         k(43) = '*'   and
+         k(44) = '+'   and
+         k(45) = ','   and
+         k(46) = '-'   and
+         k(47) = '.'   and
+         k(48) = '/'   and
+         k(49) = ':'   and
+         k(50) = ';'   and
+         k(51) = '<'   and
+         k(52) = '='   and
+         k(53) = '>'   and
+         k(54) = '_'   and
+         k(55) = '|'   and
+         k(56) = ' '   and
+         k(57) = 'a'   and
+         k(58) = 'b'   and
+         k(59) = 'c'   and
+         k(60) = 'd'   and
+         k(61) = 'e'   and
+         k(62) = 'f'   and
+         k(63) = 'g'   and
+         k(64) = 'h'   and
+         k(65) = 'i'   and
+         k(66) = 'j'   and
+         k(67) = 'k'   and
+         k(68) = 'l'   and
+         k(69) = 'm'   and
+         k(70) = 'n'   and
+         k(71) = 'o'   and
+         k(72) = 'p'   and
+         k(73) = 'q'   and
+         k(74) = 'r'   and
+         k(75) = 's'   and
+         k(76) = 't'   and
+         k(77) = 'u'   and
+         k(78) = 'v'   and
+         k(79) = 'w'   and
+         k(80) = 'x'   and
+         k(81) = 'y'   and
+         k(82) = 'z'   and
+         k(83) = '!'   and
+         k(84) = '$'   and
+         k(85) = '%'   and
+         k(86) = '@'   and
+         k(87) = '?'   and
+         k(88) = '['   and
+         k(89) = '\'   and
+         k(90) = ']'   and
+         k(91) = '^'   and
+         k(92) = '`'   and
+         k(93) = '{'   and
+         k(94) = '}'   and
+         k(95) = '~'   )
+      report "***PASSED TEST: /src/ch13/sc05/p001-002/s010107.vhd" 
+      severity NOTE;
+   assert (   k(1)  = 'A'   and
+         k(2)  = 'B'   and 
+         k(3)  = 'C'   and
+         k(4)  = 'D'   and
+         k(5)  = 'E'   and
+         k(6)  = 'F'   and
+         k(7)  = 'G'   and
+         k(8)  = 'H'   and
+         k(9)  = 'I'   and
+         k(10) = 'J'   and
+         k(11) = 'K'   and
+         k(12) = 'L'   and
+         k(13) = 'M'   and
+         k(14) = 'N'   and
+         k(15) = 'O'   and
+         k(16) = 'P'   and
+         k(17) = 'Q'   and
+         k(18) = 'R'   and
+         k(19) = 'S'   and
+         k(20) = 'T'   and
+         k(21) = 'U'   and
+         k(22) = 'V'   and
+         k(23) = 'W'   and
+         k(24) = 'X'   and
+         k(25) = 'Y'   and
+         k(26) = 'Z'   and
+         k(27) = '0'   and
+         k(28) = '1'   and
+         k(29) = '2'   and
+         k(30) = '3'   and
+         k(31) = '4'   and
+         k(32) = '5'   and
+         k(33) = '6'   and
+         k(34) = '7'   and
+         k(35) = '8'   and
+         k(36) = '9'   and
+         k(37) = '"'   and
+         k(38) = '#'   and
+         k(39) = '&'   and
+         k(40) = '''   and
+         k(41) = '('   and
+         k(42) = ')'   and
+         k(43) = '*'   and
+         k(44) = '+'   and
+         k(45) = ','   and
+         k(46) = '-'   and
+         k(47) = '.'   and
+         k(48) = '/'   and
+         k(49) = ':'   and
+         k(50) = ';'   and
+         k(51) = '<'   and
+         k(52) = '='   and
+         k(53) = '>'   and
+         k(54) = '_'   and
+         k(55) = '|'   and
+         k(56) = ' '   and
+         k(57) = 'a'   and
+         k(58) = 'b'   and
+         k(59) = 'c'   and
+         k(60) = 'd'   and
+         k(61) = 'e'   and
+         k(62) = 'f'   and
+         k(63) = 'g'   and
+         k(64) = 'h'   and
+         k(65) = 'i'   and
+         k(66) = 'j'   and
+         k(67) = 'k'   and
+         k(68) = 'l'   and
+         k(69) = 'm'   and
+         k(70) = 'n'   and
+         k(71) = 'o'   and
+         k(72) = 'p'   and
+         k(73) = 'q'   and
+         k(74) = 'r'   and
+         k(75) = 's'   and
+         k(76) = 't'   and
+         k(77) = 'u'   and
+         k(78) = 'v'   and
+         k(79) = 'w'   and
+         k(80) = 'x'   and
+         k(81) = 'y'   and
+         k(82) = 'z'   and
+         k(83) = '!'   and
+         k(84) = '$'   and
+         k(85) = '%'   and
+         k(86) = '@'   and
+         k(87) = '?'   and
+         k(88) = '['   and
+         k(89) = '\'   and
+         k(90) = ']'   and
+         k(91) = '^'   and
+         k(92) = '`'   and
+         k(93) = '{'   and
+         k(94) = '}'   and
+         k(95) = '~'   )
+      report "***FAILED TEST: c13s05b00x00p01n01i02734 - Any one of the 95 graphic characters should be a character literal." 
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02734arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd
new file mode 100644
index 0000000..7634419
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2735.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p01n01i02735ent IS
+END c13s06b00x00p01n01i02735ent;
+
+ARCHITECTURE c13s06b00x00p01n01i02735arch OF c13s06b00x00p01n01i02735ent IS
+  constant S : STRING := "";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   S = ""   ) 
+      report "***PASSED TEST: c13s06b00x00p01n01i02735"
+      severity NOTE;
+    assert (   S = ""   ) 
+      report "***FAILED TEST: c13s06b00x00p01n01i02735 - Null string as string literal lexical test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p01n01i02735arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd
new file mode 100644
index 0000000..38a6cbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p01n01i02736ent IS
+END c13s06b00x00p01n01i02736ent;
+
+ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S45 : STRING (1 to 44);
+    variable S50 : STRING (1 to 50);
+  BEGIN
+    S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
+    S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
+    wait for 5 ns;
+    assert NOT(       S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
+                      and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
+      report "***PASSED TEST: c13s06b00x00p01n01i02736"
+      severity NOTE;
+    assert (       S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
+                   and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
+      report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p01n01i02736arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd
new file mode 100644
index 0000000..b2ddd22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd
@@ -0,0 +1,526 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2737.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n01i02737ent IS
+END c13s06b00x00p03n01i02737ent;
+
+ARCHITECTURE c13s06b00x00p03n01i02737arch OF c13s06b00x00p03n01i02737ent IS
+  constant s01: string:="A ";   --  1
+  constant s02: string:="B ";   --  2
+  constant s03: string:="C ";   --  3
+  constant s04: string:="D ";   --  4
+  constant s05: string:="E ";   --  5
+  constant s06: string:="F ";   --  6
+  constant s07: string:="G ";   --  7
+  constant s08: string:="H ";   --  8
+  constant s09: string:="I ";   --  9
+  constant s10: string:="J ";   -- 10
+  constant s11: string:="K ";   -- 11
+  constant s12: string:="L ";   -- 12
+  constant s13: string:="M ";   -- 13
+  constant s14: string:="N ";   -- 14
+  constant s15: string:="O ";   -- 15
+  constant s16: string:="P ";   -- 16
+  constant s17: string:="Q ";   -- 17
+  constant s18: string:="R ";   -- 18
+  constant s19: string:="S ";   -- 19
+  constant s20: string:="T ";   -- 20
+  constant s21: string:="U ";   -- 21
+  constant s22: string:="V ";   -- 22
+  constant s23: string:="W ";   -- 23
+  constant s24: string:="X ";   -- 24
+  constant s25: string:="Y ";   -- 25
+  constant s26: string:="Z ";   -- 26
+  constant s27: string:="0 ";   -- 27
+  constant s28: string:="1 ";   -- 28
+  constant s29: string:="2 ";   -- 29
+  constant s30: string:="3 ";   -- 30
+  constant s31: string:="4 ";   -- 31
+  constant s32: string:="5 ";   -- 32
+  constant s33: string:="6 ";   -- 33
+  constant s34: string:="7 ";   -- 34
+  constant s35: string:="8 ";   -- 35
+  constant s36: string:="9 ";   -- 36
+  constant s37: string:=""" ";   -- 37
+  constant s38: string:="# ";   -- 38
+  constant s39: string:="& ";   -- 39
+  constant s40: string:="' ";   -- 40
+  constant s41: string:="( ";   -- 41
+  constant s42: string:=") ";   -- 42
+  constant s43: string:="* ";   -- 43
+  constant s44: string:="+ ";   -- 44
+  constant s45: string:=", ";   -- 45
+  constant s46: string:="- ";   -- 46
+  constant s47: string:=". ";   -- 47
+  constant s48: string:="/ ";   -- 48
+  constant s49: string:=": ";   -- 49
+  constant s50: string:="; ";   -- 50
+  constant s51: string:="< ";   -- 51
+  constant s52: string:="= ";   -- 52
+  constant s53: string:="> ";   -- 53
+  constant s54: string:="_ ";   -- 54
+  constant s55: string:="| ";   -- 55
+  constant s56: string:="  ";   -- 56
+  constant s57: string:="a ";   -- 57
+  constant s58: string:="b ";   -- 58
+  constant s59: string:="c ";   -- 59
+  constant s60: string:="d ";   -- 60
+  constant s61: string:="e ";   -- 61
+  constant s62: string:="f ";   -- 62
+  constant s63: string:="g ";   -- 63
+  constant s64: string:="h ";   -- 64
+  constant s65: string:="i ";   -- 65
+  constant s66: string:="j ";   -- 66
+  constant s67: string:="k ";   -- 67
+  constant s68: string:="l ";   -- 68
+  constant s69: string:="m ";   -- 69
+  constant s70: string:="n ";   -- 70
+  constant s71: string:="o ";   -- 71
+  constant s72: string:="p ";   -- 72
+  constant s73: string:="q ";   -- 73
+  constant s74: string:="r ";   -- 74
+  constant s75: string:="s ";   -- 75
+  constant s76: string:="t ";   -- 76
+  constant s77: string:="u ";   -- 77
+  constant s78: string:="v ";   -- 78
+  constant s79: string:="w ";   -- 79
+  constant s80: string:="x ";   -- 80
+  constant s81: string:="y ";   -- 81
+  constant s82: string:="z ";   -- 82
+  constant s83: string:="! ";   -- 83
+  constant s84: string:="$ ";   -- 84
+  constant s85: string:="% ";   -- 85
+  constant s86: string:="@ ";   -- 86
+  constant s87: string:="? ";   -- 87
+  constant s88: string:="[ ";   -- 88
+  constant s89: string:="\ ";   -- 89
+  constant s90: string:="] ";   -- 90
+  constant s91: string:="^ ";   -- 91
+  constant s92: string:="` ";   -- 92
+  constant s93: string:="{ ";   -- 93
+  constant s94: string:="} ";   -- 94
+  constant s95: string:="~ ";   -- 95
+  
+------------------------------------------------------------
+  
+  constant c01: string:=('A',' ');   --  1
+  constant c02: string:=('B',' ');   --  2
+  constant c03: string:=('C',' ');   --  3
+  constant c04: string:=('D',' ');   --  4
+  constant c05: string:=('E',' ');   --  5
+  constant c06: string:=('F',' ');   --  6
+  constant c07: string:=('G',' ');   --  7
+  constant c08: string:=('H',' ');   --  8
+  constant c09: string:=('I',' ');   --  9
+  constant c10: string:=('J',' ');   -- 10
+  constant c11: string:=('K',' ');   -- 11
+  constant c12: string:=('L',' ');   -- 12
+  constant c13: string:=('M',' ');   -- 13
+  constant c14: string:=('N',' ');   -- 14
+  constant c15: string:=('O',' ');   -- 15
+  constant c16: string:=('P',' ');   -- 16
+  constant c17: string:=('Q',' ');   -- 17  
+  constant c18: string:=('R',' ');   -- 18
+  constant c19: string:=('S',' ');   -- 19
+  constant c20: string:=('T',' ');   -- 20
+  constant c21: string:=('U',' ');   -- 21
+  constant c22: string:=('V',' ');   -- 22
+  constant c23: string:=('W',' ');   -- 23
+  constant c24: string:=('X',' ');   -- 24
+  constant c25: string:=('Y',' ');   -- 25
+  constant c26: string:=('Z',' ');   -- 26
+  constant c27: string:=('0',' ');   -- 27
+  constant c28: string:=('1',' ');   -- 28
+  constant c29: string:=('2',' ');   -- 29
+  constant c30: string:=('3',' ');   -- 30
+  constant c31: string:=('4',' ');   -- 31
+  constant c32: string:=('5',' ');   -- 32
+  constant c33: string:=('6',' ');   -- 33
+  constant c34: string:=('7',' ');   -- 34
+  constant c35: string:=('8',' ');   -- 35
+  constant c36: string:=('9',' ');   -- 36
+  constant c37: string:=('"',' ');   -- 37
+  constant c38: string:=('#',' ');   -- 38
+  constant c39: string:=('&',' ');   -- 39
+  constant c40: string:=(''',' ');   -- 40
+  constant c41: string:=('(',' ');   -- 41
+                         constant c42: string:=(')',' ');   -- 42
+  constant c43: string:=('*',' ');   -- 43
+  constant c44: string:=('+',' ');   -- 44
+  constant c45: string:=(',',' ');   -- 45
+  constant c46: string:=('-',' ');   -- 46
+  constant c47: string:=('.',' ');   -- 47
+  constant c48: string:=('/',' ');   -- 48
+  constant c49: string:=(':',' ');   -- 49
+  constant c50: string:=(';',' ');   -- 50
+  constant c51: string:=('<',' ');   -- 51
+  constant c52: string:=('=',' ');   -- 52
+  constant c53: string:=('>',' ');   -- 53
+  constant c54: string:=('_',' ');   -- 54
+  constant c55: string:=('|',' ');   -- 55
+  constant c56: string:=(' ',' ');   -- 56
+  constant c57: string:=('a',' ');   -- 57
+  constant c58: string:=('b',' ');   -- 58
+  constant c59: string:=('c',' ');   -- 59
+  constant c60: string:=('d',' ');   -- 60
+  constant c61: string:=('e',' ');   -- 61
+  constant c62: string:=('f',' ');   -- 62
+  constant c63: string:=('g',' ');   -- 63
+  constant c64: string:=('h',' ');   -- 64
+  constant c65: string:=('i',' ');   -- 65
+  constant c66: string:=('j',' ');   -- 66
+  constant c67: string:=('k',' ');   -- 67
+  constant c68: string:=('l',' ');   -- 68
+  constant c69: string:=('m',' ');   -- 69
+  constant c70: string:=('n',' ');   -- 70
+  constant c71: string:=('o',' ');   -- 71
+  constant c72: string:=('p',' ');   -- 72
+  constant c73: string:=('q',' ');   -- 73
+  constant c74: string:=('r',' ');   -- 74  
+  constant c75: string:=('s',' ');   -- 75
+  constant c76: string:=('t',' ');   -- 76
+  constant c77: string:=('u',' ');   -- 77
+  constant c78: string:=('v',' ');   -- 78
+  constant c79: string:=('w',' ');   -- 79
+  constant c80: string:=('x',' ');   -- 80
+  constant c81: string:=('y',' ');   -- 81
+  constant c82: string:=('z',' ');   -- 82
+  constant c83: string:=('!',' ');   -- 83
+  constant c84: string:=('$',' ');   -- 84
+  constant c85: string:=('%',' ');   -- 85
+  constant c86: string:=('@',' ');   -- 86
+  constant c87: string:=('?',' ');   -- 87
+  constant c88: string:=('[',' ');   -- 88
+                         constant c89: string:=('\',' ');   -- 89
+                         constant c90: string:=(']',' ');   -- 90
+  constant c91: string:=('^',' ');   -- 91
+  constant c92: string:=('`',' ');   -- 92
+  constant c93: string:=('{',' ');   -- 93
+                         constant c94: string:=('}',' ');   -- 94
+  constant c95: string:=('~',' ');   -- 95
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    assert (s01=c01) report "problem with  1  - 'A' " severity failure;
+    assert (s02=c02) report "problem with  2  - 'B' " severity failure;
+    assert (s03=c03) report "problem with  3  - 'C' " severity failure;
+    assert (s04=c04) report "problem with  4  - 'D' " severity failure;
+    assert (s05=c05) report "problem with  5  - 'E' " severity failure;
+    assert (s06=c06) report "problem with  6  - 'F' " severity failure;
+    assert (s07=c07) report "problem with  7  - 'G' " severity failure;
+    assert (s08=c08) report "problem with  8  - 'H' " severity failure;
+    assert (s09=c09) report "problem with  9  - 'I' " severity failure;
+    assert (s10=c10) report "problem with  10 - 'J' " severity failure;
+    assert (s11=c11) report "problem with  11 - 'K' " severity failure;
+    assert (s12=c12) report "problem with  12 - 'L' " severity failure;
+    assert (s13=c13) report "problem with  13 - 'M' " severity failure;
+    assert (s14=c14) report "problem with  14 - 'N' " severity failure;
+    assert (s15=c15) report "problem with  15 - 'O' " severity failure;
+    assert (s16=c16) report "problem with  16 - 'P' " severity failure;
+    assert (s17=c17) report "problem with  17 - 'Q' " severity failure;
+    assert (s18=c18) report "problem with  18 - 'R' " severity failure;
+    assert (s19=c19) report "problem with  19 - 'S' " severity failure;
+    assert (s20=c20) report "problem with  20 - 'T' " severity failure;
+    assert (s21=c21) report "problem with  21 - 'U' " severity failure;
+    assert (s22=c22) report "problem with  22 - 'V' " severity failure;
+    assert (s23=c23) report "problem with  23 - 'W' " severity failure;
+    assert (s24=c24) report "problem with  24 - 'X' " severity failure;
+    assert (s25=c25) report "problem with  25 - 'Y' " severity failure;
+    assert (s26=c26) report "problem with  26 - 'Z' " severity failure;
+    assert (s27=c27) report "problem with  27 - '0' " severity failure;
+    assert (s28=c28) report "problem with  28 - '1' " severity failure;
+    assert (s29=c29) report "problem with  29 - '2' " severity failure;
+    assert (s30=c30) report "problem with  30 - '3' " severity failure;
+    assert (s31=c31) report "problem with  31 - '4' " severity failure;
+    assert (s32=c32) report "problem with  32 - '5' " severity failure;
+    assert (s33=c33) report "problem with  33 - '6' " severity failure;
+    assert (s34=c34) report "problem with  34 - '7' " severity failure;
+    assert (s35=c35) report "problem with  35 - '8' " severity failure;
+    assert (s36=c36) report "problem with  36 - '9' " severity failure;
+    assert (s37=c37) report "problem with  37 - '""' " severity failure;
+    assert (s38=c38) report "problem with  38 - '#' " severity failure;
+    assert (s39=c39) report "problem with  39 - '&' " severity failure;
+    assert (s40=c40) report "problem with  40 - ''' " severity failure;
+    assert (s41=c41) report "problem with  41 - '(' " severity failure;
+    assert (s42=c42) report "problem with  42 - ')' " severity failure;
+    assert (s43=c43) report "problem with  43 - '*' " severity failure;
+    assert (s44=c44) report "problem with  44 - '+' " severity failure;
+    assert (s45=c45) report "problem with  45 - ',' " severity failure;
+    assert (s46=c46) report "problem with  46 - '-' " severity failure;
+    assert (s47=c47) report "problem with  47 - '.' " severity failure;
+    assert (s48=c48) report "problem with  48 - '/' " severity failure;
+    assert (s49=c49) report "problem with  49 - ':' " severity failure;
+    assert (s50=c50) report "problem with  50 - ';' " severity failure;
+    assert (s51=c51) report "problem with  51 - '<' " severity failure;
+    assert (s52=c52) report "problem with  52 - '=' " severity failure;
+    assert (s53=c53) report "problem with  53 - '>' " severity failure;
+    assert (s54=c54) report "problem with  54 - '_' " severity failure;
+    assert (s55=c55) report "problem with  55 - '|' " severity failure;
+    assert (s56=c56) report "problem with  56 - ' ' " severity failure;
+    assert (s57=c57) report "problem with  57 - 'a' " severity failure;
+    assert (s58=c58) report "problem with  58 - 'b' " severity failure;    
+    assert (s59=c59) report "problem with  59 - 'c' " severity failure;
+    assert (s60=c60) report "problem with  60 - 'd' " severity failure;
+    assert (s61=c61) report "problem with  61 - 'e' " severity failure;
+    assert (s62=c62) report "problem with  62 - 'f' " severity failure;
+    assert (s63=c63) report "problem with  63 - 'g' " severity failure;
+    assert (s64=c64) report "problem with  64 - 'h' " severity failure;
+    assert (s65=c65) report "problem with  65 - 'i' " severity failure;
+    assert (s66=c66) report "problem with  66 - 'j' " severity failure;
+    assert (s67=c67) report "problem with  67 - 'k' " severity failure;
+    assert (s68=c68) report "problem with  68 - 'l' " severity failure;
+    assert (s69=c69) report "problem with  69 - 'm' " severity failure;
+    assert (s70=c70) report "problem with  70 - 'n' " severity failure;
+    assert (s71=c71) report "problem with  71 - 'o' " severity failure;
+    assert (s72=c72) report "problem with  72 - 'p' " severity failure;
+    assert (s73=c73) report "problem with  73 - 'q' " severity failure;
+    assert (s74=c74) report "problem with  74 - 'r' " severity failure;
+    assert (s75=c75) report "problem with  75 - 's' " severity failure;
+    assert (s76=c76) report "problem with  76 - 't' " severity failure;
+    assert (s77=c77) report "problem with  77 - 'u' " severity failure;
+    assert (s78=c78) report "problem with  78 - 'v' " severity failure;
+    assert (s79=c79) report "problem with  79 - 'w' " severity failure;
+    assert (s80=c80) report "problem with  80 - 'x' " severity failure;
+    assert (s81=c81) report "problem with  81 - 'y' " severity failure;
+    assert (s82=c82) report "problem with  82 - 'z' " severity failure;
+    assert (s83=c83) report "problem with  83 - '!' " severity failure;
+    assert (s84=c84) report "problem with  84 - '$' " severity failure;
+    assert (s85=c85) report "problem with  85 - '%' " severity failure;
+    assert (s86=c86) report "problem with  86 - '@' " severity failure;
+    assert (s87=c87) report "problem with  87 - '?' " severity failure;
+    assert (s88=c88) report "problem with  88 - '[' " severity failure;
+    assert (s89=c89) report "problem with  89 - '\' " severity failure;
+    assert (s90=c90) report "problem with  90 - ']' " severity failure;
+    assert (s91=c91) report "problem with  91 - '^' " severity failure;
+    assert (s92=c92) report "problem with  92 - '`' " severity failure;
+    assert (s93=c93) report "problem with  93 - '{' " severity failure;
+    assert (s94=c94) report "problem with  94 - '}' " severity failure;
+    assert (s95=c95) report "problem with  95 - '~' " severity failure;
+
+    assert NOT(   (s01=c01) and 
+                  (s02=c02) and 
+                  (s03=c03) and 
+                  (s04=c04) and 
+                  (s05=c05) and 
+                  (s06=c06) and 
+                  (s07=c07) and 
+                  (s08=c08) and 
+                  (s09=c09) and 
+                  (s10=c10) and 
+                  (s11=c11) and 
+                  (s12=c12) and 
+                  (s13=c13) and 
+                  (s14=c14) and 
+                  (s15=c15) and 
+                  (s16=c16) and 
+                  (s17=c17) and 
+                  (s18=c18) and 
+                  (s19=c19) and 
+                  (s20=c20) and 
+                  (s21=c21) and 
+                  (s22=c22) and 
+                  (s23=c23) and 
+                  (s24=c24) and 
+                  (s25=c25) and 
+                  (s26=c26) and 
+                  (s27=c27) and 
+                  (s28=c28) and 
+                  (s29=c29) and 
+                  (s30=c30) and 
+                  (s31=c31) and 
+                  (s32=c32) and 
+                  (s33=c33) and 
+                  (s34=c34) and 
+                  (s35=c35) and 
+                  (s36=c36) and 
+                  (s37=c37) and 
+                  (s38=c38) and 
+                  (s39=c39) and 
+                  (s40=c40) and 
+                  (s41=c41) and 
+                  (s42=c42) and 
+                  (s43=c43) and 
+                  (s44=c44) and 
+                  (s45=c45) and 
+                  (s46=c46) and 
+                  (s47=c47) and 
+                  (s48=c48) and 
+                  (s49=c49) and 
+                  (s50=c50) and 
+                  (s51=c51) and 
+                  (s52=c52) and 
+                  (s53=c53) and 
+                  (s54=c54) and 
+                  (s55=c55) and 
+                  (s56=c56) and 
+                  (s57=c57) and 
+                  (s58=c58) and 
+                  (s59=c59) and 
+                  (s60=c60) and 
+                  (s61=c61) and 
+                  (s62=c62) and 
+                  (s63=c63) and 
+                  (s64=c64) and 
+                  (s65=c65) and 
+                  (s66=c66) and 
+                  (s67=c67) and 
+                  (s68=c68) and 
+                  (s69=c69) and 
+                  (s70=c70) and 
+                  (s71=c71) and 
+                  (s72=c72) and 
+                  (s73=c73) and 
+                  (s74=c74) and 
+                  (s75=c75) and 
+                  (s76=c76) and 
+                  (s77=c77) and 
+                  (s78=c78) and 
+                  (s79=c79) and 
+                  (s80=c80) and 
+                  (s81=c81) and 
+                  (s82=c82) and 
+                  (s83=c83) and 
+                  (s84=c84) and 
+                  (s85=c85) and 
+                  (s86=c86) and 
+                  (s87=c87) and 
+                  (s88=c88) and 
+                  (s89=c89) and 
+                  (s90=c90) and 
+                  (s91=c91) and 
+                  (s92=c92) and 
+                  (s93=c93) and 
+                  (s94=c94) and 
+                  (s95=c95) ) 
+      report "***PASSED TEST: c13s06b00x00p03n01i02737"
+      severity NOTE;
+    assert (   (s01=c01) and 
+               (s02=c02) and 
+               (s03=c03) and 
+               (s04=c04) and 
+               (s05=c05) and 
+               (s06=c06) and 
+               (s07=c07) and 
+               (s08=c08) and 
+               (s09=c09) and 
+               (s10=c10) and 
+               (s11=c11) and 
+               (s12=c12) and 
+               (s13=c13) and 
+               (s14=c14) and 
+               (s15=c15) and 
+               (s16=c16) and 
+               (s17=c17) and 
+               (s18=c18) and 
+               (s19=c19) and 
+               (s20=c20) and 
+               (s21=c21) and 
+               (s22=c22) and 
+               (s23=c23) and 
+               (s24=c24) and 
+               (s25=c25) and 
+               (s26=c26) and 
+               (s27=c27) and 
+               (s28=c28) and 
+               (s29=c29) and 
+               (s30=c30) and 
+               (s31=c31) and 
+               (s32=c32) and 
+               (s33=c33) and 
+               (s34=c34) and 
+               (s35=c35) and 
+               (s36=c36) and 
+               (s37=c37) and 
+               (s38=c38) and 
+               (s39=c39) and 
+               (s40=c40) and 
+               (s41=c41) and 
+               (s42=c42) and 
+               (s43=c43) and 
+               (s44=c44) and 
+               (s45=c45) and 
+               (s46=c46) and 
+               (s47=c47) and 
+               (s48=c48) and 
+               (s49=c49) and 
+               (s50=c50) and 
+               (s51=c51) and 
+               (s52=c52) and 
+               (s53=c53) and 
+               (s54=c54) and 
+               (s55=c55) and 
+               (s56=c56) and 
+               (s57=c57) and 
+               (s58=c58) and 
+               (s59=c59) and 
+               (s60=c60) and 
+               (s61=c61) and 
+               (s62=c62) and 
+               (s63=c63) and 
+               (s64=c64) and 
+               (s65=c65) and 
+               (s66=c66) and 
+               (s67=c67) and 
+               (s68=c68) and 
+               (s69=c69) and 
+               (s70=c70) and 
+               (s71=c71) and 
+               (s72=c72) and 
+               (s73=c73) and 
+               (s74=c74) and 
+               (s75=c75) and 
+               (s76=c76) and 
+               (s77=c77) and 
+               (s78=c78) and 
+               (s79=c79) and 
+               (s80=c80) and 
+               (s81=c81) and 
+               (s82=c82) and 
+               (s83=c83) and 
+               (s84=c84) and 
+               (s85=c85) and 
+               (s86=c86) and 
+               (s87=c87) and 
+               (s88=c88) and 
+               (s89=c89) and 
+               (s90=c90) and 
+               (s91=c91) and 
+               (s92=c92) and 
+               (s93=c93) and 
+               (s94=c94) and 
+               (s95=c95) ) 
+      report "***FAILED TEST: c13s06b00x00p03n01i02737 - All string literal of length 1 are equal in value to their corresponding character values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n01i02737arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd
new file mode 100644
index 0000000..25f15b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2738.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n02i02738ent IS
+END c13s06b00x00p03n02i02738ent;
+
+ARCHITECTURE c13s06b00x00p03n02i02738arch OF c13s06b00x00p03n02i02738ent IS
+  constant   c : string := ('"',' ');
+  constant   s : string := """ ";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c=s )
+      report "***PASSED TEST: c13s06b00x00p03n02i02738"
+      severity NOTE;
+    assert ( c=s )
+      report "***FAILED TEST: c13s06b00x00p03n02i02738 - A string literal that includes two adjacent quotation characters is interpreted as one quotation character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n02i02738arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd
new file mode 100644
index 0000000..db4ea6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2739.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n01i02739ent IS
+END c13s06b00x00p03n01i02739ent;
+
+ARCHITECTURE c13s06b00x00p03n01i02739arch OF c13s06b00x00p03n01i02739ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(('A'/='a')and("ABCDE"/=string'("abcde")))
+      report "***PASSED TEST: c13s06b00x00p03n01i02739"
+      severity NOTE;
+    assert (('A'/='a')and("ABCDE"/=string'("abcde")))
+      report "***FAILED TEST: c13s06b00x00p03n01i02739 - Uppercase and lowercase letters should distinct within a string literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n01i02739arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd
new file mode 100644
index 0000000..f31945a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2740.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n02i02740ent IS
+END c13s06b00x00p03n02i02740ent;
+
+ARCHITECTURE c13s06b00x00p03n02i02740arch OF c13s06b00x00p03n02i02740ent IS
+  constant C1 : CHARACTER := '"';
+  constant S1 : STRING (1 to 1) := """";
+  constant S3 : STRING (1 to 3) := "A""C";
+  constant S5 : STRING (1 to 5) := """B""D""";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (S1(1)=C1)
+                     and (S3(2)=C1)
+                     and (S5(1)=C1)
+                     and (S5(3)=C1)
+                     and (S5(5)=C1)) 
+      report "***PASSED TEST: c13s06b00x00p03n02i02740"
+      severity NOTE;
+    assert (      (S1(1)=C1)
+                  and (S3(2)=C1)
+                  and (S5(1)=C1)
+                  and (S5(3)=C1)
+                  and (S5(5)=C1)) 
+      report "***FAILED TEST: c13s06b00x00p03n02i02740 - A string literal that includes two adjacent quotation characters is interpreted as one quotation character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n02i02740arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd
new file mode 100644
index 0000000..c14bed0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2742.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n01i02742ent IS
+END c13s06b00x00p04n01i02742ent;
+
+ARCHITECTURE c13s06b00x00p04n01i02742arch OF c13s06b00x00p04n01i02742ent IS
+  constant   mystring : string := "123456789";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( mystring'length = 9 )
+      report "***PASSED TEST: c13s06b00x00p04n01i02742"
+      severity NOTE;
+    assert ( mystring'length = 9 )
+      report "***FAILED TEST: c13s06b00x00p04n01i02742 - The length of a digit string is the number of character values in the sequence represented."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n01i02742arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd
new file mode 100644
index 0000000..dcf7a48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2743.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n01i02743ent IS
+END c13s06b00x00p04n01i02743ent;
+
+ARCHITECTURE c13s06b00x00p04n01i02743arch OF c13s06b00x00p04n01i02743ent IS
+  constant   mystring : string := "abcdefghijklmnopqrstuvwxyz";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( mystring'length = 26 )
+      report "***PASSED TEST: c13s06b00x00p04n01i02743"
+      severity NOTE;
+    assert ( mystring'length = 26 )
+      report "***FAILED TEST: c13s06b00x00p04n01i02743 - The length of a character string is the number of character values in the sequence represented."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n01i02743arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd
new file mode 100644
index 0000000..ef8269c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2744.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n02i02744ent IS
+END c13s06b00x00p04n02i02744ent;
+
+ARCHITECTURE c13s06b00x00p04n02i02744arch OF c13s06b00x00p04n02i02744ent IS
+  constant   a : string := """";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a'length=1 )
+      report "***PASSED TEST: c13s06b00x00p04n02i02744"
+      severity NOTE;
+    assert ( a'length=1 )
+      report "***FAILED TEST: c13s06b00x00p04n02i02744 - Double quote should be treated as signle character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n02i02744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd
new file mode 100644
index 0000000..719215d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2745.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p10n01i02745ent IS
+END c13s06b00x00p10n01i02745ent;
+
+ARCHITECTURE c13s06b00x00p10n01i02745arch OF c13s06b00x00p10n01i02745ent IS
+  constant   mystring : string :=    "This string has too " &
+                                     "many characters.";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT( mystring="This string has too many characters." )
+      report "***PASSED TEST: c13s06b00x00p10n01i02745"
+      severity NOTE;
+    assert ( mystring="This string has too many characters." )
+      report "***FAILED TEST: c13s06b00x00p10n01i02745 - Use of & as a continuation for a string test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p10n01i02745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd
new file mode 100644
index 0000000..30684ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2747.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p02n01i02747ent IS
+END c13s07b00x00p02n01i02747ent;
+
+ARCHITECTURE c13s07b00x00p02n01i02747arch OF c13s07b00x00p02n01i02747ent IS
+  type       x1 is array (1 to 10) of bit;
+  constant    v1 : x1 := B"00_11_00_11_00";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(v1 = B"00_11_00_11_00") 
+      report "***PASSED TEST: c13s07b00x00p02n01i02747" 
+      severity NOTE;
+    assert (v1 = B"00_11_00_11_00") 
+      report "***FAILED TEST: c13s07b00x00p02n01i02747 - A bit string literal consists of a sequence of extended digits enclosed between two quotations and is preceded by a base specifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p02n01i02747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd
new file mode 100644
index 0000000..dc21077
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2758.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n01i02758ent IS
+END c13s07b00x00p05n01i02758ent;
+
+ARCHITECTURE c13s07b00x00p05n01i02758arch OF c13s07b00x00p05n01i02758ent IS
+  constant   bcap : bit_vector := x"F_F_F";
+  constant   blow : bit_vector := x"FFF";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bcap=blow )
+      report "***PASSED TEST: c13s07b00x00p05n01i02758"
+      severity NOTE;
+    assert ( bcap=blow )
+      report "***FAILED TEST: c13s07b00x00p05n01i02758 - Underscore in bit string value should not change the value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n01i02758arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd
new file mode 100644
index 0000000..bd174a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2759.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin modified this file by adding qualification to the 
+-- bit string literals in the comparisons to make them VHDL-93 compliant.
+
+ENTITY c13s07b00x00p05n02i02759ent IS
+END c13s07b00x00p05n02i02759ent;
+
+ARCHITECTURE c13s07b00x00p05n02i02759arch OF c13s07b00x00p05n02i02759ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bit_vector'(X"123456789ABCDEF") /= B"1111_1011_1011" )
+      report "***PASSED TEST: c13s07b00x00p05n02i02759"
+      severity NOTE;
+    assert ( bit_vector'(X"123456789ABCDEF") /= B"1111_1011_1011" )
+      report "***FAILED TEST: c13s07b00x00p05n02i02759 - Extended digit test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n02i02759arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd
new file mode 100644
index 0000000..1c063f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc276.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00276ent IS
+END c03s01b03x00p07n01i00276ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00276arch OF c03s01b03x00p07n01i00276ent IS
+  type twos_complement_integer1 is range -32768 to 0;
+  type twos_complement_integer2 is range 0 to 32767;
+  type J is
+    range   twos_complement_integer1'(-32000) to
+    twos_complement_integer2'( 32000)      -- Success_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00276" 
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00276 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00276arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd
new file mode 100644
index 0000000..c595135
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2760.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n03i02760ent IS
+END c13s07b00x00p05n03i02760ent;
+
+ARCHITECTURE c13s07b00x00p05n03i02760arch OF c13s07b00x00p05n03i02760ent IS
+  constant   bcap   : bit_vector := x"FfF";
+  constant   blow   : bit_vector := x"fFf";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bcap=blow )
+      report "***PASSED TEST: c13s07b00x00p05n03i02760"
+      severity NOTE;
+    assert ( bcap=blow )
+      report "***FAILED TEST: c13s07b00x00p05n03i02760 - A letter in a bit string literal should be able to be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n03i02760arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd
new file mode 100644
index 0000000..a1efc71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n01i02761ent IS
+END c13s07b00x00p05n01i02761ent;
+
+-- Dale Martin modified this file to make the bit string literal comparisons
+-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
+
+ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
+		and ( bit_vector'(O"17_5") = O"1_75")
+		and ( bit_vector'(X"7D") = X"7_D")) 
+      report "***PASSED TEST: c13s07b00x00p05n01i02761"
+      severity NOTE;
+    assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
+	     and ( bit_vector'(O"17_5")=O"1_75")
+	     and ( bit_vector'(X"7D")=X"7_D")) 
+      report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n01i02761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd
new file mode 100644
index 0000000..f22554a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2765.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p06n02i02765ent IS
+END c13s07b00x00p06n02i02765ent;
+
+ARCHITECTURE c13s07b00x00p06n02i02765arch OF c13s07b00x00p06n02i02765ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant clear : bit_vector := O"123_67_34";   -- no_failure_here
+  BEGIN
+    assert NOT(clear = O"123_67_34") 
+      report "***PASSED TEST: c13s07b00x00p06n02i02765" 
+      severity NOTE;
+    assert (clear = O"123_67_34") 
+      report "***FAILED TEST: c13s07b00x00p06n02i02765 - For the base specifier `O', the extended digits are restricted to the digits 0 through 7."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p06n02i02765arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd
new file mode 100644
index 0000000..52da4aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2767.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin modified this file to make the bit string literal comparisons
+-- valid for VHDL 93, by qualifying them with bit_vector'()
+
+ENTITY c13s07b00x00p08n01i02767ent IS
+END c13s07b00x00p08n01i02767ent;
+
+ARCHITECTURE c13s07b00x00p08n01i02767arch OF c13s07b00x00p08n01i02767ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( ( bit_vector'(B"1111_0101_1101_1010") = bit_vector'(X"F5DA") )   and
+		(bit_vector'(B"101_110_001_111") = bit_vector'(O"5617")))
+      report "***PASSED TEST: c13s07b00x00p08n01i02767"
+      severity NOTE;
+    assert ( ( bit_vector'(B"1111_0101_1101_1010") = bit_vector'(X"F5DA"))   and
+	     (bit_vector'(B"101_110_001_111") = bit_vector'(O"5617")))
+      report "***FAILED TEST: c13s07b00x00p08n01i02767 - Bit value test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p08n01i02767arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd
new file mode 100644
index 0000000..25d378b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2768.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin updated the bit_vectors in this file with bit_vector'()
+-- qualification to make it VHDL '93 compliant. (It's still '87 compliant
+-- as well.)
+
+ENTITY c13s07b00x00p08n01i02768ent IS
+END c13s07b00x00p08n01i02768ent;
+
+ARCHITECTURE c13s07b00x00p08n01i02768arch OF c13s07b00x00p08n01i02768ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bit_vector'(O"0") = "000"   and 
+		bit_vector'(O"1") = "001"   and
+		bit_vector'(O"2") = "010"   and
+		bit_vector'(O"3") = "011"   and
+		bit_vector'(O"4") = "100"   and
+		bit_vector'(O"5") = "101"   and
+		bit_vector'(O"6") = "110"   and
+		bit_vector'(O"7") = "111"   and
+		bit_vector'(O"01")    = "000001"   and
+		bit_vector'(O"10")    = "001000"   and
+		bit_vector'(O"0_1") = "000001"   and
+		bit_vector'(X"0") = "0000"   and  
+		bit_vector'(X"1") = "0001"   and
+		bit_vector'(X"2") = "0010"   and
+		bit_vector'(X"3") = "0011"   and
+		bit_vector'(X"4") = "0100"   and
+		bit_vector'(X"5") = "0101"   and
+		bit_vector'(X"6") = "0110"   and
+		bit_vector'(X"7") = "0111"   and
+		bit_vector'(X"8") = "1000"   and
+		bit_vector'(X"9") = "1001"   and
+		bit_vector'(X"A") = "1010"   and
+                bit_vector'(X"a") = "1010"   and
+		bit_vector'(X"B") = "1011"   and
+                bit_vector'(X"b") = "1011"   and
+		bit_vector'(X"C") = "1100"   and
+                bit_vector'(X"c") = "1100"   and
+		bit_vector'(X"D") = "1101"   and
+                bit_vector'(X"d") = "1101"   and
+		bit_vector'(X"E") = "1110"   and
+                bit_vector'(X"e") = "1110"   and
+		bit_vector'(X"F") = "1111"   and
+                bit_vector'(X"f") = "1111"   and
+		bit_vector'(X"01") = "00000001"   and
+		bit_vector'(X"10") = "00010000"   and
+		bit_vector'(X"0_1") = "00000001"   and
+		bit_vector'(X"E_7") = "11100111"   and
+		bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
+      report "***PASSED TEST: c13s07b00x00p08n01i02768"
+      severity NOTE;
+    assert ( bit_vector'(O"0") = "000"   and 
+	     bit_vector'(O"1") = "001"   and
+	     bit_vector'(O"2") = "010"   and
+	     bit_vector'(O"3") = "011"   and
+	     bit_vector'(O"4") = "100"   and
+	     bit_vector'(O"5") = "101"   and
+	     bit_vector'(O"6") = "110"   and
+	     bit_vector'(O"7") = "111"   and
+	     bit_vector'(O"01") = "000001"   and
+	     bit_vector'(O"10") = "001000"   and
+	     bit_vector'(O"0_1") = "000001"   and
+	     bit_vector'(X"0") = "0000"   and  
+	     bit_vector'(X"1") = "0001"   and
+	     bit_vector'(X"2") = "0010"   and
+	     bit_vector'(X"3") = "0011"   and
+	     bit_vector'(X"4") = "0100"   and
+	     bit_vector'(X"5") = "0101"   and
+	     bit_vector'(X"6") = "0110"   and
+	     bit_vector'(X"7") = "0111"   and
+	     bit_vector'(X"8") = "1000"   and
+	     bit_vector'(X"9") = "1001"   and
+	     bit_vector'(X"A") = "1010"   and
+	     bit_vector'(X"a") = "1010"   and
+	     bit_vector'(X"B") = "1011"   and
+	     bit_vector'(X"b") = "1011"   and
+	     bit_vector'(X"C") = "1100"   and
+	     bit_vector'(X"c") = "1100"   and
+	     bit_vector'(X"D") = "1101"   and
+	     bit_vector'(X"d") = "1101"   and
+	     bit_vector'(X"E") = "1110"   and
+	     bit_vector'(X"e") = "1110"   and
+	     bit_vector'(X"F") = "1111"   and
+	     bit_vector'(X"f") = "1111"   and
+	     bit_vector'(X"01") = "00000001"   and
+	     bit_vector'(X"10") = "00010000"   and
+	     bit_vector'(X"0_1") = "00000001"   and
+	     bit_vector'(X"E_7") = "11100111"   and
+	     bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
+      report "***FAILED TEST: c13s07b00x00p08n01i02768 - Bit string literal and base specifier 'O' and 'X' value transfer test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p08n01i02768arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd
new file mode 100644
index 0000000..2cb9221
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p09n01i02769ent IS
+END c13s07b00x00p09n01i02769ent;
+
+ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
+  constant   aaa : bit_vector := B"101101";
+  constant   bbb : bit_vector := O"777";
+  constant   ccc : bit_vector := X"FFFF";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
+      report "***PASSED TEST: c13s07b00x00p09n01i02769"
+      severity NOTE;
+    assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
+      report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p09n01i02769arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd
new file mode 100644
index 0000000..ca22b65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc277.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00277ent IS
+END c03s01b03x00p07n01i00277ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00277arch OF c03s01b03x00p07n01i00277ent IS
+  type twos_complement_integer1 is range -32768 to 0;
+  constant r1: twos_complement_integer1 := -32000;
+  type twos_complement_integer2 is range 0 to 32767;
+  constant r2: twos_complement_integer2 := 32000;
+  type J is
+    range r1 to r2  -- Success_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00277"
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00277 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00277arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd
new file mode 100644
index 0000000..0365a93
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2771.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c13s08b00x00p01n01i02771pkg is
+  function--This is a valid comment.
+    F1 return BOOLEAN;
+  function F2 return BOOLEAN;
+end c13s08b00x00p01n01i02771pkg;
+
+package body c13s08b00x00p01n01i02771pkg is
+  function--This is a valid comment.
+    F1 return BOOLEAN is
+
+  begin
+    return --This comment occurs within a statement!
+      FALSE-- Comments can occur anywhere and need not be
+      --           preceded by a blank
+      ;
+  end F1;
+
+  function F2 return BOOLEAN is
+    type TYP_1 is range 1 to 10;
+    variable V1--This is all one comment--not two  --  or more!
+              : TYP_1 := 2;
+  begin
+    assert TRUE
+      report "--This is not a comment--";
+    return FALSE;
+  end F2;
+end c13s08b00x00p01n01i02771pkg;
+
+ENTITY c13s08b00x00p01n01i02771ent IS
+  port (PT:BOOLEAN) ;
+  --This is a NULL entity
+END c13s08b00x00p01n01i02771ent;
+
+ARCHITECTURE c13s08b00x00p01n01i02771arch OF c13s08b00x00p01n01i02771ent IS
+
+--
+--(that was a blank comment)
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s08b00x00p01n01i02771" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING
+--that wasn't so quick!
+    ;--semicolon
+
+
+END c13s08b00x00p01n01i02771arch; --architecture A ("A comment can appear on any line of a VHDL description.")
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd
new file mode 100644
index 0000000..9d60c03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00278ent IS
+END c03s01b03x00p07n01i00278ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS
+  type twos_complement_integer is range -32768 to 32767;
+  type J is
+    range twos_complement_integer'low to twos_complement_integer'high
+    units         -- Success_here
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00278" 
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00278arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd
new file mode 100644
index 0000000..b4d939a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc279.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00279ent IS
+END c03s01b03x00p07n01i00279ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00279arch OF c03s01b03x00p07n01i00279ent IS
+  type T1 is range 1 to 10;
+  type T2 is range 100 to 1000;
+  constant V1: T1 := 5;
+  constant V2: T2 := 500;
+  type T is
+    range V1 to V2  -- No_failure_here
+    units
+      I ;  
+      J = 2 I;
+      K = 2 J;
+      L = 10 K;
+      M =    L;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : T := 310 I;
+  BEGIN
+    k := 5 I;
+    assert NOT(k=5 I) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00279" 
+      severity NOTE;
+    assert (k=5 I) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00279 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00279arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd
new file mode 100644
index 0000000..9f99881
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p08n02i00281ent IS
+END c03s01b03x00p08n02i00281ent;
+
+ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
+  type UPLE is range 1 to 8
+    units
+      single;
+      duple = 2 single;
+      triple = 3 single;
+      quadruple = 2 duple;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : UPLE := 1 duple;
+  BEGIN
+    assert NOT(k = 2 single) 
+      report "***PASSED TEST: c03s01b03x00p08n02i00281" 
+      severity NOTE;
+    assert (k = 2 single) 
+      report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p08n02i00281arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd
new file mode 100644
index 0000000..9e204be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc284.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00284ent IS
+END c03s01b03x00p12n01i00284ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00284arch OF c03s01b03x00p12n01i00284ent IS
+  type distance is range 0 to 2e9
+    units
+      -- base unit
+      mil;
+      inch = 1000 mil;
+      ft   = 12   inch;
+      yd   = 3    ft;
+      fm   = 6    ft;
+      mi   = 5280 ft;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : distance := 12 ft;
+  BEGIN
+    assert NOT((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
+      report "***PASSED TEST: c03s01b03x00p12n01i00284"
+      severity NOTE;
+    assert ((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
+      report "***FAILED TEST: c03s01b03x00p12n01i00284 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00284arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd
new file mode 100644
index 0000000..85b7e14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00285ent IS
+END c03s01b03x00p12n01i00285ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
+  type time is range 0 to 1E8 units
+                                fs;
+                                ps = 10 fs;
+                              end units;
+BEGIN
+  TESTING: PROCESS
+    variable i : integer; 
+  BEGIN
+    i:=time'pos(ps);
+    assert NOT(i=10)
+      report "***PASSED TEST: c03s01b03x00p12n01i00285"
+      severity NOTE;
+    assert (i=10)
+      report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00285arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd
new file mode 100644
index 0000000..36a0a8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2853.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p02n01i02853ent IS
+END c13s10b00x00p02n01i02853ent;
+
+ARCHITECTURE c13s10b00x00p02n01i02853arch OF c13s10b00x00p02n01i02853ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype   BYTE is BIT_VECTOR (0 to 7);
+    variable   b1 : BYTE;
+    variable    b2 : BYTE;
+  BEGIN
+    b1 := BYTE'(0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 => '1');
+    b2 := BYTE'(0 ! 1 ! 2 ! 3 ! 4 ! 5 ! 6 ! 7 => '1');
+    assert NOT( b1=b2 )
+      report "***PASSED TEST: c13s10b00x00p02n01i02853"
+      severity NOTE;
+    assert ( b1=b2 )
+      report "***FAILED TEST: c13s10b00x00p02n01i02853 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p02n01i02853arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd
new file mode 100644
index 0000000..f0786c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2854.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02854ent IS
+END c13s10b00x00p03n01i02854ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02854arch OF c13s10b00x00p03n01i02854ent IS
+  constant   one    : integer := 16:E:E1;
+  constant   two    : integer := 16#E#E1;
+  constant   three   : integer := 16#FF#;
+  constant   four   : integer := 16:FF:;
+  constant   five   : integer := 2#1110_0000#;
+  constant   six   : integer := 2:1110_0000:;
+  constant   seven   : integer := 8#776#;
+  constant   eight   : integer := 8:776:;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    one=two    and 
+                   three=four    and 
+                   five=six    and 
+                   seven=eight    )
+      report "***PASSED TEST: c13s10b00x00p03n01i02854"
+      severity NOTE;
+    assert (    one=two    and 
+                three=four    and 
+                five=six    and 
+                seven=eight    )
+      report "***FAILED TEST: c13s10b00x00p03n01i02854 - Colon(:) can replace the sharp character(#) in based literal definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02854arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd
new file mode 100644
index 0000000..362d81d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc286.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00286ent IS
+END c03s01b03x00p12n01i00286ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00286arch OF c03s01b03x00p12n01i00286ent IS
+  type time is range 0 to 1E8 units
+                                fs;
+                                ps = 10 fs;
+                              end units;
+BEGIN
+  TESTING: PROCESS
+    variable i : integer; 
+  BEGIN
+    i:=time'pos(3 ps);
+    assert NOT(i=30)
+      report "***PASSED TEST: c03s01b03x00p12n01i00286"
+      severity NOTE;
+    assert (i=30)
+      report "***FAILED TEST: c03s01b03x00p12n01i00286 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00286arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd
new file mode 100644
index 0000000..9347d7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n02i02860ent IS
+END c13s10b00x00p04n02i02860ent;
+
+ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
+  constant   a : string := %%%%;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a'length=1 and a="%" )
+      report "***PASSED TEST: c13s10b00x00p04n02i02860"
+      severity NOTE;
+    assert ( a'length=1 and a="%" )
+      report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n02i02860arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd
new file mode 100644
index 0000000..b7de3cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2861.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02861ent IS
+END c13s10b00x00p03n01i02861ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02861arch OF c13s10b00x00p03n01i02861ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real;
+  BEGIN
+    total_time := 5:1234.4321:E-10;      -- no_failure_here
+    assert NOT(total_time = 5:1234.4321:E-10) 
+      report "***PASSED TEST: c13s10b00x00p03n01i02861"
+      severity NOTE;
+    assert (total_time = 5:1234.4321:E-10) 
+      report "***FAILED TEST: c13s10b00x00p03n01i02861 - Sharp character test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02861arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd
new file mode 100644
index 0000000..bd3ea8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2862.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n03i02862ent IS
+END c13s10b00x00p04n03i02862ent;
+
+ARCHITECTURE c13s10b00x00p04n03i02862arch OF c13s10b00x00p04n03i02862ent IS
+  constant   one   : bit_vector := X"FF";
+  constant   two   : bit_vector := X%FF%;
+  constant   three   : bit_vector := o"77";
+  constant   four   : bit_vector := o%77%;
+  constant   five   : bit_vector := b"1111_1111";
+  constant   six   : bit_vector := b%1111_1111%;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    one=two    and 
+                   three=four    and 
+                   five=six    )
+      report "***PASSED TEST: c13s10b00x00p04n03i02862"
+      severity NOTE;
+    assert (    one=two    and 
+                three=four    and 
+                five=six    )
+      report "***FAILED TEST: c13s10b00x00p04n03i02862 - Percent character (%) can replace the quotation character ("") in bit string literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n03i02862arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd
new file mode 100644
index 0000000..9d70b82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2863.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02863ent IS
+END c02s01b00x00p03n01i02863ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02863arch OF c02s01b00x00p03n01i02863ent IS
+
+BEGIN
+  TESTING: PROCESS
+    procedure mytest (fpl:integer);
+    procedure mytest (fpl:integer) is
+    begin
+      assert NOT( fpl = 5 )
+        report "***PASSED TEST: c02s01b00x00p03n01i02863"
+        severity NOTE;
+      assert ( fpl = 5 )
+        report "***FAILED TEST: c02s01b00x00p03n01i02863 - Subprogram syntax test failed."
+        severity ERROR;
+    end mytest;
+  BEGIN
+    mytest(5);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02863arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd
new file mode 100644
index 0000000..8760698
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2864.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02864ent IS
+END c02s01b00x00p03n01i02864ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02864arch OF c02s01b00x00p03n01i02864ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function greater (i,l:time) return boolean;
+    function greater (i,l:time) return boolean is
+    begin
+      if i > l then
+        return TRUE;
+      else
+        return FALSE;
+      end if;
+    end greater;
+    variable result : boolean;   
+  BEGIN
+    result := greater (10 ns, 5 ns);
+    assert NOT( result = true )
+      report "***PASSED TEST: c02s01b00x00p03n01i02864"
+      severity NOTE;
+    assert ( result = true )
+      report "***FAILED TEST: c02s01b00x00p03n01i02864 - Funcation call syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02864arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd
new file mode 100644
index 0000000..e203edd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2865.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02865ent IS
+  procedure mytime;
+  procedure mytime is
+  begin
+    assert NOT( true )
+      report "***PASSED TEST: c02s01b00x00p03n01i02865"
+      severity NOTE;
+    assert ( true )
+      report "***FAILED TEST: c02s01b00x00p03n01i02865 - Subprogram declaration syntax test failed."
+      severity ERROR;
+  end mytime;
+END c02s01b00x00p03n01i02865ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02865arch OF c02s01b00x00p03n01i02865ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    mytime;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02865arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd
new file mode 100644
index 0000000..7d0c7ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2866.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02866ent IS
+  function mytime return boolean is
+  begin
+    return TRUE;
+  end mytime;
+END c02s01b00x00p03n01i02866ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02866arch OF c02s01b00x00p03n01i02866ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+  BEGIN
+    k:=mytime;
+    assert NOT( k )
+      report "***PASSED TEST: c02s01b00x00p03n01i02866"
+      severity NOTE;
+    assert ( k )
+      report "***FAILED TEST: c02s01b00x00p03n01i02866 - Wrong value returned from function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02866arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd
new file mode 100644
index 0000000..7b3af37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2868.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02868ent IS
+END c02s01b00x00p03n01i02868ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02868arch OF c02s01b00x00p03n01i02868ent IS
+  procedure subprog is
+  begin
+    assert FALSE
+      report "***PASSED TEST: c02s01b00x00p03n01i02868" 
+      severity NOTE;
+  end subprog;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprog;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02868arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd
new file mode 100644
index 0000000..71a0cf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc287.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n03i00287ent IS
+END c03s01b03x00p12n03i00287ent;
+
+ARCHITECTURE c03s01b03x00p12n03i00287arch OF c03s01b03x00p12n03i00287ent IS
+  type UPLE is range 1 to 8
+    units
+      single;
+      double    = 2 single;
+      quadruple    = 2 double;
+      octuple    = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((UPLE'POS(3 double) = 3 * UPLE'POS(double)) and (UPLE'POS(0.5 octuple) = 4))
+      report "***PASSED TEST: c03s01b03x00p12n03i00287"
+      severity NOTE;
+    assert ((UPLE'POS(3 double) = 3 * UPLE'POS(double)) and (UPLE'POS(0.5 octuple) = 4))
+      report "***FAILED TEST: c03s01b03x00p12n03i00287 - The position number of a physical literal with an abstract literal part is rounded up to the nearest integer of the product of the abstract literal part of physical literal and the position number of its unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n03i00287arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd
new file mode 100644
index 0000000..65baa43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2870.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02870ent IS
+END c02s01b00x00p03n01i02870ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02870arch OF c02s01b00x00p03n01i02870ent IS
+  
+  function func return integer is
+  begin
+    return 100 ;
+  end func ;
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(func = 100)
+      report "***PASSED TEST: c02s01b00x00p03n01i02870" 
+      severity NOTE;
+    assert (func = 100)
+      report "***FAILED TEST: c02s01b00x00p03n01i02870 - Function specification without optional formal parameter failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02870arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd
new file mode 100644
index 0000000..e916f79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2874.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n05i02874ent IS
+  function "+" (I1:Bit) return bit;  --- No_Failure_here
+END c02s01b00x00p06n05i02874ent;
+
+ARCHITECTURE c02s01b00x00p06n05i02874arch OF c02s01b00x00p06n05i02874ent IS
+  function "+" (I1:Bit) return bit is
+  begin
+    if (I1 = '1') then
+      return '1';
+    else
+      return '0';
+    end if;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit := '0';
+  BEGIN
+    k := "+"('1');
+    assert NOT(k='1')
+      report "***PASSED TEST: c02s01b00x00p06n05i02874" 
+      severity NOTE;
+    assert (k='1')
+      report "***FAILED TEST: c02s01b00x00p06n05i02874 - Operator symbol as the function designator test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n05i02874arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd
new file mode 100644
index 0000000..f08be5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2876.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n04i02876ent IS
+END c02s01b00x00p06n04i02876ent;
+
+ARCHITECTURE c02s01b00x00p06n04i02876arch OF c02s01b00x00p06n04i02876ent IS
+  procedure PX (I1 : Bit) is
+  begin
+    if (I1 = '1') then
+      assert FALSE
+        report "***PASSED TEST: c02s01b00x00p06n04i02876" 
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c02s01b00x00p06n04i02876 - A procedure designator must always be an identifier."
+        severity ERROR;
+    end if;
+  end PX;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX('1');
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n04i02876arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd
new file mode 100644
index 0000000..f4614a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2879.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02879ent IS
+  function func1(constant flag:in integer) return integer;
+  
+  function func1(constant flag:in integer) return integer is
+    variable v1 : integer;
+  begin
+    if (flag = 0) then
+      return 0;
+    else
+      return ((func1(flag-1)) + 1);
+    end if;
+  end func1;
+END c02s01b00x00p07n01i02879ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02879arch OF c02s01b00x00p07n01i02879ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    x:= func1(3);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02879"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02879 - Functions resursion call test incorrect."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02879arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd
new file mode 100644
index 0000000..6a132ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc288.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p13n01i00288ent IS
+END c03s01b03x00p13n01i00288ent;
+
+ARCHITECTURE c03s01b03x00p13n01i00288arch OF c03s01b03x00p13n01i00288ent IS
+  type distance is range 0 to 2e9
+    units
+      -- base unit
+      mil;
+      inch = 1000 mil;
+      ft = 12 inch;
+      yd = 3 ft;
+      fm = 6 ft;
+      mi = 5280 ft;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((880 * (yd + yd)) = 5280 * ft)
+      report "***PASSED TEST: c03s01b03x00p13n01i00288"
+      severity NOTE;
+    assert ((880 * (yd + yd)) = 5280 * ft)
+      report "***FAILED TEST: c03s01b03x00p13n01i00288 - The same arithmetic operations are defined for all physical types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p13n01i00288arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd
new file mode 100644
index 0000000..756ac7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2880.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02880ent IS
+  procedure proc1(constant flag:in integer; variable ret:inout integer);
+  procedure proc1(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc1((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc1;
+END c02s01b00x00p07n01i02880ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02880arch OF c02s01b00x00p07n01i02880ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    proc1(3,x);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02880"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02880 - Procedure resursion call test incorrect."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02880arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd
new file mode 100644
index 0000000..67eb1fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2881.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02881ent IS
+  function func2(constant flag:in integer) return integer;
+  function func3(constant flag:in integer) return integer;
+  
+  function func2(constant flag:in integer) return integer is
+  begin
+    if (flag = 0) then
+      return 0;
+    else  
+      return ((func3(flag-1)) + 1);
+    end if;
+  end func2;
+  
+  function func3(constant flag:in integer) return integer is
+  begin
+    if (flag = 0) then
+      return 0;
+    else  
+      return ((func2(flag-1)) + 1);
+    end if;
+  end func3;
+END c02s01b00x00p07n01i02881ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02881arch OF c02s01b00x00p07n01i02881ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    x:= func2(3);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02881"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02881 - Functions resursion call test incorrect (A-B-A type)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02881arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd
new file mode 100644
index 0000000..4fe3414
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2882.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02882ent IS
+  procedure proc2(constant flag:in integer; variable ret:inout integer);
+  procedure proc3(constant flag:in integer; variable ret:inout integer);
+
+  procedure proc2(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc3((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc2;
+
+  procedure proc3(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc2((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc3;
+END c02s01b00x00p07n01i02882ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02882arch OF c02s01b00x00p07n01i02882ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    proc2(3,x);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02882"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02882 - Procedures resursion call test incorrect (A-B-A type)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02882arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd
new file mode 100644
index 0000000..7dfc368
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2883.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p03n01i02883ent IS
+  procedure howe (k:in real; v:out real) is
+  begin
+    v := k;
+  end howe;
+END c02s01b01x00p03n01i02883ent;
+
+ARCHITECTURE c02s01b01x00p03n01i02883arch OF c02s01b01x00p03n01i02883ent IS
+  constant k:real:=3.1415;
+BEGIN
+  TESTING: PROCESS
+    variable v:real;
+  BEGIN
+    howe(k,v);
+    wait for 5 ns;
+    assert NOT( k=v )
+      report "***PASSED TEST: c02s01b01x00p03n01i02883"
+      severity NOTE;
+    assert ( k=v )
+      report "***FAILED TEST: c02s01b01x00p03n01i02883 - Wrong value returned from procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p03n01i02883arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd
new file mode 100644
index 0000000..4ee1cce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc29.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p12n01i00029ent IS
+END c04s02b00x00p12n01i00029ent;
+
+ARCHITECTURE c04s02b00x00p12n01i00029arch OF c04s02b00x00p12n01i00029ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype indication of the type INTEGER.
+    subtype SUBINT is INTEGER;
+
+    -- Declare variables of both types.
+    variable INTV : INTEGER;
+    variable SUBV : SUBINT;
+  BEGIN
+    -- Verify that we can perform "same type" operations on the
+    -- two variables.
+    SUBV := 1;
+    INTV := SUBV;
+    SUBV := INTV;
+
+    assert NOT( SUBV = INTV )
+      report "***PASSED TEST: c04s02b00x00p12n01i00029"
+      severity NOTE;
+    assert ( SUBV = INTV )
+      report "***FAILED TEST: c04s02b00x00p12n01i00029 - A subtype declaration does not define a new type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p12n01i00029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd
new file mode 100644
index 0000000..b4d35ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc290.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p13n01i00290ent IS
+  type mytime is range 1 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p13n01i00290ent;
+
+ARCHITECTURE c03s01b03x00p13n01i00290arch OF c03s01b03x00p13n01i00290ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable t,a   :mytime;
+    variable b   :integer;
+  BEGIN
+    a:=30 fs;
+    b := 10;
+    t:= a/b;
+    assert NOT(t = 3 fs) 
+      report "***PASSED TEST: c03s01b03x00p13n01i00290" 
+      severity NOTE;
+    assert (t = 3 fs) 
+      report "***FAILED TEST: c03s01b03x00p13n01i00290 - Physical type value arithmetic operation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p13n01i00290arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd
new file mode 100644
index 0000000..cf6ac1f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2900.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02900ent IS
+END c02s01b01x01p02n02i02900ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02900arch OF c02s01b01x01p02n02i02900ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  function func1(constant cc1:in integer; signal ss1:in t1)
+    return real is
+  begin
+    assert (cc1=65)
+      report "Constants of mode in for functions are not copied properly"         
+      severity failure;
+    assert (ss1=three)
+      report "Signals of mode in for functions are not copied properly"
+      severity failure;
+    return 4.1;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=three;
+    wait for 5 ns;
+    v1:=func1(c1,s1);
+    assert NOT( v1 = 4.1 )
+      report "***PASSED TEST: c02s01b01x01p02n02i02900"
+      severity NOTE;
+    assert ( v1 = 4.1 )
+      report "***FAILED TEST: c02s01b01x01p02n02i02900 - Values of actual parameters of mode in are not copied into their associated formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02900arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd
new file mode 100644
index 0000000..6dd2b0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2901.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n03i02901ent IS
+END c02s01b01x01p02n03i02901ent;
+
+ARCHITECTURE c02s01b01x01p02n03i02901arch OF c02s01b01x01p02n03i02901ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+  procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
+  begin
+    ss1<=two;
+    vv1:=43.1;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=three;
+    v1:=65.3;
+    wait for 5 ns;
+    proc1(v1,s1);
+    wait for 5 ns;
+    assert (v1=43.1)
+      report "Variables of mode inout for procedures are not copied properly"
+      severity failure;
+    assert (s1=two)
+      report "Signals of mode inout for procedures are not copied properly"
+      severity failure;
+    assert NOT( v1=43.1 and s1=two )
+      report "***PASSED TEST: c02s01b01x01p02n03i02901"
+      severity NOTE;
+    assert ( v1=43.1 and s1=two )
+      report "***FAILED TEST: c02s01b01x01p02n03i02901 - Mode inout for procedures are not copied properly"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n03i02901arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd
new file mode 100644
index 0000000..9e5088e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2902.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02902ent IS
+END c02s01b01x01p02n02i02902ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02902arch OF c02s01b01x01p02n02i02902ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  procedure proc1(constant cc1:in integer;variable vv1:in real;signal ss1:in t1) is
+  begin
+    assert (cc1=65)
+      report "Constants of mode in for procedures are not copied properly"
+      severity failure;
+    assert (vv1=43.1)
+      report "Variables of mode in for procedures are not copied properly"
+      severity failure;
+    assert (ss1=two)
+      report "Signals of mode in for procedures are not copied properly"
+      severity failure;
+    assert NOT( cc1=65 and vv1=43.1 and ss1=two )
+      report "***PASSED TEST: c02s01b01x01p02n02i02902"
+      severity NOTE;
+    assert ( cc1=65 and vv1=43.1 and ss1=two )
+      report "***FAILED TEST: c02s01b01x01p02n02i02902 - Values of actual parameters of mode in are not copied into their associated formal parameter."
+      severity ERROR;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=two;
+    v1:=43.1;
+    wait for 5 ns;
+    proc1(c1,v1,s1);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02902arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd
new file mode 100644
index 0000000..2d756ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02903ent IS
+END c02s01b01x01p02n02i02903ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
+  begin
+    assert (vv1=43.1)
+      report "Variables of mode inout for procedures are not copied properly"
+      severity failure;
+    assert (ss1=two)
+      report "Signals of mode inout for procedures are not copied properly"
+      severity failure;
+    assert NOT( vv1=43.1 and ss1=two )
+      report "***PASSED TEST: c02s01b01x01p02n02i02903"
+      severity NOTE;
+    assert ( vv1=43.1 and ss1=two )
+      report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
+      severity ERROR;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=two;
+    v1:=43.1;
+    wait for 5 ns;
+    proc1(v1,s1);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02903arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd
new file mode 100644
index 0000000..6808c61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2904.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n03i02904ent IS
+END c02s01b01x01p02n03i02904ent;
+
+ARCHITECTURE c02s01b01x01p02n03i02904arch OF c02s01b01x01p02n03i02904ent IS
+  procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer);
+  procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer) is
+  begin
+    I2 := I1;
+    I3 := 10;
+  end PX;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Bit;
+    variable V2 : Integer;
+  BEGIN
+    PX('1',V1,V2);
+    wait for 5 ns;
+    assert NOT( V1='1' and V2=10 )
+      report "***PASSED TEST: c02s01b01x01p02n03i02904"
+      severity NOTE;
+    assert ( V1='1' and V2=10 )
+      report "***FAILED TEST: c02s01b01x01p02n03i02904 - Mode out for procedures are not copied properly"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n03i02904arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd
new file mode 100644
index 0000000..2d3dfdb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p14n01i00291ent IS
+END c03s01b03x00p14n01i00291ent;
+
+ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
+  type T is
+    range -2147483647 to 2147483647   -- No_failure_here
+    units
+      I ;  
+      J = 2 I;
+      K = 2 J;
+      L = 10 K;
+      M = 1000 L;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable kk : T := 1 L;
+  BEGIN
+    assert NOT( kk = 20 J )
+      report "***PASSED TEST: c03s01b03x00p14n01i00291"
+      severity NOTE;
+    assert ( kk = 20 J )
+      report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p14n01i00291arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd
new file mode 100644
index 0000000..38a7cdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2917.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p05n01i02917ent IS
+END c02s01b01x02p05n01i02917ent;
+
+ARCHITECTURE c02s01b01x02p05n01i02917arch OF c02s01b01x02p05n01i02917ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  signal    s2 : integer;
+
+  procedure proc1(signal ss1:inout t1; signal ss2:out integer) is
+  begin
+    ss1<=two after 5 ns;
+    ss2<=2 after 5 ns;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s1<=three;
+    s2<=3;
+    wait for 5 ns;
+    assert (s1=three)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (s2=3)
+      report "Error in initial conditions detected"
+      severity failure;
+    proc1(s1,s2);
+    wait for 10 ns;
+    assert (s1=two)
+      report "Error detected in signal assignment for S1"
+      severity failure;
+    assert (s2=2)
+      report "Error detected in signal assignment for S2"
+      severity failure;
+    assert NOT( s1=two and s2=2 )
+      report "***PASSED TEST: c02s01b01x02p05n01i02917"
+      severity NOTE;
+    assert ( s1=two and s2=2 )
+      report "***FAILED TEST: c02s01b01x02p05n01i02917 - Error detected in signal assignemnts."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p05n01i02917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd
new file mode 100644
index 0000000..c9cbd30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2918.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p06n01i02918ent IS
+END c02s01b01x02p06n01i02918ent;
+
+ARCHITECTURE c02s01b01x02p06n01i02918arch OF c02s01b01x02p06n01i02918ent IS
+
+  function bit_func ( x : bit) return bit is
+  begin
+    return x;
+  end bit_func ;
+  function bit_vector_func ( x : bit_vector) return bit_vector is
+  begin
+    return x;
+  end bit_vector_func ;
+  function boolean_func ( x : boolean) return boolean is
+  begin
+    return x;
+  end boolean_func ;
+  function character_func ( x : character) return character is   
+  begin
+    return x;
+  end character_func ;
+  function integer_func ( x : integer) return integer is
+  begin
+    return x;
+  end integer_func ;
+  function real_func ( x : real) return real is
+  begin
+    return x;
+  end real_func ;
+  function string_func ( x : string) return string is  
+  begin
+    return x;
+  end string_func ;
+  function time_func ( x : time) return time is
+  begin
+    return x;
+  end time_func ;
+
+BEGIN
+  TESTING: PROCESS
+    variable v : bit_vector (1 to 3) ;
+  BEGIN
+    v(1) := '0';
+    v(2) := '1';
+    v(3) := '0';
+    assert NOT(   (bit_func('1') = '1')       and
+                  (bit_vector_func(v) = v)    and
+                  (boolean_func(true) = true)    and
+                  (character_func('X') = 'X')    and
+                  (integer_func(6) = 6)       and
+                  (real_func(3.14159) = 3.14159)    and
+                  (string_func("qwertyuiop") = "qwertyuiop") and
+                  (time_func(2 ns) = 2 ns)) 
+      report "***PASSED TEST: c02s01b01x02p06n01i02918" 
+      severity NOTE;
+    assert (   (bit_func('1') = '1')       and
+               (bit_vector_func(v) = v)    and
+               (boolean_func(true) = true)    and
+               (character_func('X') = 'X')    and
+               (integer_func(6) = 6)       and
+               (real_func(3.14159) = 3.14159)    and
+               (string_func("qwertyuiop") = "qwertyuiop") and
+               (time_func(2 ns) = 2 ns)) 
+      report "***FAILED TEST: c02s01b01x02p06n01i02918 - Static signal as actual test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p06n01i02918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd
new file mode 100644
index 0000000..b105417
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc292.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p26n01i00292ent IS
+  type mytime is range 0 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p26n01i00292ent;
+
+ARCHITECTURE c03s01b03x00p26n01i00292arch OF c03s01b03x00p26n01i00292ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i:integer;
+    variable t:mytime;
+  BEGIN
+    t:= 20 fs;
+    i:= mytime'POS(t);
+    assert NOT( i=20 )
+      report "***PASSED TEST: c03s01b03x00p26n01i00292"
+      severity NOTE;
+    assert ( i=20 )
+      report "***FAILED TEST: c03s01b03x00p26n01i00292 - POS attribute can be used to convert between abstract values and physical values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p26n01i00292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd
new file mode 100644
index 0000000..5e1ab01
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc293.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p26n01i00293ent IS
+  type mytime is range 0 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p26n01i00293ent;
+
+ARCHITECTURE c03s01b03x00p26n01i00293arch OF c03s01b03x00p26n01i00293ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i:integer;
+    variable t:mytime;
+  BEGIN
+    i:= 20;
+    t:= mytime'VAL(i);
+    assert NOT(t=20 fs) 
+      report "***PASSED TEST: c03s01b03x00p26n01i00293"
+      severity NOTE;
+    assert (t=20 fs) 
+      report "***FAILED TEST: c03s01b03x00p26n01i00293 - POS attribute can be used to convert between abstract values and physical values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p26n01i00293arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd
new file mode 100644
index 0000000..25bbb3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2932.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n01i02932ent IS
+END c02s02b00x00p07n01i02932ent;
+
+ARCHITECTURE c02s02b00x00p07n01i02932arch OF c02s02b00x00p07n01i02932ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable global_int : integer := 0;
+    
+    procedure Recursive_subr ( x: integer ) is
+    begin
+      global_int := global_int + 1;
+      if x > 1 then
+        Recursive_subr (x-1);
+      end if;
+    end Recursive_subr ;
+  BEGIN
+    Recursive_subr (10);
+    wait for 5 ns;
+    assert NOT( global_int = 10 )
+      report "***PASSED TEST: c02s02b00x00p07n01i02932"
+      severity NOTE;
+    assert ( global_int = 10 )
+      report "***FAILED TEST: c02s02b00x00p07n01i02932 - Recursive procedure test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n01i02932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd
new file mode 100644
index 0000000..82668e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc294.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n02i00294ent IS
+END c03s01b03x01p01n02i00294ent;
+
+ARCHITECTURE c03s01b03x01p01n02i00294arch OF c03s01b03x01p01n02i00294ent IS
+  signal T1 : TIME := -2147483647 ns;
+  signal T2 : TIME := +2147483467 ns;   -- no_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(T1=-2147483647 ns and T2=+2147483467 ns)
+      report "***PASSED TEST:c03s01b03x01p01n02i00294"
+      severity NOTE;
+    assert (T1=-2147483647 ns and T2=+2147483467 ns)
+      report "***FAILED TEST: c03s01b03x01p01n02i00294 - The range of TIME is guaranteed to include the range -2147483647 to +2147483467."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n02i00294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd
new file mode 100644
index 0000000..90cb3bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n05i02945pkg is
+  function F1 (i : integer) return Boolean;
+end c02s02b00x00p07n05i02945pkg;
+
+package body c02s02b00x00p07n05i02945pkg is
+  function F1 (i : integer) return Boolean is
+  begin
+    return TRUE;
+  end F1;
+end c02s02b00x00p07n05i02945pkg;
+
+
+use work.c02s02b00x00p07n05i02945pkg.all;
+ENTITY c02s02b00x00p07n05i02945ent IS
+END c02s02b00x00p07n05i02945ent;
+
+ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+  BEGIN
+    k := F1(2);
+    assert NOT( k=TRUE )
+      report "***PASSED TEST: c02s02b00x00p07n05i02945"
+      severity NOTE;
+    assert ( k=TRUE )
+      report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n05i02945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd
new file mode 100644
index 0000000..5e0fb61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2948.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p08n02i02948ent IS
+END c02s02b00x00p08n02i02948ent;
+
+ARCHITECTURE c02s02b00x00p08n02i02948arch OF c02s02b00x00p08n02i02948ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    I2   <= '1';
+    I3   <=  6;
+  end PX;    -- No_failure_here
+
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2);
+    wait for 5 ns;
+    assert NOT(S3='1' and S2=6)
+      report "***PASSED TEST: c02s02b00x00p08n02i02948"
+      severity NOTE;
+    assert (S3='1' and S2=6)
+      report "***FAILED TEST: c02s02b00x00p08n02i02948 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p08n02i02948arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd
new file mode 100644
index 0000000..55a4315
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2949.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02949ent IS
+END c02s02b00x00p12n01i02949ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02949arch OF c02s02b00x00p12n01i02949ent IS
+
+  function CreateN(constant size : in INTEGER) return STRING is
+    variable result : STRING(1 to size);
+    variable ch : CHARACTER;
+  begin
+    ch := 'A';
+    for i in result'RANGE loop
+      result(i) := ch;
+      ch := CHARACTER'SUCC(ch);
+      if ch > 'Z' then
+        ch := 'Z';
+      end if;
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert "A" = CreateN(1) report CreateN(1);
+    assert "AB" = CreateN(2) report CreateN(2);
+    assert "ABCDEFGHIJ" = CreateN(10) report CreateN(10);
+
+    assert NOT(    "A" = CreateN(1)   and
+                   "AB" = CreateN(2)   and
+                   "ABCDEFGHIJ" = CreateN(10))
+      report "***PASSED TEST: c02s02b00x00p12n01i02949"
+      severity NOTE;
+    assert (    "A" = CreateN(1)   and
+                "AB" = CreateN(2)   and
+                "ABCDEFGHIJ" = CreateN(10))
+      report "***FAILED TEST: c02s02b00x00p12n01i02949 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02949arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd
new file mode 100644
index 0000000..fb83cc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc295.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00295ent IS
+END c03s01b03x01p01n03i00295ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00295arch OF c03s01b03x01p01n03i00295ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (time'pos(fs) = 1)    and
+                (ps  = 1000 fs)    and
+                (ns  = 1000 ps) )
+      report "***PASSED TEST: c03s01b03x01p01n03i00295"
+      severity NOTE;
+    assert ( (time'pos(fs) = 1) and
+             (ps  = 1000 fs) and
+             (ns  = 1000 ps) )
+      report "***FAILED TEST: c03s01b03x01p01n03i00295 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00295arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd
new file mode 100644
index 0000000..f6bd51c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2950.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02950ent IS
+END c02s02b00x00p12n01i02950ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02950arch OF c02s02b00x00p12n01i02950ent IS
+
+  function Concat(
+    constant in1 : in STRING;
+    constant in2 : in STRING
+    ) return STRING is
+    variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
+  begin
+    for i in in1'RANGE loop
+      result(result'left + i - in1'left) := in1(i);
+    end loop;
+    for i in in2'RANGE loop
+      result(result'left + in1'length + i - in2'left) := in2(i);
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+    constant in1 : STRING := "PASS IF more:";
+    constant in2 : STRING := " HEY, THIS IS MORE!";
+  BEGIN
+
+    assert NOT( Concat(in1, in2) = "PASS IF more: HEY, THIS IS MORE!" )
+      report "***PASSED TEST: c02s02b00x00p12n01i02950"
+      severity NOTE;
+    assert ( Concat(in1, in2) = "PASS IF more: HEY, THIS IS MORE!" )
+      report "***FAILED TEST: c02s02b00x00p12n01i02950 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02950arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd
new file mode 100644
index 0000000..806feaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2951.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02951ent IS
+END c02s02b00x00p12n01i02951ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02951arch OF c02s02b00x00p12n01i02951ent IS
+
+  function Concat(
+    constant in1 : in STRING;
+    constant in2 : in STRING
+    ) return STRING is
+    variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
+  begin
+    for i in in1'RANGE loop
+      result(result'left + i - in1'left) := in1(i);
+    end loop;
+    for i in in2'RANGE loop
+      result(result'left + in1'length + i - in2'left) := in2(i);
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
+                "Let's try multiple levels!" )
+      report "***PASSED TEST: c02s02b00x00p12n01i02951"
+      severity NOTE;
+    assert ( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
+             "Let's try multiple levels!" )
+      report "***FAILED TEST: c02s02b00x00p12n01i02951 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02951arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd
new file mode 100644
index 0000000..7f67132
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2952.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p24n01i02952pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+end c02s02b00x00p24n01i02952pkg;
+
+use work.c02s02b00x00p24n01i02952pkg.all;
+ENTITY c02s02b00x00p24n01i02952ent IS
+END c02s02b00x00p24n01i02952ent;
+
+ARCHITECTURE c02s02b00x00p24n01i02952arch OF c02s02b00x00p24n01i02952ent IS
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2) ;            ---  No_failure_here
+    wait for 5 ns;
+    assert NOT(S3='1' and S2=12)
+      report "***PASSED TEST: c02s02b00x00p24n01i02952" 
+      severity NOTE;
+    assert (S3='1' and S2=12)
+      report "***FAILED TEST: c02s02b00x00p24n01i02952 - Subprogram declaration should appear before call of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p24n01i02952arch;
+
+
+package body c02s02b00x00p24n01i02952pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" 
+      severity note;
+    assert (I3 /= 5)
+      report "No failure on test" 
+      severity note;
+    I2 <=   '1';
+    I3 <=   12;
+  end PX;
+end c02s02b00x00p24n01i02952pkg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd
new file mode 100644
index 0000000..02d008e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2955.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02955ent IS
+  procedure greater (i:integer; res:out boolean);
+  procedure greater (i:integer; res:out boolean) is
+    type       mine    is (vero,falso);
+    subtype    digit    is integer range 1 to 10;
+    constant    high   :integer:=10;
+    variable    zero   :integer;
+    variable    itl   :mine;
+  begin
+    zero := 0;
+    if i <= high then
+      itl:= vero;
+      res:= TRUE;
+    else 
+      res:= FALSE;
+    end if;
+  end greater;
+END c02s02b00x00p02n01i02955ent;
+
+ARCHITECTURE c02s02b00x00p02n01i02955arch OF c02s02b00x00p02n01i02955ent IS
+  subtype digit is integer range 1 to 10;
+BEGIN
+  TESTING: PROCESS
+    variable i:digit;
+    variable k:boolean;
+  BEGIN
+    i:= 5;
+    greater (i,k);
+    wait for 5 ns;
+    assert NOT( k=TRUE )
+      report "***PASSED TEST: c02s02b00x00p02n01i02955"
+      severity NOTE;
+    assert ( k=TRUE )
+      report "***FAILED TEST: c02s02b00x00p02n01i02955 - Subprogram body syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p02n01i02955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd
new file mode 100644
index 0000000..77ca383
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2959.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02959pkg is
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN character;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN real;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN string;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN time;
+end c02s03b00x00p02n01i02959pkg;
+
+package body c02s03b00x00p02n01i02959pkg is
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN time IS
+  BEGIN
+    assert false report "boo with TIME returned" severity note;
+    RETURN 10 ns;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN string IS
+  BEGIN
+    assert false report "boo with STRING returned" severity note;
+    RETURN "STRING";
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN real IS
+  BEGIN
+    assert false report "boo with REAL returned" severity note;
+    RETURN 10.01;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER returned" severity note;
+    RETURN 55;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN character IS
+  BEGIN
+    assert false report "boo with CHARACTER returned" severity note;
+    RETURN 'Z';
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN boolean IS
+  BEGIN
+    assert false report "boo with BOOLEAN returned" severity note;
+    RETURN TRUE;
+  END;
+  
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN bit_vector IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR returned" severity
+      note;
+    RETURN "1010";
+  END;
+  
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN bit IS
+  BEGIN
+    assert false report "boo with BIT returned" severity note;
+    RETURN '1';
+  END;
+end c02s03b00x00p02n01i02959pkg;
+
+ENTITY c02s03b00x00p02n01i02959ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+  SUBTYPE bv_4 IS bit_vector(1 TO 4);
+  SUBTYPE bv_6 IS bit_vector(1 TO 6);
+  
+  FUNCTION foo (  PARM_VAL : bv_4) RETURN bit_vector IS
+  BEGIN
+    assert false report "function foo in entity e" severity note;
+    RETURN PARM_VAL;
+  END;
+END c02s03b00x00p02n01i02959ent;
+
+use work.c02s03b00x00p02n01i02959pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02959arch OF c02s03b00x00p02n01i02959ent IS
+  SIGNAL c1 : bv_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    c1 <= boo ( bv_6'(OTHERS => '1'));
+    bb <= boo (c1);
+    bv <= boo (c1);
+    bo <= boo (c1);
+    cc <= boo (c1);
+    ii <= boo (c1);
+    rr <= boo (c1);
+    ss <= boo (c1);
+    tt <= boo (c1);
+    
+    WAIT FOR 1 ns;
+    assert NOT(    (c1 = "1010") AND
+                   (bb = '1') AND
+                   (bv = "1010") AND
+                   (bo = TRUE) AND
+                   (cc = 'Z') AND
+                   (ii = 55) AND
+                   (rr = 10.01) AND
+                   (ss = "STRING") AND
+                   (tt = 10 ns))
+      report "***PASSED TEST: c02s03b00x00p02n01i02959"
+      severity NOTE;
+    assert (    (c1 = "1010") AND
+                (bb = '1') AND
+                (bv = "1010") AND
+                (bo = TRUE) AND
+                (cc = 'Z') AND
+                (ii = 55) AND
+                (rr = 10.01) AND
+                (ss = "STRING") AND
+                (tt = 10 ns))
+      report "***FAILED TEST: c02s03b00x00p02n01i02959 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02959arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd
new file mode 100644
index 0000000..879a913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd
@@ -0,0 +1,151 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02960pkg is
+  FUNCTION boo ( PARM_VAL : bit) RETURN integer;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
+  FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
+  FUNCTION boo ( PARM_VAL : character) RETURN integer;
+  FUNCTION boo ( PARM_VAL : integer) RETURN integer;
+  FUNCTION boo ( PARM_VAL : real) RETURN integer;
+  FUNCTION boo ( PARM_VAL : string) RETURN integer;
+  FUNCTION boo ( PARM_VAL : time) RETURN integer;
+end c02s03b00x00p02n01i02960pkg;
+
+package body c02s03b00x00p02n01i02960pkg is
+  FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
+  BEGIN
+    assert false report "boo with BIT param" severity note;
+    RETURN 1;
+  END;
+
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR param" severity note;
+    RETURN 2;
+  END;
+
+  FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
+  BEGIN
+    assert false report "boo with BOOLEAN param" severity note;
+    RETURN 3;
+  END;
+
+  FUNCTION boo ( PARM_VAL : character) RETURN integer IS
+  BEGIN
+    assert false report "boo with CHARACTER param" severity note;
+    RETURN 4;
+  END;
+
+  FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER param" severity note;
+    RETURN 5;
+  END;
+
+  FUNCTION boo ( PARM_VAL : real) RETURN integer IS
+  BEGIN
+    assert false report "boo with REAL param" severity note;
+    RETURN 6;
+  END;
+  
+  FUNCTION boo ( PARM_VAL : string) RETURN integer IS
+  BEGIN
+    assert false report "boo with STRING param" severity note;
+    RETURN 7;
+  END;
+  
+  FUNCTION boo ( PARM_VAL : time) RETURN integer IS
+  BEGIN
+    assert false report "boo with TIME param" severity note;
+    RETURN 8;
+  END;
+end c02s03b00x00p02n01i02960pkg;
+
+ENTITY c02s03b00x00p02n01i02960ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+  SUBTYPE bv_4 IS bit_vector(1 TO 4);
+  SUBTYPE bv_6 IS bit_vector(1 TO 6);
+  
+  FUNCTION foo (  PARM_VAL : bv_4) RETURN bit_vector IS
+  BEGIN
+    assert false report "function foo in entity e" severity note;
+    RETURN PARM_VAL;
+  END;
+END c02s03b00x00p02n01i02960ent;
+
+use work.c02s03b00x00p02n01i02960pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
+  SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    c1 <= boo(bb);
+    c2 <= boo(bv);
+    c3 <= boo(bo);
+    c4 <= boo(cc);
+    c5 <= boo(ii);
+    c6 <= boo(rr);
+    c7 <= boo(ss);
+    c8 <= boo(tt);
+    
+    WAIT FOR 1 ns;
+    assert NOT(   (c1 = 1) AND
+                  (c2 = 2) AND
+                  (c3 = 3) AND
+                  (c4 = 4) AND
+                  (c5 = 5) AND
+                  (c6 = 6) AND
+                  (c7 = 7) AND
+                  (c8 = 8)) 
+      report "***PASSED TEST: c02s03b00x00p02n01i02960"
+      severity NOTE;
+    assert (   (c1 = 1) AND
+               (c2 = 2) AND
+               (c3 = 3) AND
+               (c4 = 4) AND
+               (c5 = 5) AND
+               (c6 = 6) AND
+               (c7 = 7) AND
+               (c8 = 8)) 
+      report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02960arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd
new file mode 100644
index 0000000..a9cdb47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02961pkg is
+  FUNCTION boo ( PARM_VAL: bit:='1')       RETURN bit;
+  FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
+  FUNCTION boo ( PARM_VAL: boolean:=TRUE)    RETURN boolean;
+  FUNCTION boo ( PARM_VAL: character:='Z')    RETURN character;
+  FUNCTION boo ( PARM_VAL: integer:=55)    RETURN integer;
+  FUNCTION boo ( PARM_VAL: real:=10.01)    RETURN real;
+  FUNCTION boo ( PARM_VAL: string:="STRING")    RETURN string;
+  FUNCTION boo ( PARM_VAL: time:=10 ns)    RETURN time;
+end c02s03b00x00p02n01i02961pkg;
+
+package body c02s03b00x00p02n01i02961pkg is
+  FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
+  BEGIN
+    assert false report "boo with BIT param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
+  BEGIN
+    assert false report "boo with BOOLEAN param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
+  BEGIN
+    assert false report "boo with CHARACTER param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
+  BEGIN
+    assert false report "boo with REAL param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
+  BEGIN
+    assert false report "boo with STRING param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
+  BEGIN
+    assert false report "boo with TIME param" severity note;
+    RETURN PARM_VAL;
+  END;
+end c02s03b00x00p02n01i02961pkg;
+
+ENTITY c02s03b00x00p02n01i02961ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+END c02s03b00x00p02n01i02961ent;
+
+use work.c02s03b00x00p02n01i02961pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
+  SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    bb <= boo;
+    bv <= boo;
+    bo <= boo;
+    cc <= boo;
+    ii <= boo;
+    rr <= boo;
+    ss <= boo;
+    tt <= boo;
+    
+    WAIT FOR 1 ns;
+    assert NOT(   (bb = '1')    AND
+                  (bv = "1010")    AND
+                  (bo = TRUE)    AND
+                  (cc = 'Z')    AND
+                  (ii = 55)    AND
+                  (rr = 10.01)    AND
+                  (ss = "STRING") AND
+                  (tt = 10 ns))   
+      report "***PASSED TEST: c02s03b00x00p02n01i02961"
+      severity NOTE;
+    assert (   (bb = '1')    AND
+               (bv = "1010")    AND
+               (bo = TRUE)    AND
+               (cc = 'Z')    AND
+               (ii = 55)    AND
+               (rr = 10.01)    AND
+               (ss = "STRING") AND
+               (tt = 10 ns))   
+      report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02961arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd
new file mode 100644
index 0000000..ecc8041
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2962.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b00x00p02n01i02962ent IS
+  port    (f,h,i    : out integer);
+  type    tripe    is (alpha,beta,gamma,delta,epsilon);
+  subtype subt    is tripe range beta to epsilon;
+END c02s03b00x00p02n01i02962ent;
+
+ARCHITECTURE c02s03b00x00p02n01i02962arch OF c02s03b00x00p02n01i02962ent IS
+  function funk (signal fa,fb : tripe) return integer is
+  begin
+    return (1);
+  end;
+  function funk (signal fa,fb : bit) return integer is
+  begin
+    return (2);
+  end;
+  signal bv1       : bit_vector (1 to 40);
+  signal a,b,c    : subt;
+  signal d,e,g    : integer;
+BEGIN
+  d <= funk(a,b);
+  TESTING: PROCESS
+    variable x : integer;
+  BEGIN
+    WAIT FOR 1 ns;
+    e <= funk(c,a);
+    x := funk(c,b);
+    g <= funk(bv1(2),bv1(6));
+    wait for 5 ns;
+    assert NOT(e=1 and x=1 and g=2)
+      report "***PASSED TEST: c02s03b00x00p02n01i02962"
+      severity NOTE;
+    assert (e=1 and x=1 and g=2)
+      report "***FAILED TEST: c02s03b00x00p02n01i02962 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd
new file mode 100644
index 0000000..d6311ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2964.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b00x00p03n01i02964ent IS
+END c02s03b00x00p03n01i02964ent;
+
+ARCHITECTURE c02s03b00x00p03n01i02964arch OF c02s03b00x00p03n01i02964ent IS
+  function f1a(constant c1 : in integer) return integer is
+  begin
+    return 12;
+  end;
+  function f1a(constant c1,c2 : in integer) return integer is
+  begin
+    return 25;
+  end;
+  function f2b(constant c1 : in integer) return integer is
+  begin
+    return 22;
+  end;
+  function f2b(constant c1 : in real) return integer is
+  begin
+    return 28;
+  end;
+  function f3c(constant c0:integer; constant c1:real) return integer is
+  begin
+    return 32;
+  end;
+  function f3c(constant c1:real; constant c0:integer) return integer is
+  begin
+    return 38;
+  end;
+  function f4d(constant c1 : in integer) return integer is
+  begin
+    return 42;
+  end;
+  function f4d(constant c1 : in integer) return real is
+  begin
+    return 48.0;
+  end;
+  function f5e(constant c1 : in integer) return integer is
+  begin
+    return 52;
+  end;
+  procedure f5e(constant c1 : in integer) is
+  begin
+    return;
+  end;
+  function f6f(constant c0 : in real;constant c1 : in integer) return integer is
+  begin
+    return 62;
+  end;
+  function f6f(constant c2 : in integer;constant c3 : in real) return integer is
+  begin
+    return 68;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable i1 : integer;
+    variable r1 : real;
+    variable k  : integer := 0;
+  BEGIN
+    i1 := 8;
+    if (i1 /= 8) then
+      k := 1;
+    end if;
+    assert (i1=8)
+      report "Error in initial conditions detected"
+      severity failure;
+    i1:= f1a(4);
+    if (i1 /= 12) then
+      k := 1;
+    end if;
+    assert (i1=12)
+      report "Error differentiating overloaded subprog by number of formals"
+      severity failure;
+    i1:=f1a(16,23);
+    if (i1 /= 25) then
+      k := 1;
+    end if;
+    assert (i1=25)
+      report "Error differentiating overloaded subprog by number of formals"
+      severity failure;
+    i1:= f2b(4);
+    if (i1 /= 22) then
+      k := 1;
+    end if;
+    assert (i1=22)
+      report "Error differentiating overloaded subprog by type of formals"
+      severity failure;
+    i1:=f2b(4.0);
+    if (i1 /= 28) then
+      k := 1;
+    end if;
+    assert (i1=28)
+      report "Error differentiating overloaded subprog by type of formals"
+      severity failure;
+    i1:= f3c(4,4.0);
+    if (i1 /= 32) then
+      k := 1;
+    end if;
+    assert (i1=32)
+      report "Error differentiating overloaded subprog by order of formals"
+      severity failure;
+    i1:= f3c(4.0,4);
+    if (i1 /= 38) then
+      k := 1;
+    end if;
+    assert (i1=38)
+      report "Error differentiating overloaded subprog by order of formals"
+      severity failure;
+    i1:= f4d(4);
+    if (i1 /= 42) then
+      k := 1;
+    end if;
+    assert (i1=42)
+      report "Error differentiating overloaded subprog by return type"
+      severity failure;
+
+    r1:= f4d(4);
+    if (r1 /= 48.0) then
+      k := 1;
+    end if;
+    assert (r1=48.0)
+      report "Error differentiating overloaded subprog by return type"
+      severity failure;
+    i1:= f5e(4);
+    if (i1 /= 52) then
+      k := 1;
+    end if;
+    assert (i1=52)
+      report "Error differentiating overloaded subprog by having a return"
+      severity failure;
+    i1:= f6f(c1 => 4, c0 => 4.4);
+    if (i1 /= 62) then
+      k := 1;
+    end if;
+    assert (i1=62)
+      report "Error differentiating overloaded subprog by name of formals"
+      severity failure;
+    i1:= f6f(c3 => 4.4, c2 => 4);
+    if (i1 /= 68) then
+      k := 1;
+    end if;
+    assert (i1=68)
+      report "Error differentiating overloaded subprog by name of formals"
+      severity failure;
+    wait for 5 ns;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c02s03b00x00p03n01i02964"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c02s03b00x00p03n01i02964 - Overload subprogram call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p03n01i02964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd
new file mode 100644
index 0000000..19e3863
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p01n01i02966ent IS
+END c02s03b01x00p01n01i02966ent;
+
+ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function "and" (a, b: in integer) return boolean is
+    begin
+      return false;
+    end;
+    variable i1, i2    :integer := 2;
+    variable b1, b2    :boolean := true;
+    variable q1      :boolean ;
+    variable q2      :boolean ;
+    variable q3      :boolean ;
+  BEGIN
+    q1 := i1 and i2;
+    q2 := b1 and b2;
+    q3 := "and" (i1, i2);
+    wait for 5 ns;
+    assert NOT( q1=false and q2=true and q3=false )
+      report "***PASSED TEST: c02s03b01x00p01n01i02966"
+      severity NOTE;
+    assert ( q1=false and q2=true and q3=false )
+      report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p01n01i02966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd
new file mode 100644
index 0000000..a7f7fe5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2967.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n01i02967ent IS
+END c02s03b01x00p02n01i02967ent;
+
+ARCHITECTURE c02s03b01x00p02n01i02967arch OF c02s03b01x00p02n01i02967ent IS
+  function "not" (I1:Bit) return bit is
+  begin
+    if (I1 = '1') then
+      return '1';
+    else
+      return '0';
+    end if;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit;
+  BEGIN
+    k := not('1');
+    assert NOT(k='1')
+      report "***PASSED TEST: c02s03b01x00p02n01i02967" 
+      severity NOTE;
+    assert (k='1')
+      report "***FAILED TEST: c02s03b01x00p02n01i02967 - The subprogram specification of a unary operator must have only a single parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n01i02967arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd
new file mode 100644
index 0000000..90c94f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n02i02968ent IS
+END c02s03b01x00p02n02i02968ent;
+
+ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
+  type newt is (one,two,three,four);
+  function "abs" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of right operator"
+      severity failure;
+    assert NOT( c1=10 )
+      report "***PASSED TEST: c02s03b01x00p02n02i02968"
+      severity NOTE;
+    assert ( c1=10 )
+      report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= abs 10;
+    assert (n1=three)
+      report "Error in call to operloaded operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n02i02968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd
new file mode 100644
index 0000000..58871ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2969.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n02i02969ent IS
+END c02s03b01x00p02n02i02969ent;
+
+ARCHITECTURE c02s03b01x00p02n02i02969arch OF c02s03b01x00p02n02i02969ent IS
+  type newt is (one,two,three,four);
+  function "mod" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right operator"
+      severity failure;
+    assert NOT( c1=10 and c2=20 )
+      report "***PASSED TEST: c02s03b01x00p02n02i02969"
+      severity NOTE;
+    assert ( c1=10 and c2=20 )
+      report "***FAILED TEST: c02s03b01x00p02n02i02969 - Error in association of operands."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 10 mod 20;
+    assert (n1=three)
+      report "Error in call to operloaded operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n02i02969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd
new file mode 100644
index 0000000..72dd46f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc297.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n04i00297ent IS
+END c03s01b03x01p01n04i00297ent;
+
+ARCHITECTURE c03s01b03x01p01n04i00297arch OF c03s01b03x01p01n04i00297ent IS
+  constant T1 : TIME := 10 ns;
+  signal   S : BIT ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= '1' after T1;   
+    wait for 20 ns;
+    assert NOT(S='1') 
+      report "***PASSED TEST: c03s01b03x01p01n04i00297" 
+      severity NOTE;
+    assert (S='1') 
+      report "***FAILED TEST: c03s01b03x01p01n04i00297 - The delay specification is not of type TIME."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n04i00297arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd
new file mode 100644
index 0000000..d27ced3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2972.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02972ent IS
+END c02s03b01x00p03n01i02972ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02972arch OF c02s03b01x00p03n01i02972ent IS
+  type newt is (one,two,three,four);
+  function "+" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of unary + operator"
+      severity failure;
+    assert NOT( c1=10 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02972"
+      severity NOTE;
+    assert ( c1=10 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02972 - Error in + overloading as unary operator."
+      severity ERROR;
+    return four;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1:= +10;
+    assert (n1=four)
+      report "Error in call to overloaded unary + operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02972arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd
new file mode 100644
index 0000000..93eb39c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02973ent IS
+END c02s03b01x00p03n01i02973ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
+  type newt is (one,two,three,four);
+  function "+" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left binary  + operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right binary + operator"
+      severity failure;
+    assert NOT( c1=10 and c2=20 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02973"
+      severity NOTE;
+    assert ( c1=10 and c2=20 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 10 + 20;
+    assert (n1=three)
+      report "Error in call to overloaded binary + operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd
new file mode 100644
index 0000000..f36bdfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2974.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02974ent IS
+END c02s03b01x00p03n01i02974ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02974arch OF c02s03b01x00p03n01i02974ent IS
+  type newt is (one,two,three,four);
+  function "-" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=70)
+      report "Error in association of unary - operator"
+      severity failure;
+    assert NOT( c1=70 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02974"
+      severity NOTE;
+    assert ( c1=70 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02974 - Error in - overloading as unary operator."
+      severity ERROR;
+    return four;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1:= -70;
+    assert (n1=four)
+      report "Error in call to overloaded unary - operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02974arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd
new file mode 100644
index 0000000..5389786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2975.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02975ent IS
+END c02s03b01x00p03n01i02975ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02975arch OF c02s03b01x00p03n01i02975ent IS
+  type newt is (one,two,three,four);
+  function "-" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=70)
+      report "Error in association of left binary  - operator"
+      severity failure;
+    assert (c2=80)
+      report "Error in association of right binary - operator"
+      severity failure;
+    assert NOT( c1=70 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02975"
+      severity NOTE;
+    assert ( c1=70 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02975 - Error in - overloading as binary operator."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 70 - 80;
+    assert (n1=three)
+      report "Error in call to overloaded binary - operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02975arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd
new file mode 100644
index 0000000..b56cea0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2976.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p05n01i02976ent IS
+END c02s03b01x00p05n01i02976ent;
+
+ARCHITECTURE c02s03b01x00p05n01i02976arch OF c02s03b01x00p05n01i02976ent IS
+  subtype    si is integer range 1 to 4;
+  constant    c1 :  si := 2;
+  signal    s1 :  integer;
+
+  function "=" (constant c1,c2 : in integer) return boolean is
+  begin
+    return false;
+  end;
+
+BEGIN
+  with (c1) select
+    s1 <= 1 after 5 ns when 1,
+    2 after 5 ns when 2,
+    3 after 5 ns when 3,
+    4 after 5 ns when others;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( (s1<=2) and (s1>=2) )
+      report "***PASSED TEST: c02s03b01x00p05n01i02976"
+      severity NOTE;
+    assert ( (s1<=2) and (s1>=2) )
+      report "***FAILED TEST: c02s03b01x00p05n01i02976 - Error in use of overloaded equality operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p05n01i02976arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd
new file mode 100644
index 0000000..ae01c31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2977.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p05n01i02977ent IS
+END c02s03b01x00p05n01i02977ent;
+
+ARCHITECTURE c02s03b01x00p05n01i02977arch OF c02s03b01x00p05n01i02977ent IS
+  function "and" (constant c1,c2 : in boolean) return boolean is
+  begin
+    return true;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable b1 : boolean := true;
+    variable bf : boolean := false;
+    variable bt : boolean := true;
+  BEGIN
+    assert (b1=true)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (bf=false)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (bt=true)
+      report "Error in initial conditions detected"
+      severity failure;
+    b1 := bf and bt;
+    assert NOT( b1=true )
+      report "***PASSED TEST: c02s03b01x00p05n01i02977"
+      severity NOTE;
+    assert ( b1=true )
+      report "***FAILED TEST: c02s03b01x00p05n01i02977 - Error in invocation overloaded operator and."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p05n01i02977arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd
new file mode 100644
index 0000000..8d62a1b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2978.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p07n01i02978ent IS
+END c02s03b01x00p07n01i02978ent;
+
+ARCHITECTURE c02s03b01x00p07n01i02978arch OF c02s03b01x00p07n01i02978ent IS
+  type newt is (one,two,three,four);
+  function "abs" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of right operator"
+      severity failure;
+    return one;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1:= "abs"(10);
+    assert (n1=one)
+      report "Error in call to operloaded operator"
+      severity failure;
+    assert NOT( n1=one )
+      report "***PASSED TEST: c02s03b01x00p07n01i02978"
+      severity NOTE;
+    assert ( n1=one )
+      report "***FAILED TEST: c02s03b01x00p07n01i02978 - Error in call to operloaded operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p07n01i02978arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd
new file mode 100644
index 0000000..1229817
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2979.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p07n01i02979ent IS
+END c02s03b01x00p07n01i02979ent;
+
+ARCHITECTURE c02s03b01x00p07n01i02979arch OF c02s03b01x00p07n01i02979ent IS
+  type newt is (one,two,three,four);
+  function "mod" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right operator"
+      severity failure;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= "mod"(10,20);
+    assert NOT( n1=three )
+      report "***PASSED TEST: c02s03b01x00p07n01i02979"
+      severity NOTE;
+    assert ( n1=three )
+      report "***FAILED TEST: c02s03b01x00p07n01i02979 - Error in call to operloaded operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p07n01i02979arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd
new file mode 100644
index 0000000..0aeb385
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00298ent IS
+END c03s01b03x01p01n03i00298ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (us  = 1000 ns) and
+                (ms  = 1000 us) and
+                (sec = 1000 ms) )
+      report "***PASSED TEST: c03s01b03x01p01n03i00298"
+      severity NOTE;
+    assert (    (us  = 1000 ns) and
+                (ms  = 1000 us) and
+                (sec = 1000 ms) )
+      report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00298arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd
new file mode 100644
index 0000000..03e1369
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2980.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s04b00x00p03n02i02980ent IS
+END c02s04b00x00p03n02i02980ent;
+
+ARCHITECTURE c02s04b00x00p03n02i02980arch OF c02s04b00x00p03n02i02980ent IS
+  -- Create low-level resolution function and its subtypes.
+  function Always_Zero( S : BIT_VECTOR ) return BIT is
+  begin
+    return( '0' );
+  end Always_Zero;
+
+  subtype BIT_SUB is Always_Zero BIT;
+  type NEW_BIT_VECTOR is array( 1 to 10 ) of BIT_SUB;
+  
+  -- Create the composite signal resolved at both levels.
+  signal ONE   : NEW_BIT_VECTOR;
+BEGIN
+  
+  -- Create two drivers for the composite.
+  ONE  <= NEW_BIT_VECTOR'(B"1111111111") after 10 ns;
+  ONE  <= NEW_BIT_VECTOR'(B"0000000000") after 20 ns;
+  
+  TESTING: PROCESS(one)
+  BEGIN
+    assert NOT( ONE = B"0000000000" )
+      report "***PASSED TEST: c02s04b00x00p03n02i02980"
+      severity NOTE;
+    assert ( ONE = B"0000000000" )
+      report "***FAILED TEST: c02s04b00x00p03n02i02980 - Low level resolution function does not got called."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c02s04b00x00p03n02i02980arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd
new file mode 100644
index 0000000..75c5eba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2981.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s04b00x00p04n04i02981ent IS
+END c02s04b00x00p04n04i02981ent;
+
+ARCHITECTURE c02s04b00x00p04n04i02981arch OF c02s04b00x00p04n04i02981ent IS
+  -- Define an array of integers.
+  type INT_ARRAY is array( NATURAL range <> ) of INTEGER;
+
+  -- Define a resolution function.
+  function RESFUNC( S : INT_ARRAY ) return INTEGER is
+    -- local variables.
+    variable MAX : INTEGER := INTEGER'LOW;
+
+  begin
+    if  (S'LENGTH = 0) then
+      return INTEGER'LOW;
+    else
+      for I in S'RANGE loop
+        if  (S(I) > MAX) then
+          MAX := S(I);
+        end if;
+      end loop;
+      return MAX;
+    end if;
+  end;
+
+  -- Define a subtype of integer.
+  subtype SINT is RESFUNC INTEGER;
+
+  -- Define a bus signal.
+  signal B : SINT bus := 0;
+BEGIN
+  -- One process driving B.
+  process
+  begin
+    -- Verify initial conditions.
+    assert( B = 0 );
+    
+    -- Go to NULL.
+    B <=       null  after 10 ns;
+    
+    -- Wait until B gets updated.
+    wait on B;
+    
+    -- Verify that both drivers have been turned off.
+    assert( B = INTEGER'LOW );
+    
+    -- Turn a driver on again.
+    B <= 47 after 10 ns;
+    
+    -- Wait for B to be updated.
+    wait on B;
+    
+    -- Verify that B was updated accordingly.
+    assert( B = 47 );
+    
+    -- End of test.
+    wait;
+  end process;
+  
+  -- Second process driving B.
+  process
+  begin
+    -- Verify initial conditions.
+    assert( B = 0 );
+    
+    -- Go to NULL.
+    B <=       null  after 10 ns;
+    
+    -- Wait until B gets updated.
+    wait on B;
+    
+    -- Verify that both drivers have been turned off.
+    assert( B = INTEGER'LOW );
+    
+    -- End of test.
+    wait;
+  end process;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert FALSE
+      report "***PASSED TEST: c02s04b00x00p04n04i02981 - This test needs manual check to make sure there is no other ERROR or FAILURE assertion notice."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c02s04b00x00p04n04i02981arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd
new file mode 100644
index 0000000..ecaa350
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2982.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p01n01i02982pkg is
+  type       tristate    is ('0','1','Z');
+  subtype    bi       is integer range 1 to 2;
+  constant    lowstate   : tristate:='0';
+end c02s05b00x00p01n01i02982pkg;
+
+
+ENTITY c02s05b00x00p01n01i02982ent IS
+END c02s05b00x00p01n01i02982ent;
+
+ARCHITECTURE c02s05b00x00p01n01i02982arch OF c02s05b00x00p01n01i02982ent IS
+  use work.c02s05b00x00p01n01i02982pkg.all;
+BEGIN
+  TESTING: PROCESS
+    variable locz:tristate   :='Z';
+    variable loch:bi   :=2;
+  BEGIN
+    locz:=lowstate;
+    loch:=1;
+    wait for 5 ns;
+    assert NOT( locz='0' and loch<2 )
+      report "***PASSED TEST: c02s05b00x00p01n01i02982"
+      severity NOTE;
+    assert ( locz='0' and loch<2 )
+      report "***FAILED TEST: c02s05b00x00p01n01i02982 - Package declaration syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p01n01i02982arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd
new file mode 100644
index 0000000..557e4ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2987.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02987pkg is
+  constant wtime: time := 5 ns;
+end c02s05b00x00p06n01i02987pkg;
+
+ENTITY c02s05b00x00p06n01i02987ent IS
+END c02s05b00x00p06n01i02987ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02987arch OF c02s05b00x00p06n01i02987ent IS
+  use work.c02s05b00x00p06n01i02987pkg.wtime;
+BEGIN
+  TESTING: PROCESS
+    variable TimeCount : time := 0 ns;
+  BEGIN
+    TimeCount   := NOW;
+    wait for wtime;
+    TimeCount   := NOW - TimeCount;   
+    assert NOT( TimeCount = 5 ns )
+      report "***PASSED TEST: c02s05b00x00p06n01i02987"
+      severity NOTE;
+    assert ( TimeCount = 5 ns )
+      report "***FAILED TEST: c02s05b00x00p06n01i02987 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd
new file mode 100644
index 0000000..bb1b930
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2988.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02988pkg is
+  constant var : integer := 5;
+end c02s05b00x00p06n01i02988pkg;
+
+ENTITY c02s05b00x00p06n01i02988ent IS
+END c02s05b00x00p06n01i02988ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02988arch OF c02s05b00x00p06n01i02988ent IS
+  use work.c02s05b00x00p06n01i02988pkg.var;
+BEGIN
+  TESTING: PROCESS
+    variable fin : time := 1 ns;
+  BEGIN
+    fin := fin * var;
+    assert NOT( fin = 5 ns )
+      report "***PASSED TEST: c02s05b00x00p06n01i02988"
+      severity NOTE;
+    assert ( fin = 5 ns )
+      report "***FAILED TEST: c02s05b00x00p06n01i02988 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd
new file mode 100644
index 0000000..29c23ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02989pkg is
+  constant    c1    : INTEGER;
+  function    f    return INTEGER;
+  procedure    p(x : inout INTEGER);
+end c02s05b00x00p06n01i02989pkg;
+
+package body c02s05b00x00p06n01i02989pkg is
+  constant c1 : INTEGER := 10;
+  constant c2 : INTEGER := 20;
+  function f return INTEGER is
+  begin
+    return c1 + c2;
+  end;
+  procedure p( x: inout INTEGER) is
+  begin
+    x := c1 + c2;
+  end;
+end c02s05b00x00p06n01i02989pkg;
+
+
+ENTITY c02s05b00x00p06n01i02989ent IS
+END c02s05b00x00p06n01i02989ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
+  signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
+  signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
+BEGIN
+  TESTING: PROCESS
+    variable temp : INTEGER;
+  BEGIN
+    s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
+
+    WORK.c02s05b00x00p06n01i02989pkg.P(temp);
+    s2 <= temp;
+    wait for 5 ns;
+    assert NOT( s1 = 30 and s2 = 30 )
+      report "***PASSED TEST: c02s05b00x00p06n01i02989"
+      severity NOTE;
+    assert ( s1 = 30 and s2 = 30 )
+      report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02989arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd
new file mode 100644
index 0000000..ae1626e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc299.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00299ent IS
+END c03s01b03x01p01n03i00299ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00299arch OF c03s01b03x01p01n03i00299ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (sec = 1000 ms) and
+                (min =  60 sec) and
+                (hr  =  60 min))
+      report "***PASSED TEST:c03s01b03x01p01n03i00299"
+      severity NOTE;
+    assert (    (sec = 1000 ms) and
+                (min =  60 sec) and
+                (hr  =  60 min))
+      report "***FAILED TEST: c03s01b03x01p01n03i00299 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd
new file mode 100644
index 0000000..73d519e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2990.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02990pkg is
+  signal s_p : INTEGER := 1;
+end c02s05b00x00p06n01i02990pkg;
+ENTITY c02s05b00x00p06n01i02990ent IS
+  signal s_e : INTEGER := 2;
+END c02s05b00x00p06n01i02990ent;
+
+use work.c02s05b00x00p06n01i02990pkg.s_p;
+ARCHITECTURE c02s05b00x00p06n01i02990arch OF c02s05b00x00p06n01i02990ent IS
+  signal s_a : INTEGER := 3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s_e <= s_p;
+    wait for 1 ns;
+    s_a <= s_e;
+    wait for 5 ns;
+    assert NOT( s_a = 1 )
+      report "***PASSED TEST: c02s05b00x00p06n01i02990"
+      severity NOTE;
+    assert ( s_a = 1 )
+      report "***FAILED TEST: c02s05b00x00p06n01i02990 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02990arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd
new file mode 100644
index 0000000..b4a84f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc30.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b00x00p14n04i00030ent IS
+END c04s03b00x00p14n04i00030ent;
+
+ARCHITECTURE c04s03b00x00p14n04i00030arch OF c04s03b00x00p14n04i00030ent IS
+  signal       M1 : BIT_VECTOR(0 to 7) ;
+  constant    M2 : BIT := '1' ;
+BEGIN
+  TESTING: PROCESS
+    variable   V1 : BIT; 
+  BEGIN
+    M1(3) <=    '1' after 10 ns;
+    --- No_failure_here
+    --- M1(3) is also a signal; so this signal
+    --- assignment is possible.
+    V1    :=    M2;   
+    wait for 10 ns;
+    assert NOT( M1(3)='1' and V1='1' )
+      report "***PASSED TEST: c04s03b00x00p14n04i00030"
+      severity NOTE;
+    assert ( M1(3)='1' and V1='1' )
+      report "***FAILED TEST:c04s03b00x00p14n04i00030 - Each subelement of that object is itself an object of the same class as the given object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b00x00p14n04i00030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd
new file mode 100644
index 0000000..e93bf02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3001.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p02n01i03001pkg is
+end c02s06b00x00p02n01i03001pkg;
+
+package body c02s06b00x00p02n01i03001pkg is
+end;
+
+ENTITY c02s06b00x00p02n01i03001ent IS
+END c02s06b00x00p02n01i03001ent;
+
+ARCHITECTURE c02s06b00x00p02n01i03001arch OF c02s06b00x00p02n01i03001ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c02s06b00x00p02n01i03001" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p02n01i03001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd
new file mode 100644
index 0000000..d4b08e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3005.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03005pkg is
+  constant t: time;
+end c02s06b00x00p07n01i03005pkg;
+
+package body c02s06b00x00p07n01i03005pkg is
+  constant t: time:= 5 ns;
+end c02s06b00x00p07n01i03005pkg;
+
+ENTITY c02s06b00x00p07n01i03005ent IS
+END c02s06b00x00p07n01i03005ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03005arch OF c02s06b00x00p07n01i03005ent IS
+  use work.c02s06b00x00p07n01i03005pkg.all;
+BEGIN
+  TESTING: PROCESS
+    variable x: time;
+  BEGIN
+    x := t;
+    wait for 5 ns;
+    assert NOT( x = 5 ns )
+      report "***PASSED TEST: c02s06b00x00p07n01i03005"
+      severity NOTE;
+    assert ( x = 5 ns )
+      report "***FAILED TEST: c02s06b00x00p07n01i03005 - Deferred constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd
new file mode 100644
index 0000000..5e00be8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc301.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p03n01i00301ent IS
+END c03s01b04x00p03n01i00301ent;
+
+ARCHITECTURE c03s01b04x00p03n01i00301arch OF c03s01b04x00p03n01i00301ent IS
+  type REAL1 is range REAL'LOW to REAL'HIGH;
+BEGIN
+  TESTING: PROCESS
+    variable k : REAL1 := 6.0;
+  BEGIN
+    k := 5.0;
+    assert NOT(k=5.0) 
+      report "***PASSED TEST: c03s01b04x00p03n01i00301" 
+      severity NOTE;
+    assert (k=5.0) 
+      report "***FAILED TEST: c03s01b04x00p03n01i00301 - The range of the type defined by the floating point type is within the range given by the floating point defintion." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p03n01i00301arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd
new file mode 100644
index 0000000..4b87adb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3010.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03010pkg is
+  constant X1 : integer;
+  constant X2 : integer;
+end c02s06b00x00p07n01i03010pkg;
+
+package body c02s06b00x00p07n01i03010pkg is
+  constant X1: integer := 1;
+  constant X2: integer := X1;
+end c02s06b00x00p07n01i03010pkg;
+
+use work.c02s06b00x00p07n01i03010pkg.all;
+ENTITY c02s06b00x00p07n01i03010ent IS
+END c02s06b00x00p07n01i03010ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03010arch OF c02s06b00x00p07n01i03010ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(X1=1 and X2=1)
+      report "***PASSED TEST: c02s06b00x00p07n01i03010" 
+      severity NOTE;
+    assert (X1=1 and X2=1)
+      report "***FAILED TEST: c02s06b00x00p07n01i03010 - Deferred constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd
new file mode 100644
index 0000000..0b848ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library WORK, STD;
+use STD.STANDARD.all;   -- No_failure_here
+
+ENTITY c11s02b00x00p05n02i03016ent IS
+END c11s02b00x00p05n02i03016ent;
+
+ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS
+  signal BV : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    BV <= "01010111" after 5 ns;
+    wait for 10 ns;
+    assert NOT( BV = "01010111" )
+      report "***PASSED TEST: c11s02b00x00p05n02i03016"
+      severity NOTE;
+    assert ( BV = "01010111" )
+      report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n02i03016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd
new file mode 100644
index 0000000..6bb2199
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3022.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s03b00x00p04n02i03022pkg is
+  type T is (one,two,three,four);
+  subtype SIN is INTEGER;
+end c11s03b00x00p04n02i03022pkg;
+
+use work.c11s03b00x00p04n02i03022pkg.all;
+ENTITY c11s03b00x00p04n02i03022ent IS
+END c11s03b00x00p04n02i03022ent;
+
+ARCHITECTURE c11s03b00x00p04n02i03022arch OF c11s03b00x00p04n02i03022ent IS
+  signal S1 : T;      -- type T should be visible
+  signal S2 : SIN;    -- subtype SIN should be visible
+  signal S3 : REAL;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= one;      --literal "one" should be visible
+    S2 <= 1234;
+    wait for 5 ns;
+    assert NOT( S1 = one and S2 = 1234 )
+      report "***PASSED TEST: c11s03b00x00p04n02i03022"
+      severity NOTE;
+    assert ( S1 = one and S2 = 1234 )
+      report "***FAILED TEST: c11s03b00x00p04n02i03022 - A use clause should make certain declarations directly visible within the design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s03b00x00p04n02i03022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd
new file mode 100644
index 0000000..876fae9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library WORK, STD;
+
+ENTITY c11s02b00x00p05n01i03023ent IS
+END c11s02b00x00p05n01i03023ent;
+
+ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
+  signal S1 : STD.STANDARD.bit;   -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= '1' after 20 ns;
+    wait for 30 ns;
+    assert NOT( S1 = '1' )
+      report "***PASSED TEST: c11s02b00x00p05n01i03023"
+      severity NOTE;
+    assert ( S1 = '1' )
+      report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n01i03023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd
new file mode 100644
index 0000000..8bee475
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s03b00x00p02n01i03024pkg is
+  type T is (one,two);
+end c11s03b00x00p02n01i03024pkg;
+
+ENTITY c11s03b00x00p02n01i03024ent IS
+END c11s03b00x00p02n01i03024ent;
+
+ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
+  signal S : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= TRUE;
+    wait for 3 ns;
+    assert NOT( S = TRUE )
+      report "***PASSED TEST: c11s03b00x00p02n01i03024"
+      severity NOTE;
+    assert ( S = TRUE )
+      report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s03b00x00p02n01i03024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd
new file mode 100644
index 0000000..306ba99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3029.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s04b00x00p02n01i03029pkg is
+  type MVL is ('0', '1', 'X', 'Z') ;
+  function F1 (INPUT : Bit) return Bit;
+end c11s04b00x00p02n01i03029pkg;
+
+package body c11s04b00x00p02n01i03029pkg is
+  constant C1 : MVL := '1' ;
+  function F1 (INPUT : Bit) return Bit is
+  begin
+    if Input = '1' then
+      return '0' ;
+    else
+      return '1' ;
+    end if;
+  end F1;
+end c11s04b00x00p02n01i03029pkg;
+
+use work.c11s04b00x00p02n01i03029pkg.all;
+ENTITY c11s04b00x00p02n01i03029ent IS
+END c11s04b00x00p02n01i03029ent;
+
+ARCHITECTURE c11s04b00x00p02n01i03029arch OF c11s04b00x00p02n01i03029ent IS
+  signal S1  : MVL;
+  signal S2  : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 'Z'    after 20 ns;
+    S2 <= F1('1')    after 50 ns;
+    wait for 60 ns;
+    assert NOT(S1 = 'Z' and S2 = '0')
+      report "***PASSED TEST: c11s04b00x00p02n01i03029" 
+      severity NOTE;
+    assert (S1 = 'Z' and S2 = '0')
+      report "***FAILED TEST: c11s04b00x00p02n01i03029 - Primary unit must be analyzed before the analysis of the unit that references it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd
new file mode 100644
index 0000000..6784ea9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3032.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03032ent IS
+END c12s02b01x00p01n02i03032ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03032arch OF c12s02b01x00p01n02i03032ent IS
+  subtype subi is integer range 1   to 10;
+  subtype subr is real    range 1.0 to 10.0;
+  subtype subb is bit     range '1' to '1';
+  type c_a is array(integer range <>) of subi;
+
+  signal s1, s2, s3 : c_a(1 to 3);
+BEGIN
+  -- test array generics
+  bl1: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (1,1,1));
+    port   (s11 : OUT c_a(1 to 3));
+    port map (s11 => s1);
+  begin
+    assert ((gi(1)=1) and (gi(2)=1) and (gi(3)=1))
+      report "Generic array GI did not take on the correct low value of 1"
+      severity failure;
+    s11 <= gi;
+  end block;
+  bl2: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (5,5,5));
+    port   (s22 : OUT c_a(1 to 3));
+    port map (s22 => s2);
+  begin
+    assert ((gi(1)=5) and (gi(2)=5) and (gi(3)=5))
+      report "Generic array GI did not take on the correct middle value of 5"
+      severity failure;
+    s22 <= gi;
+  end block;
+  bl3: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (10,10,10));
+    port   (s33 : OUT c_a(1 to 3));
+    port map (s33 => s3);
+  begin
+    assert ((gi(1)=10) and (gi(2)=10) and (gi(3)=10))
+      report "Generic array GI did not take on the correct high value of 10"
+      severity failure;
+    s33 <= gi;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
+      report "***PASSED TEST: c12s02b01x00p01n02i03032"
+      severity NOTE;
+    assert ( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
+      report "***FAILED TEST: c12s02b01x00p01n02i03032 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd
new file mode 100644
index 0000000..a900c43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03033ent IS
+END c12s02b01x00p01n02i03033ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
+  subtype subi is integer range 1 to 10;
+  signal   s1,s2,s3 : subi;
+BEGIN
+
+  bl1: block
+    generic (gi : subi);
+    generic map (gi => 1);
+    port    (s11 : OUT subi);
+    port map (s11 => s1);
+  begin
+    assert (gi=1)
+      report "Generic GI did not take on the correct low value of 1"
+      severity failure;
+    s11 <= gi;
+  end block;
+  bl2: block
+    generic (gi : subi);
+    generic map (gi => 5);
+    port    (s22 : OUT subi);
+    port map (s22 => s2);
+  begin
+    assert (gi=5)
+      report "Generic GI did not take on the correct middle value of 5"         
+      severity failure;
+    s22 <= gi;
+  end block;
+  bl3: block
+    generic (gi : subi);
+    generic map (gi => 10);
+    port    (s33 : OUT subi);
+    port map (s33 => s3);
+  begin
+    assert (gi=10)
+      report "Generic GI did not take on the correct high value of 10"
+      severity failure;
+    s33 <= gi;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
+      report "***PASSED TEST: c12s02b01x00p01n02i03033"
+      severity NOTE;
+    assert ( s1 = 1 and s2 = 5 and s3 = 10 )
+      report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd
new file mode 100644
index 0000000..73e3567
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3034.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03034ent IS
+END c12s02b01x00p01n02i03034ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03034arch OF c12s02b01x00p01n02i03034ent IS
+  subtype subi is integer range 1   to 10;
+  subtype subr is real    range 1.0 to 10.0;
+  subtype subb is bit     range '1' to '1';
+
+  type c_r is
+    record
+      i : subi;
+      r : subr;
+      b : subb;
+    end record;
+
+  signal s1, s2, s3 : c_r;
+BEGIN
+  -- test record generics
+  bl4: block
+    generic(gr : c_r);
+    generic map (gr => (1,1.0,'1'));
+    port   (s11 : OUT c_r);
+    port map (s11 => s1);
+  begin
+    assert ((gr.i=1) and (gr.r=1.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct low value"
+      severity failure;
+    s11 <= gr;
+  end block;
+  bl5: block
+    generic(gr : c_r);
+    generic map (gr => (5,5.0,'1'));
+    port   (s22 : OUT c_r);
+    port map (s22 => s2);
+  begin
+    assert ((gr.i=5) and (gr.r=5.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct middle value"
+      severity failure;
+    s22 <= gr;
+  end block;
+  bl6: block
+    generic(gr : c_r);
+    generic map (gr => (10,10.0,'1'));
+    port   (s33 : OUT c_r);
+    port map (s33 => s3);
+  begin
+    assert ((gr.i=10) and (gr.r=10.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct high value"         
+      severity failure;
+    s33 <= gr;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
+      report "***PASSED TEST: c12s02b01x00p01n02i03034"
+      severity NOTE;
+    assert ( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
+      report "***FAILED TEST: c12s02b01x00p01n02i03034 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd
new file mode 100644
index 0000000..897efd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3035.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03035ent IS
+END c12s02b02x00p01n02i03035ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03035arch OF c12s02b02x00p01n02i03035ent IS
+
+BEGIN
+
+  -- test for first element association
+  bl2: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(i=>5);
+  begin
+    assert (i=5)
+      report "Generic map value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=5 and r=3.4 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03035"
+      severity NOTE;
+    assert ( i=5 and r=3.4 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03035 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd
new file mode 100644
index 0000000..689b53d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3036.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03036ent IS
+END c12s02b02x00p01n02i03036ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03036arch OF c12s02b02x00p01n02i03036ent IS
+
+BEGIN
+  -- test for no associations
+  bl1: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+    assert NOT( i=10 and r=3.4 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03036"
+      severity NOTE;
+    assert ( i=10 and r=3.4 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03036 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd
new file mode 100644
index 0000000..fdd5059
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3037.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03037ent IS
+END c12s02b02x00p01n02i03037ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03037arch OF c12s02b02x00p01n02i03037ent IS
+
+BEGIN
+
+  -- test for last element association
+  bl3: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(b=>'0');
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='0')
+      report "Generic map value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=10 and r=3.4 and b='0')
+      report "***PASSED TEST: c12s02b02x00p01n02i03037"
+      severity NOTE;
+    assert ( i=10 and r=3.4 and b='0')
+      report "***FAILED TEST: c12s02b02x00p01n02i03037 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd
new file mode 100644
index 0000000..eecbc88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3038.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03038ent IS
+END c12s02b02x00p01n02i03038ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03038arch OF c12s02b02x00p01n02i03038ent IS
+
+BEGIN
+  -- test for middle element association
+  bl4: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(r=>6.7);
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=6.7)
+      report "Generic map value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=10 and r=6.7 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03038"
+      severity NOTE;
+    assert ( i=10 and r=6.7 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03038 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd
new file mode 100644
index 0000000..306a35b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3039.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03039ent IS
+END c12s02b02x00p01n02i03039ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03039arch OF c12s02b02x00p01n02i03039ent IS
+
+BEGIN
+  -- test for first and last element associations
+  bl5: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(i=>5,b=>'0');
+  begin
+    assert (i=5)
+      report "Generic map value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='0')
+      report "Generic map value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=5 and r=3.4 and b='0')
+      report "***PASSED TEST: c12s02b02x00p01n02i03039"
+      severity NOTE;
+    assert ( i=5 and r=3.4 and b='0')
+      report "***FAILED TEST: c12s02b02x00p01n02i03039 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd
new file mode 100644
index 0000000..f13ce57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3040.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03040ent IS
+END c12s02b02x00p01n02i03040ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03040arch OF c12s02b02x00p01n02i03040ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for no associations
+  bl1 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+  begin
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10))
+      report "Default value for array generic not correct"
+      severity failure;
+    assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "Default value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1')) 
+      report "***PASSED TEST: c12s02b02x00p01n02i03040"
+      severity NOTE;
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1')) 
+      report "***FAILED TEST: c12s02b02x00p01n02i03040 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd
new file mode 100644
index 0000000..8750385
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3041.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03041ent IS
+END c12s02b02x00p01n02i03041ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03041arch OF c12s02b02x00p01n02i03041ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for first associations
+  bl2 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+    generic map(i=>(5,5,5));
+  begin
+    assert ((i(1)=5) and (i(2)=5) and (i(3)=5))
+      report "Generic map value for array generic not correct"
+      severity failure;
+    assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "Default value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "***PASSED TEST: c12s02b02x00p01n02i03041"
+      severity NOTE;
+    assert ((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "***FAILED TEST: c12s02b02x00p01n02i03041 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd
new file mode 100644
index 0000000..5728a05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3042.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03042ent IS
+END c12s02b02x00p01n02i03042ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03042arch OF c12s02b02x00p01n02i03042ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for last associations
+  bl3 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+    generic map(r=>(5,6.7,'0'));
+  begin
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10))
+      report "Default value for array generic not correct"
+      severity failure;
+    assert ((r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "Generic map value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "***PASSED TEST: c12s02b02x00p01n02i03042"
+      severity NOTE;
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "***FAILED TEST: c12s02b02x00p01n02i03042 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03042arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd
new file mode 100644
index 0000000..0180eef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3043.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03043ent IS
+END c12s02b02x00p02n03i03043ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03043arch OF c12s02b02x00p02n03i03043ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(i2=>-5, i1=>3, i4=>-4, i3=>6);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03043"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03043 - Named association of generics creates constnats without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd
new file mode 100644
index 0000000..273eeee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3044.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03044ent IS
+END c12s02b02x00p02n03i03044ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03044arch OF c12s02b02x00p02n03i03044ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(3, -5, 6, -4);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03044"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03044 - Positional association of generics creates constants without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03044arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd
new file mode 100644
index 0000000..f3cb669
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3045.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03045ent IS
+END c12s02b02x00p02n03i03045ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03045arch OF c12s02b02x00p02n03i03045ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(3, -5, i4=>-4, i3=>6);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03045"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03045 - Named association and positional association of generics creates constnats without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd
new file mode 100644
index 0000000..468aea1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3046.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b03x00p01n02i03046ent IS
+  type c_r is
+    record
+      i1 : integer;
+      r1 : real;
+      b1 : bit;
+    end record;
+  type c_a is array(1 to 3) of bit;
+END c12s02b03x00p01n02i03046ent;
+
+ARCHITECTURE c12s02b03x00p01n02i03046arch OF c12s02b03x00p01n02i03046ent IS
+  signal sr : c_r := (14,1.4,'1');
+  signal sa : c_a := "101";
+BEGIN
+  b1: block
+    port(r:c_r; a:c_a);
+    port map (r=>sr, a=>sa);
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( r=(14,1.4,'1') and a="101")
+        report "***PASSED TEST: c12s02b03x00p01n02i03046"
+        severity NOTE;
+      assert ( r=(14,1.4,'1') and a="101")
+        report "***FAILED TEST: c12s02b03x00p01n02i03046 - Ports should conform to their subtype indication."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b03x00p01n02i03046arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd
new file mode 100644
index 0000000..5c36f74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3047.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b03x00p01n02i03047ent IS
+END c12s02b03x00p01n02i03047ent;
+
+ARCHITECTURE c12s02b03x00p01n02i03047arch OF c12s02b03x00p01n02i03047ent IS
+  signal si : integer;
+  signal sr : real;
+  signal sb : bit;
+BEGIN
+  si <= 4    after 1 ns;
+  sr <= 3.2    after 1 ns;
+  sb <= '1'    after 1 ns;
+  b1: block
+    port (i:in integer := 3; r:in real := 4.5; b:in bit := '0');
+    port map (i=>si, r=>sr, b=>sb);
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( i=4 and r=3.2 and b='1')
+        report "***PASSED TEST: c12s02b03x00p01n02i03047"
+        severity NOTE;
+      assert ( i=4 and r=3.2 and b='1')
+        report "***FAILED TEST: c12s02b03x00p01n02i03047 - Ports should conform to their subtype indication."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b03x00p01n02i03047arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd
new file mode 100644
index 0000000..c1c3cb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3048.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03048ent IS
+END c12s02b04x00p03n01i03048ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03048arch OF c12s02b04x00p03n01i03048ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for first port associated
+  bl2: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (i=>si);
+  begin
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=14 and r=6.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03048"
+        severity NOTE;
+      assert ( i=14 and r=6.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03048 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03048arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd
new file mode 100644
index 0000000..fbc645c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3049.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03049ent_a IS
+  port(con : in BIT := '1'; clk : out BIT);
+END c12s02b04x00p03n01i03049ent_a;
+
+ARCHITECTURE c12s02b04x00p03n01i03049arch_a OF c12s02b04x00p03n01i03049ent_a IS
+BEGIN
+  process(con)
+  begin
+    clk <= con;
+  end process;
+END c12s02b04x00p03n01i03049arch_a;
+
+
+ENTITY c12s02b04x00p03n01i03049ent IS
+END c12s02b04x00p03n01i03049ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03049arch OF c12s02b04x00p03n01i03049ent IS
+  signal C : bit := '0';
+  component c12s02b04x00p03n01i03049ent_aa
+    port (   con : IN    bit := '1';
+             clk : OUT   bit   );
+  end component;   
+  for all : c12s02b04x00p03n01i03049ent_aa use entity work.c12s02b04x00p03n01i03049ent_a(c12s02b04x00p03n01i03049arch_a);
+BEGIN
+
+  T1 : c12s02b04x00p03n01i03049ent_aa port map (open, C);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( C = '1' )
+      report "***PASSED TEST: c12s02b04x00p03n01i03049"
+      severity NOTE;
+    assert ( C = '1' )
+      report "***FAILED TEST: c12s02b04x00p03n01i03049 - A port of mode in assumes the value of the default expression when there is no associated signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b04x00p03n01i03049arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd
new file mode 100644
index 0000000..0fa2ab0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03050ent IS
+END c12s02b04x00p03n01i03050ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
+  signal si:integer;
+  signal sr:real;
+  signal sb:bit;
+BEGIN
+  -- test for no associated ports
+  bl1: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=6.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03050"
+        severity NOTE;
+      assert ( i=4 and r=6.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd
new file mode 100644
index 0000000..0960fb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3051.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03051ent IS
+END c12s02b04x00p03n01i03051ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03051arch OF c12s02b04x00p03n01i03051ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for middle port associated
+  bl3: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (r=>sr);
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=1.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03051"
+        severity NOTE;
+      assert ( i=4 and r=1.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03051 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03051arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd
new file mode 100644
index 0000000..fee4bdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3052.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03052ent IS
+END c12s02b04x00p03n01i03052ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03052arch OF c12s02b04x00p03n01i03052ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for last port associated
+  bl4: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (b=>sb);
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=6.4 and b='0' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03052"
+        severity NOTE;
+      assert ( i=4 and r=6.4 and b='0' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03052 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd
new file mode 100644
index 0000000..149a86f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3053.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03053ent IS
+END c12s02b04x00p03n01i03053ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03053arch OF c12s02b04x00p03n01i03053ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for end ports associated
+  bl5: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (i=>si, b=>sb);
+  begin
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=14 and r=6.4 and b='0' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03053"
+        severity NOTE;
+      assert ( i=14 and r=6.4 and b='0' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03053 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd
new file mode 100644
index 0000000..427d744
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3054.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b00x00p07n03i03054ent IS
+END c12s03b00x00p07n03i03054ent;
+
+ARCHITECTURE c12s03b00x00p07n03i03054arch OF c12s03b00x00p07n03i03054ent IS
+
+BEGIN
+  bl1: block
+    signal si : integer := 3;
+    function int (signal sf : in integer) return integer is
+      constant err:integer := sf;
+    begin
+      return err;
+    end;
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( si = int(si) )
+        report "***PASSED TEST: c12s03b00x00p07n03i03054"
+        severity NOTE;
+      assert ( si = int(si) )
+        report "***FAILED TEST: c12s03b00x00p07n03i03054 - Name of a signal used in the declarative part of a subprogram test failed."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s03b00x00p07n03i03054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd
new file mode 100644
index 0000000..d87384e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3055.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s03b01x00p02n03i03055pkg is
+  subtype BYTE is BIT_VECTOR(7 downto 0);
+  function BIN_TO_INTG (IN_DATA : BYTE) return INTEGER;
+end c12s03b01x00p02n03i03055pkg;
+
+package body c12s03b01x00p02n03i03055pkg is
+  function BIN_TO_INTG (IN_DATA : BYTE) return INTEGER is
+    variable SUM : INTEGER := 0;
+  begin
+    for I in 7 downto 0 loop
+      if (IN_DATA(I) = '1') then
+        SUM := SUM + (2**I);
+      end if;
+    end loop;
+    return SUM;
+  end BIN_TO_INTG;
+end c12s03b01x00p02n03i03055pkg;
+
+use WORK.c12s03b01x00p02n03i03055pkg.all;
+ENTITY c12s03b01x00p02n03i03055ent IS
+END c12s03b01x00p02n03i03055ent;
+
+ARCHITECTURE c12s03b01x00p02n03i03055arch OF c12s03b01x00p02n03i03055ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BYTE := "00001111";
+    variable X  : INTEGER;
+  BEGIN
+    X := BIN_TO_INTG(S1) ;
+    assert NOT(X = 15)
+      report "***PASSED TEST: c12s03b01x00p02n03i03055" 
+      severity NOTE;
+    assert (X = 15)
+      report "***FAILED TEST: c12s03b01x00p02n03i03055 - Subprogram Body should be elaaborated before subprogram call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x00p02n03i03055arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd
new file mode 100644
index 0000000..ee3c0ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3057.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b01x04p10n01i03057ent IS
+END c12s03b01x04p10n01i03057ent;
+
+ARCHITECTURE c12s03b01x04p10n01i03057arch OF c12s03b01x04p10n01i03057ent IS
+
+  function f1(constant sb : in bit) return bit is
+    constant b : bit := sb;
+  begin
+    assert (b=sb)
+      report "Constant B in function F1 set to non-static variable failed"
+      severity failure;
+    assert NOT( b=sb )
+      report "***PASSED TEST: c12s03b01x04p10n01i03057"
+      severity NOTE;
+    assert ( b=sb )
+      report "***FAILED TEST: c12s03b01x04p10n01i03057 - Non-static expression initializing a constant failed."
+      severity ERROR;
+    return '1';
+  end;
+
+BEGIN
+  TESTING: PROCESS
+    variable vbi,vbr : bit;
+  BEGIN
+    vbi:='1';
+    vbr:=f1(vbi);
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x04p10n01i03057arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd
new file mode 100644
index 0000000..7c6bd05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3059.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b01x05p01n02i03059ent IS
+END c12s03b01x05p01n02i03059ent;
+
+ARCHITECTURE c12s03b01x05p01n02i03059arch OF c12s03b01x05p01n02i03059ent IS
+  signal R_NUM : BIT_VECTOR(0 to 15) := "1010101001010101";
+  alias  NUMB  : BIT_VECTOR(7 downto 0) is R_NUM(8 to 15);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( NUMB = "01010101" )
+      report "***PASSED TEST: c12s03b01x05p01n02i03059"
+      severity NOTE;
+    assert ( NUMB = "01010101" )
+      report "***FAILED TEST: c12s03b01x05p01n02i03059 - Alias for an array object has a matching element for each element of the named object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x05p01n02i03059arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd
new file mode 100644
index 0000000..f4385d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3060.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p06n03i03060ent IS
+  ATTRIBUTE attr1 : string;
+END c12s03b02x01p06n03i03060ent;
+
+ARCHITECTURE c12s03b02x01p06n03i03060arch OF c12s03b02x01p06n03i03060ent IS
+
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+1;  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+2;  END;
+
+  ATTRIBUTE attr1 OF f1 : FUNCTION IS "a string of pearls";
+  ATTRIBUTE attr1 OF f2 : FUNCTION IS "TLA";
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    ASSERT f1'attr1 = "a string of pearls" 
+      REPORT "ERROR: Bad value for f1'attr1" 
+      SEVERITY FAILURE;
+    ASSERT f2'attr1 = "TLA"                
+      REPORT "ERROR: Bad value for f2'attr1" 
+      SEVERITY FAILURE;
+--
+    ASSERT f1'attr1(1) = 'a' REPORT "ERROR: Bad value for f1'attr1(1)" SEVERITY FAILURE;
+    ASSERT f2'attr1(3) = 'A' REPORT "ERROR: Bad value for f2'attr1(3)" SEVERITY FAILURE;
+--
+    assert NOT(    f1'attr1 = "a string of pearls"   and
+                   f2'attr1 = "TLA"      and
+                   f1'attr1(1) = 'a'      and
+                   f2'attr1(3) = 'A'      )
+      report "***PASSED TEST: c12s03b02x01p06n03i03060"
+      severity NOTE;
+    assert (    f1'attr1 = "a string of pearls"   and
+                f2'attr1 = "TLA"      and
+                f1'attr1(1) = 'a'      and
+                f2'attr1(3) = 'A'      )
+      report "***FAILED TEST: c12s03b02x01p06n03i03060 - No an implicit subtype conversion is necessary for an attribute of an unconstrained array type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p06n03i03060arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd
new file mode 100644
index 0000000..dc2095d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3061.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p06n02i03061ent IS
+  SUBTYPE    s10 IS STRING (10 DOWNTO 1);
+  ATTRIBUTE    attr1 : s10;
+END c12s03b02x01p06n02i03061ent;
+
+ARCHITECTURE c12s03b02x01p06n02i03061arch OF c12s03b02x01p06n02i03061ent IS
+  
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+1;  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+2;  END;
+  
+  ATTRIBUTE attr1 OF f1,f2 : FUNCTION IS "ABCDEFGHIJ";
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    f1'attr1 = "ABCDEFGHIJ"   and
+                   f2'attr1 = "ABCDEFGHIJ"   and
+                   f1'attr1( 1) = 'J'   and
+                   f2'attr1(10) = 'A'   )
+      report "***PASSED TEST: c12s03b02x01p06n02i03061"
+      severity NOTE;
+    assert (    f1'attr1 = "ABCDEFGHIJ"   and
+                f2'attr1 = "ABCDEFGHIJ"   and
+                f1'attr1( 1) = 'J'   and
+                f2'attr1(10) = 'A'   )
+      report "***FAILED TEST: c12s03b02x01p06n02i03061 - An attribute of a constrained array type, an implicit sutype conversion is first applied as for an assignment statement test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p06n02i03061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd
new file mode 100644
index 0000000..f8f6792
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3062.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p07n01i03062ent IS
+  function setatt return integer is
+  begin
+    return 5;
+  end;
+END c12s03b02x01p07n01i03062ent;
+
+ARCHITECTURE c12s03b02x01p07n01i03062arch OF c12s03b02x01p07n01i03062ent IS
+  signal    sa    :bit;
+  attribute    ai   :integer;
+  attribute    ai of sa:signal is setatt;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert (sa'ai = setatt)
+      report "Attribute AI of signal SA was not set to the correct non-static value"
+      severity failure;
+    assert NOT( sa'ai = setatt )
+      report "***PASSED TEST: c12s03b02x01p07n01i03062"
+      severity NOTE;
+    assert ( sa'ai = setatt )
+      report "***FAILED TEST: c12s03b02x01p07n01i03062 - Non-static expression as an attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p07n01i03062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd
new file mode 100644
index 0000000..e25cd59
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3063.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x02p01n01i03063ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c12s03b02x02p01n01i03063ent;
+
+ARCHITECTURE c12s03b02x02p01n01i03063arch OF c12s03b02x02p01n01i03063ent IS
+  
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  
+    RETURN i+1;  
+  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  
+    RETURN i+2;  
+  END;
+  
+  ATTRIBUTE attr1 OF f1,f2 : FUNCTION IS f1(f2(1));
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( f1'attr1 = 4 and f2'attr1 = 4 )
+      report "***PASSED TEST: c12s03b02x02p01n01i03063"
+      severity NOTE;
+    assert ( f1'attr1 = 4 and f2'attr1 = 4 )
+      report "***FAILED TEST: c12s03b02x02p01n01i03063 - Elaboration of an attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x02p01n01i03063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd
new file mode 100644
index 0000000..d6d0d68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3066.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s04b02x00p02n01i03066ent IS
+END c12s04b02x00p02n01i03066ent;
+
+ARCHITECTURE c12s04b02x00p02n01i03066arch OF c12s04b02x00p02n01i03066ent IS
+  signal    V :    BIT_VECTOR(1 to 4);
+BEGIN
+  FG1: for i in V'range generate
+    B: block
+    begin
+      V(i) <= '0', '1' after i * 10 ns;
+      -- signals should get different delays
+    end block;
+  end generate;
+
+  TESTING: PROCESS(V)
+    variable ok : integer := 1;
+  BEGIN
+    if (Now = 10 ns) then
+      if not(V(1)'event and V(1) = '1') then
+        ok := 0;
+      end if;
+    elsif (Now = 20 ns) then
+      if not(V(2)'event and V(2) = '1') then
+        ok := 0;
+      end if;
+    elsif (Now = 30 ns) then
+      if not(V(3)'event and V(3) = '1') then
+        ok := 0;
+      end if;
+    end if;
+    if (Now > 30 ns) then
+      assert NOT( ok = 1 )
+        report "***PASSED TEST: c12s04b02x00p02n01i03066"
+        severity NOTE;
+      assert ( ok = 1 )
+        report "***FAILED TEST: c12s04b02x00p02n01i03066 - Generate statement semantic test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c12s04b02x00p02n01i03066arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd
new file mode 100644
index 0000000..d8b358f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3067.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s04b02x00p06n01i03067ent IS
+END c12s04b02x00p06n01i03067ent;
+
+ARCHITECTURE c12s04b02x00p06n01i03067arch OF c12s04b02x00p06n01i03067ent IS
+
+BEGIN
+  G1: if TRUE generate
+    assert FALSE 
+      report "***This assertion note should occur.***" 
+      severity NOTE;
+  end generate;
+  G2: if FALSE generate
+    assert FALSE 
+      report "***This assertion note should not occur.***" 
+      severity ERROR;
+  end generate;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c12s04b02x00p06n01i03067 - This test needs manual check to make sure CORRECT assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c12s04b02x00p06n01i03067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd
new file mode 100644
index 0000000..3fc0479
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3068.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03068pkg is
+  type   severity_level_cons_vector is array (15 downto 0) of severity_level;
+  constant C19 : severity_level_cons_vector := (others => note);
+end c12s06b02x00p06n01i03068pkg;
+
+use work.c12s06b02x00p06n01i03068pkg.all;
+ENTITY c12s06b02x00p06n01i03068ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   severity_level_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03068ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03068arch_a OF c12s06b02x00p06n01i03068ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03068arch_a;
+
+
+use work.c12s06b02x00p06n01i03068pkg.all;
+ENTITY c12s06b02x00p06n01i03068ent IS
+END c12s06b02x00p06n01i03068ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03068arch OF c12s06b02x00p06n01i03068ent IS
+  function scalar_complex(s : integer) return severity_level_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   severity_level_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03068ent_a(c12s06b02x00p06n01i03068arch_a);
+  signal S1 : severity_level_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03068"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03068 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd
new file mode 100644
index 0000000..937fcb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3069.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03069pkg is
+  type   boolean_cons_vector is array (15 downto 0) of boolean;
+  constant C19 : boolean_cons_vector := (others => true);
+end c12s06b02x00p06n01i03069pkg;
+
+use work.c12s06b02x00p06n01i03069pkg.all;
+ENTITY c12s06b02x00p06n01i03069ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   boolean_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03069ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03069arch_a OF c12s06b02x00p06n01i03069ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03069arch_a;
+
+
+use work.c12s06b02x00p06n01i03069pkg.all;
+ENTITY c12s06b02x00p06n01i03069ent IS
+END c12s06b02x00p06n01i03069ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03069arch OF c12s06b02x00p06n01i03069ent IS
+  function scalar_complex(s : integer) return boolean_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   boolean_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03069ent_a(c12s06b02x00p06n01i03069arch_a);
+  signal S1 : boolean_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03069"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03069 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd
new file mode 100644
index 0000000..1973e65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3070.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03070pkg is
+  type   integer_cons_vector is array (15 downto 0) of integer;
+  constant C19 : integer_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03070pkg;
+
+use work.c12s06b02x00p06n01i03070pkg.all;
+ENTITY c12s06b02x00p06n01i03070ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   integer_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03070ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03070arch_a OF c12s06b02x00p06n01i03070ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03070arch_a;
+
+
+use work.c12s06b02x00p06n01i03070pkg.all;
+ENTITY c12s06b02x00p06n01i03070ent IS
+END c12s06b02x00p06n01i03070ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03070arch OF c12s06b02x00p06n01i03070ent IS
+  function scalar_complex(s : integer) return integer_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   integer_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03070ent_a(c12s06b02x00p06n01i03070arch_a);
+  signal S1 : integer_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03070"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03070 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd
new file mode 100644
index 0000000..4014ca4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3071.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03071pkg is
+  type   time_cons_vector is array (15 downto 0) of time;
+  constant C19 : time_cons_vector := (others => 3 ns);
+end c12s06b02x00p06n01i03071pkg;
+
+use work.c12s06b02x00p06n01i03071pkg.all;
+ENTITY c12s06b02x00p06n01i03071ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   time_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03071ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03071arch_a OF c12s06b02x00p06n01i03071ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03071arch_a;
+
+
+use work.c12s06b02x00p06n01i03071pkg.all;
+ENTITY c12s06b02x00p06n01i03071ent IS
+END c12s06b02x00p06n01i03071ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03071arch OF c12s06b02x00p06n01i03071ent IS
+  function scalar_complex(s : integer) return time_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   time_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03071ent_a(c12s06b02x00p06n01i03071arch_a);
+  signal S1 : time_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03071"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03071 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd
new file mode 100644
index 0000000..c3ab548
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3072.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03072pkg is
+  type   natural_cons_vector is array (15 downto 0) of natural;
+  constant C19 : natural_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03072pkg;
+
+use work.c12s06b02x00p06n01i03072pkg.all;
+ENTITY c12s06b02x00p06n01i03072ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   natural_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03072ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03072arch_a OF c12s06b02x00p06n01i03072ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03072arch_a;
+
+
+use work.c12s06b02x00p06n01i03072pkg.all;
+ENTITY c12s06b02x00p06n01i03072ent IS
+END c12s06b02x00p06n01i03072ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03072arch OF c12s06b02x00p06n01i03072ent IS
+  function scalar_complex(s : integer) return natural_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   natural_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03072ent_a(c12s06b02x00p06n01i03072arch_a);
+  signal S1 : natural_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03072"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03072 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd
new file mode 100644
index 0000000..0840682
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3073.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03073pkg is
+  type   positive_cons_vector is array (15 downto 0) of positive;
+  constant C19 : positive_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03073pkg;
+
+use work.c12s06b02x00p06n01i03073pkg.all;
+ENTITY c12s06b02x00p06n01i03073ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   positive_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03073ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03073arch_a OF c12s06b02x00p06n01i03073ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03073arch_a;
+
+
+use work.c12s06b02x00p06n01i03073pkg.all;
+ENTITY c12s06b02x00p06n01i03073ent IS
+END c12s06b02x00p06n01i03073ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03073arch OF c12s06b02x00p06n01i03073ent IS
+  function scalar_complex(s : integer) return positive_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   positive_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03073ent_a(c12s06b02x00p06n01i03073arch_a);
+  signal S1 : positive_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03073"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03073 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd
new file mode 100644
index 0000000..cbf738f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3074.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03074pkg is
+  type    boolean_cons_vector is array (15 downto 0) of boolean;
+  type    boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  constant C19 : boolean_cons_vectorofvector := (others => (others => true));
+end c12s06b02x00p06n01i03074pkg;
+
+use work.c12s06b02x00p06n01i03074pkg.all;
+ENTITY c12s06b02x00p06n01i03074ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   boolean_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03074ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03074arch_a OF c12s06b02x00p06n01i03074ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03074arch_a;
+
+
+use work.c12s06b02x00p06n01i03074pkg.all;
+ENTITY c12s06b02x00p06n01i03074ent IS
+END c12s06b02x00p06n01i03074ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03074arch OF c12s06b02x00p06n01i03074ent IS
+  function scalar_complex(s : integer) return boolean_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   boolean_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03074ent_a(c12s06b02x00p06n01i03074arch_a);
+  signal S1 : boolean_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03074"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03074 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03074arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd
new file mode 100644
index 0000000..953f056
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03075pkg is
+  type    severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type    severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
+end c12s06b02x00p06n01i03075pkg;
+
+use work.c12s06b02x00p06n01i03075pkg.all;
+ENTITY c12s06b02x00p06n01i03075ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   severity_level_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03075ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03075arch_a;
+
+
+use work.c12s06b02x00p06n01i03075pkg.all;
+ENTITY c12s06b02x00p06n01i03075ent IS
+END c12s06b02x00p06n01i03075ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
+  function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   severity_level_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
+  signal S1 : severity_level_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03075"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd
new file mode 100644
index 0000000..93ebb63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03076pkg is
+  type    integer_cons_vector is array (15 downto 0) of integer;
+  type    integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
+  constant C19 : integer_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03076pkg;
+
+use work.c12s06b02x00p06n01i03076pkg.all;
+ENTITY c12s06b02x00p06n01i03076ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   integer_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03076ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03076arch_a;
+
+
+use work.c12s06b02x00p06n01i03076pkg.all;
+ENTITY c12s06b02x00p06n01i03076ent IS
+END c12s06b02x00p06n01i03076ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
+  function scalar_complex(s : integer) return integer_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   integer_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
+  signal S1 : integer_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03076"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03076arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd
new file mode 100644
index 0000000..0337fd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3077.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03077pkg is
+  type    real_cons_vector is array (15 downto 0) of real;
+  type    real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  constant C19 : real_cons_vectorofvector := (others => (others => 3.0));
+end c12s06b02x00p06n01i03077pkg;
+
+use work.c12s06b02x00p06n01i03077pkg.all;
+ENTITY c12s06b02x00p06n01i03077ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   real_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03077ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03077arch_a OF c12s06b02x00p06n01i03077ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03077arch_a;
+
+
+use work.c12s06b02x00p06n01i03077pkg.all;
+ENTITY c12s06b02x00p06n01i03077ent IS
+END c12s06b02x00p06n01i03077ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03077arch OF c12s06b02x00p06n01i03077ent IS
+  function scalar_complex(s : integer) return real_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   real_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03077ent_a(c12s06b02x00p06n01i03077arch_a);
+  signal S1 : real_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03077"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03077 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd
new file mode 100644
index 0000000..84c1abd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3078.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03078pkg is
+  type    time_cons_vector is array (15 downto 0) of time;
+  type    time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  constant C19 : time_cons_vectorofvector := (others => (others => 3 ns));
+end c12s06b02x00p06n01i03078pkg;
+
+use work.c12s06b02x00p06n01i03078pkg.all;
+ENTITY c12s06b02x00p06n01i03078ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   time_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03078ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03078arch_a OF c12s06b02x00p06n01i03078ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03078arch_a;
+
+
+use work.c12s06b02x00p06n01i03078pkg.all;
+ENTITY c12s06b02x00p06n01i03078ent IS
+END c12s06b02x00p06n01i03078ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03078arch OF c12s06b02x00p06n01i03078ent IS
+  function scalar_complex(s : integer) return time_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   time_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03078ent_a(c12s06b02x00p06n01i03078arch_a);
+  signal S1 : time_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03078"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03078 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd
new file mode 100644
index 0000000..d8aa950
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3079.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03079pkg is
+  type    natural_cons_vector is array (15 downto 0) of natural;
+  type    natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  constant C19 : natural_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03079pkg;
+
+use work.c12s06b02x00p06n01i03079pkg.all;
+ENTITY c12s06b02x00p06n01i03079ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   natural_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03079ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03079arch_a OF c12s06b02x00p06n01i03079ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03079arch_a;
+
+
+use work.c12s06b02x00p06n01i03079pkg.all;
+ENTITY c12s06b02x00p06n01i03079ent IS
+END c12s06b02x00p06n01i03079ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03079arch OF c12s06b02x00p06n01i03079ent IS
+  function scalar_complex(s : integer) return natural_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   natural_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03079ent_a(c12s06b02x00p06n01i03079arch_a);
+  signal S1 : natural_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03079"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03079 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd
new file mode 100644
index 0000000..2606663
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc308.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00308ent IS
+END c03s01b04x00p04n01i00308ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00308arch OF c03s01b04x00p04n01i00308ent IS
+  type REAL1 is range 1.0 to 10.0;
+  type REAL2 is range 10.0 to 20.0;
+  constant V1: REAL1 := 1.0;
+  constant V2: REAL2 := 20.0;
+  type REAL5 is range V1 to V2;
+BEGIN
+  TESTING: PROCESS
+    variable k : REAL5 := 6.0;
+  BEGIN
+    k := 5.0;
+    assert NOT(k=5.0) 
+      report "***PASSED TEST: c03s01b04x00p04n01i00308" 
+      severity NOTE;
+    assert (k=5.0) 
+      report "***FAILED TEST: c03s01b04x00p04n01i00308 - Expressions in floating point constraints in floating point type definitions need not be of the same floating point type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00308arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd
new file mode 100644
index 0000000..4477345
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3080.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03080pkg is
+  type    positive_cons_vector is array (15 downto 0) of positive;
+  type    positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  constant C19 : positive_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03080pkg;
+
+use work.c12s06b02x00p06n01i03080pkg.all;
+ENTITY c12s06b02x00p06n01i03080ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   positive_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03080ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03080arch_a OF c12s06b02x00p06n01i03080ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03080arch_a;
+
+
+use work.c12s06b02x00p06n01i03080pkg.all;
+ENTITY c12s06b02x00p06n01i03080ent IS
+END c12s06b02x00p06n01i03080ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03080arch OF c12s06b02x00p06n01i03080ent IS
+  function scalar_complex(s : integer) return positive_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   positive_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03080ent_a(c12s06b02x00p06n01i03080arch_a);
+  signal S1 : positive_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03080"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03080 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd
new file mode 100644
index 0000000..683916a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd
@@ -0,0 +1,138 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3081.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b02x00p05n01i03081ent IS
+END c12s06b02x00p05n01i03081ent;
+
+ARCHITECTURE c12s06b02x00p05n01i03081arch OF c12s06b02x00p05n01i03081ent IS
+  -- Define the resolution function we'll be using.
+  function WIRED_OR( Inputs: BIT_VECTOR) return BIT is
+    constant FLoatValue :BIT := '0';
+  begin
+    for I in Inputs'Range loop
+      if Inputs(I) = '1' then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end;
+  
+  -- Define the subtype that has this resolution function.
+  subtype RBIT is WIRED_OR BIT;
+  
+  -- This signal will have its 'ACTIVE flag monitored.
+  signal MONITOR : RBIT := '0';
+  
+  -- This signal will be used to check MONITOR'ACTIVE whenever
+  -- we want to verify that is value is OK.
+  signal CHECK   : RBIT := '0';
+BEGIN
+
+  TESTING: PROCESS
+    variable   testOK   : integer := 0;
+  BEGIN
+    -- Perform a signal value change on both signals.
+    MONITOR <= not MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( not( MONITOR'STABLE ) );
+    if (MONITOR'STABLE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'EVENT );
+    if (not(MONITOR'EVENT)) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no signal value change on MONITOR.
+    MONITOR <=     MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no activity at all on MONITOR.
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'ACTIVE ) );
+    if (MONITOR'ACTIVE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'QUIET  );
+    if (not(MONITOR'QUIET)) then
+      testOK := 1;
+    end if;
+    
+    assert NOT( testOK = 0 )
+      report "***PASSED TEST: c12s06b02x00p05n01i03081"
+      severity NOTE;
+    assert ( testOK = 0 )
+      report "***FAILED TEST: c12s06b02x00p05n01i03081 - A signal should be active if one of its sources is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p05n01i03081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd
new file mode 100644
index 0000000..f248e26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3082.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b02x00p02n01i03082ent IS
+END c12s06b02x00p02n01i03082ent;
+
+ARCHITECTURE c12s06b02x00p02n01i03082arch OF c12s06b02x00p02n01i03082ent IS
+  -- This signal will have its 'ACTIVE flag monitored.
+  signal MONITOR : BIT := '0';
+
+  -- This signal will be used to check MONITOR'ACTIVE whenever we want to verify that 
+  -- its value is OK.
+  signal CHECK : BIT := '0';
+BEGIN
+
+  TESTING: PROCESS
+    variable   testOK   : integer := 0;
+  BEGIN
+    -- Perform a signal value change on both signals.
+    MONITOR <= not MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+
+    -- Verify that the flags say what we want.
+    assert( not( MONITOR'STABLE ) );
+    if (MONITOR'STABLE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'EVENT );
+    if (not(MONITOR'EVENT)) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+
+    -- Perform no signal value change on MONITOR.
+    MONITOR <=     MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no activity at all on MONITOR.
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'ACTIVE ) );
+    if (MONITOR'ACTIVE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'QUIET  );
+    if (not(MONITOR'QUIET)) then
+      testOK := 1;
+    end if;
+    
+    assert NOT( testOK = 0 )
+      report "***PASSED TEST: c12s06b02x00p02n01i03082"
+      severity NOTE;
+    assert ( testOK = 0 )
+      report "***FAILED TEST: c12s06b02x00p02n01i03082 - A signal should be active if one of its sources is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p02n01i03082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd
new file mode 100644
index 0000000..def581d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3083.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p02n01i03083ent IS
+END c12s06b03x00p02n01i03083ent;
+
+ARCHITECTURE c12s06b03x00p02n01i03083arch OF c12s06b03x00p02n01i03083ent IS
+  signal S1 : BIT;
+  signal X1 : BIT;
+  signal S  : integer := 1;
+BEGIN
+
+  S1 <= transport '1' after 5 ns;
+
+  A : block(X1 = '1')
+  begin
+    process(GUARD)
+    begin
+      if GUARD then
+        assert false
+          report "Failure on test. Guard value shouldn't have been changed" ;
+        S <= 0;
+      end if;
+    end process;
+  end block A;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(S = 1)
+      report "***PASSED TEST: c12s06b03x00p02n01i03083" 
+      severity NOTE;
+    assert (S = 1)
+      report "***FAILED TEST: c12s06b03x00p02n01i03083 - GUARD signal is not modified in the test." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p02n01i03083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd
new file mode 100644
index 0000000..80bb6fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3084.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p02n01i03084ent IS
+END c12s06b03x00p02n01i03084ent;
+
+ARCHITECTURE c12s06b03x00p02n01i03084arch OF c12s06b03x00p02n01i03084ent IS
+  signal S1 : BIT;
+BEGIN
+
+  S1 <= transport '1' after 5 ns,
+        '0' after 15 ns;
+
+  A : block(S1 = '1')
+  begin
+    process
+    begin
+      wait on GUARD;
+      if GUARD then
+        assert false
+          report "No failure; Changes on signal S1 have modified the GUARD signal" 
+          severity NOTE;
+      else
+        assert false
+          report "No failure; Changes on signal S1 have modified the GUARD signal"
+          severity NOTE;
+      end if;
+    end process;
+  end block A;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert FALSE
+      report "***PASSED TEST: c12s06b03x00p02n01i03084 - This test needs manual check to see other two PASS assertion note."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p02n01i03084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd
new file mode 100644
index 0000000..51f239f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3085.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p03n01i03085ent IS
+END c12s06b03x00p03n01i03085ent;
+
+ARCHITECTURE c12s06b03x00p03n01i03085arch OF c12s06b03x00p03n01i03085ent IS
+  signal S1 : BIT;
+BEGIN
+  S1 <= transport '1' after 5 ns;
+  TESTING: PROCESS
+  BEGIN
+    wait on S1;
+    assert ( S1'STABLE )
+      report "***PASSED TEST: c12s06b03x00p03n01i03085"
+      severity NOTE;
+    assert NOT( S1'STABLE )
+      report "***FAILED TEST: c12s06b03x00p03n01i03085 - An event occurred on S in this simulation cycle and the current value of the signal is modified."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p03n01i03085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd
new file mode 100644
index 0000000..de2702f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3086.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b04x00p02n01i03086ent IS
+END c12s06b04x00p02n01i03086ent;
+
+ARCHITECTURE c12s06b04x00p02n01i03086arch OF c12s06b04x00p02n01i03086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable X : TIME;
+  BEGIN
+    X := NOW;
+    assert NOT( X = 0 ns )
+      report "***PASSED TEST: c12s06b04x00p02n01i03086"
+      severity NOTE;
+    assert ( X = 0 ns )
+      report "***FAILED TEST: c12s06b04x00p02n01i03086 - The time at the beginning of the simulation is not 0 ns."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b04x00p02n01i03086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd
new file mode 100644
index 0000000..0218892
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc309.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p06n01i00309ent IS
+END c03s01b04x00p06n01i00309ent;
+
+ARCHITECTURE c03s01b04x00p06n01i00309arch OF c03s01b04x00p06n01i00309ent IS
+  type R1 is range -10.0 to 10.0;
+  constant C1 : R1 := 2.0 ;
+  type R2 is range REAL'LOW to REAL'HIGH;
+  signal S1 : R1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= C1 * 2.0 after 5 ns;
+    wait for 10 ns;
+    assert NOT(S1 = 4.0)
+      report "***PASSED TEST: c03s01b04x00p06n01i00309"
+      severity NOTE;
+    assert ( S1=4.0)
+      report "***FAILED TEST: c03s01b04x00p06n01i00309 - The result of an arithmetic operation results in a value belonging to the floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p06n01i00309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd
new file mode 100644
index 0000000..e2e7c02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3099.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p09n01i03099ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p09n01i03099ent;
+
+ARCHITECTURE c05s01b00x00p09n01i03099arch OF c05s01b00x00p09n01i03099ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+
+  ATTRIBUTE attr1 OF s1,s2,s3,s4,s5,s6,s7 : SIGNAL IS 101;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT s1'attr1 = 101 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 101 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 101 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 101 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 101 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 101 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 101 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    assert NOT(    s1'attr1 = 101   and
+                   s2'attr1 = 101   and
+                   s3'attr1 = 101   and
+                   s4'attr1 = 101   and
+                   s5'attr1 = 101   and
+                   s6'attr1 = 101   and
+                   s7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p09n01i03099"
+      severity NOTE;
+    assert (    s1'attr1 = 101   and
+                s2'attr1 = 101   and
+                s3'attr1 = 101   and
+                s4'attr1 = 101   and
+                s5'attr1 = 101   and
+                s6'attr1 = 101   and
+                s7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p09n01i03099 - Attribute specification applies to the entity designators list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p09n01i03099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd
new file mode 100644
index 0000000..da82c99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd
@@ -0,0 +1,355 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc31.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00031ent IS
+END c04s03b01x01p01n01i00031ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00031arch OF c04s03b01x01p01n01i00031ent IS
+
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 1 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - without range constraint
+--
+    CONSTANT     STRING_con_1 :     STRING := "sailing";
+    CONSTANT     STRING_con_2 :     STRING := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+    CONSTANT BIT_VECTOR_con_1 : BIT_VECTOR := B"10101110";
+    CONSTANT BIT_VECTOR_con_2 : BIT_VECTOR := ( '1', '0', '1', '0', '1', '1', '1', '0');
+    CONSTANT   ut_chary_con   :   ut_chary := ( 1, 2, 3, 9, 8, 7);
+    CONSTANT    ct_word_con   :    ct_word := ( '0', '0', '0', '0', '0', '0', '0', '0',
+                                                '0', '0', '0', '0', '0', '0', '0', '0');
+    CONSTANT  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+    CONSTANT  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');    
+    CONSTANT  cst_digit_con   :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+    CONSTANT    rt_date_con   :    rt_date := (1, Jan, 1989);
+    CONSTANT   rst_date_con   :   rst_date := (1, Apr, 2000);
+    
+----------------------------------------------------------------------------------------------------------
+  BEGIN
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con(NUL) = 1 REPORT "ut_chary_con('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(SOH) = 2 REPORT "ut_chary_con('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(STX) = 3 REPORT "ut_chary_con('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(ETX) = 9 REPORT "ut_chary_con('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(EOT) = 8 REPORT "ut_chary_con('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(ENQ) = 7 REPORT "ut_chary_con('f') not properly intialized" SEVERITY FAILURE;
+    
+    FOR I IN 0 TO 15
+    LOOP
+      ASSERT ct_word_con(I) = '0' REPORT "ct_word_con(I) not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con('0') = 0 REPORT "cst_digit_con('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('1') = 1 REPORT "cst_digit_con('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('2') = 2 REPORT "cst_digit_con('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('3') = 3 REPORT "cst_digit_con('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('4') = 4 REPORT "cst_digit_con('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('5') = 5 REPORT "cst_digit_con('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('6') = 6 REPORT "cst_digit_con('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('7') = 7 REPORT "cst_digit_con('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('8') = 8 REPORT "cst_digit_con('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('9') = 9 REPORT "cst_digit_con('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rt_date_con.day   = 1    REPORT "rt_date_con.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rt_date_con.month = Jan  REPORT "rt_date_con.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rt_date_con.year  = 1989 REPORT "rt_date_con.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con.day   = 1    REPORT "rst_date_con.day   not properly intialized" SEVERITY
+      FAILURE;
+    ASSERT rst_date_con.month = Apr  REPORT "rst_date_con.month not properly intialized" SEVERITY
+      FAILURE;
+    ASSERT rst_date_con.year  = 2000 REPORT "rst_date_con.year  not properly intialized" SEVERITY
+      FAILURE;
+
+---------------------------------------------------------------------------------------------
+
+    assert NOT(     STRING_con_1(1) = 's'      and 
+                    STRING_con_1(2) = 'a'      and    
+                    STRING_con_1(3) = 'i'      and    
+                    STRING_con_1(4) = 'l'      and    
+                    STRING_con_1(5) = 'i'      and 
+                    STRING_con_1(6) = 'n'      and 
+                    STRING_con_1(7) = 'g'      and 
+                    STRING_con_2(1) = 's'      and 
+                    STRING_con_2(2) = 'a'      and 
+                    STRING_con_2(3) = 'i'      and 
+                    STRING_con_2(4) = 'l'      and 
+                    STRING_con_2(5) = 'i'      and 
+                    STRING_con_2(6) = 'n'      and 
+                    STRING_con_2(7) = 'g'      and 
+                    BIT_VECTOR_con_1(0) = '1'   and 
+                    BIT_VECTOR_con_1(1) = '0'   and 
+                    BIT_VECTOR_con_1(2) = '1'   and 
+                    BIT_VECTOR_con_1(3) = '0'   and 
+                    BIT_VECTOR_con_1(4) = '1'   and 
+                    BIT_VECTOR_con_1(5) = '1'   and 
+                    BIT_VECTOR_con_1(6) = '1'   and 
+                    BIT_VECTOR_con_1(7) = '0'   and 
+                    BIT_VECTOR_con_2(0) = '1'   and 
+                    BIT_VECTOR_con_2(1) = '0'   and 
+                    BIT_VECTOR_con_2(2) = '1'   and 
+                    BIT_VECTOR_con_2(3) = '0'   and 
+                    BIT_VECTOR_con_2(4) = '1'   and 
+                    BIT_VECTOR_con_2(5) = '1'   and 
+                    BIT_VECTOR_con_2(6) = '1'   and 
+                    BIT_VECTOR_con_2(7) = '0'   and 
+                    ut_chary_con(NUL) = 1      and 
+                    ut_chary_con(SOH) = 2      and 
+                    ut_chary_con(STX) = 3      and 
+                    ut_chary_con(ETX) = 9      and 
+                    ut_chary_con(EOT) = 8      and 
+                    ut_chary_con(ENQ) = 7      and  
+                    ct_word_con(0) = '0'      and 
+                    ct_word_con(1) = '0'      and 
+                    ct_word_con(2) = '0'      and 
+                    ct_word_con(3) = '0'      and 
+                    ct_word_con(4) = '0'      and 
+                    ct_word_con(5) = '0'      and 
+                    ct_word_con(6) = '0'      and 
+                    ct_word_con(7) = '0'      and 
+                    ct_word_con(8) = '0'      and 
+                    ct_word_con(9) = '0'      and 
+                    ct_word_con(10) = '0'      and 
+                    ct_word_con(11) = '0'      and 
+                    ct_word_con(12) = '0'      and 
+                    ct_word_con(13) = '0'      and 
+                    ct_word_con(14) = '0'      and 
+                    ct_word_con(15) = '0'      and 
+                    cst_str10_con_1(1) = 'a'   and 
+                    cst_str10_con_1(2) = 'b'   and 
+                    cst_str10_con_1(3) = 'c'   and 
+                    cst_str10_con_1(4) = 'd'   and 
+                    cst_str10_con_1(5) = 'e'   and 
+                    cst_str10_con_1(6) = 'f'   and 
+                    cst_str10_con_1(7) = 'g'   and 
+                    cst_str10_con_1(8) = 'h'   and 
+                    cst_str10_con_1(9) = 'i'   and 
+                    cst_str10_con_1(10)= 'j'   and 
+                    cst_str10_con_2(1) = 'a'   and 
+                    cst_str10_con_2(2) = 'b'   and 
+                    cst_str10_con_2(3) = 'c'   and 
+                    cst_str10_con_2(4) = 'd'   and 
+                    cst_str10_con_2(5) = 'e'   and 
+                    cst_str10_con_2(6) = 'f'   and 
+                    cst_str10_con_2(7) = 'g'   and 
+                    cst_str10_con_2(8) = 'h'   and 
+                    cst_str10_con_2(9) = 'i'   and 
+                    cst_str10_con_2(10)= 'j'   and 
+                    cst_digit_con('0') = 0      and 
+                    cst_digit_con('1') = 1      and 
+                    cst_digit_con('2') = 2      and 
+                    cst_digit_con('3') = 3      and 
+                    cst_digit_con('4') = 4      and 
+                    cst_digit_con('5') = 5      and 
+                    cst_digit_con('6') = 6      and 
+                    cst_digit_con('7') = 7      and 
+                    cst_digit_con('8') = 8      and 
+                    cst_digit_con('9') = 9      and 
+                    rt_date_con.day   = 1      and 
+                    rt_date_con.month = Jan    and 
+                    rt_date_con.year  = 1989   and 
+                    rst_date_con.day   = 1      and 
+                    rst_date_con.month = Apr    and 
+                    rst_date_con.year  = 2000   )    
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss01/p001/s010101.vhd"
+      severity NOTE;
+    assert (        STRING_con_1(1) = 's'      and 
+                    STRING_con_1(2) = 'a'      and    
+                    STRING_con_1(3) = 'i'      and    
+                    STRING_con_1(4) = 'l'      and    
+                    STRING_con_1(5) = 'i'      and 
+                    STRING_con_1(6) = 'n'      and 
+                    STRING_con_1(7) = 'g'      and 
+                    STRING_con_2(1) = 's'      and 
+                    STRING_con_2(2) = 'a'      and 
+                    STRING_con_2(3) = 'i'      and 
+                    STRING_con_2(4) = 'l'      and 
+                    STRING_con_2(5) = 'i'      and 
+                    STRING_con_2(6) = 'n'      and 
+                    STRING_con_2(7) = 'g'      and 
+                    BIT_VECTOR_con_1(0) = '1'   and 
+                    BIT_VECTOR_con_1(1) = '0'   and 
+                    BIT_VECTOR_con_1(2) = '1'   and 
+                    BIT_VECTOR_con_1(3) = '0'   and 
+                    BIT_VECTOR_con_1(4) = '1'   and 
+                    BIT_VECTOR_con_1(5) = '1'   and 
+                    BIT_VECTOR_con_1(6) = '1'   and 
+                    BIT_VECTOR_con_1(7) = '0'   and 
+                    BIT_VECTOR_con_2(0) = '1'   and 
+                    BIT_VECTOR_con_2(1) = '0'   and 
+                    BIT_VECTOR_con_2(2) = '1'   and 
+                    BIT_VECTOR_con_2(3) = '0'   and 
+                    BIT_VECTOR_con_2(4) = '1'   and 
+                    BIT_VECTOR_con_2(5) = '1'   and 
+                    BIT_VECTOR_con_2(6) = '1'   and 
+                    BIT_VECTOR_con_2(7) = '0'   and 
+                    ut_chary_con(NUL) = 1      and 
+                    ut_chary_con(SOH) = 2      and 
+                    ut_chary_con(STX) = 3      and 
+                    ut_chary_con(ETX) = 9      and 
+                    ut_chary_con(EOT) = 8      and 
+                    ut_chary_con(ENQ) = 7      and  
+                    ct_word_con(0) = '0'      and 
+                    ct_word_con(1) = '0'      and 
+                    ct_word_con(2) = '0'      and 
+                    ct_word_con(3) = '0'      and 
+                    ct_word_con(4) = '0'      and 
+                    ct_word_con(5) = '0'      and 
+                    ct_word_con(6) = '0'      and 
+                    ct_word_con(7) = '0'      and 
+                    ct_word_con(8) = '0'      and 
+                    ct_word_con(9) = '0'      and 
+                    ct_word_con(10) = '0'      and 
+                    ct_word_con(11) = '0'      and 
+                    ct_word_con(12) = '0'      and 
+                    ct_word_con(13) = '0'      and 
+                    ct_word_con(14) = '0'      and 
+                    ct_word_con(15) = '0'      and 
+                    cst_str10_con_1(1) = 'a'   and 
+                    cst_str10_con_1(2) = 'b'   and 
+                    cst_str10_con_1(3) = 'c'   and 
+                    cst_str10_con_1(4) = 'd'   and 
+                    cst_str10_con_1(5) = 'e'   and 
+                    cst_str10_con_1(6) = 'f'   and 
+                    cst_str10_con_1(7) = 'g'   and 
+                    cst_str10_con_1(8) = 'h'   and 
+                    cst_str10_con_1(9) = 'i'   and 
+                    cst_str10_con_1(10)= 'j'   and 
+                    cst_str10_con_2(1) = 'a'   and 
+                    cst_str10_con_2(2) = 'b'   and 
+                    cst_str10_con_2(3) = 'c'   and 
+                    cst_str10_con_2(4) = 'd'   and 
+                    cst_str10_con_2(5) = 'e'   and 
+                    cst_str10_con_2(6) = 'f'   and 
+                    cst_str10_con_2(7) = 'g'   and 
+                    cst_str10_con_2(8) = 'h'   and 
+                    cst_str10_con_2(9) = 'i'   and 
+                    cst_str10_con_2(10)= 'j'   and 
+                    cst_digit_con('0') = 0      and 
+                    cst_digit_con('1') = 1      and 
+                    cst_digit_con('2') = 2      and 
+                    cst_digit_con('3') = 3      and 
+                    cst_digit_con('4') = 4      and 
+                    cst_digit_con('5') = 5      and 
+                    cst_digit_con('6') = 6      and 
+                    cst_digit_con('7') = 7      and 
+                    cst_digit_con('8') = 8      and 
+                    cst_digit_con('9') = 9      and 
+                    rt_date_con.day   = 1      and 
+                    rt_date_con.month = Jan    and 
+                    rt_date_con.year  = 1989   and 
+                    rst_date_con.day   = 1      and 
+                    rst_date_con.month = Apr    and 
+                    rst_date_con.year  = 2000   )   
+      report "***FAILED TEST: c04s03b01x01p01n01i00031 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00031arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd
new file mode 100644
index 0000000..20bc82d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3100.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p10n01i03100ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p10n01i03100ent;
+
+ARCHITECTURE c05s01b00x00p10n01i03100arch OF c05s01b00x00p10n01i03100ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+  
+  CONSTANT c1,c2,c3 : BIT            :=   '0';
+  CONSTANT c4,c5    : INTEGER        :=     1;
+  CONSTANT c6,c7    : STRING(1 TO 3) := "ABC";
+  
+  ATTRIBUTE attr1 OF s3, s7 : SIGNAL IS 1;
+  ATTRIBUTE attr1 OF OTHERS : SIGNAL IS 20;
+  
+  ATTRIBUTE attr1 OF c1,c2,c3,c4,c5,c6,c7 : CONSTANT IS 101;
+  ATTRIBUTE attr1 OF OTHERS               : CONSTANT IS 20;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 01 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 01 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    
+    ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
+    ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
+    ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
+    ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
+    ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
+    ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
+    ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
+
+    assert NOT(    s1'attr1 = 20   and
+                   s2'attr1 = 20   and
+                   s3'attr1 = 01   and
+                   s4'attr1 = 20   and
+                   s5'attr1 = 20   and
+                   s6'attr1 = 20   and
+                   s7'attr1 = 01   and
+                   c1'attr1 = 101   and
+                   c2'attr1 = 101   and
+                   c3'attr1 = 101   and
+                   c4'attr1 = 101   and
+                   c5'attr1 = 101   and
+                   c6'attr1 = 101   and
+                   c7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p10n01i03100"
+      severity NOTE;
+    assert (    s1'attr1 = 20   and
+                s2'attr1 = 20   and
+                s3'attr1 = 01   and
+                s4'attr1 = 20   and
+                s5'attr1 = 20   and
+                s6'attr1 = 20   and
+                s7'attr1 = 01   and
+                c1'attr1 = 101   and
+                c2'attr1 = 101   and
+                c3'attr1 = 101   and
+                c4'attr1 = 101   and
+                c5'attr1 = 101   and
+                c6'attr1 = 101   and
+                c7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p10n01i03100 - Reserved word others in entity name list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p10n01i03100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd
new file mode 100644
index 0000000..4e1c66b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3101.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p11n01i03101ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p11n01i03101ent;
+
+ARCHITECTURE c05s01b00x00p11n01i03101arch OF c05s01b00x00p11n01i03101ent IS
+
+  FUNCTION   one  ( par1      : INTEGER ) RETURN INTEGER IS BEGIN END;
+  FUNCTION   two  ( par1      : INTEGER ) RETURN INTEGER IS BEGIN END;
+  FUNCTION   tww  ( par1,par2 : STRING  ) RETURN INTEGER IS BEGIN END;
+
+  ATTRIBUTE attr1 OF all: FUNCTION IS 99;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT  one'attr1 = 99 REPORT "ERROR: Wrong value for  one 'attr1" SEVERITY FAILURE;
+    ASSERT  two'attr1 = 99 REPORT "ERROR: Wrong value for  two 'attr1" SEVERITY FAILURE;
+    ASSERT  tww'attr1 = 99 REPORT "ERROR: Wrong value for  tww 'attr1" SEVERITY FAILURE;
+
+    assert NOT(    one'attr1    = 99   and   
+                   two'attr1    = 99   and
+                   tww'attr1    = 99   )
+      report "***PASSED TEST: c05s01b00x00p11n01i03101"
+      severity NOTE;
+    assert (    one'attr1    = 99   and   
+                two'attr1    = 99   and
+                tww'attr1    = 99   )
+      report "***FAILED TEST: c05s01b00x00p11n01i03101 - Reserved word all as attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p11n01i03101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd
new file mode 100644
index 0000000..0a32a18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3102.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p11n01i03102ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p11n01i03102ent;
+
+ARCHITECTURE c05s01b00x00p11n01i03102arch OF c05s01b00x00p11n01i03102ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+
+  CONSTANT c1,c2,c3 : BIT            :=   '0';
+  CONSTANT c4,c5    : INTEGER        :=     1;
+  CONSTANT c6,c7    : STRING(1 TO 3) := "ABC";
+
+  ATTRIBUTE attr1 OF ALL : SIGNAL IS 20;
+
+  ATTRIBUTE attr1 OF ALL : CONSTANT IS 101;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 20 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 20 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    
+    ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
+    ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
+    ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
+    ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
+    ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
+    ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
+    ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
+
+    assert NOT(    s1'attr1 = 20   and
+                   s2'attr1 = 20   and
+                   s3'attr1 = 20   and
+                   s4'attr1 = 20   and
+                   s5'attr1 = 20   and
+                   s6'attr1 = 20   and
+                   s7'attr1 = 20   and
+                   c1'attr1 = 101   and
+                   c2'attr1 = 101   and
+                   c3'attr1 = 101   and
+                   c4'attr1 = 101   and
+                   c5'attr1 = 101   and
+                   c6'attr1 = 101   and
+                   c7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p11n01i03102"
+      severity NOTE;
+    assert (    s1'attr1 = 20   and
+                s2'attr1 = 20   and
+                s3'attr1 = 20   and
+                s4'attr1 = 20   and
+                s5'attr1 = 20   and
+                s6'attr1 = 20   and
+                s7'attr1 = 20   and
+                c1'attr1 = 101   and
+                c2'attr1 = 101   and
+                c3'attr1 = 101   and
+                c4'attr1 = 101   and
+                c5'attr1 = 101   and
+                c6'attr1 = 101   and
+                c7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p11n01i03102 - Reserved work all as attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p11n01i03102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd
new file mode 100644
index 0000000..dfb5700
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3109.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p17n01i03109pkg is
+  attribute p   : POSITIVE;
+  attribute p    of c05s01b00x00p17n01i03109pkg : package is 10; --- No_Failure_here
+end c05s01b00x00p17n01i03109pkg;
+
+
+use work.c05s01b00x00p17n01i03109pkg.all;
+ENTITY c05s01b00x00p17n01i03109ent IS
+  attribute p    of c05s01b00x00p17n01i03109ent : entity is 20;   -- No_Failure_here
+END c05s01b00x00p17n01i03109ent;
+
+ARCHITECTURE c05s01b00x00p17n01i03109arch OF c05s01b00x00p17n01i03109ent IS
+  attribute p    of c05s01b00x00p17n01i03109arch : architecture is 30;  -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   c05s01b00x00p17n01i03109ent'p   = 20   and
+                  c05s01b00x00p17n01i03109arch'p = 30   )
+      report "***PASSED TEST: c05s01b00x00p17n01i03109" 
+      severity NOTE;
+    assert (   c05s01b00x00p17n01i03109ent'p   = 20   and
+               c05s01b00x00p17n01i03109arch'p = 30   )
+      report "***FAILED TEST: c05s01b00x00p17n01i03109 - Attribute specification for an attribute of a design unit test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p17n01i03109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd
new file mode 100644
index 0000000..5ce3bbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc311.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p07n01i00311ent IS
+END c03s01b04x00p07n01i00311ent;
+
+ARCHITECTURE c03s01b04x00p07n01i00311arch OF c03s01b04x00p07n01i00311ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable radius : real := +1.0E38;  -- No_failure_here
+    variable area   : real := -1.0E38;  -- No_failure_here
+  BEGIN
+    area := radius;
+    assert NOT(area = +1.0E38)
+      report "***PASSED TEST: c03s01b04x00p07n01i00311"
+      severity NOTE;
+    assert (area = +1.0E38)
+      report "***FAILED TEST: c03s01b04x00p07n01i00311 - When a real variable is declared, the value of that variable may be any value between -1E38 and +1E38, inclusive."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p07n01i00311arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd
new file mode 100644
index 0000000..ef48977
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3110.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p34n01i03110ent_a IS
+  PORT    ( Y : IN   BIT ;
+            Z : OUT   INTEGER );
+  ATTRIBUTE    A : INTEGER;
+  ATTRIBUTE    A OF Y : SIGNAL IS 1;
+END c05s01b00x00p34n01i03110ent_a;
+
+ARCHITECTURE c05s01b00x00p34n01i03110arch_a OF c05s01b00x00p34n01i03110ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+    ASSERT Y'A = 1 
+      REPORT "ERROR: Bad value for Y'A" SEVERITY FAILURE;
+    if (Y'A = 1) then
+      Z <= 100;
+    end if;
+    WAIT;
+  END PROCESS;
+END c05s01b00x00p34n01i03110arch_a;
+
+
+
+ENTITY c05s01b00x00p34n01i03110ent IS
+  ATTRIBUTE A : INTEGER;
+END c05s01b00x00p34n01i03110ent;
+
+ARCHITECTURE c05s01b00x00p34n01i03110arch OF c05s01b00x00p34n01i03110ent IS
+  COMPONENT c05s01b00x00p34n01i03110ent_a
+    PORT (    Y : IN   BIT ;
+              Z : OUT   INTEGER );
+  END COMPONENT;
+  for all : c05s01b00x00p34n01i03110ent_a use entity work.c05s01b00x00p34n01i03110ent_a(c05s01b00x00p34n01i03110arch_a); 
+
+  SIGNAL       X : BIT;
+  SIGNAL       XX: INTEGER;
+  ATTRIBUTE    A OF X : SIGNAL IS 2;
+BEGIN
+
+  inst1 : c05s01b00x00p34n01i03110ent_a PORT MAP ( Y => X , Z => XX );
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( X'A = 2 and XX = 100 )
+      report "***PASSED TEST: c05s01b00x00p34n01i03110"
+      severity NOTE;
+    assert ( X'A = 2 and XX = 100 )
+      report "***FAILED TEST: c05s01b00x00p34n01i03110 - User defined attribute represent local information only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p34n01i03110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd
new file mode 100644
index 0000000..839a0a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3111.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p06n01i03111ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p06n01i03111ent_a;
+
+ARCHITECTURE c05s02b00x00p06n01i03111arch_a OF c05s02b00x00p06n01i03111ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p06n01i03111arch_a;
+
+
+
+ENTITY c05s02b00x00p06n01i03111ent IS
+END c05s02b00x00p06n01i03111ent;
+
+ARCHITECTURE c05s02b00x00p06n01i03111arch OF c05s02b00x00p06n01i03111ent IS
+  signal       s1   : Bit := '0';
+  signal       s2   : Bit := '1';
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  for u1 : virtual use entity work.c05s02b00x00p06n01i03111ent_a (c05s02b00x00p06n01i03111arch_a);
+BEGIN
+
+  u1 : virtual
+    generic map ( true ) port map (s1, s2);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert NOT( s2 = s1 )
+      report "***PASSED TEST: c05s02b00x00p06n01i03111"
+      severity NOTE;
+    assert ( s2 = s1 )
+      report "***FAILED TEST: c05s02b00x00p06n01i03111 - Component instantiation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p06n01i03111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
new file mode 100644
index 0000000..d65f875
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3112.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p06n01i03112ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p06n01i03112ent_a;
+
+ARCHITECTURE c05s02b00x00p06n01i03112arch_a OF c05s02b00x00p06n01i03112ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p06n01i03112arch_a;
+
+
+
+ENTITY c05s02b00x00p06n01i03112ent IS
+END c05s02b00x00p06n01i03112ent;
+
+ARCHITECTURE c05s02b00x00p06n01i03112arch OF c05s02b00x00p06n01i03112ent IS
+  signal       s1   : Bit := '0';
+  signal       s2   : Bit := '1';
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+BEGIN
+
+  u1 : virtual generic map ( true ) port map (s1, s2);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert NOT( s2 = s1 )
+      report "***PASSED TEST: c05s02b00x00p06n01i03112"
+      severity NOTE;
+    assert ( s2 = s1 )
+      report "***FAILED TEST: c05s02b00x00p06n01i03112 - Component instance configuration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p06n01i03112arch;
+
+
+
+configuration c05s02b00x00p06n01i03112cfg of c05s02b00x00p06n01i03112ent is
+  for c05s02b00x00p06n01i03112arch
+    for u1 : virtual use entity work.c05s02b00x00p06n01i03112ent_a (c05s02b00x00p06n01i03112arch_a);
+    end for;
+  end for;
+end c05s02b00x00p06n01i03112cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd
new file mode 100644
index 0000000..0dbe577
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3113.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p07n01i03113ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p07n01i03113ent_a;
+
+ARCHITECTURE c05s02b00x00p07n01i03113arch_a OF c05s02b00x00p07n01i03113ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p07n01i03113arch_a;
+
+configuration c05s02b00x00p07n01i03113cfg_a of c05s02b00x00p07n01i03113ent_a is
+  for c05s02b00x00p07n01i03113arch_a
+  end for;
+end c05s02b00x00p07n01i03113cfg_a;
+
+
+
+ENTITY c05s02b00x00p07n01i03113ent IS
+END c05s02b00x00p07n01i03113ent;
+
+ARCHITECTURE c05s02b00x00p07n01i03113arch OF c05s02b00x00p07n01i03113ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+  
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b00x00p07n01i03113"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b00x00p07n01i03113 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in a configuration block."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p07n01i03113arch;
+
+
+configuration c05s02b00x00p07n01i03113cfg of c05s02b00x00p07n01i03113ent is
+  for c05s02b00x00p07n01i03113arch
+    for u1     : virtual  use entity work.c05s02b00x00p07n01i03113ent_a(c05s02b00x00p07n01i03113arch_a);
+    end for;
+    for others : virtual  use entity work.c05s02b00x00p07n01i03113ent_a(c05s02b00x00p07n01i03113arch_a);
+    end for;
+  end for;
+end c05s02b00x00p07n01i03113cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd
new file mode 100644
index 0000000..0a45d2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p07n01i03114ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p07n01i03114ent_a;
+
+ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p07n01i03114arch_a;
+
+configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
+  for c05s02b00x00p07n01i03114arch_a
+  end for;
+end c05s02b00x00p07n01i03114cfg_a;
+
+
+
+ENTITY c05s02b00x00p07n01i03114ent IS
+END c05s02b00x00p07n01i03114ent;
+
+ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  
+  for u1     : virtual  use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
+  for others : virtual  use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
+  
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+  
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b00x00p07n01i03114"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p07n01i03114arch;
+
+
+configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
+  for c05s02b00x00p07n01i03114arch
+  end for;
+end c05s02b00x00p07n01i03114cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd
new file mode 100644
index 0000000..ee2b29d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3115.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03115ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03115ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch_a OF c05s02b01x01p03n01i03115ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03115arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch_b OF c05s02b01x01p03n01i03115ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03115arch_b;
+
+
+configuration c05s02b01x01p03n01i03115cfg_a of c05s02b01x01p03n01i03115ent_a is
+  for c05s02b01x01p03n01i03115arch_a
+  end for;
+end c05s02b01x01p03n01i03115cfg_a;
+
+
+configuration c05s02b01x01p03n01i03115cfg_b of c05s02b01x01p03n01i03115ent_a is
+  for c05s02b01x01p03n01i03115arch_b
+  end for;
+end c05s02b01x01p03n01i03115cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03115ent IS
+END c05s02b01x01p03n01i03115ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch OF c05s02b01x01p03n01i03115ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 60 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03115"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03115 - Absense of an explicit architecture test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03115arch;
+
+
+configuration c05s02b01x01p03n01i03115cfg of c05s02b01x01p03n01i03115ent is
+  for c05s02b01x01p03n01i03115arch
+    for all : ic_socket use entity work.c05s02b01x01p03n01i03115ent_a; 
+    end for;
+  end for;
+end c05s02b01x01p03n01i03115cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd
new file mode 100644
index 0000000..7099358
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3116.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03116ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03116ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch_a OF c05s02b01x01p03n01i03116ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03116arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch_b OF c05s02b01x01p03n01i03116ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03116arch_b;
+
+
+configuration c05s02b01x01p03n01i03116cfg_a of c05s02b01x01p03n01i03116ent_a is
+  for c05s02b01x01p03n01i03116arch_a
+  end for;
+end c05s02b01x01p03n01i03116cfg_a;
+
+
+configuration c05s02b01x01p03n01i03116cfg_b of c05s02b01x01p03n01i03116ent_a is
+  for c05s02b01x01p03n01i03116arch_b
+  end for;
+end c05s02b01x01p03n01i03116cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03116ent IS
+END c05s02b01x01p03n01i03116ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch OF c05s02b01x01p03n01i03116ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : ic_socket use entity work.c05s02b01x01p03n01i03116ent_a; 
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 60 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03116"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03116 - Absense of an explicit architecture test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03116arch;
+
+
+configuration c05s02b01x01p03n01i03116cfg of c05s02b01x01p03n01i03116ent is
+  for c05s02b01x01p03n01i03116arch
+  end for;
+end c05s02b01x01p03n01i03116cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd
new file mode 100644
index 0000000..0ace134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3117.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03117ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03117ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch_a OF c05s02b01x01p03n01i03117ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03117arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch_b OF c05s02b01x01p03n01i03117ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03117arch_b;
+
+
+configuration c05s02b01x01p03n01i03117cfg_a of c05s02b01x01p03n01i03117ent_a is
+  for c05s02b01x01p03n01i03117arch_a
+  end for;
+end c05s02b01x01p03n01i03117cfg_a;
+
+
+configuration c05s02b01x01p03n01i03117cfg_b of c05s02b01x01p03n01i03117ent_a is
+  for c05s02b01x01p03n01i03117arch_b
+  end for;
+end c05s02b01x01p03n01i03117cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03117ent IS
+END c05s02b01x01p03n01i03117ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch OF c05s02b01x01p03n01i03117ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03117"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03117 - Entity declaration denoted by the entity name together with an architecture body binding in configuration blocks test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03117arch;
+
+
+configuration c05s02b01x01p03n01i03117cfg of c05s02b01x01p03n01i03117ent is
+  for c05s02b01x01p03n01i03117arch
+    for all : ic_socket use entity work.c05s02b01x01p03n01i03117ent_a (c05s02b01x01p03n01i03117arch_a); 
+    end for;
+  end for;
+end c05s02b01x01p03n01i03117cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd
new file mode 100644
index 0000000..d34e814
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3118.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03118ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03118ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch_a OF c05s02b01x01p03n01i03118ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03118arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch_b OF c05s02b01x01p03n01i03118ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03118arch_b;
+
+
+configuration c05s02b01x01p03n01i03118cfg_a of c05s02b01x01p03n01i03118ent_a is
+  for c05s02b01x01p03n01i03118arch_a
+  end for;
+end c05s02b01x01p03n01i03118cfg_a;
+
+
+configuration c05s02b01x01p03n01i03118cfg_b of c05s02b01x01p03n01i03118ent_a is
+  for c05s02b01x01p03n01i03118arch_b
+  end for;
+end c05s02b01x01p03n01i03118cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03118ent IS
+END c05s02b01x01p03n01i03118ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch OF c05s02b01x01p03n01i03118ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : ic_socket use entity work.c05s02b01x01p03n01i03118ent_a (c05s02b01x01p03n01i03118arch_a); 
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03118"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03118 - Entity declaration denoted by the entity name together with an architecture body binding in architecture declaration." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03118arch;
+
+
+configuration c05s02b01x01p03n01i03118cfg of c05s02b01x01p03n01i03118ent is
+  for c05s02b01x01p03n01i03118arch
+  end for;
+end c05s02b01x01p03n01i03118cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd
new file mode 100644
index 0000000..151794e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03119ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03119ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03119arch_a;
+
+configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
+  for c05s02b01x01p05n01i03119arch_a
+  end for;
+end c05s02b01x01p05n01i03119cfg_a;
+
+
+--
+
+ENTITY c05s02b01x01p05n01i03119ent IS
+END c05s02b01x01p05n01i03119ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03119"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03119arch;
+
+
+configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
+  for c05s02b01x01p05n01i03119arch
+    for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03119cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd
new file mode 100644
index 0000000..7acaec8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc312.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p07n03i00312ent IS
+END c03s01b04x00p07n03i00312ent;
+
+ARCHITECTURE c03s01b04x00p07n03i00312arch OF c03s01b04x00p07n03i00312ent IS
+  type R1 is range -10.0 to 10.0;
+  type R2 is range REAL'LOW to REAL'HIGH;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : real := 0.000001;
+    variable V2 : real := 0.000002;
+    variable V3 : real ;
+  BEGIN
+    V3 := V2 - V1;
+    assert NOT(V3 = 0.000001)
+      report "***PASSED TEST: c03s01b04x00p07n03i00312"
+      severity NOTE;
+    assert ( V3 = 0.000001 )
+      report "***FAILED TEST: c03s01b04x00p07n03i00312 -  A minimum of six digits of precision is included in the representation of floating point types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p07n03i00312arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd
new file mode 100644
index 0000000..2b10267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3120.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03120ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03120ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03120arch_a OF c05s02b01x01p05n01i03120ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03120arch_a;
+
+configuration c05s02b01x01p05n01i03120cfg_a of c05s02b01x01p05n01i03120ent_a is
+  for c05s02b01x01p05n01i03120arch_a
+  end for;
+end c05s02b01x01p05n01i03120cfg_a;
+
+
+--
+
+
+ENTITY c05s02b01x01p05n01i03120ent IS
+END c05s02b01x01p05n01i03120ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03120arch OF c05s02b01x01p05n01i03120ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : virtual use configuration work.c05s02b01x01p05n01i03120cfg_a;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03120"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03120 - Use a configuration that is fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03120arch;
+
+
+configuration c05s02b01x01p05n01i03120cfg of c05s02b01x01p05n01i03120ent is
+  for c05s02b01x01p05n01i03120arch
+  end for;
+end c05s02b01x01p05n01i03120cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd
new file mode 100644
index 0000000..bfcb2ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3121.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03121ent_aa IS
+END c05s02b01x01p05n01i03121ent_aa;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_aa OF c05s02b01x01p05n01i03121ent_aa IS
+
+BEGIN
+END c05s02b01x01p05n01i03121arch_aa;
+
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_bb OF c05s02b01x01p05n01i03121ent_aa IS
+
+BEGIN
+END c05s02b01x01p05n01i03121arch_bb;
+
+--
+
+ENTITY c05s02b01x01p05n01i03121ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03121ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_a OF c05s02b01x01p05n01i03121ent_a IS
+  component zippy
+  end component;
+BEGIN
+  u1 : zippy;
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03121arch_a;
+
+configuration c05s02b01x01p05n01i03121cfg_a of c05s02b01x01p05n01i03121ent_a is
+  for c05s02b01x01p05n01i03121arch_a
+    for u1 : zippy use entity work.c05s02b01x01p05n01i03121ent_aa;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03121cfg_a;
+
+--
+
+ENTITY c05s02b01x01p05n01i03121ent IS
+END c05s02b01x01p05n01i03121ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch OF c05s02b01x01p05n01i03121ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03121"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03121 - Use a configuration that is not fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03121arch;
+
+
+
+configuration c05s02b01x01p05n01i03121cfg of c05s02b01x01p05n01i03121ent is
+  for c05s02b01x01p05n01i03121arch
+    for all : virtual use configuration work.c05s02b01x01p05n01i03121cfg_a;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03121cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd
new file mode 100644
index 0000000..170bcf7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3122.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p07n01i03122ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p07n01i03122ent_a;
+
+ARCHITECTURE c05s02b01x01p07n01i03122arch_a OF c05s02b01x01p07n01i03122ent_a IS
+
+BEGIN
+  p2 <= p1 after 10  ns;
+END c05s02b01x01p07n01i03122arch_a;
+
+configuration c05s02b01x01p07n01i03122cfg_a of c05s02b01x01p07n01i03122ent_a is
+  for c05s02b01x01p07n01i03122arch_a
+  end for;
+end c05s02b01x01p07n01i03122cfg_a;
+
+
+--
+
+
+ENTITY c05s02b01x01p07n01i03122ent IS
+END c05s02b01x01p07n01i03122ent;
+
+ARCHITECTURE c05s02b01x01p07n01i03122arch OF c05s02b01x01p07n01i03122ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p07n01i03122"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p07n01i03122 - Explicitly OPEN entity aspects in configuration blocks test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p07n01i03122arch;
+
+configuration c05s02b01x01p07n01i03122cfg of c05s02b01x01p07n01i03122ent is
+  for c05s02b01x01p07n01i03122arch
+    for all : ic_socket use OPEN;
+    end for;
+  end for;
+end c05s02b01x01p07n01i03122cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd
new file mode 100644
index 0000000..e92e68f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3123.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p01n01i03123ent_a IS
+  generic ( socket_g1 : Boolean;
+            socket_g2 : Bit;
+            socket_g3 : character;
+            socket_g4 : severity_level;
+            socket_g5 : integer;
+            socket_g6 : real;
+            socket_g7 : time;
+            socket_g8 : natural;
+            socket_g9 : positive
+            );
+  port    ( socket_p1 : inout Boolean;
+            socket_p2 : inout Bit;
+            socket_p3 : inout character;
+            socket_p4 : inout severity_level;
+            socket_p5 : inout integer;
+            socket_p6 : inout real;
+            socket_p7 : inout time;
+            socket_p8 : inout natural;
+            socket_p9 : inout positive
+            );
+END c05s02b01x02p01n01i03123ent_a;
+
+ARCHITECTURE c05s02b01x02p01n01i03123arch_a OF c05s02b01x02p01n01i03123ent_a IS
+
+BEGIN
+  socket_p1 <= socket_g1 after 22 ns;
+  socket_p2 <= socket_g2 after 22 ns;
+  socket_p3 <= socket_g3 after 22 ns;
+  socket_p4 <= socket_g4 after 22 ns;
+  socket_p5 <= socket_g5 after 22 ns;
+  socket_p6 <= socket_g6 after 22 ns;
+  socket_p7 <= socket_g7 after 22 ns;
+  socket_p8 <= socket_g8 after 22 ns;
+  socket_p9 <= socket_g9 after 22 ns;
+END c05s02b01x02p01n01i03123arch_a;
+
+
+
+ENTITY c05s02b01x02p01n01i03123ent IS
+END c05s02b01x02p01n01i03123ent;
+
+ARCHITECTURE c05s02b01x02p01n01i03123arch OF c05s02b01x02p01n01i03123ent IS
+  component ic_socket
+    generic ( socket_g1 : Boolean;
+              socket_g2 : Bit;
+              socket_g3 : character;
+              socket_g4 : severity_level;
+              socket_g5 : integer;
+              socket_g6 : real;
+              socket_g7 : time;
+              socket_g8 : natural;
+              socket_g9 : positive
+              );
+    port    ( socket_p1 : inout Boolean;
+              socket_p2 : inout Bit;
+              socket_p3 : inout character;
+              socket_p4 : inout severity_level;
+              socket_p5 : inout integer;
+              socket_p6 : inout real;
+              socket_p7 : inout time;
+              socket_p8 : inout natural;
+              socket_p9 : inout positive
+              );
+  end component;
+  signal socket_p1 :  Boolean;
+  signal socket_p2 :  Bit;
+  signal socket_p3 :  character;
+  signal socket_p4 :  severity_level;
+  signal socket_p5 :  integer;
+  signal socket_p6 :  real;
+  signal socket_p7 :  time;
+  signal socket_p8 :  natural;
+  signal socket_p9 :  positive;
+BEGIN
+  instance : ic_socket
+    generic map ( true,
+                  '1',
+                  '$',
+                  warning,
+                  -100002,
+                  -9.999,
+                  20 ns,
+                  23423,
+                  4564576
+                  )
+    port map    ( socket_p1,
+                  socket_p2,
+                  socket_p3,
+                  socket_p4,
+                  socket_p5,
+                  socket_p6,
+                  socket_p7,
+                  socket_p8,
+                  socket_p9
+                  );
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    socket_p1 = true   and
+                   socket_p2 = '1'      and
+                   socket_p3 = '$'      and
+                   socket_p4 = warning   and
+                   socket_p5 = -100002   and
+                   socket_p6 = -9.999   and
+                   socket_p7 = 20 ns   and
+                   socket_p8 = 23423   and
+                   socket_p9 = 4564576   )
+      report "***PASSED TEST: c05s02b01x02p01n01i03123"
+      severity NOTE;
+    assert (    socket_p1 = true   and
+                socket_p2 = '1'      and
+                socket_p3 = '$'      and
+                socket_p4 = warning   and
+                socket_p5 = -100002   and
+                socket_p6 = -9.999   and
+                socket_p7 = 20 ns   and
+                socket_p8 = 23423   and
+                socket_p9 = 4564576   )
+      report "***FAILED TEST: c05s02b01x02p01n01i03123 - Positional association generic and port list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x02p01n01i03123arch;
+
+
+
+
+configuration c05s02b01x02p01n01i03123cfg of c05s02b01x02p01n01i03123ent is
+  for c05s02b01x02p01n01i03123arch
+    for instance : ic_socket use entity work.c05s02b01x02p01n01i03123ent_a (c05s02b01x02p01n01i03123arch_a)
+                               generic map (    socket_g1,
+                                                socket_g2,
+                                                socket_g3,
+                                                socket_g4,
+                                                socket_g5,
+                                                socket_g6,
+                                                socket_g7,
+                                                socket_g8,
+                                                socket_g9
+                                                )
+                               port map    ( socket_p1,
+                                             socket_p2,
+                                             socket_p3,
+                                             socket_p4,
+                                             socket_p5,
+                                             socket_p6,
+                                             socket_p7,
+                                             socket_p8,
+                                             socket_p9
+                                             );
+    end for;
+  end for;
+end c05s02b01x02p01n01i03123cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd
new file mode 100644
index 0000000..7d4df7f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3125.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p08n01i03125ent_a IS
+  generic ( message : string );
+END c05s02b01x02p08n01i03125ent_a;
+
+ARCHITECTURE c05s02b01x02p08n01i03125arch_a OF c05s02b01x02p08n01i03125ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( message = "Hello there..." )
+      report "***PASSED TEST: c05s02b01x02p08n01i03125"
+      severity NOTE;
+    assert ( message = "Hello there..." )
+      report "***FAILED TEST: c05s02b01x02p08n01i03125 - Generic maps work does not work properly with unconstrained generic elements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p08n01i03125arch_a;
+
+
+
+ENTITY c05s02b01x02p08n01i03125ent IS
+END c05s02b01x02p08n01i03125ent;
+
+ARCHITECTURE c05s02b01x02p08n01i03125arch OF c05s02b01x02p08n01i03125ent IS
+  component ic_socket
+    generic ( message : string );
+  end component;
+BEGIN
+  u1 : ic_socket generic map ("Hello there...");
+
+END c05s02b01x02p08n01i03125arch;
+
+
+configuration c05s02b01x02p08n01i03125cfg of c05s02b01x02p08n01i03125ent is
+  for c05s02b01x02p08n01i03125arch
+    for u1 : ic_socket use entity work.c05s02b01x02p08n01i03125ent_a(c05s02b01x02p08n01i03125arch_a);
+    end for;
+  end for;
+end c05s02b01x02p08n01i03125cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd
new file mode 100644
index 0000000..310d018
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3126.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03126ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03126ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03126arch_a OF c05s02b01x02p12n01i03126ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03126"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03126 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03126arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03126ent IS
+END c05s02b01x02p12n01i03126ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03126arch OF c05s02b01x02p12n01i03126ent IS
+  component ic_socket
+    generic ( g1 : integer := 2 );
+  end component;
+  for instance : ic_socket use entity work.c05s02b01x02p12n01i03126ent_a (c05s02b01x02p12n01i03126arch_a)
+    generic map ( g1 => g1 + g1 );
+BEGIN
+
+  instance : ic_socket ;
+
+END c05s02b01x02p12n01i03126arch;
+
+
+configuration c05s02b01x02p12n01i03126cfg of c05s02b01x02p12n01i03126ent is
+  for c05s02b01x02p12n01i03126arch
+  end for;
+end c05s02b01x02p12n01i03126cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd
new file mode 100644
index 0000000..ddf9399
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3127.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03127ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03127ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03127arch_a OF c05s02b01x02p12n01i03127ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03127"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03127 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03127arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03127ent IS
+END c05s02b01x02p12n01i03127ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03127arch OF c05s02b01x02p12n01i03127ent IS
+  component ic_socket
+    generic ( g1 : integer := 2 );
+  end component;
+BEGIN
+
+  instance : ic_socket ;
+
+END c05s02b01x02p12n01i03127arch;
+
+
+configuration c05s02b01x02p12n01i03127_cfg of c05s02b01x02p12n01i03127ent is
+  for c05s02b01x02p12n01i03127arch
+    -- takes local generic and associates it to the formal.
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03127ent_a(c05s02b01x02p12n01i03127arch_a)
+                               generic map (g1 => g1 + g1 );
+    end for;
+  end for;
+end c05s02b01x02p12n01i03127_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd
new file mode 100644
index 0000000..e042f45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3128.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03128ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03128ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03128arch_a OF c05s02b01x02p12n01i03128ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03128"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03128 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03128arch_a;
+
+
+
+ENTITY c05s02b01x02p12n01i03128ent IS
+END c05s02b01x02p12n01i03128ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03128arch OF c05s02b01x02p12n01i03128ent IS
+
+BEGIN
+  labeled : block
+    component ic_socket
+      generic ( g1 : integer := 2 );
+    end component;
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03128ent_a (c05s02b01x02p12n01i03128arch_a)
+      generic map ( g1 => g1 + g1 );
+  begin
+    instance : ic_socket ;
+  end block;
+
+END c05s02b01x02p12n01i03128arch;
+
+
+configuration c05s02b01x02p12n01i03128cfg of c05s02b01x02p12n01i03128ent is
+  for c05s02b01x02p12n01i03128arch
+  end for;
+end c05s02b01x02p12n01i03128cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd
new file mode 100644
index 0000000..38d0c6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x01p01n02i00313ent IS
+END c03s01b04x01p01n02i00313ent;
+
+ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
+  constant C1 : REAL := -1.0E38 ;
+  constant C2 : REAL := +1.0E38 ;
+BEGIN
+  TESTING: PROCESS
+    variable k1 : real;
+    variable k2 : real;
+  BEGIN
+    k1 := C1;
+    k2 := C2;
+    assert NOT(k1=C1 and k2=C2)
+      report "***PASSED TEST: c03s01b04x01p01n02i00313"
+      severity NOTE;
+    assert (k1=C1 and k2=C2)
+      report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x01p01n02i00313arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd
new file mode 100644
index 0000000..ee996fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3137.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03137ent IS
+END c05s02b02x00p02n01i03137ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03137arch OF c05s02b02x00p02n01i03137ent IS
+  component c05s02b02x00p02n01i03137ent_a
+  end component;
+BEGIN
+
+  comp1 : c05s02b02x00p02n01i03137ent_a;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p02n01i03137"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p02n01i03137arch;
+
+
+configuration c05s02b02x00p02n01i03137cfg of c05s02b02x00p02n01i03137ent is
+  for c05s02b02x00p02n01i03137arch
+    for comp1 : c05s02b02x00p02n01i03137ent_a use OPEN;
+    end for;
+  end for;
+end c05s02b02x00p02n01i03137cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd
new file mode 100644
index 0000000..3eabe09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3138.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03138ent IS
+END c05s02b02x00p02n01i03138ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03138arch OF c05s02b02x00p02n01i03138ent IS
+  component c05s02b02x00p02n01i03138ent_a
+  end component;
+  for comp1 : c05s02b02x00p02n01i03138ent_a use OPEN;
+BEGIN
+
+  comp1 : c05s02b02x00p02n01i03138ent_a;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p02n01i03138"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p02n01i03138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd
new file mode 100644
index 0000000..24c7c8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3139.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03139ent IS
+END c05s02b02x00p02n01i03139ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03139arch OF c05s02b02x00p02n01i03139ent IS
+
+begin
+  l : block
+    component c05s02b02x00p02n01i03139ent_a
+    end component;
+    for comp1 : c05s02b02x00p02n01i03139ent_a use OPEN;
+  BEGIN
+
+    comp1 : c05s02b02x00p02n01i03139ent_a;
+
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***PASSED TEST: c05s02b02x00p02n01i03139"
+        severity NOTE;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c05s02b02x00p02n01i03139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd
new file mode 100644
index 0000000..be9f05d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc314.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x01p01n03i00314ent IS
+END c03s01b04x01p01n03i00314ent;
+
+ARCHITECTURE c03s01b04x01p01n03i00314arch OF c03s01b04x01p01n03i00314ent IS
+  subtype T1 is REAL range 1.0 to 10.0 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(T1'LEFT < T1'RIGHT)
+      report "***PASSED TEST: c03s01b04x01p01n03i00314"
+      severity NOTE;
+    assert (T1'LEFT < T1'RIGHT)
+      report "***FAILED TEST: c03s01b04x01p01n03i00314 - The range of REAL is defined with an ascending range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x01p01n03i00314arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd
new file mode 100644
index 0000000..916440b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3140.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03140ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03140ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03140arch_a OF c05s02b02x00p10n01i03140ent_a IS
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03140"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03140 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03140arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03140ent IS
+END c05s02b02x00p10n01i03140ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03140arch OF c05s02b02x00p10n01i03140ent IS
+  component c05s02b02x00p10n01i03140ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p10n01i03140ent_a;
+
+END c05s02b02x00p10n01i03140arch;
+
+
+configuration c05s02b02x00p10n01i03140cfg of c05s02b02x00p10n01i03140ent is
+  for c05s02b02x00p10n01i03140arch
+    for comp1 : c05s02b02x00p10n01i03140ent_a use entity work.c05s02b02x00p10n01i03140ent_a(c05s02b02x00p10n01i03140arch_a);
+    end for;
+  end for;
+end c05s02b02x00p10n01i03140cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd
new file mode 100644
index 0000000..aa5f218
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3141.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03141ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03141ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03141arch_a OF c05s02b02x00p10n01i03141ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03141"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03141 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03141arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03141ent IS
+END c05s02b02x00p10n01i03141ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03141arch OF c05s02b02x00p10n01i03141ent IS
+  component c05s02b02x00p10n01i03141ent_a
+  end component;
+  for comp1 : c05s02b02x00p10n01i03141ent_a use entity work.c05s02b02x00p10n01i03141ent_a(c05s02b02x00p10n01i03141arch_a);
+BEGIN
+  comp1 : c05s02b02x00p10n01i03141ent_a;
+
+END c05s02b02x00p10n01i03141arch;
+
+
+configuration c05s02b02x00p10n01i03141_cfg of c05s02b02x00p10n01i03141ent is
+  for c05s02b02x00p10n01i03141arch
+  end for;
+end c05s02b02x00p10n01i03141_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd
new file mode 100644
index 0000000..310d4da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3142.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03142ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03142ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03142arch_a OF c05s02b02x00p10n01i03142ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03142"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03142 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03142arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03142ent IS
+END c05s02b02x00p10n01i03142ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03142arch OF c05s02b02x00p10n01i03142ent IS
+
+begin
+  l : block
+    component c05s02b02x00p10n01i03142ent_a
+    end component;
+    for comp1 : c05s02b02x00p10n01i03142ent_a use entity work.c05s02b02x00p10n01i03142ent_a(c05s02b02x00p10n01i03142arch_a);
+  BEGIN
+    comp1 : c05s02b02x00p10n01i03142ent_a;
+  end block;
+
+END c05s02b02x00p10n01i03142arch;
+
+
+configuration c05s02b02x00p10n01i03142cfg of c05s02b02x00p10n01i03142ent is
+  for c05s02b02x00p10n01i03142arch
+  end for;
+end c05s02b02x00p10n01i03142cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd
new file mode 100644
index 0000000..674f1bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3143.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03143ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03143ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03143arch_a OF c05s02b02x00p10n01i03143ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03143"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03143 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03143arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03143ent IS
+END c05s02b02x00p10n01i03143ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03143arch OF c05s02b02x00p10n01i03143ent IS
+  component c05s02b02x00p10n01i03143ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p10n01i03143ent_a;
+END c05s02b02x00p10n01i03143arch;
+
+
+configuration c05s02b02x00p10n01i03143cfg of c05s02b02x00p10n01i03143ent is
+  for c05s02b02x00p10n01i03143arch
+    for comp1 : c05s02b02x00p10n01i03143ent_a use entity work.c05s02b02x00p10n01i03143ent_a(c05s02b02x00p10n01i03143arch_a)
+                                                generic map(OPEN);
+    end for;
+  end for;
+end c05s02b02x00p10n01i03143cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd
new file mode 100644
index 0000000..fc6ac39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3144.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03144ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03144ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03144arch_a OF c05s02b02x00p10n01i03144ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03144"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03144 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03144arch_a;
+
+--
+
+ENTITY c05s02b02x00p10n01i03144ent IS
+END c05s02b02x00p10n01i03144ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03144arch OF c05s02b02x00p10n01i03144ent IS
+  component c05s02b02x00p10n01i03144ent_a
+  end component;
+  for comp1 : c05s02b02x00p10n01i03144ent_a use entity work.c05s02b02x00p10n01i03144ent_a(c05s02b02x00p10n01i03144arch_a)
+    generic map(OPEN);
+BEGIN
+  comp1 : c05s02b02x00p10n01i03144ent_a;
+END c05s02b02x00p10n01i03144arch;
+
+
+configuration c05s02b02x00p10n01i03144cfg of c05s02b02x00p10n01i03144ent is
+  for c05s02b02x00p10n01i03144arch
+  end for;
+end c05s02b02x00p10n01i03144cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd
new file mode 100644
index 0000000..f4ce821
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3145.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03145ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03145ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03145arch_a OF c05s02b02x00p10n01i03145ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03145"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03145 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03145arch_a;
+
+--
+
+ENTITY c05s02b02x00p10n01i03145ent IS
+END c05s02b02x00p10n01i03145ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03145arch OF c05s02b02x00p10n01i03145ent IS
+begin
+  l : block
+    component c05s02b02x00p10n01i03145ent_a
+    end component;
+    for comp1 : c05s02b02x00p10n01i03145ent_a use entity work.c05s02b02x00p10n01i03145ent_a(c05s02b02x00p10n01i03145arch_a)
+      generic map(OPEN);
+  BEGIN
+    comp1 : c05s02b02x00p10n01i03145ent_a;
+  end block;
+END c05s02b02x00p10n01i03145arch;
+
+
+configuration c05s02b02x00p10n01i03145cfg of c05s02b02x00p10n01i03145ent is
+  for c05s02b02x00p10n01i03145arch
+  end for;
+end c05s02b02x00p10n01i03145cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd
new file mode 100644
index 0000000..cb81136
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3146.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03146ent_a IS
+END c05s02b02x00p08n01i03146ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03146arch_a OF c05s02b02x00p08n01i03146ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03146 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03146arch_a;
+
+
+--most recently analyzed ...
+ARCHITECTURE c05s02b02x00p08n01i03146arch_b OF c05s02b02x00p08n01i03146ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03146"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03146arch_b;
+
+
+--
+
+ENTITY c05s02b02x00p08n01i03146ent IS
+END c05s02b02x00p08n01i03146ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03146arch OF c05s02b02x00p08n01i03146ent IS
+  component c05s02b02x00p08n01i03146ent_c
+  end component;
+  for comp1 : c05s02b02x00p08n01i03146ent_c use entity work.c05s02b02x00p08n01i03146ent_a;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03146ent_c;
+END c05s02b02x00p08n01i03146arch;
+
+
+
+
+configuration c05s02b02x00p08n01i03146cfg of c05s02b02x00p08n01i03146ent is
+  for c05s02b02x00p08n01i03146arch
+  end for;
+end c05s02b02x00p08n01i03146cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd
new file mode 100644
index 0000000..00b7b2d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03147ent_a IS
+END c05s02b02x00p08n01i03147ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03147arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03147"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03147arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03147ent IS
+END c05s02b02x00p08n01i03147ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
+  component c05s02b02x00p08n01i03147ent_c
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03147ent_c;
+END c05s02b02x00p08n01i03147arch;
+
+
+
+configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
+  for c05s02b02x00p08n01i03147arch
+    for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03147cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd
new file mode 100644
index 0000000..c950077
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3148.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03148ent_a IS
+END c05s02b02x00p08n01i03148ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03148arch_a OF c05s02b02x00p08n01i03148ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03148 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03148arch_a;
+
+
+--most recently analyzed ...
+ARCHITECTURE c05s02b02x00p08n01i03148arch_b OF c05s02b02x00p08n01i03148ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03148"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03148arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03148ent IS
+END c05s02b02x00p08n01i03148ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03148arch OF c05s02b02x00p08n01i03148ent IS
+
+begin
+  blk : block
+    component c05s02b02x00p08n01i03148ent_c
+    end component;
+    for comp1 : c05s02b02x00p08n01i03148ent_c use entity work.c05s02b02x00p08n01i03148ent_a;
+  BEGIN
+    comp1 : c05s02b02x00p08n01i03148ent_c;
+  end block;
+
+END c05s02b02x00p08n01i03148arch;
+
+
+configuration c05s02b02x00p08n01i03148_cfg of c05s02b02x00p08n01i03148ent is
+  for c05s02b02x00p08n01i03148arch
+  end for;
+end c05s02b02x00p08n01i03148_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd
new file mode 100644
index 0000000..5c9b660
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3149.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03149ent_a IS
+END c05s02b02x00p08n01i03149ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch_a OF c05s02b02x00p08n01i03149ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03149 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03149arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch_b OF c05s02b02x00p08n01i03149ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03149"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03149arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03149ent IS
+END c05s02b02x00p08n01i03149ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch OF c05s02b02x00p08n01i03149ent IS
+  component c05s02b02x00p08n01i03149ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03149ent_a;
+
+END c05s02b02x00p08n01i03149arch;
+
+
+configuration c05s02b02x00p08n01i03149cfg of c05s02b02x00p08n01i03149ent is
+  for c05s02b02x00p08n01i03149arch
+    for comp1 : c05s02b02x00p08n01i03149ent_a use entity work.c05s02b02x00p08n01i03149ent_a(c05s02b02x00p08n01i03149arch_b);
+    end for;
+  end for;
+end c05s02b02x00p08n01i03149cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd
new file mode 100644
index 0000000..56f1a62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3150.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03150ent_a IS
+END c05s02b02x00p08n01i03150ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_a OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_a;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_c OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_c;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_b OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03150"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_b;
+
+--
+
+ENTITY c05s02b02x00p08n01i03150ent IS
+END c05s02b02x00p08n01i03150ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch OF c05s02b02x00p08n01i03150ent IS
+  component c05s02b02x00p08n01i03150ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03150ent_a;
+
+END c05s02b02x00p08n01i03150arch;
+
+
+
+configuration c05s02b02x00p08n01i03150cfg of c05s02b02x00p08n01i03150ent is
+  for c05s02b02x00p08n01i03150arch
+    for comp1 : c05s02b02x00p08n01i03150ent_a use entity work.c05s02b02x00p08n01i03150ent_a;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03150cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd
new file mode 100644
index 0000000..18189fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3151.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03151ent_a IS
+END c05s02b02x00p08n01i03151ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_a OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_a;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_c OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_c;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_b OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03151"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_b;
+
+--
+
+ENTITY c05s02b02x00p08n01i03151ent IS
+END c05s02b02x00p08n01i03151ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch OF c05s02b02x00p08n01i03151ent IS
+  component c05s02b02x00p08n01i03151ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03151ent_a;
+
+END c05s02b02x00p08n01i03151arch;
+
+
+
+configuration c05s02b02x00p08n01i03151cfg of c05s02b02x00p08n01i03151ent is
+  for c05s02b02x00p08n01i03151arch
+  end for;
+end c05s02b02x00p08n01i03151cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd
new file mode 100644
index 0000000..72ff2d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3152.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03152ent_a IS
+END c05s02b02x00p08n01i03152ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_a OF c05s02b02x00p08n01i03152ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03152 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_b OF c05s02b02x00p08n01i03152ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03152 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_b;
+
+
+
+ENTITY c05s02b02x00p08n01i03152ent_c IS
+END c05s02b02x00p08n01i03152ent_c;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_c OF c05s02b02x00p08n01i03152ent_c IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03152"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_c;
+
+
+
+ENTITY c05s02b02x00p08n01i03152ent IS
+END c05s02b02x00p08n01i03152ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch OF c05s02b02x00p08n01i03152ent IS
+  component c05s02b02x00p08n01i03152ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03152ent_a;
+
+END c05s02b02x00p08n01i03152arch;
+
+
+
+configuration c05s02b02x00p08n01i03152cfg of c05s02b02x00p08n01i03152ent is
+  for c05s02b02x00p08n01i03152arch
+    for comp1 : c05s02b02x00p08n01i03152ent_a use entity work.c05s02b02x00p08n01i03152ent_c;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03152cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd
new file mode 100644
index 0000000..5d6118c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3153.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03153ent IS
+END c05s03b00x00p01n01i03153ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03153arch OF c05s03b00x00p01n01i03153ent IS
+
+begin
+--Enclose the whole schematic in a block
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+    
+    -- Define the signal.
+    subtype    RBIT    is RESFUNC BIT;
+    signal       SIG    : RBIT bus;
+    
+    -- Define the disconnect specification.
+    disconnect    SIG    : RBIT after 0 ns;
+    
+    -- Define the GUARD signal.
+    signal    GUARD    : BOOLEAN := FALSE;
+  BEGIN
+    -- Define the guarded signal assignment.
+    L1: block
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+    TESTING: PROCESS
+      variable    pass : integer := 0;
+    BEGIN
+
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      wait on SIG;
+      assert( SIG = '1' );
+      if ( SIG = '1' ) then
+        pass := pass + 1;
+      end if;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      wait on SIG;
+      assert( SIG = '0' );
+      if ( SIG = '0' ) then
+        pass := pass + 1;
+      end if;
+
+      wait for 50 ns; 
+      assert NOT( pass = 2 )
+        report "***PASSED TEST: c05s03b00x00p01n01i03153"
+        severity NOTE;
+      assert ( pass = 2 )
+        report "***FAILED TEST: c05s03b00x00p01n01i03153 - Disconnect in block statement does not work properly."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p01n01i03153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd
new file mode 100644
index 0000000..3ca724b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03154ent IS
+END c05s03b00x00p01n01i03154ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
+  -- Define res function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+  
+  -- Define the signal.
+  subtype    RBIT    is RESFUNC BIT;
+  signal    SIG    : RBIT bus;
+  
+  -- Define the disconnect specification.
+  disconnect    SIG    : RBIT after 0 ns;
+  
+  -- Define the GUARD signal.
+  signal    GUARD    : BOOLEAN := FALSE;
+BEGIN
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+  TESTING: PROCESS
+    variable    pass : integer := 0;
+  BEGIN
+
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    wait on SIG;
+    assert( SIG = '1' );
+    if ( SIG = '1' ) then
+      pass := pass + 1;
+    end if;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    wait on SIG;
+    assert( SIG = '0' );
+    if ( SIG = '0' ) then
+      pass := pass + 1;
+    end if;
+
+    wait for 50 ns; 
+    assert NOT( pass = 2 )
+      report "***PASSED TEST: c05s03b00x00p01n01i03154"
+      severity NOTE;
+    assert ( pass = 2 )
+      report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p01n01i03154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd
new file mode 100644
index 0000000..3e2cdb8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03155ent IS
+END c05s03b00x00p01n01i03155ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS
+
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+  
+  -- Define the signal.
+  subtype    RBIT    is RESFUNC BIT;
+  signal       SIG    : RBIT bus;
+  
+  -- Define the disconnect specification.
+  disconnect    SIG    : RBIT after 0 ns;
+  
+  -- Define the GUARD signal.
+  signal    GUARD    : BOOLEAN := FALSE;
+BEGIN
+  -- Define the guarded signal assignment.
+  L1: block( GUARD = TRUE )
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+  TESTING: PROCESS
+    variable    pass : integer := 0;
+  BEGIN
+
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    wait on SIG;
+    assert( SIG = '1' );
+    if ( SIG = '1' ) then
+      pass := pass + 1;
+    end if;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    wait on SIG;
+    assert( SIG = '0' );
+    if ( SIG = '0' ) then
+      pass := pass + 1;
+    end if;
+
+    wait for 50 ns; 
+    assert NOT( pass = 2 )
+      report "***PASSED TEST: c05s03b00x00p01n01i03155"
+      severity NOTE;
+    assert ( pass = 2 )
+      report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p01n01i03155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd
new file mode 100644
index 0000000..ddb3854
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3156.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03156ent IS
+END c05s03b00x00p01n01i03156ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03156arch OF c05s03b00x00p01n01i03156ent IS
+
+begin
+--Enclose the whole schematic in a block.
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+    
+    -- Define the signal.
+    subtype    RBIT    is RESFUNC BIT;
+    signal       SIG    : RBIT bus;
+    
+    -- Define the disconnect specification.
+    disconnect    SIG    : RBIT after 0 ns;
+    
+    -- Define the GUARD signal.
+    signal    GUARD    : BOOLEAN := FALSE;
+  BEGIN
+    -- Define the guarded signal assignment.
+    L1: block( GUARD = TRUE )
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+    TESTING: PROCESS
+      variable    pass : integer := 0;
+    BEGIN
+
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      wait on SIG;
+      assert( SIG = '1' );
+      if ( SIG = '1' ) then
+        pass := pass + 1;
+      end if;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      wait on SIG;
+      assert( SIG = '0' );
+      if ( SIG = '0' ) then
+        pass := pass + 1;
+      end if;
+
+      wait for 50 ns; 
+      assert NOT( pass = 2 )
+        report "***PASSED TEST: c05s03b00x00p01n01i03156"
+        severity NOTE;
+      assert ( pass = 2 )
+        report "***FAILED TEST: c05s03b00x00p01n01i03156 - Disconnect in block statement does not work properly."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p01n01i03156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd
new file mode 100644
index 0000000..ccd9ede
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3157.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03157ent IS
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+
+  -- Define the signal.
+  subtype RBIT is RESFUNC BIT;
+  signal SIG : RBIT bus;
+
+  -- Use the implicit disconnect specification here.
+
+  -- Define the GUARD signal.
+  signal GUARD : BOOLEAN := FALSE;
+begin
+END c05s03b00x00p16n01i03157ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03157arch OF c05s03b00x00p16n01i03157ent IS
+
+BEGIN
+
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '1' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '0' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+
+    assert NOT( SIG = '0' and ShouldBeTime = NOW )
+      report "***PASSED TEST: c05s03b00x00p16n01i03157"
+      severity NOTE;
+    assert ( SIG = '0' and ShouldBeTime = NOW )
+      report "***FAILED TEST: c05s03b00x00p16n01i03157 - Default disconnect specification test failed."
+      severity ERROR;
+    
+    -- Define a second driver for SIG, just for kicks.
+    -- Should never get invoked.  Not have an effect on the value.
+    SIG <= '0' after 10 ns;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p16n01i03157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd
new file mode 100644
index 0000000..458e092
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3158.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03158ent IS
+END c05s03b00x00p16n01i03158ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03158arch OF c05s03b00x00p16n01i03158ent IS
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+
+  -- Define the signal.
+  subtype RBIT is RESFUNC BIT;
+  signal SIG : RBIT bus;
+
+  -- Use the implicit disconnect specification here.
+
+  -- Define the GUARD signal.
+  signal GUARD : BOOLEAN := FALSE;
+BEGIN
+
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '1' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '0' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+
+    assert NOT( SIG = '0' and ShouldBeTime = NOW )
+      report "***PASSED TEST: c05s03b00x00p16n01i03158"
+      severity NOTE;
+    assert ( SIG = '0' and ShouldBeTime = NOW )
+      report "***FAILED TEST: c05s03b00x00p16n01i03158 - Default disconnect specification test failed."
+      severity ERROR;
+    
+    -- Define a second driver for SIG, just for kicks.
+    -- Should never get invoked.  Not have an effect on the value.
+    SIG <= '0' after 10 ns;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p16n01i03158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd
new file mode 100644
index 0000000..3aca948
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3159.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03159ent IS
+END c05s03b00x00p16n01i03159ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03159arch OF c05s03b00x00p16n01i03159ent IS
+
+begin
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+
+    -- Define the signal.
+    subtype RBIT is RESFUNC BIT;
+    signal SIG : RBIT bus;
+
+    -- Use the implicit disconnect specification here.
+
+    -- Define the GUARD signal.
+    signal GUARD : BOOLEAN := FALSE;
+  BEGIN
+
+    -- Define the guarded signal assignment.
+    L1: block
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+
+    TESTING: PROCESS
+      variable ShouldBeTime : TIME;
+    BEGIN
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      ShouldBeTime := NOW;
+      wait on SIG;
+      assert( SIG = '1' ) severity FAILURE;
+      assert( ShouldBeTime = NOW ) severity FAILURE;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      ShouldBeTime := NOW;
+      wait on SIG;
+      assert( SIG = '0' ) severity FAILURE;
+      assert( ShouldBeTime = NOW ) severity FAILURE;
+
+      assert NOT( SIG = '0' and ShouldBeTime = NOW )
+        report "***PASSED TEST: c05s03b00x00p16n01i03159"
+        severity NOTE;
+      assert ( SIG = '0' and ShouldBeTime = NOW )
+        report "***FAILED TEST: c05s03b00x00p16n01i03159 - Default disconnect specification test failed."
+        severity ERROR;
+      
+      -- Define a second driver for SIG, just for kicks.
+      -- Should never get invoked.  Not have an effect on the value.
+      SIG <= '0' after 10 ns;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p16n01i03159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd
new file mode 100644
index 0000000..ecfacad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3160.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p166n01i03160ent IS
+END c14s01b00x00p166n01i03160ent;
+
+ARCHITECTURE c14s01b00x00p166n01i03160arch OF c14s01b00x00p166n01i03160ent IS
+  signal clk : BIT:= '0';
+BEGIN
+
+  clk <= '1' after 10 ns;
+
+  TESTING: PROCESS(clk)
+  BEGIN
+    if (NOW > 1 ns) then
+      assert NOT( clk'EVENT and NOW = 10 ns )
+        report "***PASSED TEST: c14s01b00x00p166n01i03160"
+        severity NOTE;
+      assert ( clk'EVENT and NOW = 10 ns )
+        report "***FAILED TEST: c14s01b00x00p166n01i03160 - Attribute EVENT test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c14s01b00x00p166n01i03160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd
new file mode 100644
index 0000000..a28b0ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3162.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p07n01i03162ent IS
+END c14s01b00x00p07n01i03162ent;
+
+ARCHITECTURE c14s01b00x00p07n01i03162arch OF c14s01b00x00p07n01i03162ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    subtype BTRUE    is BOOLEAN range TRUE to TRUE;
+    subtype ST    is INTEGER range -5 to 20;
+
+    type E is (A,B,C,D);
+    type P is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+
+  BEGIN
+    wait for 5 ns;
+    assert NOT(       (E'BASE'LEFT   =E'LEFT)
+                      and    (REAL'BASE'HIGH   =REAL'HIGH)
+                      and    (E'BASE'POS(C)   =E'POS(C))
+                      and    (ST'BASE'VAL(1)   =INTEGER'VAL(1))
+                      and    (INTEGER'BASE'PRED(1)   =INTEGER'PRED(1))
+                      and    (P'BASE'SUCC(2 Y)   =P'SUCC(2 Y)))
+      report "***PASSED TEST: /src/ch14/sc01/p007/s010101.vhd"
+      severity NOTE;
+    assert (       (E'BASE'LEFT   =E'LEFT)
+                   and    (REAL'BASE'HIGH   =REAL'HIGH)
+                   and    (E'BASE'POS(C)   =E'POS(C))
+                   and    (ST'BASE'VAL(1)   =INTEGER'VAL(1))
+                   and    (INTEGER'BASE'PRED(1)   =INTEGER'PRED(1))
+                   and    (P'BASE'SUCC(2 Y)   =P'SUCC(2 Y)))
+      report "***FAILED TEST: c14s01b00x00p07n01i03162 - Result of T'BASE must be same as the base type of T."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p07n01i03162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd
new file mode 100644
index 0000000..b8c9fbf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3163.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03163ent IS
+END c14s01b00x00p12n01i03163ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03163arch OF c14s01b00x00p12n01i03163ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'left = 0    and
+                   roufbit'left = 15   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03163"
+      severity NOTE;
+    assert (    fourbit'left = 0    and
+                roufbit'left = 15   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03163 - Predefined attribute LEFT for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd
new file mode 100644
index 0000000..7ff3b5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3164.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03164ent IS
+END c14s01b00x00p12n01i03164ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03164arch OF c14s01b00x00p12n01i03164ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'left = red )
+      report "***PASSED TEST: c14s01b00x00p12n01i03164"
+      severity NOTE;
+    assert ( color'left = red )
+      report "***FAILED TEST: c14s01b00x00p12n01i03164 - Predefined attribute LEFT for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
new file mode 100644
index 0000000..9260ddc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03165ent IS
+END c14s01b00x00p12n01i03165ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+  subtype xyz is real range 20.0 to 0.0;
+  subtype zyx is real range 0.0 downto 20.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    abc'left = 0.0   and
+                   cba'left = 20.0   and
+                   xyz'left = 20.0   and
+                   zyx'left = 0.0   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03165"
+      severity NOTE;
+    assert (    abc'left = 0.0   and
+                cba'left = 20.0   and
+                xyz'left = 20.0   and
+                zyx'left = 0.0   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd
new file mode 100644
index 0000000..50d93f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3166.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03166ent IS
+END c14s01b00x00p12n01i03166ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03166arch OF c14s01b00x00p12n01i03166ent IS
+  constant L : REAL := -10.0;
+  constant R : REAL := 10.0;
+
+  type RT1 is range L to R;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    RT1'left = RT1(L)   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03166"
+      severity NOTE;
+    assert (    RT1'left = RT1(L)   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03166 - Predefined attribute LEFT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd
new file mode 100644
index 0000000..a77aeca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03167ent IS
+END c14s01b00x00p17n01i03167ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'right = 15    and
+                   roufbit'right = 0   )
+      report "***PASSED TEST: c14s01b00x00p17n01i03167"
+      severity NOTE;
+    assert (    fourbit'right = 15    and
+                roufbit'right = 0   )
+      report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd
new file mode 100644
index 0000000..8de3186
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3168.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03168ent IS
+END c14s01b00x00p17n01i03168ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03168arch OF c14s01b00x00p17n01i03168ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'right = blue )
+      report "***PASSED TEST: c14s01b00x00p17n01i03168"
+      severity NOTE;
+    assert ( color'right = blue )
+      report "***FAILED TEST: c14s01b00x00p17n01i03168 - Predefined attribute RIGHT for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd
new file mode 100644
index 0000000..48ced92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3169.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03169ent IS
+END c14s01b00x00p17n01i03169ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03169arch OF c14s01b00x00p17n01i03169ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+  subtype xyz is real range 20.0 to 0.0;
+  subtype zyx is real range 0.0 downto 20.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    abc'right = 20.0   and
+                   cba'right = 0.0      and
+                   xyz'right = 0.0      and
+                   zyx'right = 20.0   )   
+      report "***PASSED TEST: c14s01b00x00p17n01i03169"
+      severity NOTE;
+    assert (    abc'right = 20.0   and
+                cba'right = 0.0      and
+                xyz'right = 0.0      and
+                zyx'right = 20.0   )   
+      report "***FAILED TEST: c14s01b00x00p17n01i03169 - Predefined attribute RIGHT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd
new file mode 100644
index 0000000..00e02af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc317.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b00x00p03n02i00317ent IS
+END c03s02b00x00p03n02i00317ent;
+
+ARCHITECTURE c03s02b00x00p03n02i00317arch OF c03s02b00x00p03n02i00317ent IS
+  type MVL is ('0','1','X','Z') ;
+  type T1 is array (0 to 31) of BIT;
+  type T2 is record
+               D : Integer range 1 to 30;
+               M : Integer range 1 to 12;
+               Y : Integer range 0 to 2000;  -- No_failure_here
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL := 'X';
+  BEGIN
+    assert NOT(k='X') 
+      report "***PASSED TEST: c03s02b00x00p03n02i00317" 
+      severity NOTE;
+    assert (k='X') 
+      report "***FAILED TEST: c03s02b00x00p03n02i00317 - A composite type may contain elements that are of scalar types and composite types (array and record types)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b00x00p03n02i00317arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd
new file mode 100644
index 0000000..99b07ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03170ent IS
+END c14s01b00x00p17n01i03170ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
+  constant L : REAL := -10.0;
+  constant R : REAL := 10.0;
+
+  type RT1 is range L to R;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    RT1'right = RT1(R)   )   
+      report "***PASSED TEST: c14s01b00x00p17n01i03170"
+      severity NOTE;
+    assert (    RT1'right = RT1(R)   )   
+      report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03170arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd
new file mode 100644
index 0000000..3bae856
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3171.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03171ent IS
+END c14s01b00x00p22n01i03171ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03171arch OF c14s01b00x00p22n01i03171ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   fourbit'high = 15   and
+                  roufbit'high = 15   ) 
+      report "***PASSED TEST: c14s01b00x00p22n01i03171"
+      severity NOTE;
+    assert (   fourbit'high = 15   and
+               roufbit'high = 15   ) 
+      report "***FAILED TEST: c14s01b00x00p22n01i03171 - Predefined attribute HIGH test for integer subtype failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd
new file mode 100644
index 0000000..ace935b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3172.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03172ent IS
+END c14s01b00x00p22n01i03172ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03172arch OF c14s01b00x00p22n01i03172ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'high = blue )
+      report "***PASSED TEST: c14s01b00x00p22n01i03172"
+      severity NOTE;
+    assert ( color'high = blue )
+      report "***FAILED TEST: c14s01b00x00p22n01i03172 - Predefined attribute HIGH test for enumeration type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd
new file mode 100644
index 0000000..dfa96c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3173.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03173ent IS
+END c14s01b00x00p22n01i03173ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03173arch OF c14s01b00x00p22n01i03173ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   abc'high = 20.0   and
+                  cba'high = 20.0   )
+      report "***PASSED TEST: c14s01b00x00p22n01i03173"
+      severity NOTE;
+    assert (   abc'high = 20.0   and
+               cba'high = 20.0   )
+      report "***FAILED TEST: c14s01b00x00p22n01i03173 - Predefined attribute HIGH test for floating point type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd
new file mode 100644
index 0000000..a6730a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3174.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03174ent IS
+END c14s01b00x00p22n01i03174ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03174arch OF c14s01b00x00p22n01i03174ent IS
+  signal gate    : BOOLEAN;
+  signal s    : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    gate <= s < CHARACTER'HIGH after 2 ns;
+    wait for 5 ns;
+    assert NOT( gate = TRUE )
+      report "***PASSED TEST: c14s01b00x00p22n01i03174"
+      severity NOTE;
+    assert ( gate = TRUE )
+      report "***FAILED TEST: c14s01b00x00p22n01i03174 - Predefined attribute HIGH test for character type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd
new file mode 100644
index 0000000..2f2eab9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3175.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03175ent IS
+END c14s01b00x00p27n01i03175ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03175arch OF c14s01b00x00p27n01i03175ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   fourbit'low = 0      and
+                  roufbit'low = 0      ) 
+      report "***PASSED TEST: c14s01b00x00p27n01i03175"
+      severity NOTE;
+    assert (   fourbit'low = 0      and
+               roufbit'low = 0      ) 
+      report "***FAILED TEST: c14s01b00x00p27n01i03175 - Predefined attribute LOW for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd
new file mode 100644
index 0000000..7d842a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3176.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03176ent IS
+END c14s01b00x00p27n01i03176ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03176arch OF c14s01b00x00p27n01i03176ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'low = red )
+      report "***PASSED TEST: c14s01b00x00p27n01i03176"
+      severity NOTE;
+    assert ( color'low = red )
+      report "***FAILED TEST: c14s01b00x00p27n01i03176 - Predefined attribute LOW for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd
new file mode 100644
index 0000000..b327926
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3177.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03177ent IS
+END c14s01b00x00p27n01i03177ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03177arch OF c14s01b00x00p27n01i03177ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   abc'low = 0.0   and
+                  cba'low = 0.0   )
+      report "***PASSED TEST: c14s01b00x00p27n01i03177"
+      severity NOTE;
+    assert (   abc'low = 0.0   and
+               cba'low = 0.0   )
+      report "***FAILED TEST: c14s01b00x00p27n01i03177 - Predefined attribute LOW for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd
new file mode 100644
index 0000000..31ac87e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3178.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p64n01i03178ent IS
+END c14s01b00x00p64n01i03178ent;
+
+ARCHITECTURE c14s01b00x00p64n01i03178arch OF c14s01b00x00p64n01i03178ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'succ(0) = 1   and
+                   roufbit'succ(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p64n01i03178"
+      severity NOTE;
+    assert (    fourbit'succ(0) = 1   and
+                roufbit'succ(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p64n01i03178 - Predefined attribute SUCC for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p64n01i03178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd
new file mode 100644
index 0000000..d48db84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3179.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p71n01i03179ent IS
+END c14s01b00x00p71n01i03179ent;
+
+ARCHITECTURE c14s01b00x00p71n01i03179arch OF c14s01b00x00p71n01i03179ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'pred(15) = 14   and
+                   roufbit'pred(15) = 14   )
+      report "***PASSED TEST: c14s01b00x00p71n01i03179"
+      severity NOTE;
+    assert (    fourbit'pred(15) = 14   and
+                roufbit'pred(15) = 14   )
+      report "***FAILED TEST: c14s01b00x00p71n01i03179 - Predefined attribute PRED for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p71n01i03179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd
new file mode 100644
index 0000000..d0bf960
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc318.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00318ent IS
+END c03s02b01x00p03n01i00318ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00318arch OF c03s02b01x00p03n01i00318ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL_vector is array (0 to 63)of MVL;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(5) := 'Z';
+    assert NOT(k(5)='Z')
+      report "***PASSED TEST: c03s02b01x00p03n01i00318"
+      severity NOTE;
+    assert (k(5)='Z')
+      report "***FAILED TEST: c03s02b01x00p03n01i00318 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00318arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd
new file mode 100644
index 0000000..943ce74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3180.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p78n01i03180ent IS
+END c14s01b00x00p78n01i03180ent;
+
+ARCHITECTURE c14s01b00x00p78n01i03180arch OF c14s01b00x00p78n01i03180ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'leftof(15) = 14   and
+                   roufbit'leftof(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p78n01i03180"
+      severity NOTE;
+    assert (    fourbit'leftof(15) = 14   and
+                roufbit'leftof(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p78n01i03180 - Predefined attribute LEFTOF for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p78n01i03180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd
new file mode 100644
index 0000000..8afe89d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p85n01i03181ent IS
+END c14s01b00x00p85n01i03181ent;
+
+ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'rightof(0) = 1   and
+                   roufbit'leftof(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p85n01i03181"
+      severity NOTE;
+    assert (    fourbit'rightof(0) = 1   and
+                roufbit'leftof(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p85n01i03181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd
new file mode 100644
index 0000000..6ce00dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3182.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p116n01i03182ent IS
+END c14s01b00x00p116n01i03182ent;
+
+ARCHITECTURE c14s01b00x00p116n01i03182arch OF c14s01b00x00p116n01i03182ent IS
+
+  constant C : INTEGER := 1;
+--
+  type t2 is array(c to c + c, 1 to 10) of integer;
+  
+-- transitive cases
+  type t3 is array(t2'range(1), t2'reverse_range(2)) of integer;
+  
+-- 'Range (of two-dimensional array type)
+  type rt311 is range t3'range(1);
+  type rt312 is range t3'range(2);
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    rt311'LEFT = rt311(c)   and
+                   rt311'RIGHT= rt311(c+c)   and
+                   rt312'LEFT = rt312(10)   and
+                   rt312'RIGHT= rt312(1)   )
+      report "***PASSED TEST: c14s01b00x00p116n01i03182"
+      severity NOTE;
+    assert (    rt311'LEFT = rt311(c)   and
+                rt311'RIGHT= rt311(c+c)   and
+                rt312'LEFT = rt312(10)   and
+                rt312'RIGHT= rt312(1)   )
+      report "***FAILED TEST: c14s01b00x00p116n01i03182 - Predefined attribute range test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p116n01i03182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd
new file mode 100644
index 0000000..da63404
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3183.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p122n01i03183ent IS
+END c14s01b00x00p122n01i03183ent;
+
+ARCHITECTURE c14s01b00x00p122n01i03183arch OF c14s01b00x00p122n01i03183ent IS
+
+  constant C : INTEGER := 1;
+--
+  type t2 is array(c to c + c, 1 to 10) of integer;
+  
+-- transitive cases
+  type t3 is array(t2'range(1), t2'reverse_range(2)) of integer;
+  
+-- 'Reverse_Range (of two-dimensional array type)
+  type rt321 is range t3'reverse_range(1);
+  type rt322 is range t3'reverse_range(2);
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    rt321'LEFT = rt321(c+c)   and
+                   rt321'RIGHT= rt321(c)   and
+                   rt322'LEFT = rt322(1)   and
+                   rt322'RIGHT= rt322(10)   )
+      report "***PASSED TEST: c14s01b00x00p122n01i03183"
+      severity NOTE;
+    assert (    rt321'LEFT = rt321(c+c)   and
+                rt321'RIGHT= rt321(c)   and
+                rt322'LEFT = rt322(1)   and
+                rt322'RIGHT= rt322(10)   )
+      report "***FAILED TEST: c14s01b00x00p122n01i03183 - Predefined attribute reverse_range test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p122n01i03183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd
new file mode 100644
index 0000000..d3bcec6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3184.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p128n01i03184ent IS
+END c14s01b00x00p128n01i03184ent;
+
+ARCHITECTURE c14s01b00x00p128n01i03184arch OF c14s01b00x00p128n01i03184ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V : STRING(1 to 5) := "Hello";
+  BEGIN
+    assert V'LENGTH = 5;
+    assert V(1) = 'H';
+    assert V(5) = 'o';
+    assert NOT( V'LENGTH = 5 )
+      report "***PASSED TEST: c14s01b00x00p128n01i03184"
+      severity NOTE;
+    assert ( V'LENGTH = 5 )
+      report "***FAILED TEST: c14s01b00x00p128n01i03184 - Attribute of length test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p128n01i03184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd
new file mode 100644
index 0000000..a223dee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3185.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03185ent IS
+END c14s03b00x00p42n01i03185ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03185arch OF c14s03b00x00p42n01i03185ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.02";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,integer'(1994));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03185 - This test will write TEXT of integer type into file iofile.02."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd
new file mode 100644
index 0000000..00a53f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03186ent IS
+END c14s03b00x00p42n01i03186ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV    : TEXT open write_mode is "iofile.01";
+    variable L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
+      WRITELINE   (FILEV, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd
new file mode 100644
index 0000000..a0552a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3187.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03187ent IS
+END c14s03b00x00p42n01i03187ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03187arch OF c14s03b00x00p42n01i03187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.04";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,real'(1994.5));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03187 - This test will write TEXT into file iofile.04."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd
new file mode 100644
index 0000000..b84de21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3188.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03188ent IS
+END c14s03b00x00p42n01i03188ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03188arch OF c14s03b00x00p42n01i03188ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.06";
+    variable    L   : LINE;
+    variable   vtime   : time;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vtime);
+      if (vtime /= 1994 ns) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03188" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03188 - procedure READLINE for time TEXT file test failed, plese check s010106.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd
new file mode 100644
index 0000000..bcf4b89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3189.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03189ent IS
+END c14s03b00x00p42n01i03189ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03189arch OF c14s03b00x00p42n01i03189ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.02";
+    variable    L   : LINE;
+    variable   vinteger: integer;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vinteger);
+      if (vinteger /= 1994) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03189" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03189 - procedure READLINE for integer TEXT file test failed, plese check s010102.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03189arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd
new file mode 100644
index 0000000..570bb8a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc319.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00319ent IS
+END c03s02b01x00p03n01i00319ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00319arch OF c03s02b01x00p03n01i00319ent IS
+  type bit_vctor is array (natural range <>) of bit;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    subtype kk is bit_vctor(0 to 63);
+    variable k : kk;
+  BEGIN
+    k(5) := '0';
+    assert NOT(k(5)='0')
+      report "***PASSED TEST: c03s02b01x00p03n01i00319"
+      severity NOTE;
+    assert (k(5)='0')
+      report "***FAILED TEST: c03s02b01x00p03n01i00319 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00319arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd
new file mode 100644
index 0000000..c7674b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3190.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03190ent IS
+END c14s03b00x00p42n01i03190ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03190arch OF c14s03b00x00p42n01i03190ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.08";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,bit'('1'));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03190 - This test will write TEXT into file iofile.08."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03190arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd
new file mode 100644
index 0000000..e2ca739
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3191.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03191ent IS
+END c14s03b00x00p42n01i03191ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03191arch OF c14s03b00x00p42n01i03191ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.04";
+    variable    L   : LINE;
+    variable   vreal   : real;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vreal);
+      vreal := vreal - 1994.5;
+      if NOT((vreal > -0.00001) and (vreal < 0.00001)) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03191"
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03191 - procedure READLINE for real TEXT file test failed, plese check s010104.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03191arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd
new file mode 100644
index 0000000..47fed57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3192.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03192ent IS
+END c14s03b00x00p42n01i03192ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03192arch OF c14s03b00x00p42n01i03192ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.06";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,time'(1994 ns));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03192 - This test will write TEXT into file iofile.06."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd
new file mode 100644
index 0000000..65e9bd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3193.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03193ent IS
+END c14s03b00x00p42n01i03193ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03193arch OF c14s03b00x00p42n01i03193ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.08";
+    variable    L   : LINE;
+    variable   vbit   : bit;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vbit);
+      if (vbit /= '1') then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03193" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03193 - procedure READLINE for bit TEXT file test failed, plese check s010108.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03193arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd
new file mode 100644
index 0000000..9deb9d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3194.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03194ent IS
+END c14s03b00x00p42n01i03194ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03194arch OF c14s03b00x00p42n01i03194ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.09";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,bit_vector'("11000011"));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03194 - This test will write TEXT into file iofile.09."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd
new file mode 100644
index 0000000..13087d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3195.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03195ent IS
+END c14s03b00x00p42n01i03195ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03195arch OF c14s03b00x00p42n01i03195ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.09";
+    variable    L      : LINE;
+    variable   vbitvector   : bit_vector(0 to 7);
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vbitvector);
+      if (vbitvector /= "11000011") then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03195" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03195 - procedure READLINE for bit_vector TEXT file test failed, plese check s010110.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03195arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd
new file mode 100644
index 0000000..b0d89c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3196.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03196ent IS
+END c14s03b00x00p42n01i03196ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03196arch OF c14s03b00x00p42n01i03196ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.10";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,boolean'(TRUE));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03196 - This test will write TEXT into file iofile.10."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03196arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd
new file mode 100644
index 0000000..df91036
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3197.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03197ent IS
+END c14s03b00x00p42n01i03197ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03197arch OF c14s03b00x00p42n01i03197ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.10";
+    variable    L      : LINE;
+    variable   vboolean   : boolean;
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vboolean);
+      if (vboolean /= TRUE) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03197"
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03197 - procedure READLINE for boolean TEXT file test failed, plese check s010112.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd
new file mode 100644
index 0000000..8a492e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3198.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03198ent IS
+END c14s03b00x00p42n01i03198ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03198arch OF c14s03b00x00p42n01i03198ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.12";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,character'('n'));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03198 - This test will write TEXT into file iofile.12."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd
new file mode 100644
index 0000000..69726b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3199.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03199ent IS
+END c14s03b00x00p42n01i03199ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03199arch OF c14s03b00x00p42n01i03199ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.12";
+    variable    L      : LINE;
+    variable   vcharacter   : character;
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vcharacter);
+      if (vcharacter /= 'n') then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03199" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03199 - procedure READLINE for character TEXT file test failed, plese check s010114.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd
new file mode 100644
index 0000000..f979ce7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd
@@ -0,0 +1,518 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc32.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00032ent IS
+END c04s03b01x01p01n01i00032ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00032arch OF c04s03b01x01p01n01i00032ent IS
+
+--
+--          Declaration of composite types
+--
+  TYPE    U1 IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type
+  TYPE    C1 IS ARRAY (5 TO 9)             OF BIT;          -- constrained array type
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+
+  TYPE R1 IS
+    RECORD
+      month : month_name;
+      day   : INTEGER RANGE 0 TO 31;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+--          Declaration of composite - composite types
+--
+  TYPE US1 IS ARRAY (INTEGER RANGE   <>  ) OF STRING     ( 1      TO  8 );
+  TYPE UV1 IS ARRAY (INTEGER RANGE   <>  ) OF BIT_VECTOR ( 3  DOWNTO  0 );
+  TYPE UU1 IS ARRAY (INTEGER RANGE   <>  ) OF U1         ('a'     TO 'd');
+  TYPE UC1 IS ARRAY (INTEGER RANGE   <>  ) OF C1;
+  TYPE UR1 IS ARRAY (INTEGER RANGE   <>  ) OF R1;
+  
+  TYPE CS1 IS ARRAY (INTEGER RANGE 0 TO 3) OF STRING     ( 1      TO  8 );
+  TYPE CV1 IS ARRAY (INTEGER RANGE 0 TO 3) OF BIT_VECTOR ( 3  DOWNTO  0 );
+  TYPE CU1 IS ARRAY (INTEGER RANGE 0 TO 3) OF U1         ('a'     TO 'd');
+  TYPE CC1 IS ARRAY (INTEGER RANGE 0 TO 3) OF C1;
+  TYPE CR1 IS ARRAY (INTEGER RANGE 0 TO 3) OF R1;
+  
+  TYPE RAR IS RECORD
+                eS1 : STRING     ( 1      TO  8 );
+                eV1 : BIT_VECTOR ( 3  DOWNTO  0 );
+                eU1 : U1         ('a'     TO 'd');
+                eC1 : C1                         ;
+                eR1 : R1                         ;
+              END RECORD;
+----------------------------------------------------------------------------------------
+--
+--          CONSTANT declarations - initial aggregate value
+--           NOTE: index constraints for the unconstrained types are
+--                  established by the intial value.
+--
+  CONSTANT US1_con_1 : US1          := (
+    (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
+    (BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI ),
+    (DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
+    (CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP)
+    );
+  
+  CONSTANT UV1_con_1 : UV1          := (
+    ('0', '1', '0', '0'),
+    ('1', '0', '1', '1'),
+    ('1', '0', '0', '0'),
+    ('0', '1', '0', '1')
+    );
+  
+  CONSTANT UU1_con_1 : UU1          := (
+    (  1,   2,   3,   4),
+    (  5,   6,   7,   8),
+    (  9,  10,  11,  12),
+    ( 13,  14,  15,  16)
+    );
+  
+  CONSTANT UC1_con_1 : UC1          := (
+    ('0', '1', '0', '0', '1'),
+    ('0', '1', '1', '1', '0'),
+    ('0', '0', '0', '1', '0'),
+    ('1', '0', '0', '0', '1')
+    );
+  
+  CONSTANT UR1_con_1 : UR1          := (   (Feb,05,1701),
+                                           (Apr,10,1802),
+                                           (Jun,15,1903),
+                                           (Aug,20,2004)  );
+  
+  CONSTANT CS1_con_1 : CS1          := (
+    (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
+    (BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI ),
+    (DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
+    (CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP)
+
+    );
+  
+  CONSTANT CV1_con_1 : CV1          := (
+    ('0', '1', '0', '0'),
+    ('1', '0', '1', '1'),
+    ('1', '0', '0', '0'),
+    ('0', '1', '0', '1')
+    );
+
+  CONSTANT CU1_con_1 : CU1          := (
+    (  1,   2,   3,   4),
+    (  5,   6,   7,   8),
+    (  9,  10,  11,  12),
+    ( 13,  14,  15,  16)
+    );
+  
+  CONSTANT CC1_con_1 : CC1          := (
+    ('0', '1', '0', '0', '1'),
+    ('0', '1', '1', '1', '0'),
+    ('0', '0', '0', '1', '0'),
+    ('1', '0', '0', '0', '1')
+    );
+  
+  CONSTANT CR1_con_1 : CR1          := ( (Feb,05,1701),
+                                         (Apr,10,1802),
+                                         (Jun,15,1903),
+                                         (Aug,20,2004)  );
+  
+  CONSTANT RAR_con_1 : RAR          := (
+    (SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS ),
+    ('1', '1', '0', '0'),
+    (  1,   2,   3,   4),
+    ('0', '1', '0', '0', '1'),
+    (Feb,29,0108) );
+  
+--
+--          CONSTANT declarations - aggregate of strings initial value
+--
+  CONSTANT US1_con_2 : US1          := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
+  CONSTANT UV1_con_2 : UV1          := (    B"0100",    B"1011",    B"1000",    B"0101" );
+  CONSTANT UC1_con_2 : UC1          := (   B"01001",   B"01110",   B"00010",   B"10001" );
+  
+  CONSTANT CS1_con_2 : CS1          := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
+  CONSTANT CV1_con_2 : CV1          := (    B"0100",    B"1011",    B"1000",    B"0101" );
+  CONSTANT CC1_con_2 : CC1          := (   B"01001",   B"01110",   B"00010",   B"10001" );
+  
+  CONSTANT RAR_con_2 : RAR          := ( "@ABCDEFG",    B"1100",  (1,2,3,4),  B"01001", (Feb,29,0108) );
+  
+  
+-----------------------------------------------------------------------------------------
+BEGIN
+  TESTING: PROCESS
+--
+--          Declarationi for generation of BIT test pattern
+--
+    VARIABLE bval  : BIT;
+    VARIABLE index : INTEGER;
+    VARIABLE ii    : INTEGER;
+
+    variable k    : integer := 0;
+    
+    PROCEDURE pattern ( index : INOUT INTEGER; bval : OUT BIT ) IS
+--
+--                if starting index value is 59, the
+--                test pattern is 01001011100001010001111 (repeats)
+--
+    BEGIN
+      IF index > 100
+      THEN  bval  := '1';
+            index := index - 100;
+      ELSE  bval  := '0';
+      END IF;
+      index := index * 2;
+    END;
+
+  BEGIN
+
+----------------------------------------------------------------------------------------
+--
+--              Verify initial values
+--
+    FOR I IN 0 TO 3 LOOP   ii := INTEGER'LEFT + I;
+                           FOR J IN 1 TO 8 LOOP
+                             if (US1_con_1(ii)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
+                               k := 1;
+                             end if;
+                             ASSERT US1_con_1(ii)(J) = CHARACTER'VAL((I*8)+(J-1))
+                               REPORT "ERROR: Bad initial value of US1_con_1" SEVERITY FAILURE;
+                           END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 3 DOWNTO  0 LOOP
+                            pattern ( index, bval );
+                            if (UV1_con_1(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UV1_con_1(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UV1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 0;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 'a' TO 'd' LOOP
+                            index := index + 1;
+                            if (UU1_con_1(ii)(J) /= index) then
+                              k := 1;
+                            end if;
+                            ASSERT UU1_con_1(ii)(J) = index
+                              REPORT "ERROR: Bad initial value of UU1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 5 TO 9 LOOP
+                            pattern ( index, bval );
+                            if (UC1_con_1(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UC1_con_1(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UC1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          if (UR1_con_1(ii).month /= month_name'VAL((I*2)+1)) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).month = month_name'VAL((I*2)+1)
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).month" SEVERITY FAILURE;
+                          if (UR1_con_1(ii).day /= I*5 +5) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).day = I*5 + 5
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).day" SEVERITY FAILURE;
+                          if (UR1_con_1(ii).year /= 1701 +(I*101)) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).year = 1701 + (I*101)
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).year" SEVERITY FAILURE;
+    END LOOP;
+    
+--
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 1 TO 8 LOOP
+        if (CS1_con_1(I)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
+          k := 1;
+        end if;
+        ASSERT CS1_con_1(I)(J) = CHARACTER'VAL((I*8)+(J-1))
+          REPORT "ERROR: Bad initial value of CS1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 3 DOWNTO  0 LOOP
+        pattern ( index, bval );
+        if (CV1_con_1(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CV1_con_1(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CV1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 0;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 'a' TO 'd' LOOP
+        index := index + 1;
+        if (CU1_con_1(I)(J) /= index) then
+          k := 1;
+        end if;
+        ASSERT CU1_con_1(I)(J) = index
+          REPORT "ERROR: Bad initial value of CU1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 5 TO 9 LOOP
+        pattern ( index, bval );
+        if (CC1_con_1(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CC1_con_1(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CC1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    FOR I IN 0 TO 3 LOOP
+      if (CR1_con_1(I).month /= month_name'VAL((I*2)+1)) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).month = month_name'VAL((I*2)+1)
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).month" SEVERITY FAILURE;
+      if (CR1_con_1(I).day /= (I+1)*5) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).day = (I+1)*5
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).day" SEVERITY FAILURE;
+      if (CR1_con_1(I).year /= 1701 + (I*101)) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).year = 1701 + (I*101)
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).year" SEVERITY FAILURE;
+    END LOOP;
+    
+--
+    FOR J IN 1 TO 8 LOOP
+      if (RAR_con_1.eS1(J) /= CHARACTER'VAL(J)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eS1(J) = CHARACTER'VAL(J)
+        REPORT "ERROR: Bad initial value of RAR_con_1.eS1" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR J IN 3 DOWNTO  0 LOOP
+      if (RAR_con_1.eV1(J) /= BIT'VAL(J/2)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eV1(J) = BIT'VAL(J/2)
+        REPORT "ERROR: Bad initial value of RAR_con_1.eV1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 0;
+    FOR J IN 'a' TO 'd' LOOP
+      index := index + 1;
+      if (RAR_con_1.eU1(J) /= index) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eU1(J) = index
+        REPORT "ERROR: Bad initial value of RAR_con_1.eU1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 59;
+    FOR J IN 5 TO 9 LOOP
+      pattern ( index, bval );
+      if (RAR_con_1.eC1(J) /= bval) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eC1(J) = bval
+        REPORT "ERROR: Bad initial value of RAR_con_1.eC1" SEVERITY FAILURE;
+    END LOOP;
+    
+    if (RAR_con_1.eR1.month /= FEB) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.month = FEB
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.month" SEVERITY FAILURE;
+    if (RAR_con_1.eR1.day /= 29) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.day = 29
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.day" SEVERITY FAILURE;
+    if (RAR_con_1.eR1.year /= 0108) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.year = 0108
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY FAILURE;
+    
+-- ----------------------------------------------------------------------------------
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 1 TO 8 LOOP
+                            if (US1_con_2(ii)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
+                              k := 1;
+                            end if;
+                            ASSERT US1_con_2(ii)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
+                              REPORT "ERROR: Bad initial value of US1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 3 DOWNTO  0 LOOP
+                            pattern ( index, bval );
+                            if (UV1_con_2(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UV1_con_2(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UV1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 5 TO 9 LOOP
+                            pattern ( index, bval );
+                            if (UC1_con_2(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UC1_con_2(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UC1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+--
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 1 TO 8 LOOP
+        if (CS1_con_2(I)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
+          k := 1;
+        end if;
+        ASSERT CS1_con_2(I)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
+          REPORT "ERROR: Bad initial value of CS1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 3 DOWNTO  0 LOOP
+        pattern ( index, bval );
+        if (CV1_con_2(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CV1_con_2(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CV1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 5 TO 9 LOOP
+        pattern ( index, bval );
+        if (CC1_con_2(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CC1_con_2(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CC1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+--
+    FOR J IN 1 TO 8 LOOP
+      if (RAR_con_2.eS1(J) /= CHARACTER'VAL((J-1)+64)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eS1(J) = CHARACTER'VAL((J-1)+64)
+        REPORT "ERROR: Bad initial value of RAR_con_2.eS1" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR J IN 3 DOWNTO  0 LOOP
+      if (RAR_con_2.eV1(J) /= BIT'VAL(J/2)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eV1(J) = BIT'VAL(J/2)
+        REPORT "ERROR: Bad initial value of RAR_con_2.eV1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 0;
+    FOR J IN 'a' TO 'd' LOOP
+      index := index + 1;
+      if (RAR_con_2.eU1(J) /= index) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eU1(J) = index
+        REPORT "ERROR: Bad initial value of RAR_con_2.eU1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 59;
+    FOR J IN 5 TO 9 LOOP
+      pattern ( index, bval );
+      if (RAR_con_2.eC1(J) /= bval) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eC1(J) = bval
+        REPORT "ERROR: Bad initial value of RAR_con_2.eC1" SEVERITY FAILURE;
+    END LOOP;
+    
+    if (RAR_con_2.eR1.month /= FEB) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.month = FEB
+      REPORT "ERROR: Bad initial value of RAR_con_2.eR1.month" SEVERITY FAILURE;
+    if (RAR_con_2.eR1.day /=29) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.day = 29
+      REPORT "ERROR: Bad initial value of RAR_con_2.eR1.day" SEVERITY FAILURE;
+    if (RAR_con_2.eR1.year /= 0108) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.year = 0108
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY
+      FAILURE;
+    
+---------------------------------------------------------------------------------------------
+
+    assert NOT(    k = 0  )
+      report "***PASSED TEST: c04s03b01x01p01n01i00032"
+      severity NOTE;
+    assert (    k = 0  )
+      report "***FAILED TEST:c04s03b01x01p01n01i00032 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd
new file mode 100644
index 0000000..b00bbfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc320.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00320ent IS
+END c03s02b01x00p03n01i00320ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00320arch OF c03s02b01x00p03n01i00320ent IS
+  type matrix1 is array (integer range <>, integer range <>) of real;
+  type matrix2 is array (integer range <>, positive range <>) of real;
+  type matrix4 is array (bit range <>, bit range <>) of TIME;
+BEGIN
+  TESTING: PROCESS
+    subtype kk is matrix1(0 to 6,0 to 6);
+    variable k : kk;
+  BEGIN
+    k(5,5) := 0.1;
+    assert NOT(k(5,5)=0.1)
+      report "***PASSED TEST: c03s02b01x00p03n01i00320"
+      severity NOTE;
+    assert (k(5,5)=0.1)
+      report "***FAILED TEST: c03s02b01x00p03n01i00320 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00320arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd
new file mode 100644
index 0000000..646048f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3200.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03200ent IS
+END c14s03b00x00p42n01i03200ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03200arch OF c14s03b00x00p42n01i03200ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.14";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,string'("niu"));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03200 - This test will write TEXT into file iofile.14."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd
new file mode 100644
index 0000000..a188a4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3201.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03201ent IS
+END c14s03b00x00p42n01i03201ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03201arch OF c14s03b00x00p42n01i03201ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.14";
+    variable    L      : LINE;
+    variable   vstring      : string(1 to 3);
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vstring);
+      if (vstring /= "niu") then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03201" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03201 - procedure READLINE for string TEXT file test failed, plese check s010116.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd
new file mode 100644
index 0000000..e3328ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3202.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p56n01i03202ent IS
+END c14s03b00x00p56n01i03202ent;
+
+ARCHITECTURE c14s03b00x00p56n01i03202arch OF c14s03b00x00p56n01i03202ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.61";
+    variable    L   : LINE;
+    variable    Bi   : BIT;
+    variable    Bo   : BOOLEAN;
+    variable    BV   : Bit_Vector(1 to 60);
+    variable    BV2   : Bit_Vector(1 to 60);
+
+    -- Define the ScanForStars subprogram
+    procedure ScanForStars(L: inout Line) is
+      variable Index : Natural := 1;
+      variable C1, C2: Character := ' ';
+    begin
+      while C1 = ' ' loop
+        Read(L, C1);
+      end loop;
+      Read(L, C2);
+      assert C1 = '*' and C2 = '*'
+        report "Could not find two stars";
+    end;
+  BEGIN
+    -- Read the entire line..
+    READLINE(F, L);
+    assert L.all = "hello world"
+      report "Could not find opening banner...";
+    
+    -- Read the blank line...
+    READLINE(F, L);
+    assert L.all = ""
+      report "Could not find blank line...";
+    
+    -- Read some BITS...
+    for width in 1 to 10 loop
+      READLINE(F, L);
+      READ(L, Bi);
+      assert Bi = '0'
+        report "Failed in Read(BIT).  (Should be '0')";
+      ScanForStars(L);
+      READ(L, Bi);
+      assert Bi = '1'
+        report "Failed in Read(BIT).  (Should be '1')";
+      ScanForStars(L);
+    end loop;
+    READLINE(F, L);
+    
+    -- Read some Bit vectors...
+    for i in BV'Range loop
+      BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
+    end loop;
+    
+    for width in 15 downto 1 loop
+      READLINE(F, L);
+      READ(L, BV2(1 to 2*width));
+      assert BV2(1 to 2*width) = BV((15-width)*2+1 to 30)
+        report "Failed in Read(BIT_VECTOR). (Left side)";
+      ScanForStars(L);
+      READ(L, BV2(1 to 2*width));
+      assert BV2(1 to 2*width) = BV(1 to 2*width)
+        report "Failed in Read(BIT_VECTOR). (Right side)";
+    end loop;
+    READLINE(F, L);
+    
+    -- Read some BOOLEANs...
+    for i in 10 downto 1 loop
+      READLINE(F, L);
+      READ(L, Bo);
+      assert Bo = FALSE
+        report "Failed in Read(BOOLEAN).  (Left side)";
+      ScanForStars(L);
+      READ(L, Bo);
+      assert Bo = TRUE
+        report "Failed in Read(BOOLEAN).  (Right side)";
+    end loop;
+    READLINE(F, L);
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p56n01i03202 - This test file will read in an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and needs manual check to make sure that there is no ERROR assertion note."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p56n01i03202arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd
new file mode 100644
index 0000000..b794010
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3203.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p56n01i03203ent IS
+END c14s03b00x00p56n01i03203ent;
+
+ARCHITECTURE c14s03b00x00p56n01i03203arch OF c14s03b00x00p56n01i03203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.61";
+    variable    L   : LINE;
+    variable    BV   : Bit_Vector(1 to 60);
+  BEGIN
+    -- Write an arbitrary line...
+    L := new STRING'("hello world");
+    WRITELINE(F, L);
+    
+    -- Write a blank line...
+    WRITELINE(F, L);
+    
+    -- Write some BITs...
+    for i in 1 to 10 loop
+      WRITE(L, Bit'('0'), RIGHT, i);
+      WRITE(L, String'("**"), RIGHT, 12-i);
+      WRITE(L, Bit'('1'), LEFT, i);
+      WRITE(L, String'("**"), LEFT, 0);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    
+    -- Write some Bit vectors...
+    for i in BV'Range loop
+      BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
+    end loop;
+    
+    for i in 15 downto 1 loop
+      WRITE(L, BV((15-i)*2+1 to 30), RIGHT, 30);
+      WRITE(L, String'("**"), RIGHT, 3);
+      WRITE(L, BV(1 to 2*i), LEFT, 30);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    
+    -- Write some BOOLEANs...
+    for i in 10 downto 1 loop
+      WRITE(L, Boolean'(FALSE), RIGHT, i);
+      WRITE(L, String'("**"), RIGHT, 12-i);
+      WRITE(L, Boolean'(TRUE), RIGHT, 11-i);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    wait for 10 ns;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p56n01i03203 - This test file will output an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and next test file will be used to verify the correctness of the this writing test."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p56n01i03203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd
new file mode 100644
index 0000000..e1d20da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3204.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library STD;
+use STD.TEXTIO.all;
+ENTITY c14s03b00x00p59n01i03204ent IS
+END c14s03b00x00p59n01i03204ent;
+
+ARCHITECTURE c14s03b00x00p59n01i03204arch OF c14s03b00x00p59n01i03204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F_out   : Text open write_mode is "iofile.47";
+    variable    L_out   : Line;
+    type       TA    is array (INTEGER range <>) of TIME;
+    constant    A   : TA := (-1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
+  BEGIN
+
+    for i in A'RANGE loop
+      Write(L_out, A(i), UNIT=>fs, FIELD=>25);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ps, FIELD=>25);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ns, FIELD=>25);
+      WriteLine(F_out, L_out);
+      WriteLine(F_out, L_out);
+    end loop;
+    wait for 10 fs;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p59n01i03204 - This test will output an output file, and that file will be compared with s010401.ref file."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p59n01i03204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd
new file mode 100644
index 0000000..d68db12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library STD;
+use STD.TEXTIO.all;
+ENTITY c14s03b00x00p59n01i03205ent IS
+END c14s03b00x00p59n01i03205ent;
+
+ARCHITECTURE c14s03b00x00p59n01i03205arch OF c14s03b00x00p59n01i03205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F_out   : Text open write_mode is "iofile.64";
+    variable    L_out   : Line;
+    type       TA    is array (INTEGER range <>) of TIME;
+    constant    A   : TA := (1 hr, -1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
+  BEGIN
+
+    for i in A'RANGE loop
+      Write(L_out, A(i), UNIT=>ps);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ns);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>us);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ms);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>sec);
+      WriteLine(F_out, L_out);
+      WriteLine(F_out, L_out);
+    end loop;
+    wait for 10 fs;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p59n01i03205 - This test will output an output file, and that file will be compared with s010402.ref file."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p59n01i03205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd
new file mode 100644
index 0000000..24c549c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p60n01i03206ent IS
+END c14s03b00x00p60n01i03206ent;
+
+ARCHITECTURE c14s03b00x00p60n01i03206arch OF c14s03b00x00p60n01i03206ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    procedure write1 is
+      file F: TEXT open write_mode is "iofile.64";
+      variable    L: LINE;
+
+    begin
+      write(L, Integer'(12));
+      writeline(F, L);
+      write(L, Integer'(34));
+      writeline(F, L);
+      write(L, Integer'(56));
+      writeline(F, L);
+      write(L, Integer'(78));
+      writeline(F, L);
+      write(L, Integer'(90));
+      writeline(F, L);
+
+    end write1;
+
+    procedure read1 is
+      file F: TEXT open read_mode is "s010301.in";
+      variable    L: LINE;
+      variable    i,v_integer : Integer;
+    begin
+      i := 0;
+      while not ENDFILE(F) loop
+        readline(F, L);
+        i := i + 1;
+      end loop;
+
+      Assert i /= 4
+        report "Line count to ENDFILE is incorrect"
+        severity ERROR;
+      assert NOT( i = 5 )
+        report "***PASSED TEST: c14s03b00x00p60n01i03206"
+        severity NOTE;
+      assert ( i = 5 )
+        report "***FAILED TEST: c14s03b00x00p60n01i03206 - Procedure ENDLINE test failed."
+        severity ERROR;
+    end read1;
+
+  BEGIN
+    write1;
+    wait for 10 ns;
+    read1;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p60n01i03206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd
new file mode 100644
index 0000000..47e9140
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc322.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00322ent IS
+END c03s02b01x00p04n01i00322ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00322arch OF c03s02b01x00p04n01i00322ent IS
+  type bit_vctor is array (0 to 7) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(0 to 7) := "11110000";
+    assert NOT(k(0 to 7)="11110000")
+      report "***PASSED TEST: c03s02b01x00p04n01i00322"
+      severity NOTE;
+    assert ( k(0 to 7)="11110000" )
+      report "***FAILED TEST: c03s02b01x00p04n01i00322 - In the constrainted array definition, the reserved word array is followed by an index constraint and the reserved word if."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00322arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd
new file mode 100644
index 0000000..eb99b87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc323.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00323ent IS
+END c03s02b01x00p04n01i00323ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00323arch OF c03s02b01x00p04n01i00323ent IS
+  type bit_vctor is array (14 downto 7) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(14 downto 7) :="11110000";
+    assert NOT(k(14 downto 7)="11110000")
+      report "***PASSED TEST: c03s02b01x00p04n01i00323"
+      severity NOTE;
+    assert ( k(14 downto 7)="11110000" )
+      report "***FAILED TEST: c03s02b01x00p04n01i00323 - In the constrainted array definition, the reserved word array is followed by an index constraint and the reserved word if."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00323arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd
new file mode 100644
index 0000000..c9a18d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc326.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00326ent IS
+END c03s02b01x00p04n01i00326ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00326arch OF c03s02b01x00p04n01i00326ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+
+  type array_type is array (1 to 10) of rec_type;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : array_type;
+  BEGIN
+    k(1).x := 5;
+    k(1).y := 1.0;
+    k(1).z := true;
+    k(1).b := '1';
+    assert NOT(k(1).x=5 and k(1).y=1.0 and k(1).z=true and k(1).b='1') 
+      report "***PASSED TEST: c03s02b01x00p04n01i00326"
+      severity NOTE;
+    assert (k(1).x=5 and k(1).y=1.0 and k(1).z=true and k(1).b='1') 
+      report "***FAILED TEST: c03s02b01x00p04n01i00326 - The index constraint is not valid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00326arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd
new file mode 100644
index 0000000..ce97d61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc33.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00033ent IS
+END c04s03b01x01p01n01i00033ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00033arch OF c04s03b01x01p01n01i00033ent IS
+  constant  INDEX : integer range 0 to 99 := 0;   --No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( INDEX = 0 )
+      report "***PASSED TEST:c04s03b01x01p01n01i00033"      severity NOTE;
+    assert ( INDEX = 0 )
+      report "***FAILED TEST: c04s03b01x01p01n01i00033 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd
new file mode 100644
index 0000000..938d916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00333ent IS
+END c03s02b01x00p06n01i00333ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
+  type bit_vctor is array (1 to 8, 1 to 8) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1,8) := 56;
+    assert NOT(k(1,8)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00333"
+      severity NOTE;
+    assert (k(1,8)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00333arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd
new file mode 100644
index 0000000..5fe1047
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc334.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00334ent IS
+END c03s02b01x00p06n01i00334ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00334arch OF c03s02b01x00p06n01i00334ent IS
+  type bit_vctor is array (1 to 8, 8 downto 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1,8) := 56;
+    assert NOT(k(1,8)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00334" 
+      severity NOTE;
+    assert (k(1,8)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00334 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00334arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd
new file mode 100644
index 0000000..88a3552
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00335ent IS
+END c03s02b01x00p06n01i00335ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
+  type bit_vctor is array (1 to 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1) := 56;
+    assert NOT(k(1)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00335" 
+      severity NOTE;
+    assert (k(1)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00335arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd
new file mode 100644
index 0000000..c08b3e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc337.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p07n01i00337ent IS
+END c03s02b01x00p07n01i00337ent;
+
+ARCHITECTURE c03s02b01x00p07n01i00337arch OF c03s02b01x00p07n01i00337ent IS
+  type bit_vctor is array (positive range 1 to 8) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(1 to 8) := "11110000";
+    assert NOT(k(1 to 8) = "11110000")
+      report "***PASSED TEST: c03s02b01x00p07n01i00337"
+      severity NOTE;
+    assert (k(1 to 8) = "11110000")
+      report "***FAILED TEST: c03s02b01x00p07n01i00337 - The discrete ranges must be either a discrete subtype indication or a range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p07n01i00337arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd
new file mode 100644
index 0000000..ec5941c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc339.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p07n01i00339ent IS
+END c03s02b01x00p07n01i00339ent;
+
+ARCHITECTURE c03s02b01x00p07n01i00339arch OF c03s02b01x00p07n01i00339ent IS
+  type one is array (integer range 1 to 10) of bit;
+  type two is array (1 to 10, bit range '0' to '1') of bit;
+  type three is array (1 to 10, bit range '0' to '1', character) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : one;
+  BEGIN
+    k(5) := '1';
+    assert NOT(k(5) = '1') 
+      report "***PASSED TEST: c03s02b01x00p07n01i00339" 
+      severity NOTE;
+    assert (k(5)='1') 
+      report "***FAILED TEST: c03s02b01x00p07n01i00339 - The discrete range is neither a valid discrete subtype indication nor a valid range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p07n01i00339arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd
new file mode 100644
index 0000000..51d4c86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc341.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n02i00341ent IS
+END c03s02b01x00p09n02i00341ent;
+
+ARCHITECTURE c03s02b01x00p09n02i00341arch OF c03s02b01x00p09n02i00341ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       T_A1_S       is ARRAY(INTEGER range <>) of INTEGER;
+    subtype    ST_A1_S    is T_A1_S(INTEGER range 1 to 3);
+    type       T_A1_A1_S    is ARRAY(INTEGER range <>) of ST_A1_S;
+    subtype    ST_A1_A1_S    is T_A1_A1_S(INTEGER range 6 downto 4);
+
+    variable V_A1_A1_S    : ST_A1_A1_S;
+  BEGIN
+    V_A1_A1_S(6)(1) := 61;
+    V_A1_A1_S(6)(2) := 62;
+    V_A1_A1_S(6)(3) := 63;
+    V_A1_A1_S(5)(1) := 51;
+    V_A1_A1_S(5)(2) := 52;
+    V_A1_A1_S(5)(3) := 53;
+    V_A1_A1_S(4)(1) := 41;
+    V_A1_A1_S(4)(2) := 42;
+    V_A1_A1_S(4)(3) := 43;
+    wait for 5 ns;
+    assert NOT(    V_A1_A1_S(6)(1) = 61   and
+                   V_A1_A1_S(6)(2) = 62   and
+                   V_A1_A1_S(6)(3) = 63   and
+                   V_A1_A1_S(5)(1) = 51   and
+                   V_A1_A1_S(5)(2) = 52   and
+                   V_A1_A1_S(5)(3) = 53   and
+                   V_A1_A1_S(4)(1) = 41   and
+                   V_A1_A1_S(4)(2) = 42   and
+                   V_A1_A1_S(4)(3) = 43)
+      report "***PASSED TEST: c03s02b01x00p09n02i00341"
+      severity NOTE;
+    assert (    V_A1_A1_S(6)(1) = 61   and
+                V_A1_A1_S(6)(2) = 62   and
+                V_A1_A1_S(6)(3) = 63   and
+                V_A1_A1_S(5)(1) = 51   and
+                V_A1_A1_S(5)(2) = 52   and
+                V_A1_A1_S(5)(3) = 53   and
+                V_A1_A1_S(4)(1) = 41   and
+                V_A1_A1_S(4)(2) = 42   and
+                V_A1_A1_S(4)(3) = 43)
+      report "***FAILED TEST: c03s02b01x00p09n02i00341 - For each possible sequence of index values that can be formed by selecting one value for each index for a multimensioal array, there is a distinct element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n02i00341arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd
new file mode 100644
index 0000000..8177b1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n03i00343ent IS
+END c03s02b01x00p09n03i00343ent;
+
+ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
+  type M1 is array (1 to 4) of BIT;
+  signal X1 : M1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X1(1) <= '0' after 10 ns;
+    X1(2) <= '1' after 20 ns;
+    X1(3) <= '1' after 30 ns;
+    X1(4) <= '0' after 40 ns;   -- No_failure_here
+    wait for 50 ns;
+    assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
+      report "***PASSED TEST: c03s02b01x00p09n03i00343"
+      severity NOTE;
+    assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
+      report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n03i00343arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd
new file mode 100644
index 0000000..0ab8da6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc344.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n01i00344ent IS
+END c03s02b01x00p09n01i00344ent;
+
+ARCHITECTURE c03s02b01x00p09n01i00344arch OF c03s02b01x00p09n01i00344ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       T_A1_S       is ARRAY(INTEGER range <>) of INTEGER;
+    subtype    ST_A1_S    is T_A1_S(INTEGER range 1 to 3);
+
+    variable    V_A1_S       : ST_A1_S;
+  BEGIN
+    V_A1_S(1) := 11;
+    V_A1_S(2) := 22;
+    V_A1_S(3) := 33;
+    wait for 5 ns;
+    assert NOT(   V_A1_S(1) = 11   and
+                  V_A1_S(2) = 22   and
+                  V_A1_S(3) = 33   )
+      report "***PASSED TEST: c03s02b01x00p09n01i00344"
+      severity NOTE;
+    assert (   V_A1_S(1) = 11   and
+               V_A1_S(2) = 22   and
+               V_A1_S(3) = 33   )
+      report "***FAILED TEST: c03s02b01x00p09n01i00344 - For each possible index value there should be a distinct element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n01i00344arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd
new file mode 100644
index 0000000..f76562e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc346.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p10n05i00346ent IS
+END c03s02b01x00p10n05i00346ent;
+
+ARCHITECTURE c03s02b01x00p10n05i00346arch OF c03s02b01x00p10n05i00346ent IS
+  type MEM is array(INTEGER range <>) of BIT;
+BEGIN
+  TESTING: PROCESS
+    variable S1 : MEM(1 to 5);
+    variable S2 : MEM(28 downto 7);
+  BEGIN
+    S1(1 to 5) := "11111";
+    S2(28 downto 21) := "00001111";
+    assert NOT(S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
+      report "***PASSED TEST: c03s02b01x00p10n05i00346"
+      severity NOTE;
+    assert (S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
+      report "***FAILED TEST: c03s02b01x00p10n05i00346 - Different objects of the same unconstrained array type can have different bounds and direction."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p10n05i00346arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd
new file mode 100644
index 0000000..a3e9dbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p15n01i00347ent IS
+END c03s02b01x00p15n01i00347ent;
+
+ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
+  type MEM is array(5 downto 0) of BIT;  -- No_failure_here
+  signal S1 : MEM := "000000";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S1(4 downto 3) = "00")
+      report "***PASSED TEST: c03s02b01x00p15n01i00347"
+      severity NOTE;
+    assert (S1(4 downto 3) = "00")
+      report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p15n01i00347arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd
new file mode 100644
index 0000000..e5edda9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc349.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p01n01i00349ent IS
+  type atest is array(1 to 20) of bit;
+END c03s02b01x01p01n01i00349ent;
+
+ARCHITECTURE c03s02b01x01p01n01i00349arch OF c03s02b01x01p01n01i00349ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 0;
+  BEGIN
+    a:=atest'length;
+    assert NOT( a=20 )
+      report "***PASSED TEST: c03s02b01x01p01n01i00349"
+      severity NOTE;
+    assert ( a=20 )
+      report "***FAILED TEST: c03s02b01x01p01n01i00349 - Array length is not equal the declared array range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p01n01i00349arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd
new file mode 100644
index 0000000..26dbcc5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc35.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00035ent IS
+END c04s03b01x01p01n01i00035ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00035arch OF c04s03b01x01p01n01i00035ent IS
+  type large is range 0 to 2_000_000_000      --   < 2**31-1
+    units
+      sbu; 
+      lbu = 2000000000 sbu;
+    end units;
+  constant   SC : large := sbu;
+  constant   LC : large := lbu;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( LC = 2000000000 * SC )
+      report "***PASSED TEST: c04s03b01x01p01n01i00035"
+      severity NOTE;
+    assert ( LC = 2000000000 * SC )
+      report "***FAILED TEST: c04s03b01x01p01n01i00035 - Large physical type declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd
new file mode 100644
index 0000000..1873354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc350.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p01n01i00350ent IS
+END c03s02b01x01p01n01i00350ent;
+
+ARCHITECTURE c03s02b01x01p01n01i00350arch OF c03s02b01x01p01n01i00350ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1 :    STRING(1 to 20);
+    subtype    ST is    STRING(1 to 10);
+    variable    V2 :    ST;
+  BEGIN
+    assert V1'LEFT    = 1;
+    assert V1'RIGHT = 20;
+    assert ST'LEFT    = 1;
+    assert ST'RIGHT = 10;
+    assert V2'LEFT    = 1;
+    assert V2'RIGHT = 10;
+    assert NOT(     V1'LEFT  = 1    and
+                    V1'RIGHT = 20   and
+                    ST'LEFT  = 1   and
+                    ST'RIGHT = 10   and
+                    V2'LEFT  = 1   and
+                    V2'RIGHT = 10   )
+      report "***PASSED TEST: c03s02b01x01p01n01i00350"
+      severity NOTE;
+    assert (     V1'LEFT  = 1    and
+                 V1'RIGHT = 20   and
+                 ST'LEFT  = 1   and
+                 ST'RIGHT = 10   and
+                 V2'LEFT  = 1   and
+                 V2'RIGHT = 10   )
+      report "***FAILED TEST: c03s02b01x01p01n01i00350 - Index constraint test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p01n01i00350arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd
new file mode 100644
index 0000000..f9f02ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc351.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00351ent IS
+END c03s02b01x01p02n01i00351ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00351arch OF c03s02b01x01p02n01i00351ent IS
+  type bit_vctor is array (-1 to 8) of integer;  --Expect_success
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(5) := 5;
+    assert NOT(k(5)=5) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00351" 
+      severity NOTE;
+    assert (k(5)=5) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00351 - An implicit conversion to the predefined type INTEGER is assumed if each bound is either a numeric literal or an attribute, and the type of both bounds(prior to implicit conversion) is the type universal_integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00351arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd
new file mode 100644
index 0000000..786dbfe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc355.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00355ent IS
+END c03s02b01x01p02n01i00355ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00355arch OF c03s02b01x01p02n01i00355ent IS
+  type bit_vctor is array (-1 to 8) of integer;  --Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(-1) := 5;
+    assert NOT(k(-1)=5) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00355" 
+      severity NOTE;
+    assert (k(-1)=5) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00355 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00355arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd
new file mode 100644
index 0000000..f1b1386
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc359.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00359ent IS
+END c03s02b01x01p02n01i00359ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00359arch OF c03s02b01x01p02n01i00359ent IS
+  type sense is (hear, touch, smell, see);
+  type page is array (hear to see) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : page;
+  BEGIN
+    k(hear)   := '0';
+    k(touch):= '1';
+    k(smell):= '0';
+    k(see)  := '1';
+    wait for 2 ns;
+    assert NOT(   k(hear) = '0' and 
+                  k(touch)= '1' and 
+                  k(smell)= '0' and
+                  k(see)  = '1') 
+      report "***PASSED TEST: c03s02b01x01p02n01i00359" 
+      severity NOTE;
+    assert (   k(hear) = '0' and 
+               k(touch)= '1' and 
+               k(smell)= '0' and
+               k(see)  = '1') 
+      report "***FAILED TEST: c03s02b01x01p02n01i00359 - Bounds are of different discrete types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd
new file mode 100644
index 0000000..36c1eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00036ent IS
+END c04s03b01x01p02n01i00036ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS
+  constant a  : positive := 1;              -- No_failure_here
+  constant b  : natural  := 1;              -- No_failure_here
+  constant a1 : positive := a + 1;          -- No_failure_here
+  constant a2 : positive := a + a;          -- No_failure_here
+  constant a3 : positive := a * (a/a + 1);  -- No_failure_here
+  constant b1 : natural  := b + 1;          -- No_failure_here
+  constant b2 : natural  := b + b;          -- No_failure_here
+  constant b3 : natural  := b * (b/b + 1);  -- No_failure_here
+  constant b4 : natural  := b - b;          -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    a   = 1   and
+                   b   = 1   and
+                   a1   = 2   and
+                   a2   = 2   and
+                   a3   = 2   and
+                   b1   = 2   and
+                   b2   = 2   and
+                   b3   = 2   and
+                   b4   = 0   )
+      report "***PASSED TEST: c04s03b01x01p02n01i00036"
+      severity NOTE;
+    assert (    a   = 1   and
+                b   = 1   and
+                a1   = 2   and
+                a2   = 2   and
+                a3   = 2   and
+                b1   = 2   and
+                b2   = 2   and
+                b3   = 2   and
+                b4   = 0   )
+      report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd
new file mode 100644
index 0000000..48a0e28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc361.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00361ent IS
+END c03s02b01x01p02n01i00361ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00361arch OF c03s02b01x01p02n01i00361ent IS
+  type MVL1 is ('0', '1');
+  type MVL2 is ('X', 'Z');
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for I in MVL1'POS('0') to MVL2'POS('Z') loop  -- No_failure_here
+      k := k + 1;
+    end loop;
+    assert NOT(k=2) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00361" 
+      severity NOTE;
+    assert (k=2) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00361 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00361arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd
new file mode 100644
index 0000000..7c92198
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc364.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00364ent IS
+END c03s02b01x01p03n01i00364ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00364arch OF c03s02b01x01p03n01i00364ent IS
+  subtype    decade is integer;
+  type       MVL_vector is array (positive range 1 to 50) of decade range 2 to 5;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(1)  := 2;
+    k(50) := 5;
+    assert NOT (k(1)=2 and k(50)=5) 
+      report "***PASSED TEST: c03s02b01x01p03n01i00364" 
+      severity NOTE;
+    assert (k(1)=2 and k(50)=5) 
+      report "***FAILED TEST: c03s02b01x01p03n01i00364 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd
new file mode 100644
index 0000000..4694654
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc365.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00365ent IS
+END c03s02b01x01p03n01i00365ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00365arch OF c03s02b01x01p03n01i00365ent IS
+  subtype decade is integer;
+  type MVL_vector is array (decade range 1 to 50) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(1)  := 2;
+    k(50) := 5;
+    assert NOT (k(1)=2 and k(50)=5) 
+      report "***PASSED TEST: c03s02b01x01p03n01i00365" 
+      severity NOTE;
+    assert (k(1)=2 and k(50)=5) 
+      report "***FAILED TEST: c03s02b01x01p03n01i00365 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd
new file mode 100644
index 0000000..e0a7c54
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc366.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00366ent IS
+END c03s02b01x01p03n01i00366ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00366arch OF c03s02b01x01p03n01i00366ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type tribit is array (natural range <>) of MVL;
+  subtype word is tribit (0 to 16); -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : word;
+  BEGIN
+    k(0)  := '0';
+    k(16) := 'Z';
+    assert NOT (k(0)='0' and k(16)='Z') 
+      report "***PASSED TEST: c03s02b01x01p03n01i00366" 
+      severity NOTE;
+    assert (k(0)='0' and k(16)='Z') 
+      report "***FAILED TEST: c03s02b01x01p03n01i00366 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd
new file mode 100644
index 0000000..fa011ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc37.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00037ent IS
+END c04s03b01x01p02n01i00037ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00037arch OF c04s03b01x01p02n01i00037ent IS
+  constant C1 : Boolean   := true; -- No_failure_here
+  constant C2 : bit       := '0';  -- No_failure_here
+  constant C3 : integer   := 123;  -- No_failure_here
+  constant C4 : positive  := 34;   -- No_failure_here
+  constant C5 : natural   := 12;   -- No_failure_here
+  constant C6 : real      := 1.20; -- No_failure_here
+  constant C7 : character := 'C';  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    C1   = true   and
+                   C2   = '0'   and
+                   C3   = 123   and
+                   C4   = 34   and
+                   C5   = 12   and
+                   C6   = 1.20   and
+                   C7   = 'C'   )   
+      report "***PASSED TEST: c04s03b01x01p02n01i00037"
+      severity NOTE;
+    assert (    C1   = true   and
+                C2   = '0'   and
+                C3   = 123   and
+                C4   = 34   and
+                C5   = 12   and
+                C6   = 1.20   and
+                C7   = 'C'   )   
+      report "***FAILED TEST: c04s03b01x01p02n01i00037 - Constant declaration syntactic format test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd
new file mode 100644
index 0000000..d33bd8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc376.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00376ent IS
+END c03s02b01x01p03n03i00376ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00376arch OF c03s02b01x01p03n03i00376ent IS
+  type my_word is array (0 to 3) of bit;
+  type it     is array (integer range my_word'range) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable itt : it;
+  BEGIN
+    assert NOT(itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0') 
+      report "***PASSED TEST: c03s02b01x01p03n03i00376" 
+      severity NOTE;
+    assert (itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0') 
+      report "***FAILED TEST: c03s02b01x01p03n03i00376 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00376arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd
new file mode 100644
index 0000000..13af3f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc377.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00377ent IS
+END c03s02b01x01p03n03i00377ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00377arch OF c03s02b01x01p03n03i00377ent IS
+  type it2 is array (bit range '0' to '1') of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : it2;
+  BEGIN
+    k('0') := '1';
+    k('1') := '0';
+    assert NOT (   k('0') = '1' and 
+                   k('1') = '0') 
+      report "***PASSED TEST: c03s02b01x01p03n03i00377" 
+      severity NOTE;
+    assert  (   k('0') = '1' and 
+                k('1') = '0') 
+      report "***FAILED TEST: c03s02b01x01p03n03i00377 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00377arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd
new file mode 100644
index 0000000..1204064
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00378ent IS
+END c03s02b01x01p03n03i00378ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
+  type       M1 is array (positive range <>) of integer;
+  subtype    M2 is M1 (2 to 200);    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : M2;
+  BEGIN
+    k(2)   := 2;
+    k(200) := 200;
+    assert NOT (   k(2) = 2 and 
+                   k(200) = 200) 
+      report "***PASSED TEST: c03s02b01x01p03n03i00378"
+      severity NOTE;
+    assert  (   k(2) = 2 and 
+                k(200) = 200) 
+      report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00378arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd
new file mode 100644
index 0000000..e316b8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc38.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00038ent IS
+END c04s03b01x01p02n01i00038ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00038arch OF c04s03b01x01p02n01i00038ent IS
+  constant C1 : Boolean := ( (2 >= 1) or ( (1 <= 10) and (2 = 1 + 1) ) );
+                                        -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = true )
+      report "***PASSED TEST: c04s03b01x01p02n01i00038"
+      severity NOTE;
+    assert ( C1 = true )
+      report "***FAILED TEST: c04s03b01x01p02n01i00038 - A complex expression assigned to the constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd
new file mode 100644
index 0000000..cc0812a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc381.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00381ent IS
+END c03s02b01x01p04n01i00381ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00381arch OF c03s02b01x01p04n01i00381ent IS
+  type bit_vctor is array (bit range '0' to '1') of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k('0') := 1;
+    k('1') := 0;
+    assert NOT (k('0') = 1 and
+                k('1') = 0 ) 
+      report "***PASSED TEST: c03s02b01x01p04n01i00381" 
+      severity NOTE;
+    assert     (k('0') = 1 and
+                k('1') = 0 ) 
+      report "***FAILED TEST: c03s02b01x01p04n01i00381 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00381arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd
new file mode 100644
index 0000000..2bd6790
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc382.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00382ent IS
+END c03s02b01x01p04n01i00382ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00382arch OF c03s02b01x01p04n01i00382ent IS
+  type days is (sun, mon, tue, wed, thu, fri, sat);
+  type bit_vctor is array (days range mon to fri) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(mon) := 1;
+    k(tue) := 2;
+    k(wed) := 3;
+    k(thu) := 4;
+    k(fri) := 5;
+    assert NOT (   k(mon) = 1 and 
+                   k(tue) = 2 and
+                   k(wed) = 3 and 
+                   k(thu) = 4 and 
+                   k(fri) = 5 )
+      report "***PASSED TEST: c03s02b01x01p04n01i00382"
+      severity NOTE;
+    assert  (   k(mon) = 1 and 
+                k(tue) = 2 and
+                k(wed) = 3 and 
+                k(thu) = 4 and 
+                k(fri) = 5 )
+      report "***FAILED TEST: c03s02b01x01p04n01i00382 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00382arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd
new file mode 100644
index 0000000..ea4abe9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc385.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n02i00385ent IS
+END c03s02b01x01p04n02i00385ent;
+
+ARCHITECTURE c03s02b01x01p04n02i00385arch OF c03s02b01x01p04n02i00385ent IS
+  type bit_vctor is array (10 to 7) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s02b01x01p04n02i00385"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n02i00385arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd
new file mode 100644
index 0000000..f7766cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc386.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n02i00386ent IS
+END c03s02b01x01p04n02i00386ent;
+
+ARCHITECTURE c03s02b01x01p04n02i00386arch OF c03s02b01x01p04n02i00386ent IS
+  type bit_vctor is array (0 downto 7) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s02b01x01p04n02i00386"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n02i00386arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd
new file mode 100644
index 0000000..70b63c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc387.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n03i00387ent IS
+END c03s02b01x01p04n03i00387ent;
+
+ARCHITECTURE c03s02b01x01p04n03i00387arch OF c03s02b01x01p04n03i00387ent IS
+  type M1 is array (positive range 1 to 5) of integer;
+  signal S1 : M1 := (1,2,3,4,5); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S1(1)=1 and
+               S1(2)=2 and
+               S1(3)=3 and
+               S1(4)=4 and
+               S1(5)=5 )
+      report "***PASSED TEST: c03s02b01x01p04n03i00387"
+      severity NOTE;
+    assert (   S1(1)=1 and
+               S1(2)=2 and
+               S1(3)=3 and
+               S1(4)=4 and
+               S1(5)=5 )
+      report "***FAILED TEST: c03s02b01x01p04n03i00387 - An array value staisfies an index constraint if at each index position the array value and the index constrint have the same index range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n03i00387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd
new file mode 100644
index 0000000..f57f55c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc388.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n03i00388ent IS
+END c03s02b01x01p04n03i00388ent;
+
+ARCHITECTURE c03s02b01x01p04n03i00388arch OF c03s02b01x01p04n03i00388ent IS
+  type SQ_ARR is array(0 to 1, 0 to 2) of BIT;
+BEGIN
+  TESTING: PROCESS
+    variable M2 :  SQ_ARR :=  (('0','1','1'),('1','0','0')); -- No_failure_here
+  BEGIN
+    assert NOT(    M2(0,0)='0' and
+                   M2(0,1)='1' and
+                   M2(0,2)='1' and
+                   M2(1,0)='1' and
+                   M2(1,1)='0' and
+                   M2(1,2)='0')   
+      report "***PASSED TEST: c03s02b01x01p04n03i00388"
+      severity NOTE;
+    assert (    M2(0,0)='0' and
+                M2(0,1)='1' and
+                M2(0,2)='1' and
+                M2(1,0)='1' and
+                M2(1,1)='0' and
+                M2(1,2)='0')   
+      report "***FAILED TEST: c03s02b01x01p04n03i00388 - An array value staisfies an index constraint if at each index position the array value and the index constrint have the same index range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n03i00388arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd
new file mode 100644
index 0000000..2b55041
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00039ent IS
+END c04s03b01x01p02n01i00039ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
+  constant C1 : Boolean := 10 = 10;    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = true )
+      report "***PASSED TEST: c04s03b01x01p02n01i00039"
+      severity NOTE;
+    assert ( C1 = true )
+      report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd
new file mode 100644
index 0000000..3f61c4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc392.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00392ent IS
+END c03s02b01x01p06n01i00392ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00392arch OF c03s02b01x01p06n01i00392ent IS
+  type   M1 is array (positive range <>) of integer;
+  signal S1 : M1(3 to 30) ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1(3)  <= 3  after 3 ns;
+    S1(30) <= 30 after 3 ns;
+    wait for 10 ns;
+    assert NOT(S1(3)=3 and S1(30)=30) 
+      report "***PASSED TEST: c03s02b01x01p06n01i00392" 
+      severity NOTE;
+    assert (S1(3)=3 and S1(30)=30) 
+      report "***FAILED TEST: c03s02b01x01p06n01i00392 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd
new file mode 100644
index 0000000..570bedf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc393.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00393ent IS
+END c03s02b01x01p06n01i00393ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00393arch OF c03s02b01x01p06n01i00393ent IS
+  type   M1 is array (positive range <>) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : M1(4 to 10) ;  -- No_failure_here
+  BEGIN
+    V1(4)   := 4;
+    V1(10)   := 10;
+    assert NOT(V1(4)=4 and V1(10)=10)
+      report "***PASSED TEST: c03s02b01x01p06n01i00393" 
+      severity NOTE;
+    assert (V1(4)=4 and V1(10)=10)
+      report "***FAILED TEST: c03s02b01x01p06n01i00393 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00393arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd
new file mode 100644
index 0000000..46acb77
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc395.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00395ent IS
+END c03s02b01x01p06n02i00395ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00395arch OF c03s02b01x01p06n02i00395ent IS
+  type A1 is array (positive range 1 to 2) of BOOLEAN;
+
+  type R1 is record
+               RE1: A1;  -- no_failure_here
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : R1;
+  BEGIN
+    k.RE1(1) := TRUE;
+    k.RE1(2) := FALSE;
+    assert NOT(    k.RE1(1) = TRUE and 
+                   k.RE1(2) = FALSE )
+      report "***PASSED TEST: c03s02b01x01p06n02i00395"
+      severity NOTE;
+    assert (    k.RE1(1) = TRUE and 
+                k.RE1(2) = FALSE )
+      report "***FAILED TEST: c03s02b01x01p06n02i00395 - Record element cannot be an unconstrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00395arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd
new file mode 100644
index 0000000..1eedb7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc397.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00397ent IS
+END c03s02b01x01p06n02i00397ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00397arch OF c03s02b01x01p06n02i00397ent IS
+  type I1 is range 1 to 5;
+  type M1 is array (positive range 1 to 6) of integer;
+  type M2 is array (I1'(1) to I1'(2)) of M1; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : M2;
+  BEGIN
+    k(1) := (1,2,3,4,5,6);
+    k(2) := (7,8,9,10,11,12);
+    assert NOT(k(1)=(1,2,3,4,5,6) and k(2)=(7,8,9,10,11,12)) 
+      report "***PASSED TEST: c03s02b01x01p06n02i00397" 
+      severity NOTE;
+    assert (k(1)=(1,2,3,4,5,6) and k(2)=(7,8,9,10,11,12)) 
+      report "***FAILED TEST: c03s02b01x01p06n02i00397 - Array element cannot be an unconstrained array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00397arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd
new file mode 100644
index 0000000..8ec5644
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc398.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p07n01i00398ent IS
+END c03s02b01x01p07n01i00398ent;
+
+ARCHITECTURE c03s02b01x01p07n01i00398arch OF c03s02b01x01p07n01i00398ent IS
+  constant X : BIT_VECTOR := "0101";
+BEGIN
+  TESTING: PROCESS
+    variable i : integer;
+  BEGIN
+    i   := X'length;
+    assert NOT(i=4)
+      report "***PASSED TEST: c03s02b01x01p07n01i00398"
+      severity NOTE;
+    assert (i=4)
+      report "***FAILED TEST: c03s02b01x01p07n01i00398 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p07n01i00398arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd
new file mode 100644
index 0000000..b41f7d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc399.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p07n01i00399ent IS
+END c03s02b01x01p07n01i00399ent;
+
+ARCHITECTURE c03s02b01x01p07n01i00399arch OF c03s02b01x01p07n01i00399ent IS
+  constant X : BIT_VECTOR(0 to 3) := "0101";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
+      report "***PASSED TEST: c03s02b01x01p07n01i00399"
+      severity NOTE;
+    assert (X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
+      report "***FAILED TEST: c03s02b01x01p07n01i00399 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p07n01i00399arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd
new file mode 100644
index 0000000..f273bdd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc40.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00040ent IS
+END c04s03b01x01p02n01i00040ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00040arch OF c04s03b01x01p02n01i00040ent IS
+  constant C1 : Real := ( (1.23 + 1.45) - (6.04 - 5.99) + ((2.4) / (1.2)) );
+                                        -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = 4.63 )
+      report "***PASSED TEST: c04s03b01x01p02n01i00040"
+      severity NOTE;
+    assert ( C1 = 4.63 )
+      report "***FAILED TEST: c04s03b01x01p02n01i00040- A complex real expression assigned to the real constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd
new file mode 100644
index 0000000..9fb403a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p08n01i00400ent IS
+END c03s02b01x01p08n01i00400ent;
+
+ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS
+  type       MEM is array (positive range <>) of BIT;
+  attribute    X  : MEM;
+  attribute    X of MEM: type is ('1','0','1') ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
+      report "***PASSED TEST: c03s02b01x01p08n01i00400"
+      severity NOTE;
+    assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
+      report "***FAILED TEST: c03s02b01x01p08n01i00400 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p08n01i00400arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd
new file mode 100644
index 0000000..c22b7a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc401.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p09n01i00401ent IS
+END c03s02b01x01p09n01i00401ent;
+
+ARCHITECTURE c03s02b01x01p09n01i00401arch OF c03s02b01x01p09n01i00401ent IS
+  type MEM is array (integer range <>) of BIT;
+  type LIN is access MEM;
+BEGIN
+  TESTING: PROCESS
+    variable HD : LIN := new MEM'("000111000");   -- No_failure_here
+  BEGIN
+    assert NOT(HD.all = "000111000")
+      report "***PASSED TEST: c03s02b01x01p09n01i00401"
+      severity NOTE;
+    assert (HD.all = "000111000")
+      report "***FAILED TEST: c03s02b01x01p09n01i00401 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p09n01i00401arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd
new file mode 100644
index 0000000..bef475b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc402.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p11n01i00402ent IS
+END c03s02b01x01p11n01i00402ent;
+
+ARCHITECTURE c03s02b01x01p11n01i00402arch OF c03s02b01x01p11n01i00402ent IS
+  function WR_OR(Input : BIT_VECTOR) return BIT is
+  begin
+    for I in Input'Range loop
+      if Input(I) = '1' then
+        return '1';
+      end if;
+    end loop;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BIT_VECTOR(0 to 3) := "0101" ;
+    variable V2 : BIT;
+  BEGIN
+    V2 := WR_OR(V1) ;  -- No_failure_here
+    assert NOT(V2 = '1')
+      report "***PASSED TEST: c03s02b01x01p11n01i00402"
+      severity NOTE;
+    assert ( V2 = '1' )
+      report "***FAILED TEST: c03s02b01x01p11n01i00402 - For a formal parameter of a subprogram that is of an unconstrained array type, the index ranges are obtained from the corresponding association element in the applicable subprogram call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p11n01i00402arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd
new file mode 100644
index 0000000..cb8465d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc403.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p18n01i00403ent IS
+END c03s02b01x01p18n01i00403ent;
+
+ARCHITECTURE c03s02b01x01p18n01i00403arch OF c03s02b01x01p18n01i00403ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5) ;
+  function WR_OR(Input : ME1) return M1 is
+  begin
+    for I in Input'Range loop
+      if Input(I) = 20 then
+        return "11111" ;
+      end if;
+    end loop;
+  end WR_OR;
+  procedure F2 (X1 : in MEM) is
+  begin
+    assert NOT(X1="11111")
+      report "***PASSED TEST: c03s02b01x01p18n01i00403"
+      severity NOTE;
+    assert (X1="11111")
+      report "***FAILED TEST: c03s02b01x01p18n01i00403 - "
+      severity ERROR;
+  end F2;
+BEGIN
+  TESTING: PROCESS
+    variable V1 :ME2  := (10, 20, 30, 40);
+  BEGIN
+    F2(WR_OR(V1)) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p18n01i00403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd
new file mode 100644
index 0000000..eda2042
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc404.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p18n01i00404ent IS
+END c03s02b01x01p18n01i00404ent;
+
+ARCHITECTURE c03s02b01x01p18n01i00404arch OF c03s02b01x01p18n01i00404ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5) ;
+  procedure F2 (X1 : in MEM) is
+  begin
+    assert NOT((X1'LOW = 1) and (X1'High = 5))
+      report "***PASSED TEST: c03s02b01x01p18n01i00404" 
+      SEVERITY NOTE;
+    assert ((X1'LOW = 1) and (X1'High = 5))
+      report "***FAILED TEST: c03s02b01x01p18n01i00404 - The index ranges are obtained from the actual designator." 
+      SEVERITY ERROR;
+  end F2;
+  signal S1 : M1 := "01110" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    F2(S1) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p18n01i00404arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd
new file mode 100644
index 0000000..b6a822b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc406.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00406ent IS
+END c03s02b01x01p19n01i00406ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00406arch OF c03s02b01x01p19n01i00406ent IS
+
+  constant C1 : boolean := true;
+
+  function complex_scalar(s : boolean) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean;
+  signal S2 : boolean;
+  signal S3 : boolean := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00406" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00406 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00406arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd
new file mode 100644
index 0000000..9ceaa0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc407.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00407ent IS
+END c03s02b01x01p19n01i00407ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00407arch OF c03s02b01x01p19n01i00407ent IS
+
+  constant C1 : bit := '1';
+
+  function complex_scalar(s : bit) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return bit is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : bit;
+  signal S2 : bit;
+  signal S3 : bit := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00407" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00407 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00407arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd
new file mode 100644
index 0000000..766774a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc408.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00408ent IS
+END c03s02b01x01p19n01i00408ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00408arch OF c03s02b01x01p19n01i00408ent IS
+
+  constant C1 : character := 's';
+
+  function complex_scalar(s : character) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return character is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : character;
+  signal S2 : character;
+  signal S3 : character := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00408" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00408 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00408arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd
new file mode 100644
index 0000000..fe818a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc409.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00409ent IS
+END c03s02b01x01p19n01i00409ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00409arch OF c03s02b01x01p19n01i00409ent IS
+
+  constant C1 : severity_level := note;
+
+  function complex_scalar(s : severity_level) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level;
+  signal S2 : severity_level;
+  signal S3 : severity_level := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00409" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00409 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00409arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd
new file mode 100644
index 0000000..1b6c3ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00041ent IS
+END c04s03b01x01p02n01i00041ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
+  constant B1 : Bit := '0';         -- No_failure_here
+  constant B2 : Character := '0';   -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( B1 = '0' and B2 = '0' )
+      report "***PASSED TEST: c04s03b01x01p02n01i00041"
+      severity NOTE;
+    assert ( B1 = '0' and B2 = '0' )
+      report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd
new file mode 100644
index 0000000..5fb3c3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc410.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00410ent IS
+END c03s02b01x01p19n01i00410ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00410arch OF c03s02b01x01p19n01i00410ent IS
+
+  constant C1 : integer := 3;
+
+  function complex_scalar(s : integer) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer;
+  signal S2 : integer;
+  signal S3 : integer := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00410" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00410 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00410arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd
new file mode 100644
index 0000000..2cf3762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc411.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00411ent IS
+END c03s02b01x01p19n01i00411ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00411arch OF c03s02b01x01p19n01i00411ent IS
+
+  constant C1 : real := 3.0;
+
+  function complex_scalar(s : real) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real;
+  signal S2 : real;
+  signal S3 : real := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00411" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00411 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00411arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd
new file mode 100644
index 0000000..dfab23f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc412.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00412ent IS
+END c03s02b01x01p19n01i00412ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00412arch OF c03s02b01x01p19n01i00412ent IS
+
+  constant C1 : time := 3 ns;
+
+  function complex_scalar(s : time) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time;
+  signal S2 : time;
+  signal S3 : time := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00412" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00412 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd
new file mode 100644
index 0000000..44f3a28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc413.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00413ent IS
+END c03s02b01x01p19n01i00413ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00413arch OF c03s02b01x01p19n01i00413ent IS
+
+  constant C1 : natural := 1;
+
+  function complex_scalar(s : natural) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural;
+  signal S2 : natural;
+  signal S3 : natural := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00413" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00413 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00413arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd
new file mode 100644
index 0000000..4eed7e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc414.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00414ent IS
+END c03s02b01x01p19n01i00414ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00414arch OF c03s02b01x01p19n01i00414ent IS
+
+  constant C1 : positive := 1;
+
+  function complex_scalar(s : positive) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive;
+  signal S2 : positive;
+  signal S3 : positive := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00414" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00414 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00414arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd
new file mode 100644
index 0000000..6a2225c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc415.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00415ent IS
+END c03s02b01x01p19n01i00415ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00415arch OF c03s02b01x01p19n01i00415ent IS
+
+  type       boolean_cons_vector is array (15 downto 0) of boolean;
+  constant    C1 : boolean_cons_vector := (others => true);
+
+  function complex_scalar(s : boolean_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_cons_vector;
+  signal S2 : boolean_cons_vector;
+  signal S3 : boolean_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00415" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00415 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00415arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd
new file mode 100644
index 0000000..6d7ad56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc416.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00416ent IS
+END c03s02b01x01p19n01i00416ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00416arch OF c03s02b01x01p19n01i00416ent IS
+
+  type       severity_level_cons_vector is array (15 downto 0) of severity_level;
+  constant    C1 : severity_level_cons_vector := (others => note);
+
+  function complex_scalar(s : severity_level_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_cons_vector;
+  signal S2 : severity_level_cons_vector;
+  signal S3 : severity_level_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00416" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00416 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00416arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd
new file mode 100644
index 0000000..2a560ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00417ent IS
+END c03s02b01x01p19n01i00417ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
+
+  type       real_cons_vector is array (15 downto 0) of real;
+  constant    C1 : real_cons_vector := (others => 3.0);
+
+  function complex_scalar(s : real_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_cons_vector;
+  signal S2 : real_cons_vector;
+  signal S3 : real_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00417" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00417arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd
new file mode 100644
index 0000000..0049171
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00418ent IS
+END c03s02b01x01p19n01i00418ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
+
+  type       integer_cons_vector is array (15 downto 0) of integer;
+  constant    C1 : integer_cons_vector := (others => 3);
+
+  function complex_scalar(s : integer_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_cons_vector;
+  signal S2 : integer_cons_vector;
+  signal S3 : integer_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00418" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00418arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd
new file mode 100644
index 0000000..cd42bcb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc419.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00419ent IS
+END c03s02b01x01p19n01i00419ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00419arch OF c03s02b01x01p19n01i00419ent IS
+
+  type       time_cons_vector is array (15 downto 0) of time;
+  constant    C1 : time_cons_vector := (others => 3 ns);
+
+  function complex_scalar(s : time_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_cons_vector;
+  signal S2 : time_cons_vector;
+  signal S3 : time_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00419" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00419 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00419arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd
new file mode 100644
index 0000000..5bb5fbb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc420.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00420ent IS
+END c03s02b01x01p19n01i00420ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00420arch OF c03s02b01x01p19n01i00420ent IS
+
+  type       natural_cons_vector is array (15 downto 0) of natural;
+  constant    C1 : natural_cons_vector := (others => 1);
+
+  function complex_scalar(s : natural_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_cons_vector;
+  signal S2 : natural_cons_vector;
+  signal S3 : natural_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00420" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00420 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00420arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd
new file mode 100644
index 0000000..67f6e4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc421.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00421ent IS
+END c03s02b01x01p19n01i00421ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00421arch OF c03s02b01x01p19n01i00421ent IS
+
+  type       positive_cons_vector is array (15 downto 0) of positive;
+  constant    C1 : positive_cons_vector := (others => 1);
+
+  function complex_scalar(s : positive_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_cons_vector;
+  signal S2 : positive_cons_vector;
+  signal S3 : positive_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00421" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00421 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd
new file mode 100644
index 0000000..02585b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00422ent IS
+END c03s02b01x01p19n01i00422ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
+
+  type       boolean_cons_vector is array (15 downto 0) of boolean;
+  type       boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  constant    C1 : boolean_cons_vectorofvector := (others => (others => true));
+
+  function complex_scalar(s : boolean_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_cons_vectorofvector;
+  signal S2 : boolean_cons_vectorofvector;
+  signal S3 : boolean_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00422" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00422arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd
new file mode 100644
index 0000000..c220456
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc423.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00423ent IS
+END c03s02b01x01p19n01i00423ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00423arch OF c03s02b01x01p19n01i00423ent IS
+
+  type       severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type       severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  constant    C1 : severity_level_cons_vectorofvector := (others => (others => note));
+
+  function complex_scalar(s : severity_level_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_cons_vectorofvector;
+  signal S2 : severity_level_cons_vectorofvector;
+  signal S3 : severity_level_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00423" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00423 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00423arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd
new file mode 100644
index 0000000..599c709
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc424.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00424ent IS
+END c03s02b01x01p19n01i00424ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00424arch OF c03s02b01x01p19n01i00424ent IS
+
+  type       integer_cons_vector is array (15 downto 0) of integer;
+  type       integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
+  constant    C1 : integer_cons_vectorofvector := (others => (others => 3));
+
+  function complex_scalar(s : integer_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_cons_vectorofvector;
+  signal S2 : integer_cons_vectorofvector;
+  signal S3 : integer_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00424"
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00424 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00424arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd
new file mode 100644
index 0000000..405096c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc425.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00425ent IS
+END c03s02b01x01p19n01i00425ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00425arch OF c03s02b01x01p19n01i00425ent IS
+
+  type       real_cons_vector is array (15 downto 0) of real;
+  type       real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  constant    C1 : real_cons_vectorofvector := (others => (others => 3.0));
+
+  function complex_scalar(s : real_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_cons_vectorofvector;
+  signal S2 : real_cons_vectorofvector;
+  signal S3 : real_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00425" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00425 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd
new file mode 100644
index 0000000..c338283
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc426.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00426ent IS
+END c03s02b01x01p19n01i00426ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00426arch OF c03s02b01x01p19n01i00426ent IS
+
+  type       time_cons_vector is array (15 downto 0) of time;
+  type       time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  constant    C1 : time_cons_vectorofvector := (others => (others => 3 ns));
+
+  function complex_scalar(s : time_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_cons_vectorofvector;
+  signal S2 : time_cons_vectorofvector;
+  signal S3 : time_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00426" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00426 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00426arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd
new file mode 100644
index 0000000..b13ee7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc427.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00427ent IS
+END c03s02b01x01p19n01i00427ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00427arch OF c03s02b01x01p19n01i00427ent IS
+
+  type       natural_cons_vector is array (15 downto 0) of natural;
+  type       natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  constant    C1 : natural_cons_vectorofvector := (others => (others => 1));
+
+  function complex_scalar(s : natural_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_cons_vectorofvector;
+  signal S2 : natural_cons_vectorofvector;
+  signal S3 : natural_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00427" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00427 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00427arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd
new file mode 100644
index 0000000..4c46091
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc428.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00428ent IS
+END c03s02b01x01p19n01i00428ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00428arch OF c03s02b01x01p19n01i00428ent IS
+
+  type       positive_cons_vector is array (15 downto 0) of positive;
+  type       positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  constant    C1 : positive_cons_vectorofvector := (others => (others => 1));
+
+  function complex_scalar(s : positive_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_cons_vectorofvector;
+  signal S2 : positive_cons_vectorofvector;
+  signal S3 : positive_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00428" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00428 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00428arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd
new file mode 100644
index 0000000..cc123e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc429.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00429ent IS
+END c03s02b01x01p19n01i00429ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00429arch OF c03s02b01x01p19n01i00429ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2boolean_cons_vector is array (row,column) of boolean;
+  constant    C1 : s2boolean_cons_vector := (others => (others => true));
+
+  function complex_scalar(s : s2boolean_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2boolean_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2boolean_cons_vector;
+  signal S2 : s2boolean_cons_vector;
+  signal S3 : s2boolean_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00429" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00429 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00429arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd
new file mode 100644
index 0000000..a48679e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc43.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00043ent IS
+END c04s03b01x01p02n01i00043ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00043arch OF c04s03b01x01p02n01i00043ent IS
+  constant integer:integer := 1;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(integer = 1)
+      report "***PASSED TEST: c04s03b01x01p02n01i00043" 
+      severity NOTE;
+    assert (integer = 1)
+      report "***FAILED TEST:c04s03b01x01p02n01i00043 - Constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd
new file mode 100644
index 0000000..755215b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc430.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00430ent IS
+END c03s02b01x01p19n01i00430ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00430arch OF c03s02b01x01p19n01i00430ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2bit_cons_vector is array (row,column) of bit;
+  constant    C1 : s2bit_cons_vector := (others => (others => '1'));
+
+  function complex_scalar(s : s2bit_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2bit_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2bit_cons_vector;
+  signal S2 : s2bit_cons_vector;
+  signal S3 : s2bit_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00430" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00430 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00430arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd
new file mode 100644
index 0000000..042fa3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc431.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00431ent IS
+END c03s02b01x01p19n01i00431ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00431arch OF c03s02b01x01p19n01i00431ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2char_cons_vector is array (row,column) of character;
+  constant    C1 : s2char_cons_vector := (others => (others => 's'));
+
+  function complex_scalar(s : s2char_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2char_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2char_cons_vector;
+  signal S2 : s2char_cons_vector;
+  signal S3 : s2char_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00431" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00431 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00431arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd
new file mode 100644
index 0000000..b373ae6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc432.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00432ent IS
+END c03s02b01x01p19n01i00432ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00432arch OF c03s02b01x01p19n01i00432ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2severity_level_cons_vector is array (row,column) of severity_level;
+  constant    C1 : s2severity_level_cons_vector := (others => (others => note));
+
+  function complex_scalar(s : s2severity_level_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2severity_level_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2severity_level_cons_vector;
+  signal S2 : s2severity_level_cons_vector;
+  signal S3 : s2severity_level_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00432" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00432 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00432arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd
new file mode 100644
index 0000000..9fd67a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00433ent IS
+END c03s02b01x01p19n01i00433ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2integer_cons_vector is array (row,column) of integer;
+  constant    C1 : s2integer_cons_vector := (others => (others => 3));
+
+  function complex_scalar(s : s2integer_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2integer_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2integer_cons_vector;
+  signal S2 : s2integer_cons_vector;
+  signal S3 : s2integer_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00433" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00433arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd
new file mode 100644
index 0000000..3c12114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00434ent IS
+END c03s02b01x01p19n01i00434ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2real_cons_vector is array (row,column) of real;
+  constant    C1 : s2real_cons_vector := (others => (others => 3.0));
+
+  function complex_scalar(s : s2real_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2real_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2real_cons_vector;
+  signal S2 : s2real_cons_vector;
+  signal S3 : s2real_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00434" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00434arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd
new file mode 100644
index 0000000..0123503
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc435.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00435ent IS
+END c03s02b01x01p19n01i00435ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00435arch OF c03s02b01x01p19n01i00435ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2time_cons_vector is array (row,column) of time;
+  constant    C1 : s2time_cons_vector := (others => (others => 3 ns));
+
+  function complex_scalar(s : s2time_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2time_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2time_cons_vector;
+  signal S2 : s2time_cons_vector;
+  signal S3 : s2time_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00435" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00435 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00435arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd
new file mode 100644
index 0000000..915c8d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc436.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00436ent IS
+END c03s02b01x01p19n01i00436ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00436arch OF c03s02b01x01p19n01i00436ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2natural_cons_vector is array (row,column) of natural;
+  constant    C1 : s2natural_cons_vector := (others => (others => 1));
+
+  function complex_scalar(s : s2natural_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2natural_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2natural_cons_vector;
+  signal S2 : s2natural_cons_vector;
+  signal S3 : s2natural_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00436" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00436 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00436arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd
new file mode 100644
index 0000000..f8df127
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc437.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00437ent IS
+END c03s02b01x01p19n01i00437ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00437arch OF c03s02b01x01p19n01i00437ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2positive_cons_vector is array (row,column) of positive;
+  constant    C1 : s2positive_cons_vector := (others => (others => 1));
+
+  function complex_scalar(s : s2positive_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2positive_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2positive_cons_vector;
+  signal S2 : s2positive_cons_vector;
+  signal S3 : s2positive_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00437" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00437 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00437arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd
new file mode 100644
index 0000000..e9dca6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc438.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00438ent IS
+END c03s02b01x01p19n01i00438ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00438arch OF c03s02b01x01p19n01i00438ent IS
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant    C10 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+  function complex_scalar(s : record_std_package) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_std_package is
+  begin
+    return C10;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_std_package;
+  signal S2 : record_std_package;
+  signal S3 : record_std_package := C10;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C10) and (S2 = C10)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00438" 
+      severity NOTE;
+    assert ((S1 = C10) and (S2 = C10)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00438 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00438arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd
new file mode 100644
index 0000000..10ae3f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd
@@ -0,0 +1,137 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00439ent IS
+END c03s02b01x01p19n01i00439ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant    C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+
+  function complex_scalar(s : record_cons_array) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_cons_array is
+  begin
+    return C51;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_cons_array;
+  signal S2 : record_cons_array;
+  signal S3 : record_cons_array := C51;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C51) and (S2 = C51)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00439" 
+      severity NOTE;
+    assert ((S1 = C51) and (S2 = C51)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00439arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd
new file mode 100644
index 0000000..679f7c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc440.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00440ent IS
+END c03s02b01x01p19n01i00440ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00440arch OF c03s02b01x01p19n01i00440ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector       is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+
+  function complex_scalar(s : record_2cons_array) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_2cons_array is
+  begin
+    return C52;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_2cons_array;
+  signal S2 : record_2cons_array;
+  signal S3 : record_2cons_array := C52;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C52) and (S2 = C52)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00440" 
+      severity NOTE;
+    assert ((S1 = C52) and (S2 = C52)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00440 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00440arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd
new file mode 100644
index 0000000..8b1771d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00441ent IS
+END c03s02b01x01p19n01i00441ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector       is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector       is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+
+  function complex_scalar(s : record_cons_arrayofarray) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_cons_arrayofarray is
+  begin
+    return C53;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_cons_arrayofarray;
+  signal S2 : record_cons_arrayofarray;
+  signal S3 : record_cons_arrayofarray := C53;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C53) and (S2 = C53)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00441" 
+      severity NOTE;
+    assert ((S1 = C53) and (S2 = C53)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00441arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd
new file mode 100644
index 0000000..653e7be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc442.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00442ent IS
+END c03s02b01x01p19n01i00442ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00442arch OF c03s02b01x01p19n01i00442ent IS
+
+  type boolean_vector       is array (natural range <>) of boolean;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+
+  constant C1 : boolean    := true;
+
+  constant C70 : boolean_vector_st :=(others => C1);
+
+  function complex_scalar(s : boolean_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_vector_st;
+  signal S2 : boolean_vector_st;
+  signal S3 : boolean_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00442" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00442 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00442arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd
new file mode 100644
index 0000000..ebba779
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc443.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00443ent IS
+END c03s02b01x01p19n01i00443ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00443arch OF c03s02b01x01p19n01i00443ent IS
+
+  type severity_level_vector is array (natural range <>) of severity_level;
+
+  subtype severity_level_vector_st    is severity_level_vector(0 to 15);
+
+  constant C1 : severity_level    := note;
+
+  constant C70 : severity_level_vector_st :=(others => C1);
+
+  function complex_scalar(s : severity_level_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_vector_st;
+  signal S2 : severity_level_vector_st;
+  signal S3 : severity_level_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00443" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00443 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00443arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd
new file mode 100644
index 0000000..4b566f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc444.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00444ent IS
+END c03s02b01x01p19n01i00444ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00444arch OF c03s02b01x01p19n01i00444ent IS
+
+  type integer_vector       is array (natural range <>) of integer;
+  subtype integer_vector_st    is integer_vector(0 to 15);
+
+  constant C1 : integer    := 4;
+
+  constant C70 : integer_vector_st :=(others => C1);
+
+  function complex_scalar(s : integer_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_vector_st;
+  signal S2 : integer_vector_st;
+  signal S3 : integer_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00444" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00444 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00444arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd
new file mode 100644
index 0000000..810a144
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00445ent IS
+END c03s02b01x01p19n01i00445ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS
+
+  type real_vector is array (natural range <>) of real;
+
+  subtype real_vector_st    is real_vector(0 to 15);
+
+  constant C1 : real    := 4.0;
+
+  constant C70 : real_vector_st :=(others => C1);
+
+  function complex_scalar(s : real_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_vector_st;
+  signal S2 : real_vector_st;
+  signal S3 : real_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00445" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00445arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd
new file mode 100644
index 0000000..b2aadd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc446.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00446ent IS
+END c03s02b01x01p19n01i00446ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00446arch OF c03s02b01x01p19n01i00446ent IS
+
+  type time_vector is array (natural range <>) of time;
+
+  subtype time_vector_st    is time_vector(0 to 15);
+
+  constant C1 : time    := 4 ns;
+
+  constant C70 : time_vector_st :=(others => C1);
+
+  function complex_scalar(s : time_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_vector_st;
+  signal S2 : time_vector_st;
+  signal S3 : time_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00446" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00446 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd
new file mode 100644
index 0000000..9bd4e84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc447.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00447ent IS
+END c03s02b01x01p19n01i00447ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00447arch OF c03s02b01x01p19n01i00447ent IS
+
+  type natural_vector is array (natural range <>) of natural;
+
+  subtype natural_vector_st    is natural_vector(0 to 15);
+
+  constant C1 : natural    := 4;
+
+  constant C70 : natural_vector_st :=(others => C1);
+
+  function complex_scalar(s : natural_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_vector_st;
+  signal S2 : natural_vector_st;
+  signal S3 : natural_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00447" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00447 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00447arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd
new file mode 100644
index 0000000..6777c0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc448.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00448ent IS
+END c03s02b01x01p19n01i00448ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00448arch OF c03s02b01x01p19n01i00448ent IS
+
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype positive_vector_st    is positive_vector(0 to 15);
+
+  constant C1 : positive    := 4;
+
+  constant C70 : positive_vector_st :=(others => C1);
+
+  function complex_scalar(s : positive_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_vector_st;
+  signal S2 : positive_vector_st;
+  signal S3 : positive_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00448" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00448 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd
new file mode 100644
index 0000000..098ef16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00449ent IS
+END c03s02b01x01p19n01i00449ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C70 : boolean_vector_st    :=(others => C1);
+  constant C71 : severity_level_vector_st   :=(others => C4);
+  constant C72 : integer_vector_st   :=(others => C5);
+  constant C73 : real_vector_st      :=(others => C6);
+  constant C74 : time_vector_st      :=(others => C7);
+  constant C75 : natural_vector_st   :=(others => C8);
+  constant C76 : positive_vector_st   :=(others => C9);
+
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+
+  function complex_scalar(s : record_array_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_array_st is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_array_st;
+  signal S2 : record_array_st;
+  signal S3 : record_array_st := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00449" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00449arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd
new file mode 100644
index 0000000..fdb2c86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc45.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00045ent IS
+END c04s03b01x01p02n01i00045ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00045arch OF c04s03b01x01p02n01i00045ent IS
+  type    T1_0 is array (integer range <>) of integer;
+  subtype    T1_1 is T1_0 (1 to 2);
+  subtype    T1_2 is T1_0 (1 to 4);
+
+  type    T2_0 is array (integer range <>) of T1_2;
+  subtype    T2_1 is T2_0 (1 to 2);
+  subtype    T2_2 is T2_0 (1 to 4);
+
+  -- Create some constants for constructing the real tests...
+  constant C1   : T1_1 := (1, 2);
+  constant C2   : T1_1 := C1;
+  constant C3   : T1_2 := (1, 2, 3, 4);
+  constant C4   : T1_2 := C3;
+
+  -- Success_here : on all constant declarations below
+  
+  constant C5   : T2_1 := ((1, 2, 3, 4), (5, 6, 7, 8));
+  constant C6   : T2_1 := (C3, C4);
+  constant C7   : T2_1 := (C1 & C2, C2 & C1);
+  constant C8   : T2_1 := (1 & 2 & C2, C3);
+  constant C10: T2_2 := ((1, 2, 3, 4), (5, 6, 7, 8),
+                         (9, 0, 1, 2), (3, 4, 5, 6));
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   C1 = (1,2)      and
+                  C2 = (1,2)      and
+                  C3 = (1,2,3,4)      and
+                  C4 = (1,2,3,4)      and
+                  C5 = ((1, 2, 3, 4), (5, 6, 7, 8))   and
+                  C6 = ((1, 2, 3, 4), (1, 2, 3, 4))   and
+                  C7 = ((1, 2, 1, 2), (1, 2, 1, 2))   and
+                  C8 = ((1, 2, 1, 2), (1, 2, 3, 4))   and
+                  C10= (   (1, 2, 3, 4), (5, 6, 7, 8),
+                           (9, 0, 1, 2), (3, 4, 5, 6))   )
+      report "***PASSED TEST: c04s03b01x01p02n01i00045"
+      severity NOTE;
+    assert (   C1 = (1,2)      and
+               C2 = (1,2)      and
+               C3 = (1,2,3,4)      and
+               C4 = (1,2,3,4)      and
+               C5 = ((1, 2, 3, 4), (5, 6, 7, 8))   and
+               C6 = ((1, 2, 3, 4), (1, 2, 3, 4))   and
+               C7 = ((1, 2, 1, 2), (1, 2, 1, 2))   and
+               C8 = ((1, 2, 1, 2), (1, 2, 3, 4))   and
+               C10= (   (1, 2, 3, 4), (5, 6, 7, 8),
+                        (9, 0, 1, 2), (3, 4, 5, 6))   )
+      report "***FAILED TEST: c04s03b01x01p02n01i00045 - Syntactic error in constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd
new file mode 100644
index 0000000..e06b208
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc450.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00450ent IS
+END c03s02b01x01p19n01i00450ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00450arch OF c03s02b01x01p19n01i00450ent IS
+
+  type four_value is ('Z','0','1','X');               --enumerated type
+
+  constant C77 : four_value := 'Z';
+
+  function complex_scalar(s : four_value) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value;
+  signal S2 : four_value;
+  signal S3 : four_value := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00450" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00450 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00450arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd
new file mode 100644
index 0000000..1bed837
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc451.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00451ent IS
+END c03s02b01x01p19n01i00451ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00451arch OF c03s02b01x01p19n01i00451ent IS
+
+  type four_value    is ('Z','0','1','X');               --enumerated type
+  type four_value_map   is array(four_value) of boolean;
+
+  constant C77 : four_value_map := (true,true,true,true);
+
+  function complex_scalar(s : four_value_map) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_map is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_map;
+  signal S2 : four_value_map;
+  signal S3 : four_value_map := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00451"
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00451 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00451arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd
new file mode 100644
index 0000000..6494f55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc452.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00452ent IS
+END c03s02b01x01p19n01i00452ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00452arch OF c03s02b01x01p19n01i00452ent IS
+
+  type    four_value    is ('Z','0','1','X');               --enumerated type
+  subtype binary       is four_value range '0' to '1';
+
+  constant C77 : binary := '0';
+
+  function complex_scalar(s : binary) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return binary is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : binary;
+  signal S2 : binary;
+  signal S3 : binary := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00452" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00452 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd
new file mode 100644
index 0000000..7cee687
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc453.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00453ent IS
+END c03s02b01x01p19n01i00453ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00453arch OF c03s02b01x01p19n01i00453ent IS
+
+  type    four_value       is ('Z','0','1','X');      --enumerated type
+  type    four_value_vector    is array (natural range <>) of four_value;
+
+  constant C77 : four_value_vector := ('1','0','1','0');
+
+  function complex_scalar(s : four_value_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_vector is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_vector(0 to 3);
+  signal S2 : four_value_vector(0 to 3);
+  signal S3 : four_value_vector(0 to 3) := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00453" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00453 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00453arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd
new file mode 100644
index 0000000..cc8b5f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc454.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00454ent IS
+END c03s02b01x01p19n01i00454ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00454arch OF c03s02b01x01p19n01i00454ent IS
+
+  type    byte is array(0 to 7) of bit;
+
+  constant C77 : byte := (others => '0');
+
+  function complex_scalar(s : byte) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return byte is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : byte;
+  signal S2 : byte;
+  signal S3 : byte := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00454"
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00454 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00454arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd
new file mode 100644
index 0000000..aafcd68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc455.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00455ent IS
+END c03s02b01x01p19n01i00455ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00455arch OF c03s02b01x01p19n01i00455ent IS
+
+  subtype    word is bit_vector(0 to  15);
+
+  constant C77 : word := (others => '0');
+
+  function complex_scalar(s : word) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return word is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : word;
+  signal S2 : word;
+  signal S3 : word := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00455" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00455 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00455arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd
new file mode 100644
index 0000000..f4de737
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc456.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00456ent IS
+END c03s02b01x01p19n01i00456ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00456arch OF c03s02b01x01p19n01i00456ent IS
+
+
+  type       four_value     is ('Z','0','1','X');
+  type       four_value_vector is array (natural range <>) of four_value;
+  function    resolution14(i:in four_value_vector) return four_value is
+    variable temp : four_value := 'Z';
+  begin
+    return temp;
+  end resolution14;
+
+  subtype    four_value_state is resolution14 four_value;
+  constant    C56 : four_value_state := 'Z';
+
+
+  function complex_scalar(s : four_value_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_state is
+  begin
+    return C56;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_state;
+  signal S2 : four_value_state;
+  signal S3 : four_value_state := C56;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C56) and (S2 = C56)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00456" 
+      severity NOTE;
+    assert ((S1 = C56) and (S2 = C56)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00456 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd
new file mode 100644
index 0000000..2fc9781
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc457.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00457ent IS
+END c03s02b01x01p19n01i00457ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00457arch OF c03s02b01x01p19n01i00457ent IS
+
+
+  type       four_value     is ('Z','0','1','X');
+  type       four_value_vector is array (natural range <>) of four_value;
+  function    resolution14(i:in four_value_vector) return four_value is
+    variable temp : four_value := 'Z';
+  begin
+    return temp;
+  end resolution14;
+
+  subtype    four_value_state is resolution14 four_value;
+  type       state_vector is array (natural range <>) of four_value_state;
+  constant    C63 : state_vector := ('Z','Z','Z','Z');
+
+  function complex_scalar(s : state_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return state_vector is
+  begin
+    return C63;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : state_vector(0 to 3);
+  signal S2 : state_vector(0 to 3);
+  signal S3 : state_vector(0 to 3) := C63;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C63) and (S2 = C63)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00457"
+      severity NOTE;
+    assert ((S1 = C63) and (S2 = C63)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00457 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd
new file mode 100644
index 0000000..6940f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc458.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00458ent IS
+END c03s02b01x01p19n01i00458ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00458arch OF c03s02b01x01p19n01i00458ent IS
+
+  subtype    word is bit_vector(0 to  15);
+  constant    size :integer := 7;
+  type       primary_memory is array(0 to size) of word;
+
+  constant    C61 : word := (others =>'0' );
+  constant    C64 : primary_memory := (others => C61);
+
+  function complex_scalar(s : primary_memory) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return primary_memory is
+  begin
+    return C64;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : primary_memory;
+  signal S2 : primary_memory;
+  signal S3 : primary_memory:= C64;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C64) and (S2 = C64)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00458" 
+      severity NOTE;
+    assert ((S1 = C64) and (S2 = C64)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00458 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd
new file mode 100644
index 0000000..d649a97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc459.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00459ent IS
+END c03s02b01x01p19n01i00459ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00459arch OF c03s02b01x01p19n01i00459ent IS
+
+  type       four_value    is ('Z','0','1','X');
+  subtype    binary       is four_value range '0' to '1';
+  subtype    word       is bit_vector(0 to  15);
+  constant    size :integer := 7;
+  type       primary_memory    is array(0 to size) of word;
+
+  type primary_memory_module is   
+    record   
+      enable      :binary;
+      memory_number   :primary_memory;
+    end record;   
+
+  constant    C61 : word := (others =>'0' );
+  constant    C64 : primary_memory := (others => C61);
+  constant    C65 : primary_memory_module := ('1',C64);
+
+  function complex_scalar(s : primary_memory_module) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return primary_memory_module is
+  begin
+    return C65;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : primary_memory_module;
+  signal S2 : primary_memory_module;
+  signal S3 : primary_memory_module:= C65;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C65) and (S2 = C65)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00459" 
+      severity NOTE;
+    assert ((S1 = C65) and (S2 = C65)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00459 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd
new file mode 100644
index 0000000..ba9bfa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc460.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00460ent IS
+END c03s02b01x01p19n01i00460ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00460arch OF c03s02b01x01p19n01i00460ent IS
+
+  type       four_value    is ('Z','0','1','X');
+  subtype    binary       is four_value range '0' to '1';
+  subtype    word       is bit_vector(0 to  15);
+  constant    size       :integer := 7;
+  type       primary_memory    is array(0 to size) of word;
+
+  type primary_memory_module is   
+    record   
+      enable      :binary;
+      memory_number   :primary_memory;
+    end record;   
+
+  type       whole_memory is array(0 to size) of primary_memory_module;
+
+  constant    C61 : word       := (others =>'0' );
+  constant    C64 : primary_memory    := (others => C61);
+  constant    C65 : primary_memory_module := ('1',C64);
+  constant    C66 : whole_memory    := (others => C65);
+
+  function complex_scalar(s : whole_memory) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return whole_memory is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : whole_memory;
+  signal S2 : whole_memory;
+  signal S3 : whole_memory:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00460" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00460 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd
new file mode 100644
index 0000000..35b2681
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc461.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00461ent IS
+END c03s02b01x01p19n01i00461ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00461arch OF c03s02b01x01p19n01i00461ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  constant    C66 : current := 1 A;
+
+  function complex_scalar(s : current) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return current is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : current;
+  signal S2 : current;
+  signal S3 : current:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00461" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00461 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd
new file mode 100644
index 0000000..498b9d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc462.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00462ent IS
+END c03s02b01x01p19n01i00462ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00462arch OF c03s02b01x01p19n01i00462ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  constant C66 : resistance := 1 Ohm;
+
+  function complex_scalar(s : resistance) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return resistance is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : resistance;
+  signal S2 : resistance;
+  signal S3 : resistance:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00462" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00462 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd
new file mode 100644
index 0000000..139b718
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc463.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00463ent IS
+END c03s02b01x01p19n01i00463ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00463arch OF c03s02b01x01p19n01i00463ent IS
+
+  subtype    delay is integer range 1 to 10;
+  constant    C66 : delay := 2;
+
+  function complex_scalar(s : delay) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return delay is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : delay;
+  signal S2 : delay;
+  signal S3 : delay:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00463"
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00463 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd
new file mode 100644
index 0000000..10ab7bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00464ent IS
+END c03s02b01x01p19n01i00464ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       boolean_vector       is array (natural range <>) of boolean;
+  subtype    boolean_vector_range    is boolean_vector(hi_to_low_range);
+  constant    C66: boolean_vector_range := (others => true);
+
+  function complex_scalar(s : boolean_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_vector_range;
+  signal S2 : boolean_vector_range;
+  signal S3 : boolean_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00464"
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00464arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd
new file mode 100644
index 0000000..8645c79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00465ent IS
+END c03s02b01x01p19n01i00465ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range       is integer range low_number to hi_number;
+  type       severity_level_vector       is array (natural range <>) of severity_level;
+  subtype    severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  constant    C66: severity_level_vector_range := (others => note);
+
+  function complex_scalar(s : severity_level_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_vector_range;
+  signal S2 : severity_level_vector_range;
+  signal S3 : severity_level_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00465" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00465arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd
new file mode 100644
index 0000000..0bef526
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc466.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00466ent IS
+END c03s02b01x01p19n01i00466ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00466arch OF c03s02b01x01p19n01i00466ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       integer_vector       is array (natural range <>) of integer;
+  subtype    integer_vector_range    is integer_vector(hi_to_low_range);
+  constant    C66: integer_vector_range := (others => 3);
+
+  function complex_scalar(s : integer_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_vector_range;
+  signal S2 : integer_vector_range;
+  signal S3 : integer_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00466" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00466 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00466arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd
new file mode 100644
index 0000000..f3a9571
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc467.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00467ent IS
+END c03s02b01x01p19n01i00467ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00467arch OF c03s02b01x01p19n01i00467ent IS
+
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       real_vector       is array (natural range <>) of real;
+  subtype    real_vector_range    is real_vector(hi_to_low_range);
+  constant    C66: real_vector_range := (others => 3.0);
+
+  function complex_scalar(s : real_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_vector_range;
+  signal S2 : real_vector_range;
+  signal S3 : real_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00467" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00467 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00467arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd
new file mode 100644
index 0000000..f65bc93
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc468.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00468ent IS
+END c03s02b01x01p19n01i00468ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00468arch of c03s02b01x01p19n01i00468ent IS
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       time_vector       is array (natural range <>) of time;
+  subtype    time_vector_range    is time_vector(hi_to_low_range);
+  constant    C66: time_vector_range := (others => 3 ns);
+
+  function complex_scalar(s : time_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_vector_range;
+  signal S2 : time_vector_range;
+  signal S3 : time_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00468" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00468 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00468arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd
new file mode 100644
index 0000000..f048228
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc469.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00469ent IS
+END c03s02b01x01p19n01i00469ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00469arch OF c03s02b01x01p19n01i00469ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       natural_vector       is array (natural range <>) of natural;
+  subtype    natural_vector_range    is natural_vector(hi_to_low_range);
+  constant    C66: natural_vector_range := (others => 1);
+
+  function complex_scalar(s : natural_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_vector_range;
+  signal S2 : natural_vector_range;
+  signal S3 : natural_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00469" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00469 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00469arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd
new file mode 100644
index 0000000..7cedecb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc470.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00470ent IS
+END c03s02b01x01p19n01i00470ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00470arch OF c03s02b01x01p19n01i00470ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       positive_vector    is array (natural range <>) of positive;
+  subtype    positive_vector_range    is positive_vector(hi_to_low_range);
+  constant    C66: positive_vector_range := (others => 1);
+
+  function complex_scalar(s : positive_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_vector_range;
+  signal S2 : positive_vector_range;
+  signal S3 : positive_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00470" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00470 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00470arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd
new file mode 100644
index 0000000..e07d9c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc471.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00471ent IS
+END c03s02b01x01p19n01i00471ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00471arch OF c03s02b01x01p19n01i00471ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C66: array_rec_std(0 to 7)    := (others => C50)  ;
+
+  function complex_scalar(s : array_rec_std(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_std is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_std(0 to 7);
+  signal S2 : array_rec_std(0 to 7);
+  signal S3 : array_rec_std(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00471" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00471 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00471arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd
new file mode 100644
index 0000000..de06920
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc472.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00472ent IS
+END c03s02b01x01p19n01i00472ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00472arch OF c03s02b01x01p19n01i00472ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C66 : array_rec_cons (0 to 7)    := (others => C51);
+
+
+  function complex_scalar(s : array_rec_cons(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_cons is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_cons(0 to 7);
+  signal S2 : array_rec_cons(0 to 7);
+  signal S3 : array_rec_cons(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00472" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00472 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00472arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd
new file mode 100644
index 0000000..9f9bf5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00473ent IS
+END c03s02b01x01p19n01i00473ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type array_rec_2cons is array (integer range <>) of record_2cons_array;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C66 : array_rec_2cons(0 to 7)   := (others => C52) ;
+
+
+  function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_2cons is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_2cons(0 to 7);
+  signal S2 : array_rec_2cons(0 to 7);
+  signal S3 : array_rec_2cons(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00473" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00473arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd
new file mode 100644
index 0000000..cf47d92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd
@@ -0,0 +1,268 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc474.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00474ent IS
+END c03s02b01x01p19n01i00474ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00474arch OF c03s02b01x01p19n01i00474ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector       is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type s2boolean_vector    is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector    is array (natural range<>,natural range <>) of bit;
+  type s2char_vector    is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector    is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector    is array (natural range <>,natural range <>) of integer;
+  type s2real_vector    is array (natural range <>,natural range <>) of real;
+  type s2time_vector    is array (natural range <>,natural range <>) of time;
+  type s2natural_vector    is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector    is array (natural range <>,natural range <>) of positive;
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector       is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector       is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                            end record;
+
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector       := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector       := (others => C5);
+  constant C22 : real_cons_vector       := (others => C6);
+  constant C23 : time_cons_vector       := (others => C7);
+  constant C24 : natural_cons_vector       := (others => C8);
+  constant C25 : positive_cons_vector       := (others => C9);
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector    :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st    := (others => C1);
+  constant C71 : severity_level_vector_st   := (others => C4);
+  constant C72 : integer_vector_st   := (others => C5);
+  constant C73 : real_vector_st      := (others => C6);
+  constant C74 : time_vector_st      := (others => C7);
+  constant C75 : natural_vector_st   := (others => C8);
+  constant C76 : positive_vector_st   := (others => C9);
+
+  constant C77 : record_array_st       := (C70,C71,C72,C73,C74,C75,C76);
+
+  constant C55 : record_of_records    := (C50,C51,C52,C53,C77);
+
+  constant C66 : array_rec_rec(0 to 7)    := (others => C55);
+
+  function complex_scalar(s : array_rec_rec(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_rec is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_rec(0 to 7);
+  signal S2 : array_rec_rec(0 to 7);
+  signal S3 : array_rec_rec(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00474" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00474 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd
new file mode 100644
index 0000000..af23b42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc475.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00475ent IS
+END c03s02b01x01p19n01i00475ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00475arch OF c03s02b01x01p19n01i00475ent IS
+
+  type       boolean_vector is array (natural range <>) of boolean;
+
+  function resolution1(i:in boolean_vector) return boolean is
+    variable temp : boolean:= true;
+  begin
+    return temp;
+  end resolution1;
+
+  subtype    boolean_state is resolution1 boolean;
+  constant    C66 : boolean_state   := true;
+
+  function complex_scalar(s : boolean_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_state;
+  signal S2 : boolean_state;
+  signal S3 : boolean_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00475" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00475 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
new file mode 100644
index 0000000..bea5f69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc476.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00476ent IS
+END c03s02b01x01p19n01i00476ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00476arch OF c03s02b01x01p19n01i00476ent IS
+
+  type    severity_level_vector is array (natural range <>) of severity_level;
+
+  function resolution2(i:in severity_level_vector) return severity_level is
+    variable temp : severity_level := note;
+  begin
+    return temp;
+  end resolution2;
+
+  subtype    severity_level_state is resolution2 severity_level;
+
+  constant    C66 : severity_level_state   := note;
+
+  function complex_scalar(s : severity_level_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_state;
+  signal S2 : severity_level_state;
+  signal S3 : severity_level_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00476" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00476 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00476arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd
new file mode 100644
index 0000000..a7676a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00477ent IS
+END c03s02b01x01p19n01i00477ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
+
+  function resolution3(i:in bit_vector) return bit is
+    variable temp : bit := '1';
+  begin
+    return temp;
+  end resolution3;
+
+  subtype    bit_state is resolution3 bit;
+  constant    C66 : bit_state   := '1';
+
+  function complex_scalar(s : bit_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return bit_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : bit_state;
+  signal S2 : bit_state;
+  signal S3 : bit_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00477" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00477arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd
new file mode 100644
index 0000000..622ae9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc478.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00478ent IS
+END c03s02b01x01p19n01i00478ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00478arch OF c03s02b01x01p19n01i00478ent IS
+
+  function resolution4(i:in string) return character is
+    variable temp : character := 's' ;
+  begin
+    return temp;
+  end resolution4;
+  subtype    character_state is resolution4 character;
+  constant    C66 : character_state   := 's';
+
+  function complex_scalar(s : character_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return character_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : character_state;
+  signal S2 : character_state;
+  signal S3 : character_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00478" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00478 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00478arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd
new file mode 100644
index 0000000..0ef6f1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00479ent IS
+END c03s02b01x01p19n01i00479ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
+
+  type    integer_vector is array (natural range <>) of integer;
+
+  function resolution5(i:in integer_vector) return integer is
+    variable temp : integer := 3;
+  begin
+    return temp;
+  end resolution5;
+
+  subtype    integer_state is resolution5 integer;
+  constant    C66 : integer_state   := 3;
+
+  function complex_scalar(s : integer_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_state;
+  signal S2 : integer_state;
+  signal S3 : integer_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00479" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00479arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd
new file mode 100644
index 0000000..539d0b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc480.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00480ent IS
+END c03s02b01x01p19n01i00480ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00480arch OF c03s02b01x01p19n01i00480ent IS
+
+  type    real_vector is array (natural range <>) of real;
+  function resolution6(i:in real_vector) return real is
+    variable temp : real := 3.0;
+  begin
+    return temp;
+  end resolution6;
+
+  subtype    real_state is resolution6 real;
+  constant    C66 : real_state   := 3.0;
+
+  function complex_scalar(s : real_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_state;
+  signal S2 : real_state;
+  signal S3 : real_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00480" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00480 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00480arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd
new file mode 100644
index 0000000..a18c2c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc481.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00481ent IS
+END c03s02b01x01p19n01i00481ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00481arch OF c03s02b01x01p19n01i00481ent IS
+
+  type    natural_vector is array (natural range <>) of natural;
+  function resolution8(i:in natural_vector) return natural is
+    variable temp : natural := 1;
+  begin
+    return temp;
+  end resolution8;
+  subtype    natural_state is resolution8 natural;
+  constant    C66 : natural_state   := 1;
+
+  function complex_scalar(s : natural_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_state;
+  signal S2 : natural_state;
+  signal S3 : natural_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00481" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00481 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00481arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd
new file mode 100644
index 0000000..5e0cafa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc482.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00482ent IS
+END c03s02b01x01p19n01i00482ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00482arch OF c03s02b01x01p19n01i00482ent IS
+
+  type    positive_vector is array (natural range <>) of positive;
+  function resolution9(i:in positive_vector) return positive is
+    variable temp : positive := 1;
+  begin
+    return temp;
+  end resolution9;
+  subtype    positive_state is resolution9 positive;
+  constant    C66 : positive_state   := 1;
+
+  function complex_scalar(s : positive_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_state;
+  signal S2 : positive_state;
+  signal S3 : positive_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00482" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00482 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00482arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd
new file mode 100644
index 0000000..67e33b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc483.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00483ent IS
+END c03s02b01x01p19n01i00483ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00483arch OF c03s02b01x01p19n01i00483ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+
+  type    array_rec_std is array (integer range <>) of record_std_package;
+  function resolution10(i:in array_rec_std) return record_std_package is
+    variable temp : record_std_package := C50;
+  begin
+    return temp;
+  end resolution10;
+  subtype    array_rec_std_state is resolution10 record_std_package;
+
+  constant C66 : array_rec_std_state   := C50;
+
+  function complex_scalar(s : array_rec_std_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_std_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_std_state;
+  signal S2 : array_rec_std_state;
+  signal S3 : array_rec_std_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00483" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00483 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd
new file mode 100644
index 0000000..b539324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd
@@ -0,0 +1,148 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc484.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p19n01i00484ent_a IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END c03s02b01x01p19n01i00484ent_a;
+
+architecture c03s02b01x01p19n01i00484arch_a of c03s02b01x01p19n01i00484ent_a is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00484ent IS
+END c03s02b01x01p19n01i00484ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00484arch OF c03s02b01x01p19n01i00484ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;   
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    :=  (others => C7);
+  constant C24 : natural_cons_vector    :=  (others => C8);
+  constant C25 : positive_cons_vector    :=  (others => C9);
+
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+
+  function resolution11(i:in array_rec_cons) return record_cons_array is
+    variable temp : record_cons_array := C51;
+  begin
+    return temp;
+  end resolution11;
+  subtype array_rec_cons_state is resolution11 record_cons_array;
+
+  constant C66 : array_rec_cons_state   := C51;
+
+  function complex_scalar(s : array_rec_cons_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_cons_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component c03s02b01x01p19n01i00484ent_a1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : c03s02b01x01p19n01i00484ent_a1 use entity work.c03s02b01x01p19n01i00484ent_a(c03s02b01x01p19n01i00484arch_a);
+
+  signal S1 : array_rec_cons_state;
+  signal S2 : array_rec_cons_state;
+  signal S3 : array_rec_cons_state:= C66;
+BEGIN
+  T1: c03s02b01x01p19n01i00484ent_a1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00484" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00484 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00484arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd
new file mode 100644
index 0000000..4adf6d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd
@@ -0,0 +1,156 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc485.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p19n01i00485ent_a IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END c03s02b01x01p19n01i00485ent_a;
+
+architecture c03s02b01x01p19n01i00485ent_a of c03s02b01x01p19n01i00485ent_a is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00485ent IS
+END c03s02b01x01p19n01i00485ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00485arch OF c03s02b01x01p19n01i00485ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+
+  type    array_rec_2cons is array (integer range <>) of record_2cons_array;
+
+  function resolution12(i:in array_rec_2cons) return record_2cons_array is
+    variable temp : record_2cons_array := C52;
+  begin
+    return temp;
+  end resolution12;
+  subtype array_rec_2cons_state is resolution12 record_2cons_array;
+
+  constant C66 : array_rec_2cons_state:= C52; 
+
+  function complex_scalar(s : array_rec_2cons_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_2cons_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component c03s02b01x01p19n01i00485ent_a1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : c03s02b01x01p19n01i00485ent_a1 use entity work.c03s02b01x01p19n01i00485ent_a(c03s02b01x01p19n01i00485ent_a);
+
+  signal S1 : array_rec_2cons_state;
+  signal S2 : array_rec_2cons_state;
+  signal S3 : array_rec_2cons_state:= C66;
+BEGIN
+  T1: c03s02b01x01p19n01i00485ent_a1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00485" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00485 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd
new file mode 100644
index 0000000..33a8db0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd
@@ -0,0 +1,270 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00486ent IS
+END c03s02b01x01p19n01i00486ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
+
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                            end record;
+
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+
+  constant C70 : boolean_vector_st    :=(others => C1);
+  constant C71 : severity_level_vector_st   :=(others => C4);
+  constant C72 : integer_vector_st   :=(others => C5);
+  constant C73 : real_vector_st      :=(others => C6);
+  constant C74 : time_vector_st      :=(others => C7);
+  constant C75 : natural_vector_st   :=(others => C8);
+  constant C76 : positive_vector_st   :=(others => C9);
+
+  constant C77 : record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records    := (C50,C51,C52,C53,C77);
+
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  function resolution13(i:in array_rec_rec) return record_of_records is
+    variable temp : record_of_records :=C55 ;
+  begin
+    return temp;
+  end resolution13;
+
+  subtype array_rec_rec_state is resolution13 record_of_records;   
+
+  constant C66 : array_rec_rec_state   := C55; 
+
+  function complex_scalar(s : array_rec_rec_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_rec_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_rec_state;
+  signal S2 : array_rec_rec_state;
+  signal S3 : array_rec_rec_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00486" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd
new file mode 100644
index 0000000..330e7c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p20n01i00487ent IS
+END c03s02b01x01p20n01i00487ent;
+
+ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5);
+  procedure F2 (X1 : inout MEM) is
+  begin
+    assert NOT((X1'LOW = 1) and (X1'High = 5))
+      report "***PASSED TEST: c03s02b01x01p20n01i00487"
+      severity NOTE;
+    assert ((X1'LOW = 1) and (X1'High = 5))
+      report "***FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator."
+      severity ERROR;
+  end F2;
+BEGIN
+  TESTING: PROCESS
+    variable S1 : M1 := "01110";
+  BEGIN
+    F2(S1) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p20n01i00487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd
new file mode 100644
index 0000000..b0c4be7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc488.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00488ent IS
+END c03s02b02x00p01n01i00488ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00488arch OF c03s02b02x00p01n01i00488ent IS
+  type T0 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+               el7 : real;
+               el8 : real;
+               el9 : real;
+               el10 : real;
+             end record;
+  type T1 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+             end record;
+  type T2 is record
+               el5 : real;
+               el6 : real;
+               el7 : real;
+             end record;
+  function FUNC1(recd1: T0) return T1 is
+    variable recd2:T1;
+  begin -- procedure FUNC1
+    recd2.el1 := recd1.el6;
+    recd2.el2 := recd1.el1;
+    recd2.el3 := recd1.el3;
+    recd2.el4 := recd1.el2;
+    recd2.el5 := recd1.el6;
+    recd2.el6 := recd1.el10;
+    return recd2;
+  end FUNC1;
+
+  function FUNC3(recd1: T0) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC3
+    recd2.el5 := recd1.el5;
+    recd2.el6 := recd1.el6;
+    recd2.el7 := recd1.el1;
+    return recd2;
+  end FUNC3;
+  
+  function FUNC4(recd1: T2) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC4
+    recd2.el5 := recd1.el7;
+    recd2.el6 := recd1.el5;
+    recd2.el7 := recd1.el5;
+    return recd2;
+  end FUNC4;
+
+BEGIN
+  TESTING: PROCESS
+    variable rec1: T0;
+    variable v1,v2:T1;
+    variable v3,v4:T2;
+  BEGIN
+    rec1 := (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
+    wait for 1 ns;
+    v1 := FUNC1(rec1);
+    v3 := FUNC3(rec1);
+    v4 := FUNC4(v3);
+    wait for 1 ns;
+    assert NOT( (v1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (v3 = (5.5,6.6,1.1))       AND
+                (v4 = (1.1,5.5,5.5)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00488"
+      severity NOTE;
+    assert (    (v1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (v3 = (5.5,6.6,1.1))       AND
+                (v4 = (1.1,5.5,5.5)))
+      report "***FAILED TEST: c03s02b02x00p01n01i00488 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00488arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd
new file mode 100644
index 0000000..a764d5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc489.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00489ent IS
+  type small is
+    record
+      bt : bit;
+      bv : bit_vector (11 downto 0);
+      r  : real range 0.0 to real'high;
+      bb : boolean;
+      i  : integer range 1 to 20;
+    end record;
+END c03s02b02x00p01n01i00489ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00489arch OF c03s02b02x00p01n01i00489ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1 : small;
+    alias A1_bv : bit_vector (11 downto 0) is A1.bv;
+    alias A1_bt : bit is A1.bt;
+    alias A1_i  : integer is A1.i;
+    alias A1_r  : real is A1.r;
+    alias A1_bb : boolean is A1.bb;
+  BEGIN
+
+    assert NOT(   ( A1.bv = x"000")   and
+                  ( A1.bt = '0')      and
+                  ( A1.bb = false)   and
+                  ( A1.i  = 1)      and
+                  ( A1.r  = 0.0)      and
+                  ( A1_bv = x"000")   and
+                  ( A1_bt = '0')      and
+                  ( A1_bb = false)   and
+                  ( A1_i  = 1)      and
+                  ( A1_r  = 0.0)      )
+      report "***PASSED TEST: c03s02b02x00p01n01i00489"
+      severity NOTE;
+    assert (   ( A1.bv = x"000")   and
+               ( A1.bt = '0')      and
+               ( A1.bb = false)   and
+               ( A1.i  = 1)      and
+               ( A1.r  = 0.0)      and
+               ( A1_bv = x"000")   and
+               ( A1_bt = '0')      and
+               ( A1_bb = false)   and
+               ( A1_i  = 1)      and
+               ( A1_r  = 0.0)      )
+      report "***FAILED TEST: c03s02b02x00p01n01i00489 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00489arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd
new file mode 100644
index 0000000..232ed5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00490ent IS
+END c03s02b02x00p01n01i00490ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
+  type T0 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+               el7 : real;
+               el8 : real;
+               el9 : real;
+               el10 : real;
+             end record;
+  type T1 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+             end record;
+  type T2 is record
+               el5 : real;
+               el6 : real;
+               el7 : real;
+             end record;
+  function FUNC1(signal recd1: T0) return T1 is
+    variable recd2:T1;
+  begin -- procedure FUNC1
+    recd2.el1 := recd1.el6;
+    recd2.el2 := recd1.el1;
+    recd2.el3 := recd1.el3;
+    recd2.el4 := recd1.el2;
+    recd2.el5 := recd1.el6;
+    recd2.el6 := recd1.el10;
+    return recd2;
+  end FUNC1;
+  
+  function FUNC3(signal recd1: T0) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC3
+    recd2.el5 := recd1.el5;
+    recd2.el6 := recd1.el6;
+    recd2.el7 := recd1.el1;
+    return recd2;
+  end FUNC3;
+  
+  function FUNC4(signal recd1: T2) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC4
+    recd2.el5 := recd1.el7;
+    recd2.el6 := recd1.el5;
+    recd2.el7 := recd1.el5;
+    return recd2;
+  end FUNC4;
+  
+  signal rec1: T0;
+  signal s1,v2:T1;
+  signal s3,s4:T2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
+    wait for 1 ns;
+    s1 <= FUNC1(rec1);
+    s3 <= FUNC3(rec1);
+    wait for 1 ns;
+    s4 <= FUNC4(s3);
+    wait for 1 ns;
+    assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (s3 = (5.5,6.6,1.1))       AND
+                (s4 = (1.1,5.5,5.5)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00490"
+      severity NOTE;
+    assert (    (s1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (s3 = (5.5,6.6,1.1))       AND
+                (s4 = (1.1,5.5,5.5)))
+      report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00490arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd
new file mode 100644
index 0000000..b7f6afb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc491.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00491ent IS
+END c03s02b02x00p01n01i00491ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00491arch OF c03s02b02x00p01n01i00491ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1 return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := "0001";
+    recd2.b    := '1';
+    recd2.bo    := true;
+    recd2.i    := 777;
+    recd2.r    := 333.767;
+    recd2.t    := 44 ms;
+    recd2.e    := seven;
+    recd2.c    := '%';
+    return recd2;
+  end FUNC1;
+BEGIN
+  TESTING: PROCESS
+    variable var2: T1;
+    variable OkayCount: integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var2 := FUNC1;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    := FUNC1.i;
+    var2.b    := FUNC1.b;
+    var2.bo := FUNC1.bo;
+    var2.bv := FUNC1.bv;
+    var2.r    := FUNC1.r;
+    var2.t    := FUNC1.t;
+    var2.e    := FUNC1.e;
+    var2.c    := FUNC1.c;
+    
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1.element" severity note;
+    end if;
+    wait for 1 ns;
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00491"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00491 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00491arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd
new file mode 100644
index 0000000..4361ef5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd
@@ -0,0 +1,165 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc492.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00492ent IS
+END c03s02b02x00p01n01i00492ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00492arch OF c03s02b02x00p01n01i00492ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type TR is record
+               i    : integer;
+               b    : bit;
+               bo    : boolean;
+               bv    : bit_vector (0 to 3);
+               r    : real;
+               t    : time;
+               e    : etype;
+               c    : character;
+             end record;
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1(signal recd1: TR) return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := recd1.bv;
+    recd2.b    := recd1.b;
+    recd2.bo    := recd1.bo;
+    recd2.i    := recd1.i;
+    recd2.r    := recd1.r;
+    recd2.t    := recd1.t;
+    recd2.e    := recd1.e;
+    recd2.c    := recd1.c;
+    return recd2;
+  end FUNC1;
+  function FUNC2(signal recd1: TR) return integer is
+  begin
+    return recd1.i;
+  end;
+  function FUNC3(signal recd1: TR) return bit is
+  begin
+    return recd1.b;
+  end;
+  function FUNC4(signal recd1: TR) return boolean is
+  begin
+    return recd1.bo;
+  end;
+  function FUNC5(signal recd1: TR) return bit_vector is
+  begin
+    return recd1.bv;
+  end;
+  function FUNC6(signal recd1: TR) return real is
+  begin
+    return recd1.r;
+  end;
+  function FUNC7(signal recd1: TR) return time is
+  begin
+    return recd1.t;
+  end;
+  function FUNC8(signal recd1: TR) return etype is
+  begin
+    return recd1.e;
+  end;
+  function FUNC9(signal recd1: TR) return character is
+  begin
+    return recd1.c;
+  end;
+  
+  signal var1: TR;
+  signal var2: T1;
+  
+BEGIN
+  TESTING: PROCESS
+    variable OkayCount : integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var1 <= (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
+    wait for 1 ns;
+    var2 <= FUNC1(var1);
+    wait for 1 ns;
+    assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
+    assert var2.b = '1'    report "var2.b /= 1"     severity note;
+    assert var2.bo = true    report "var2.bo /= true" severity note;
+    assert var2.i = 777    report "var2.i /= 777"     severity note;
+    assert var2.r = 333.767 report "var2.r /= 333.767"    severity note;
+    assert var2.t = 44 ms    report "var2.t /= 44 ms" severity note;
+    assert var2.e = seven    report "var2.e /= seven" severity note;
+    assert var2.c = '%'    report "var2.c /= c"     severity note;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    wait for 1 ns;
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    <= FUNC2(var1);
+    var2.b    <= FUNC3(var1);
+    var2.bo <= FUNC4(var1);
+    var2.bv <= FUNC5(var1);
+    var2.r    <= FUNC6(var1);
+    var2.t    <= FUNC7(var1);
+    var2.e    <= FUNC8(var1);
+    var2.c    <= FUNC9(var1);
+    wait for 1 ns;
+    assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
+    assert var2.b = '1'    report "var2.b /= 1"     severity note;
+    assert var2.bo = true    report "var2.bo /= true" severity note;
+    assert var2.i = 777    report "var2.i /= 777"     severity note;
+    assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
+    assert var2.t = 44 ms    report "var2.t /= 44 ms" severity note;
+    assert var2.e = seven    report "var2.e /= seven" severity note;
+    assert var2.c = '%'    report "var2.c /= c"     severity note;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC2-8" severity note;
+    end if;
+    wait for 1 ns;
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00492"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00492 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00492arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd
new file mode 100644
index 0000000..706dfb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc493.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00493ent IS
+END c03s02b02x00p01n01i00493ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00493arch OF c03s02b02x00p01n01i00493ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type TR is record
+               i    : integer;
+               b    : bit;
+               bo    : boolean;
+               bv    : bit_vector (0 to 3);
+               r    : real;
+               t    : time;
+               e    : etype;
+               c    : character;
+             end record;
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1(recd1: TR) return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := recd1.bv;
+    recd2.b    := recd1.b;
+    recd2.bo    := recd1.bo;
+    recd2.i    := recd1.i;
+    recd2.r    := recd1.r;
+    recd2.t    := recd1.t;
+    recd2.e    := recd1.e;
+    recd2.c    := recd1.c;
+    return recd2;
+  end FUNC1;
+  function FUNC2(recd1: TR) return integer is
+  begin
+    return recd1.i;
+  end;
+  function FUNC3(recd1: TR) return bit is
+  begin
+    return recd1.b;
+  end;
+  function FUNC4(recd1: TR) return boolean is
+  begin
+    return recd1.bo;
+  end;
+  function FUNC5(recd1: TR) return bit_vector is
+  begin
+    return recd1.bv;
+  end;
+  function FUNC6(recd1: TR) return real is
+  begin
+    return recd1.r;
+  end;
+  function FUNC7(recd1: TR) return time is
+  begin
+    return recd1.t;
+  end;
+  function FUNC8(recd1: TR) return etype is
+  begin
+    return recd1.e;
+  end;
+  function FUNC9(recd1: TR) return character is
+  begin
+    return recd1.c;
+  end;
+  
+BEGIN
+  TESTING: PROCESS
+    variable var1: TR;
+    variable var2: T1;
+    variable OkayCount: integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var1 := (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
+    var2 := FUNC1(var1);
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    := FUNC2(var1);wait for 1 ns;assert var2.i=777 report "i no good" severity note;
+    var2.b    := FUNC3(var1);wait for 1 ns;assert var2.b='1' report "b no good" severity note;
+    var2.bo := FUNC4(var1);wait for 1 ns;assert var2.bo=true report "bo no good" severity note;
+    var2.bv := FUNC5(var1);wait for 1 ns;assert var2.bv="0001" report "bv no good" severity note;
+    var2.r    := FUNC6(var1);wait for 1 ns;assert var2.r=333.767 report "r no good" severity note;
+    var2.t    := FUNC7(var1);wait for 1 ns;assert var2.t=44 ms report "t no good" severity note;
+    var2.e    := FUNC8(var1);wait for 1 ns;assert var2.e=seven report "e no good" severity note;
+    var2.c    := FUNC9(var1);wait for 1 ns;assert var2.c='%' report "c no good" severity note;
+    
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC2-9" severity note;
+    end if;
+    wait for 1 ns; 
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00493"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00493 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00493arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd
new file mode 100644
index 0000000..54be917
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc494.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00494ent IS
+END c03s02b02x00p01n01i00494ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00494arch OF c03s02b02x00p01n01i00494ent IS
+  type colors is (orange,blue,red,black,white,magenta,ochre,yellow,green);
+  type TR is RECORD
+               i    : integer;
+               ch    : character;
+               bi    : bit;
+               bool    : boolean;
+               bv    : bit_vector (3000 to 3007);
+               r    : real;
+               str    : STRING (1 to 7);
+               ti    : TIME;
+               color    : colors;
+             END RECORD;
+  type TY is array(integer range <>) of TR;
+  subtype T0 is TY (1 to 10);
+  subtype T1 is TY (1 to 6);
+  subtype T2 is TY (5 to 7);
+  
+  function FUNC1(array1: T0) return T1 is -- formal param object class defaults to constant
+    variable array2:T1;
+  begin -- procedure FUNC1
+    array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
+    return array2;
+  end FUNC1;
+  
+  function FUNC2(array1: TY) return T1 is
+    variable array2:T1;
+  begin -- procedure FUNC2
+    array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
+    return array2;
+  end FUNC2;
+  
+  function FUNC3(array1: T0) return T2 is
+    variable array2:T2;
+  begin -- procedure FUNC3
+    array2 := array1(5 to 6) & array1(1 to 1); --slices
+    return array2;
+  end FUNC3;
+  
+  function FUNC4(array1: T2) return T2 is
+    variable array2:T2;
+  begin -- procedure FUNC4
+    array2 := array1 (7 to 7) & array1(5 to 5) &
+              array1(5 to 5); --slices
+    return array2;
+  end FUNC4; 
+BEGIN
+  TESTING: PROCESS
+    variable arr1: T0;
+    variable v1,v2:T1;
+    variable v3,v4:T2;
+  BEGIN
+    arr1(1) := (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange);
+    arr1(2) := (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue);
+    arr1(3) := (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red);
+    arr1(4) := (4,'d','1',true, "00000100",4.4,"four   ",4.4 ms,black);
+    arr1(5) := (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white);
+    arr1(6) := (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta);
+    arr1(7) := (7,'g','0',false,"00000111",7.7,"seven  ",7.7 ms,ochre);
+    arr1(8) := (8,'h','1',true, "00001000",8.8,"eight  ",8.8 ms,yellow);
+    arr1(9) := (9,'i','0',false,"00001001",9.9,"nine   ",9.9 ms,green);
+    arr1(10):=(10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white);
+    wait for 1 ns;
+    v1 := FUNC1(arr1);
+    v2 := FUNC2(arr1);
+    v3 := FUNC3(arr1);
+    v4 := FUNC4(v3);
+    
+    wait for 1 ns;
+    assert NOT( (v1(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v1(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v1(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                (v1(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                (v1(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v1(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                (v2(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v2(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v2(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                (v2(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                (v2(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v2(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                (v3(5) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                (v3(6) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v3(7) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v4(5) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v4(6) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                (v4(7) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00494"
+      severity NOTE;
+    assert      ( (v1(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v1(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v1(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                  (v1(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                  (v1(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v1(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                  (v2(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v2(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v2(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                  (v2(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                  (v2(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v2(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                  (v3(5) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                  (v3(6) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v3(7) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v4(5) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v4(6) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                  (v4(7) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)))
+      report "***FAILED TEST:c03s02b02x00p01n01i00494 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00494arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd
new file mode 100644
index 0000000..df66da6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc495.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00495ent IS
+END c03s02b02x00p01n01i00495ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00495arch OF c03s02b02x00p01n01i00495ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type tRecord1 is
+      record
+        element1 : INTEGER;
+        element2 : CHARACTER;
+      end record;
+
+    type tRecord2 is
+      record
+        element3 : INTEGER;
+        element4 : CHARACTER;
+        element5 : tRecord1;
+      end record;
+
+    variable V1 : tRecord1 := (1, '1');
+    variable V2 : tRecord2 := (2, '2', (3, '3'));
+  BEGIN
+    assert V1.element1 = 1;
+    assert V1.element2 = '1';
+    assert V2.element3 = 2;
+    assert V2.element4 = '2';
+    assert V2.element5.element1 = 3;
+    assert V2.element5.element2 = '3';
+    wait for 1 ns;
+    assert NOT(   V1.element1 = 1      and
+                  V1.element2 = '1'   and
+                  V2.element3 = 2      and
+                  V2.element4 = '2'   and
+                  V2.element5.element1 = 3   and
+                  V2.element5.element2 = '3'   ) 
+      report "***PASSED TEST: c03s02b02x00p01n01i00495"
+      severity NOTE;
+    assert (   V1.element1 = 1      and
+               V1.element2 = '1'   and
+               V2.element3 = 2      and
+               V2.element4 = '2'   and
+               V2.element5.element1 = 3   and
+               V2.element5.element2 = '3'   ) 
+      report "***FAILED TEST: c03s02b02x00p01n01i00495 - Record type in record type declartion test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd
new file mode 100644
index 0000000..fc5f062
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc496.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00496ent IS
+END c03s02b02x00p02n01i00496ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00496arch OF c03s02b02x00p02n01i00496ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : rec_type;
+  BEGIN
+    k.x := '1';
+    k.y := 5;
+    k.z := true;
+    assert NOT(k.x='1' and k.y=5 and k.z=true)
+      report "***PASSED TEST: c03s02b02x00p02n01i00496"
+      severity NOTE;
+    assert (k.x='1' and k.y=5 and k.z=true)
+      report "***FAILED TEST: c03s02b02x00p02n01i00496 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd
new file mode 100644
index 0000000..5c393f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc497.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00497ent IS
+END c03s02b02x00p02n01i00497ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00497arch OF c03s02b02x00p02n01i00497ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k,kk : rec_type;
+  BEGIN
+    k.x := '1';
+    k.y := 5;
+    k.z := true;
+    kk  := k;
+    assert NOT(kk.x='1' and kk.y=5 and kk.z=true)
+      report "***PASSED TEST: c03s02b02x00p02n01i00497"
+      severity NOTE;
+    assert (kk.x='1' and kk.y=5 and kk.z=true)
+      report "***FAILED TEST: c03s02b02x00p02n01i00497 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00497arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd
new file mode 100644
index 0000000..114b1e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc498.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00498ent IS
+END c03s02b02x00p02n01i00498ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00498arch OF c03s02b02x00p02n01i00498ent IS
+  type Month_name is (jan, dec);
+  type Date is
+    record
+      Day      : integer range 1 to 31;
+      Month   : Month_name;
+      Year   : integer range 0 to 4000;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : Date;
+  BEGIN
+    k.Day   :=   16;
+    k.Month   :=   jan;
+    k.Year   :=   1993;   
+    assert NOT(k.Day=16 and k.Month=jan and k.Year =1993)
+      report "***PASSED TEST: c03s02b02x00p02n01i00498"
+      severity NOTE;
+    assert (k.Day=16 and k.Month=jan and k.Year =1993)
+      report "***FAILED TEST: c03s02b02x00p02n01i00498 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00498arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd
new file mode 100644
index 0000000..e4eb17f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc499.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00499ent IS
+END c03s02b02x00p02n01i00499ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00499arch OF c03s02b02x00p02n01i00499ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+  type rec2_type is
+    record
+      x : integer;
+      y : integer;
+      z : boolean;
+      b : rec_type;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v2 : rec2_type;
+  BEGIN
+    v2.x  := 12;
+    v2.y  := 10;
+    v2.z  := true;
+    v2.b.b  := bit'('0');
+    assert NOT(v2.x=12 and v2.y=10 and v2.z=true and v2.b.b ='0')
+      report "***PASSED TEST: c03s02b02x00p02n01i00499"
+      severity NOTE;
+    assert (v2.x=12 and v2.y=10 and v2.z=true and v2.b.b ='0')
+      report "***FAILED TEST: c03s02b02x00p02n01i00499 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd
new file mode 100644
index 0000000..2bdf462
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc500.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00500ent IS
+END c03s02b02x00p02n01i00500ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00500arch OF c03s02b02x00p02n01i00500ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : rec_type;
+  BEGIN
+    v1.x  := 12;
+    v1.y  := 1.2;
+    v1.z  := true;
+    v1.b  := bit'('0');
+    assert NOT(v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0')
+      report "***PASSED TEST: c03s02b02x00p02n01i00500"
+      severity NOTE;
+    assert (v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0')
+      report "***FAILED TEST: c03s02b02x00p02n01i00500 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd
new file mode 100644
index 0000000..1459d27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00501ent IS
+END c03s02b02x00p02n01i00501ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : integer;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : rec_type;
+  BEGIN
+    v1.x  := 12;
+    v1.y  := v1.x * 111;
+    assert NOT(v1.x=12 and v1.y=1332) 
+      report "***PASSED TEST: c03s02b02x00p02n01i00501"
+      severity NOTE;
+    assert (v1.x=12 and v1.y=1332) 
+      report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00501arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd
new file mode 100644
index 0000000..a196805
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc503.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p03n01i00503ent IS
+END c03s02b02x00p03n01i00503ent;
+
+ARCHITECTURE c03s02b02x00p03n01i00503arch OF c03s02b02x00p03n01i00503ent IS
+  type R2 is record
+               R11,R12 : INTEGER;
+               R21,R22,R23 : BOOLEAN;
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : R2;
+  BEGIN
+    k.R11   := 1;
+    k.R12   := 2;
+    k.R21   := true;
+    k.R22   := false;
+    k.R23   := true;
+    wait for 2 ns;
+    assert NOT(k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
+      report "***PASSED TEST: c03s02b02x00p03n01i00503"
+      severity NOTE;
+    assert (k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
+      report "***FAILED TEST: c03s02b02x00p03n01i00503 - A multiple object declaration is equivalent to a sequence of the corresponding number of single object declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p03n01i00503arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd
new file mode 100644
index 0000000..f961fd8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc505.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n01i00505ent IS
+  subtype    DAY1    is INTEGER range 1 to 31;
+  type       MONTH1    is (   January, February, March, April, May, June, July,
+                              August, September, October, November, December);
+END c03s02b02x00p06n01i00505ent;
+
+ARCHITECTURE c03s02b02x00p06n01i00505arch OF c03s02b02x00p06n01i00505ent IS
+  type DATE1 is record
+                  day:    DAY1;
+                  month:  MONTH1;
+                  year:   INTEGER range 0 to 4000;
+                end record;
+  type EVENT is record
+                  text:   STRING (1 to 20);
+                  date:   DATE1;
+                end record;
+  signal event_signal : EVENT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    event_signal <= (text => "Go to Wall Street NY",
+                     date => (27, January, 1991)) after 10 ns;
+    wait for 20 ns;
+    assert NOT( event_signal.text = "Go to Wall Street NY" )
+      report "***PASSED TEST: c03s02b02x00p06n01i00505"
+      severity NOTE;
+    assert ( event_signal.text = "Go to Wall Street NY" )
+      report "***FAILED TEST: c03s02b02x00p06n01i00505 - Element declaration test in record type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n01i00505arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd
new file mode 100644
index 0000000..e404b53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc512.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p07n01i00512ent IS
+END c03s02b02x00p07n01i00512ent;
+
+ARCHITECTURE c03s02b02x00p07n01i00512arch OF c03s02b02x00p07n01i00512ent IS
+  type DATE is
+    record
+      DAY,D1,D2  : Integer;
+      MONTH : Integer;
+      YEAR : Integer;
+    end record;
+  type DAT is
+    record
+      DAY : Integer;
+      D1  : Integer;
+      D2  : Integer;
+      MONTH : Integer;
+      YEAR : Integer;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : DATE    := (5,5,5,10,15) ;
+    variable V2 : DAT    := (5,5,5,10,15);
+  BEGIN
+    assert NOT(V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
+      report "***PASSED TEST: c03s02b02x00p07n01i00512"
+      severity NOTE;
+    assert (V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
+      report "***FAILED TEST: c03s02b02x00p07n01i00512 - An element declaration with several identifiers is equivalent to a sequence of single element declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p07n01i00512arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd
new file mode 100644
index 0000000..3ee8305
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc513.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p02n01i00513ent IS
+END c03s03b00x00p02n01i00513ent;
+
+ARCHITECTURE c03s03b00x00p02n01i00513arch OF c03s03b00x00p02n01i00513ent IS
+  type a is range 1 to 10;
+  type b is access a;   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k :b;
+  BEGIN
+    assert NOT(k = null)
+      report "***PASSED TEST: c03s03b00x00p02n01i00513"
+      severity NOTE;
+    assert ( k = null )
+      report "***FAILED TEST: c03s03b00x00p02n01i00513 - In the access type definition, the reserved word access must be followed by a subtype definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p02n01i00513arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd
new file mode 100644
index 0000000..298bb5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc515.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n01i00515ent IS
+END c03s03b00x00p03n01i00515ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00515arch OF c03s03b00x00p03n01i00515ent IS
+  type A is access integer;
+BEGIN
+  TESTING: PROCESS
+    variable V: A ;
+  BEGIN
+    assert NOT(V = null)
+      report "***PASSED TEST: c03s03b00x00p03n01i00515"
+      severity NOTE;
+    assert ( V = null )
+      report "***FAILED TEST: c03s03b00x00p03n01i00515 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00515arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd
new file mode 100644
index 0000000..c03d7bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc516.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00516ent IS
+END c03s03b00x00p03n04i00516ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00516arch OF c03s03b00x00p03n04i00516ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    type color is (red, green, blue);
+    constant azure : color := blue;
+    constant first : color := color'low;
+
+    type enum_ptr is access color;
+    variable v_enum_ptr1: enum_ptr := new color'(blue);
+    variable v_enum_ptr2: enum_ptr;
+    variable v_enum_ptr3: enum_ptr := v_enum_ptr1;
+    variable v_enum_ptr4: enum_ptr := new color'(red);
+    variable v_enum_ptr5: enum_ptr := v_enum_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+
+    assert v_enum_ptr1.all = blue;
+    if (v_enum_ptr1.all = blue) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr2     = null;
+    if (v_enum_ptr2     = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr3.all = blue;
+    if (v_enum_ptr3.all = blue) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr4.all = red;
+    if (v_enum_ptr4.all = red) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr5.all = red;
+    if (v_enum_ptr5.all = red) then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_enum_ptr2 := new color'(green);
+
+    assert v_enum_ptr2.all = green;
+    if (v_enum_ptr2.all = green) then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert (v_enum_ptr3.all = color'succ(green));
+    if (v_enum_ptr3.all = color'succ(green)) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'pred(v_enum_ptr2.all));
+    if (v_enum_ptr5.all = color'pred(v_enum_ptr2.all)) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (color'pred(v_enum_ptr3.all) = green);
+    if (color'pred(v_enum_ptr3.all) = green) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'low);
+    if (v_enum_ptr5.all = color'low) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all = color'high);
+    if (v_enum_ptr3.all = color'high) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'left);
+    if (v_enum_ptr5.all = color'left) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all = color'right);
+    if (v_enum_ptr3.all = color'right) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all > v_enum_ptr5.all) = true;
+    if (v_enum_ptr3.all > v_enum_ptr5.all) then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert NOT(OKtest = 14) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00516"
+      severity NOTE;
+    assert (OKtest = 14) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00516 - Enumeration type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00516arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd
new file mode 100644
index 0000000..a874420
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd
@@ -0,0 +1,1380 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00517pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00517pkg;
+
+USE   work.c03s03b00x00p03n04i00517pkg.ALL;
+ENTITY c03s03b00x00p03n04i00517ent IS
+END c03s03b00x00p03n04i00517ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
+--
+--          Access type declarations
+--
+  TYPE at_scre_1 IS ACCESS t_scre_1 ;
+  TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
+  TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
+  TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
+  TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
+  TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
+  TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
+  TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
+  TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
+--
+--
+BEGIN
+  TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+    VARIABLE AV0_scre_1 : at_scre_1 ;
+    VARIABLE AV2_scre_1 : at_scre_1 ;
+    VARIABLE AV0_cca1_1 : at_cca1_1 ;
+    VARIABLE AV2_cca1_1 : at_cca1_1 ;
+    VARIABLE AV0_cca1_2 : at_cca1_2 ;
+    VARIABLE AV2_cca1_2 : at_cca1_2 ;
+    VARIABLE AV0_cca1_3 : at_cca1_3 ;
+    VARIABLE AV2_cca1_3 : at_cca1_3 ;
+    VARIABLE AV0_cca1_4 : at_cca1_4 ;
+    VARIABLE AV2_cca1_4 : at_cca1_4 ;
+    VARIABLE AV0_cmre_1 : at_cmre_1 ;
+    VARIABLE AV2_cmre_1 : at_cmre_1 ;
+    VARIABLE AV0_cmre_2 : at_cmre_2 ;
+    VARIABLE AV2_cmre_2 : at_cmre_2 ;
+    VARIABLE AV0_cca1_7 : at_cca1_7 ;
+    VARIABLE AV2_cca1_7 : at_cca1_7 ;
+    VARIABLE AV0_cmre_3 : at_cmre_3 ;
+    VARIABLE AV2_cmre_3 : at_cmre_3 ;
+--
+--
+  BEGIN
+--
+--          Allocation of access values
+--
+    AV0_scre_1 := NEW t_scre_1 ;
+    AV0_cca1_1 := NEW t_cca1_1 ;
+    AV0_cca1_2 := NEW t_cca1_2 ;
+    AV0_cca1_3 := NEW t_cca1_3 ;
+    AV0_cca1_4 := NEW t_cca1_4 ;
+    AV0_cmre_1 := NEW t_cmre_1 ;
+    AV0_cmre_2 := NEW t_cmre_2 ;
+    AV0_cca1_7 := NEW t_cca1_7 ;
+    AV0_cmre_3 := NEW t_cmre_3 ;
+---
+    AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
+    AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
+    AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
+    AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
+    AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
+    AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
+    AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
+    AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
+    AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
+--
+--
+    ASSERT AV0_scre_1.all = C0_scre_1  
+      REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
+    ASSERT AV2_scre_1.all = C2_scre_1  
+      REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
+    ASSERT AV0_cca1_1.all = C0_cca1_1  
+      REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
+    ASSERT AV2_cca1_1.all = C2_cca1_1  
+      REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
+    ASSERT AV0_cca1_2.all = C0_cca1_2  
+      REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
+    ASSERT AV2_cca1_2.all = C2_cca1_2  
+      REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
+    ASSERT AV0_cca1_3.all = C0_cca1_3  
+      REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
+    ASSERT AV2_cca1_3.all = C2_cca1_3  
+      REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
+    ASSERT AV0_cca1_4.all = C0_cca1_4  
+      REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
+    ASSERT AV2_cca1_4.all = C2_cca1_4  
+      REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
+    ASSERT AV0_cmre_1.all = C0_cmre_1  
+      REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
+    ASSERT AV2_cmre_1.all = C2_cmre_1  
+      REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
+    ASSERT AV0_cmre_2.all = C0_cmre_2  
+      REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
+    ASSERT AV2_cmre_2.all = C2_cmre_2  
+      REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
+    ASSERT AV0_cca1_7.all = C0_cca1_7  
+      REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
+    ASSERT AV2_cca1_7.all = C2_cca1_7  
+      REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
+    ASSERT AV0_cmre_3.all = C0_cmre_3  
+      REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
+    ASSERT AV2_cmre_3.all = C2_cmre_3  
+      REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
+--
+--
+    assert NOT( ( AV0_scre_1.all = C0_scre_1 ) 
+                and ( AV2_scre_1.all = C2_scre_1 ) 
+                and ( AV0_cca1_1.all = C0_cca1_1 ) 
+                and ( AV2_cca1_1.all = C2_cca1_1 ) 
+                and ( AV0_cca1_2.all = C0_cca1_2 ) 
+                and ( AV2_cca1_2.all = C2_cca1_2 ) 
+                and ( AV0_cca1_3.all = C0_cca1_3 ) 
+                and ( AV2_cca1_3.all = C2_cca1_3 ) 
+                and ( AV0_cca1_4.all = C0_cca1_4 ) 
+                and ( AV2_cca1_4.all = C2_cca1_4 ) 
+                and ( AV0_cmre_1.all = C0_cmre_1 ) 
+                and ( AV2_cmre_1.all = C2_cmre_1 ) 
+                and ( AV0_cmre_2.all = C0_cmre_2 ) 
+                and ( AV2_cmre_2.all = C2_cmre_2 ) 
+                and ( AV0_cca1_7.all = C0_cca1_7 ) 
+                and ( AV2_cca1_7.all = C2_cca1_7 ) 
+                and ( AV0_cmre_3.all = C0_cmre_3 ) 
+                and ( AV2_cmre_3.all = C2_cmre_3 )) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00517"
+      severity NOTE;
+    assert (    ( AV0_scre_1.all = C0_scre_1 ) 
+                and ( AV2_scre_1.all = C2_scre_1 ) 
+                and ( AV0_cca1_1.all = C0_cca1_1 ) 
+                and ( AV2_cca1_1.all = C2_cca1_1 ) 
+                and ( AV0_cca1_2.all = C0_cca1_2 ) 
+                and ( AV2_cca1_2.all = C2_cca1_2 ) 
+                and ( AV0_cca1_3.all = C0_cca1_3 ) 
+                and ( AV2_cca1_3.all = C2_cca1_3 ) 
+                and ( AV0_cca1_4.all = C0_cca1_4 ) 
+                and ( AV2_cca1_4.all = C2_cca1_4 ) 
+                and ( AV0_cmre_1.all = C0_cmre_1 ) 
+                and ( AV2_cmre_1.all = C2_cmre_1 ) 
+                and ( AV0_cmre_2.all = C0_cmre_2 ) 
+                and ( AV2_cmre_2.all = C2_cmre_2 ) 
+                and ( AV0_cca1_7.all = C0_cca1_7 ) 
+                and ( AV2_cca1_7.all = C2_cca1_7 ) 
+                and ( AV0_cmre_3.all = C0_cmre_3 ) 
+                and ( AV2_cmre_3.all = C2_cmre_3 )) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00517arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd
new file mode 100644
index 0000000..2427b94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd
@@ -0,0 +1,699 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc519.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c03s03b00x00p03n01i00519pkg is
+----------------------------------USING ONLY WHITE MATTER---------------------------------
+------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr    is access boolean ;              --simple boolean type
+  type bit_ptr    is access bit ;                  --simple bit type
+  type char_ptr    is access character;             --simple character type
+  type severity_level_ptr    is access severity_level;--simple severity type
+  type integer_ptr    is access integer;               --simple integer type
+  type real_ptr    is access real;                  --simple real type
+  type time_ptr    is access time;                  --simple time type
+  type natural_ptr    is access natural;               --simple natural type
+  type positive_ptr    is access positive;              --simple positive type
+  type string_ptr    is access string;                --simple string type
+  type bit_vector_ptr    is access bit_vector;            --simple bit_vector type
+
+------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+-------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  
+-------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  
+-------------------------------------------------------------------------------------------
+  
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector    is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector       is array (natural range <>,natural range <>) of bit;
+  type s2char_vector       is array (natural range <>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector    is array (natural range <>,natural range <>) of integer;
+  type s2real_vector       is array (natural range <>,natural range <>) of real;
+  type s2time_vector       is array (natural range <>,natural range <>) of time;
+  type s2natural_vector    is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector    is array (natural range <>,natural range <>) of positive;
+  
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column    is range 1 to 64;
+  type row    is range 1 to 1024;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+-------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+--------------------------------------------------------------------------------------------
+
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                     --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                      --simple integer type
+                          g:real_ptr ;                                 --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i:natural_ptr;                                  --simple natural type
+                          j:positive_ptr;                                    --simple positive type
+                          k:string_ptr;                                   --simple string type
+                          l:bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+--------------------------------------------------------------------------------------------
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+--------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+--------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr       is access boolean_vector;
+  type severity_level_vector_ptr    is access severity_level_vector;
+  type integer_vector_ptr       is access integer_vector;
+  type real_vector_ptr       is access real_vector;
+  type time_vector_ptr       is access time_vector;
+  type natural_vector_ptr       is access natural_vector;
+  type positive_vector_ptr       is access positive_vector;
+--------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr    is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr    is access severity_level_cons_vector;
+  type integer_cons_vector_ptr    is access integer_cons_vector;
+  type real_cons_vector_ptr       is access real_cons_vector;
+  type time_cons_vector_ptr       is access time_cons_vector;
+  type natural_cons_vector_ptr    is access natural_cons_vector;
+  type positive_cons_vector_ptr    is access positive_cons_vector;
+--------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr    is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr    is access real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr    is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr       is access positive_cons_vectorofvector;
+--------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr       is access boolean_vector;
+  type s2bit_vector_ptr       is access s2bit_vector;
+  type s2char_vector_ptr       is access s2char_vector;
+  type s2severity_level_vector_ptr    is access s2severity_level_vector;
+  type s2integer_vector_ptr       is access s2integer_vector;
+  type s2real_vector_ptr       is access s2real_vector;
+  type s2time_vector_ptr       is access s2time_vector;
+  type s2positive_vector_ptr       is access s2positive_vector;
+--------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr    is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr       is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr       is access s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr       is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr    is access s2integer_cons_vector;
+  type s2real_cons_vector_ptr       is access s2real_cons_vector;
+  type s2time_cons_vector_ptr       is access s2time_cons_vector;
+  type s2natural_cons_vector_ptr    is access natural_cons_vector;
+  type s2positive_cons_vector_ptr    is access s2positive_cons_vector;
+--------------------------------------------------------------------------------------------
+  type record_std_package_ptr    is access record_std_package;
+  type record_cons_array_ptr       is access record_cons_array;
+  type record_2cons_array_ptr    is access record_2cons_array;
+  type record_cons_arrayofarray_ptr    is access record_cons_arrayofarray;
+  type record_of_ptr_ptr       is access record_of_ptr;
+  type record_of_records_ptr       is access record_of_records;
+  
+--------------------------------------------------------------------------------------------
+  
+--------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-------------------------------
+  
+  
+  type four_value is ('Z','0','1','X');                                    --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;              --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                    --constrained array
+  function resolution(i:in four_value_vector) return four_value;           --bus resolution
+  subtype four_value_state is resolution four_value;                       --function type   
+  type state_vector is array (natural range <>) of four_value_state;             --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                        --array of an array
+  type primary_memory_module is                                             --record with field
+    record                                                                  --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;           --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr       is access four_value;
+  type four_value_map_ptr    is access four_value_map;
+  type binary_ptr       is access binary;
+  type four_value_vector_ptr    is access four_value_vector;            --ennumerated type
+  type byte_ptr       is access byte;
+  type word_ptr       is access word;
+  type four_value_state_ptr    is access four_value_state;
+  type state_vector_ptr    is access state_vector;                 --type returned by resolu.
+  type primary_memory_ptr    is access primary_memory;
+  type whole_memory_ptr    is access whole_memory;
+  type current_ptr       is access current;
+  type resistance_ptr       is access resistance;
+  type delay_ptr       is access delay;
+  
+-----------------------------------------------------------------------------------------
+end c03s03b00x00p03n01i00519pkg;
+
+package body c03s03b00x00p03n01i00519pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c03s03b00x00p03n01i00519pkg;
+
+use work.c03s03b00x00p03n01i00519pkg.all;
+ENTITY c03s03b00x00p03n01i00519ent IS
+END c03s03b00x00p03n01i00519ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00519arch OF c03s03b00x00p03n01i00519ent IS
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr ;
+    variable var2 : bit_ptr ;
+    variable var3 : char_ptr ;
+    variable var4 : severity_level_ptr ;
+    variable var5 : integer_ptr ;
+    variable var6 : real_ptr ;
+    variable var7 : time_ptr ;
+    variable var8 : natural_ptr ;
+    variable var9 : positive_ptr ;
+    variable var10 : string_ptr ;
+    variable var11 : bit_vector_ptr ;
+    variable var12 : boolean_vector_ptr ;
+    variable var13 : severity_level_vector_ptr ;
+    variable var14 : integer_vector_ptr ;
+    variable var15 : real_vector_ptr ;
+    variable var16 : time_vector_ptr ;
+    variable var17 : natural_vector_ptr ;
+    variable var18 : positive_vector_ptr ;
+    variable var19 : boolean_cons_vector_ptr ;
+    variable var20 : severity_level_cons_vector_ptr ;
+    variable var21 : integer_cons_vector_ptr ;
+    variable var22 : real_cons_vector_ptr ;
+    variable var23 : time_cons_vector_ptr ;
+    variable var24 : natural_cons_vector_ptr ;
+    variable var25 : positive_cons_vector_ptr ;
+    variable var26 : boolean_cons_vectorofvector_ptr ;
+    variable var27 : sev_lvl_cons_vecofvec_ptr ;
+    variable var28 : integer_cons_vectorofvector_ptr ;
+    variable var29 : real_cons_vectorofvector_ptr ;
+    variable var30 : time_cons_vectorofvector_ptr ;
+    variable var31 : natural_cons_vectorofvector_ptr ;
+    variable var32 : posi_cons_vecofvec_ptr ;
+    variable var33 : s2boolean_vector_ptr ;
+    variable var34 : s2bit_vector_ptr ;
+    variable var35 : s2char_vector_ptr ;
+    variable var36 : s2severity_level_vector_ptr ;
+    variable var37 : s2integer_vector_ptr ;
+    variable var38 : s2real_vector_ptr ;
+    variable var39 : s2time_vector_ptr ;
+    variable var40 : s2positive_vector_ptr ;
+    variable var41 : s2boolean_cons_vector_ptr ;
+    variable var42 : s2bit_cons_vector_ptr ;
+    variable var43 : s2char_cons_vector_ptr ;
+    variable var44 : s2sev_lvl_cons_vec_ptr ;
+    variable var45 : s2integer_cons_vector_ptr ;
+    variable var46 : s2real_cons_vector_ptr ;
+    variable var47 : s2time_cons_vector_ptr ;
+    variable var48 : s2natural_cons_vector_ptr ;
+    variable var49 : s2positive_cons_vector_ptr ;
+    variable var50 : record_std_package_ptr ;
+    variable var51 : record_cons_array_ptr ;
+    variable var52 : record_2cons_array_ptr ;
+    variable var53 : record_cons_arrayofarray_ptr ;
+    variable var54 : record_of_ptr_ptr ;
+    variable var55 : record_of_records_ptr ;
+    variable var56 : four_value_ptr ;
+    variable var57 : four_value_map_ptr ;
+    variable var58 : binary_ptr ;
+    variable var59 : four_value_vector_ptr ;
+    variable var60 : byte_ptr ;
+    variable var61 : word_ptr ;
+    variable var62 : four_value_state_ptr ;
+    variable var63 : state_vector_ptr ;
+    variable var64 : primary_memory_ptr ;
+    variable var65 : whole_memory_ptr ;
+    variable var66 : current_ptr ;
+    variable var67 : resistance_ptr ;
+    variable var68 : delay_ptr ;
+  BEGIN
+    assert (var1 = null)
+      report "var1 has not been set to null." severity FAILURE ;
+    assert (var2 = null)
+      report "var2 has not been set to null." severity FAILURE ;
+    assert (var3 = null)
+      report "var3 has not been set to null." severity FAILURE ;
+    assert (var4 = null)
+      report "var4 has not been set to null." severity FAILURE ;
+    assert (var5 = null)
+      report "var5 has not been set to null." severity FAILURE ;
+    assert (var6 = null)
+      report "var6 has not been set to null." severity FAILURE ;
+    assert (var7 = null)
+      report "var7 has not been set to null." severity FAILURE ;
+    assert (var8 = null)
+      report "var8 has not been set to null." severity FAILURE ;
+    assert (var9 = null)
+      report "var9 has not been set to null." severity FAILURE ;
+    assert (var10 = null)
+      report "var10 has not been set to null." severity FAILURE ;
+    assert (var11 = null)
+      report "var11 has not been set to null." severity FAILURE ;
+    assert (var12 = null)
+      report "var12 has not been set to null." severity FAILURE ;
+    assert (var13 = null)
+      report "var13 has not been set to null." severity FAILURE ;
+    assert (var14 = null)
+      report "var14 has not been set to null." severity FAILURE ;
+    assert (var15 = null)
+      report "var15 has not been set to null." severity FAILURE ;
+    assert (var16 = null)
+      report "var16 has not been set to null." severity FAILURE ;
+    assert (var17 = null)
+      report "var17 has not been set to null." severity FAILURE ;
+    assert (var18 = null)
+      report "var18 has not been set to null." severity FAILURE ;
+    assert (var19 = null)
+      report "var19 has not been set to null." severity FAILURE ;
+    assert (var20 = null)
+      report "var20 has not been set to null." severity FAILURE ;
+    assert (var21 = null)
+      report "var21 has not been set to null." severity FAILURE ;
+    assert (var22 = null)
+      report "var22 has not been set to null." severity FAILURE ;
+    assert (var23 = null)
+      report "var23 has not been set to null." severity FAILURE ;
+    assert (var24 = null)
+      report "var24 has not been set to null." severity FAILURE ;
+    assert (var25 = null)
+      report "var25 has not been set to null." severity FAILURE ;
+    assert (var26 = null)
+      report "var26 has not been set to null." severity FAILURE ;
+    assert (var27 = null)
+      report "var27 has not been set to null." severity FAILURE ;
+    assert (var28 = null)
+      report "var28 has not been set to null." severity FAILURE ;
+    assert (var29 = null)
+      report "var29 has not been set to null." severity FAILURE ;
+    assert (var30 = null)
+      report "var30 has not been set to null." severity FAILURE ;
+    assert (var31 = null)
+      report "var31 has not been set to null." severity FAILURE ;
+    assert (var32 = null)
+      report "var32 has not been set to null." severity FAILURE ;
+    assert (var33 = null)
+      report "var33 has not been set to null." severity FAILURE ;
+    assert (var34 = null)
+      report "var34 has not been set to null." severity FAILURE ;
+    assert (var35 = null)
+      report "var35 has not been set to null." severity FAILURE ;
+    assert (var36 = null)
+      report "var36 has not been set to null." severity FAILURE ;
+    assert (var37 = null)
+      report "var37 has not been set to null." severity FAILURE ;
+    assert (var38 = null)
+      report "var38 has not been set to null." severity FAILURE ;
+    assert (var39 = null)
+      report "var39 has not been set to null." severity FAILURE ;
+    assert (var40 = null)
+      report "var40 has not been set to null." severity FAILURE ;
+    assert (var41 = null)
+      report "var41 has not been set to null." severity FAILURE ;
+    assert (var42 = null)
+      report "var42 has not been set to null." severity FAILURE ;
+    assert (var43 = null)
+      report "var43 has not been set to null." severity FAILURE ;
+    assert (var44 = null)
+      report "var44 has not been set to null." severity FAILURE ;
+    assert (var45 = null)
+      report "var45 has not been set to null." severity FAILURE ;
+    assert (var46 = null)
+      report "var46 has not been set to null." severity FAILURE ;
+    assert (var47 = null)
+      report "var47 has not been set to null." severity FAILURE ;
+    assert (var48 = null)
+      report "var48 has not been set to null." severity FAILURE ;
+    assert (var49 = null)
+      report "var49 has not been set to null." severity FAILURE ;
+    assert (var50 = null)
+      report "var50 has not been set to null." severity FAILURE ;
+    assert (var51 = null)
+      report "var51 has not been set to null." severity FAILURE ;
+    assert (var52 = null)
+      report "var52 has not been set to null." severity FAILURE ;
+    assert (var53 = null)
+      report "var53 has not been set to null." severity FAILURE ;
+    assert (var54 = null)
+      report "var54 has not been set to null." severity FAILURE ;
+    assert (var55 = null)
+      report "var55 has not been set to null." severity FAILURE ;
+    assert (var56 = null)
+      report "var56 has not been set to null." severity FAILURE ;
+    assert (var57 = null)
+      report "var57 has not been set to null." severity FAILURE ;
+    assert (var58 = null)
+      report "var58 has not been set to null." severity FAILURE ;
+    assert (var59 = null)
+      report "var59 has not been set to null." severity FAILURE ;
+    assert (var60 = null)
+      report "var60 has not been set to null." severity FAILURE ;
+    assert (var61 = null)
+      report "var61 has not been set to null." severity FAILURE ;
+    assert (var62 = null)
+      report "var62 has not been set to null." severity FAILURE ;
+    assert (var63 = null)
+      report "var63 has not been set to null." severity FAILURE ;
+    assert (var64 = null)
+      report "var64 has not been set to null." severity FAILURE ;
+    assert (var65 = null)
+      report "var65 has not been set to null." severity FAILURE ;
+    assert (var66 = null)
+      report "var66 has not been set to null." severity FAILURE ;
+    assert (var67 = null)
+      report "var67 has not been set to null." severity FAILURE ;
+    assert (var68 = null)
+      report "var68 has not been set to null." severity FAILURE ;
+    assert   NOT((var1 = null)
+                 and (var2 = null)
+                 and (var3 = null)
+                 and (var4 = null)
+                 and (var5 = null)
+                 and (var6 = null)
+                 and (var7 = null)
+                 and (var8 = null)
+                 and (var9 = null)
+                 and (var10 = null)
+                 and (var11 = null)
+                 and (var12 = null)
+                 and (var13 = null)
+                 and (var14 = null)
+                 and (var15 = null)
+                 and (var16 = null)
+                 and (var17 = null)
+                 and (var18 = null)
+                 and (var19 = null)
+                 and (var20 = null)
+                 and (var21 = null)
+                 and (var22 = null)
+                 and (var23 = null)
+                 and (var24 = null)
+                 and (var25 = null)
+                 and (var26 = null)
+                 and (var27 = null)
+                 and (var28 = null)
+                 and (var29 = null)
+                 and (var30 = null)
+                 and (var31 = null)
+                 and (var32 = null)
+                 and (var33 = null)
+                 and (var34 = null)
+                 and (var35 = null)
+                 and (var36 = null)
+                 and (var37 = null)
+                 and (var38 = null)
+                 and (var39 = null)
+                 and (var40 = null)
+                 and (var41 = null)
+                 and (var42 = null)
+                 and (var43 = null)
+                 and (var44 = null)
+                 and (var45 = null)
+                 and (var46 = null)
+                 and (var47 = null)
+                 and (var48 = null)
+                 and (var49 = null)
+                 and (var50 = null)
+                 and (var51 = null)
+                 and (var52 = null)
+                 and (var53 = null)
+                 and (var54 = null)
+                 and (var55 = null)
+                 and (var56 = null)
+                 and (var57 = null)
+                 and (var58 = null)
+                 and (var59 = null)
+                 and (var60 = null)
+                 and (var61 = null)
+                 and (var62 = null)
+                 and (var63 = null)
+                 and (var64 = null)
+                 and (var65 = null)
+                 and (var66 = null)
+                 and (var67 = null)
+                 and (var68 = null))
+      report "***PASSED TEST: c03s03b00x00p03n01i00519"
+      severity NOTE;
+    assert      ((var1 = null)
+                 and (var2 = null)
+                 and (var3 = null)
+                 and (var4 = null)
+                 and (var5 = null)
+                 and (var6 = null)
+                 and (var7 = null)
+                 and (var8 = null)
+                 and (var9 = null)
+                 and (var10 = null)
+                 and (var11 = null)
+                 and (var12 = null)
+                 and (var13 = null)
+                 and (var14 = null)
+                 and (var15 = null)
+                 and (var16 = null)
+                 and (var17 = null)
+                 and (var18 = null)
+                 and (var19 = null)
+                 and (var20 = null)
+                 and (var21 = null)
+                 and (var22 = null)
+                 and (var23 = null)
+                 and (var24 = null)
+                 and (var25 = null)
+                 and (var26 = null)
+                 and (var27 = null)
+                 and (var28 = null)
+                 and (var29 = null)
+                 and (var30 = null)
+                 and (var31 = null)
+                 and (var32 = null)
+                 and (var33 = null)
+                 and (var34 = null)
+                 and (var35 = null)
+                 and (var36 = null)
+                 and (var37 = null)
+                 and (var38 = null)
+                 and (var39 = null)
+                 and (var40 = null)
+                 and (var41 = null)
+                 and (var42 = null)
+                 and (var43 = null)
+                 and (var44 = null)
+                 and (var45 = null)
+                 and (var46 = null)
+                 and (var47 = null)
+                 and (var48 = null)
+                 and (var49 = null)
+                 and (var50 = null)
+                 and (var51 = null)
+                 and (var52 = null)
+                 and (var53 = null)
+                 and (var54 = null)
+                 and (var55 = null)
+                 and (var56 = null)
+                 and (var57 = null)
+                 and (var58 = null)
+                 and (var59 = null)
+                 and (var60 = null)
+                 and (var61 = null)
+                 and (var62 = null)
+                 and (var63 = null)
+                 and (var64 = null)
+                 and (var65 = null)
+                 and (var66 = null)
+                 and (var67 = null)
+                 and (var68 = null))
+      report "***FAILED TEST: c03s03b00x00p03n01i00519 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00519arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd
new file mode 100644
index 0000000..9fd174f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc52.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n01i00052pkg is
+  constant test: integer;
+end c04s03b01x01p04n01i00052pkg;
+
+package body c04s03b01x01p04n01i00052pkg is
+  constant test, test2: integer := 10; -- No_failure_here
+end c04s03b01x01p04n01i00052pkg;
+
+
+use work.c04s03b01x01p04n01i00052pkg.all;
+ENTITY c04s03b01x01p04n01i00052ent IS
+END c04s03b01x01p04n01i00052ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00052arch OF c04s03b01x01p04n01i00052ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( test = 10 ) 
+      report "***PASSED TEST: c04s03b01x01p04n01i00052"
+      severity NOTE;
+    assert ( test = 10 ) 
+      report "***FAILED TEST: c04s03b01x01p04n01i00052 - A deferred constant declaration appear in a package declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n01i00052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd
new file mode 100644
index 0000000..cdfa796
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd
@@ -0,0 +1,1366 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc520.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00520pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00520pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00520pkg;
+
+USE   work.c03s03b00x00p03n04i00520pkg.ALL;ENTITY c03s03b00x00p03n04i00520ent IS
+                                                                                      END c03s03b00x00p03n04i00520ent;
+
+                                                                                      ARCHITECTURE c03s03b00x00p03n04i00520arch OF c03s03b00x00p03n04i00520ent IS
+--
+--          Access type declarations
+--
+                                                                                        TYPE at_usa1_1 IS ACCESS t_usa1_1 ;
+                                                                                        TYPE at_usa1_2 IS ACCESS t_usa1_2 ;
+                                                                                        TYPE at_usa1_3 IS ACCESS t_usa1_3 ;
+                                                                                        TYPE at_usa1_4 IS ACCESS t_usa1_4 ;
+                                                                                        TYPE at_csa1_1 IS ACCESS t_csa1_1 ;
+                                                                                        TYPE at_csa1_2 IS ACCESS t_csa1_2 ;
+                                                                                        TYPE at_csa1_3 IS ACCESS t_csa1_3 ;
+                                                                                        TYPE at_csa1_4 IS ACCESS t_csa1_4 ;
+--
+--
+                                                                                      BEGIN
+                                                                                        TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+                                                                                          VARIABLE AV0_usa1_1 : at_usa1_1 ;
+                                                                                          VARIABLE AV2_usa1_1 : at_usa1_1 ;
+                                                                                          VARIABLE AV0_usa1_2 : at_usa1_2 ;
+                                                                                          VARIABLE AV2_usa1_2 : at_usa1_2 ;
+                                                                                          VARIABLE AV0_usa1_3 : at_usa1_3 ;
+                                                                                          VARIABLE AV2_usa1_3 : at_usa1_3 ;
+                                                                                          VARIABLE AV0_usa1_4 : at_usa1_4 ;
+                                                                                          VARIABLE AV2_usa1_4 : at_usa1_4 ;
+                                                                                          VARIABLE AV0_csa1_1 : at_csa1_1 ;
+                                                                                          VARIABLE AV2_csa1_1 : at_csa1_1 ;
+                                                                                          VARIABLE AV0_csa1_2 : at_csa1_2 ;
+                                                                                          VARIABLE AV2_csa1_2 : at_csa1_2 ;
+                                                                                          VARIABLE AV0_csa1_3 : at_csa1_3 ;
+                                                                                          VARIABLE AV2_csa1_3 : at_csa1_3 ;
+                                                                                          VARIABLE AV0_csa1_4 : at_csa1_4 ;
+                                                                                          VARIABLE AV2_csa1_4 : at_csa1_4 ;
+--
+--
+                                                                                        BEGIN
+--
+--          Allocation of access values
+--
+                                                                                          AV0_usa1_1 := NEW t_usa1_1 (st_ind1 ) ;
+                                                                                          AV0_usa1_2 := NEW t_usa1_2 (st_ind2 ) ;
+                                                                                          AV0_usa1_3 := NEW t_usa1_3 (st_ind3 ) ;
+                                                                                          AV0_usa1_4 := NEW t_usa1_4 (st_ind4 ) ;
+                                                                                          AV0_csa1_1 := NEW t_csa1_1 ;
+                                                                                          AV0_csa1_2 := NEW t_csa1_2 ;
+                                                                                          AV0_csa1_3 := NEW t_csa1_3 ;
+                                                                                          AV0_csa1_4 := NEW t_csa1_4 ;
+---
+                                                                                          AV2_usa1_1 := NEW t_usa1_1 ' ( C2_csa1_1 ) ;
+                                                                                          AV2_usa1_2 := NEW t_usa1_2 ' ( C2_csa1_2 ) ;
+                                                                                          AV2_usa1_3 := NEW t_usa1_3 ' ( C2_csa1_3 ) ;
+                                                                                          AV2_usa1_4 := NEW t_usa1_4 ' ( C2_csa1_4 ) ;
+                                                                                          AV2_csa1_1 := NEW t_csa1_1 ' ( C2_csa1_1 ) ;
+                                                                                          AV2_csa1_2 := NEW t_csa1_2 ' ( C2_csa1_2 ) ;
+                                                                                          AV2_csa1_3 := NEW t_csa1_3 ' ( C2_csa1_3 ) ;
+                                                                                          AV2_csa1_4 := NEW t_csa1_4 ' ( C2_csa1_4 ) ;
+--
+--
+                                                                                          ASSERT AV0_usa1_1.all = C0_csa1_1  
+                                                                                            REPORT "Improper initialization of AV0_usa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_1.all = C2_csa1_1  
+                                                                                            REPORT "Improper initialization of AV2_usa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_2.all = C0_csa1_2  
+                                                                                            REPORT "Improper initialization of AV0_usa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_2.all = C2_csa1_2  
+                                                                                            REPORT "Improper initialization of AV2_usa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_3.all = C0_csa1_3  
+                                                                                            REPORT "Improper initialization of AV0_usa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_3.all = C2_csa1_3  
+                                                                                            REPORT "Improper initialization of AV2_usa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_4.all = C0_csa1_4  
+                                                                                            REPORT "Improper initialization of AV0_usa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_4.all = C2_csa1_4  
+                                                                                            REPORT "Improper initialization of AV2_usa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_1.all = C0_csa1_1  
+                                                                                            REPORT "Improper initialization of AV0_csa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_1.all = C2_csa1_1  
+                                                                                            REPORT "Improper initialization of AV2_csa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_2.all = C0_csa1_2  
+                                                                                            REPORT "Improper initialization of AV0_csa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_2.all = C2_csa1_2  
+                                                                                            REPORT "Improper initialization of AV2_csa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_3.all = C0_csa1_3  
+                                                                                            REPORT "Improper initialization of AV0_csa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_3.all = C2_csa1_3  
+                                                                                            REPORT "Improper initialization of AV2_csa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_4.all = C0_csa1_4  
+                                                                                            REPORT "Improper initialization of AV0_csa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_4.all = C2_csa1_4  
+                                                                                            REPORT "Improper initialization of AV2_csa1_4" SEVERITY FAILURE;
+--
+--
+                                                                                          assert NOT( ( AV0_usa1_1.all = C0_csa1_1 ) 
+                                                                                                      and ( AV2_usa1_1.all = C2_csa1_1 ) 
+                                                                                                      and ( AV0_usa1_2.all = C0_csa1_2 ) 
+                                                                                                      and ( AV2_usa1_2.all = C2_csa1_2 ) 
+                                                                                                      and ( AV0_usa1_3.all = C0_csa1_3 ) 
+                                                                                                      and ( AV2_usa1_3.all = C2_csa1_3 ) 
+                                                                                                      and ( AV0_usa1_4.all = C0_csa1_4 ) 
+                                                                                                      and ( AV2_usa1_4.all = C2_csa1_4 ) 
+                                                                                                      and ( AV0_csa1_1.all = C0_csa1_1 ) 
+                                                                                                      and ( AV2_csa1_1.all = C2_csa1_1 ) 
+                                                                                                      and ( AV0_csa1_2.all = C0_csa1_2 ) 
+                                                                                                      and ( AV2_csa1_2.all = C2_csa1_2 ) 
+                                                                                                      and ( AV0_csa1_3.all = C0_csa1_3 ) 
+                                                                                                      and ( AV2_csa1_3.all = C2_csa1_3 ) 
+                                                                                                      and ( AV0_csa1_4.all = C0_csa1_4 ) 
+                                                                                                      and ( AV2_csa1_4.all = C2_csa1_4 )) 
+                                                                                            report "***PASSED TEST: c03s03b00x00p03n04i00520"
+                                                                                            severity NOTE;
+                                                                                          assert    (   ( AV0_usa1_1.all = C0_csa1_1 ) 
+                                                                                                        and ( AV2_usa1_1.all = C2_csa1_1 ) 
+                                                                                                        and ( AV0_usa1_2.all = C0_csa1_2 ) 
+                                                                                                        and ( AV2_usa1_2.all = C2_csa1_2 ) 
+                                                                                                        and ( AV0_usa1_3.all = C0_csa1_3 ) 
+                                                                                                        and ( AV2_usa1_3.all = C2_csa1_3 ) 
+                                                                                                        and ( AV0_usa1_4.all = C0_csa1_4 ) 
+                                                                                                        and ( AV2_usa1_4.all = C2_csa1_4 ) 
+                                                                                                        and ( AV0_csa1_1.all = C0_csa1_1 ) 
+                                                                                                        and ( AV2_csa1_1.all = C2_csa1_1 ) 
+                                                                                                        and ( AV0_csa1_2.all = C0_csa1_2 ) 
+                                                                                                        and ( AV2_csa1_2.all = C2_csa1_2 ) 
+                                                                                                        and ( AV0_csa1_3.all = C0_csa1_3 ) 
+                                                                                                        and ( AV2_csa1_3.all = C2_csa1_3 ) 
+                                                                                                        and ( AV0_csa1_4.all = C0_csa1_4 ) 
+                                                                                                        and ( AV2_csa1_4.all = C2_csa1_4 )) 
+                                                                                            report "***FAILED TEST: c03s03b00x00p03n04i00520 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+                                                                                            severity ERROR;
+                                                                                          wait;
+                                                                                        END PROCESS TESTING;
+
+                                                                                      END c03s03b00x00p03n04i00520arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd
new file mode 100644
index 0000000..323baad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd
@@ -0,0 +1,1373 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc521.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00521pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00521pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00521pkg;
+
+USE   work.c03s03b00x00p03n04i00521pkg.ALL;
+ENTITY c03s03b00x00p03n04i00521ent IS
+END c03s03b00x00p03n04i00521ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00521arch OF c03s03b00x00p03n04i00521ent IS
+--
+--          Access type declarations
+--
+  TYPE at_usa2_1 IS ACCESS t_usa2_1 ;
+  TYPE at_usa3_1 IS ACCESS t_usa3_1 ;
+  TYPE at_usa4_1 IS ACCESS t_usa4_1 ;
+  TYPE at_csa2_1 IS ACCESS t_csa2_1 ;
+  TYPE at_csa3_1 IS ACCESS t_csa3_1 ;
+  TYPE at_csa4_1 IS ACCESS t_csa4_1 ;
+  TYPE at_cca2_1 IS ACCESS t_cca2_1 ;
+  TYPE at_cca2_2 IS ACCESS t_cca2_2 ;
+  TYPE at_cca3_1 IS ACCESS t_cca3_1 ;
+  TYPE at_cca3_2 IS ACCESS t_cca3_2 ;
+--
+--
+BEGIN
+  TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+    VARIABLE AV0_usa2_1 : at_usa2_1 ;
+    VARIABLE AV2_usa2_1 : at_usa2_1 ;
+    VARIABLE AV0_usa3_1 : at_usa3_1 ;
+    VARIABLE AV2_usa3_1 : at_usa3_1 ;
+    VARIABLE AV0_usa4_1 : at_usa4_1 ;
+    VARIABLE AV2_usa4_1 : at_usa4_1 ;
+    VARIABLE AV0_csa2_1 : at_csa2_1 ;
+    VARIABLE AV2_csa2_1 : at_csa2_1 ;
+    VARIABLE AV0_csa3_1 : at_csa3_1 ;
+    VARIABLE AV2_csa3_1 : at_csa3_1 ;
+    VARIABLE AV0_csa4_1 : at_csa4_1 ;
+    VARIABLE AV2_csa4_1 : at_csa4_1 ;
+    VARIABLE AV0_cca2_1 : at_cca2_1 ;
+    VARIABLE AV2_cca2_1 : at_cca2_1 ;
+    VARIABLE AV0_cca2_2 : at_cca2_2 ;
+    VARIABLE AV2_cca2_2 : at_cca2_2 ;
+    VARIABLE AV0_cca3_1 : at_cca3_1 ;
+    VARIABLE AV2_cca3_1 : at_cca3_1 ;
+    VARIABLE AV0_cca3_2 : at_cca3_2 ;
+    VARIABLE AV2_cca3_2 : at_cca3_2 ;
+--
+--
+  BEGIN
+--
+--          Allocation of access values
+--
+    AV0_usa2_1 := NEW t_usa2_1 (                  st_ind2, st_ind1 ) ;
+    AV0_usa3_1 := NEW t_usa3_1 (         st_ind3, st_ind2, st_ind1 ) ;
+    AV0_usa4_1 := NEW t_usa4_1 (st_ind4, st_ind3, st_ind2, st_ind1 ) ;
+    AV0_csa2_1 := NEW t_csa2_1 ;
+    AV0_csa3_1 := NEW t_csa3_1 ;
+    AV0_csa4_1 := NEW t_csa4_1 ;
+    AV0_cca2_1 := NEW t_cca2_1 ;
+    AV0_cca2_2 := NEW t_cca2_2 ;
+    AV0_cca3_1 := NEW t_cca3_1 ;
+    AV0_cca3_2 := NEW t_cca3_2 ;
+---
+    AV2_usa2_1 := NEW t_usa2_1 ' ( C2_csa2_1 ) ;
+    AV2_usa3_1 := NEW t_usa3_1 ' ( C2_csa3_1 ) ;
+    AV2_usa4_1 := NEW t_usa4_1 ' ( C2_csa4_1 ) ;
+    AV2_csa2_1 := NEW t_csa2_1 ' ( C2_csa2_1 ) ;
+    AV2_csa3_1 := NEW t_csa3_1 ' ( C2_csa3_1 ) ;
+    AV2_csa4_1 := NEW t_csa4_1 ' ( C2_csa4_1 ) ;
+    AV2_cca2_1 := NEW t_cca2_1 ' ( C2_cca2_1 ) ;
+    AV2_cca2_2 := NEW t_cca2_2 ' ( C2_cca2_2 ) ;
+    AV2_cca3_1 := NEW t_cca3_1 ' ( C2_cca3_1 ) ;
+    AV2_cca3_2 := NEW t_cca3_2 ' ( C2_cca3_2 ) ;
+--
+--
+    ASSERT AV0_usa2_1.all = C0_csa2_1  
+      REPORT "Improper initialization of AV0_usa2_1" SEVERITY FAILURE;
+    ASSERT AV2_usa2_1.all = C2_csa2_1  
+      REPORT "Improper initialization of AV2_usa2_1" SEVERITY FAILURE;
+    ASSERT AV0_usa3_1.all = C0_csa3_1  
+      REPORT "Improper initialization of AV0_usa3_1" SEVERITY FAILURE;
+    ASSERT AV2_usa3_1.all = C2_csa3_1  
+      REPORT "Improper initialization of AV2_usa3_1" SEVERITY FAILURE;
+    ASSERT AV0_usa4_1.all = C0_csa4_1  
+      REPORT "Improper initialization of AV0_usa4_1" SEVERITY FAILURE;
+    ASSERT AV2_usa4_1.all = C2_csa4_1  
+      REPORT "Improper initialization of AV2_usa4_1" SEVERITY FAILURE;
+    ASSERT AV0_csa2_1.all = C0_csa2_1  
+      REPORT "Improper initialization of AV0_csa2_1" SEVERITY FAILURE;
+    ASSERT AV2_csa2_1.all = C2_csa2_1  
+      REPORT "Improper initialization of AV2_csa2_1" SEVERITY FAILURE;
+    ASSERT AV0_csa3_1.all = C0_csa3_1  
+      REPORT "Improper initialization of AV0_csa3_1" SEVERITY FAILURE;
+    ASSERT AV2_csa3_1.all = C2_csa3_1  
+      REPORT "Improper initialization of AV2_csa3_1" SEVERITY FAILURE;
+    ASSERT AV0_csa4_1.all = C0_csa4_1  
+      REPORT "Improper initialization of AV0_csa4_1" SEVERITY FAILURE;
+    ASSERT AV2_csa4_1.all = C2_csa4_1  
+      REPORT "Improper initialization of AV2_csa4_1" SEVERITY FAILURE;
+    ASSERT AV0_cca2_1.all = C0_cca2_1  
+      REPORT "Improper initialization of AV0_cca2_1" SEVERITY FAILURE;
+    ASSERT AV2_cca2_1.all = C2_cca2_1  
+      REPORT "Improper initialization of AV2_cca2_1" SEVERITY FAILURE;
+    ASSERT AV0_cca2_2.all = C0_cca2_2  
+      REPORT "Improper initialization of AV0_cca2_2" SEVERITY FAILURE;
+    ASSERT AV2_cca2_2.all = C2_cca2_2  
+      REPORT "Improper initialization of AV2_cca2_2" SEVERITY FAILURE;
+    ASSERT AV0_cca3_1.all = C0_cca3_1  
+      REPORT "Improper initialization of AV0_cca3_1" SEVERITY FAILURE;
+    ASSERT AV2_cca3_1.all = C2_cca3_1  
+      REPORT "Improper initialization of AV2_cca3_1" SEVERITY FAILURE;
+    ASSERT AV0_cca3_2.all = C0_cca3_2  
+      REPORT "Improper initialization of AV0_cca3_2" SEVERITY FAILURE;
+    ASSERT AV2_cca3_2.all = C2_cca3_2  
+      REPORT "Improper initialization of AV2_cca3_2" SEVERITY FAILURE;
+--
+--
+    assert NOT( ( AV0_usa2_1.all = C0_csa2_1 ) 
+                and ( AV2_usa2_1.all = C2_csa2_1 ) 
+                and ( AV0_usa3_1.all = C0_csa3_1 ) 
+                and ( AV2_usa3_1.all = C2_csa3_1 ) 
+                and ( AV0_usa4_1.all = C0_csa4_1 ) 
+                and ( AV2_usa4_1.all = C2_csa4_1 ) 
+                and ( AV0_csa2_1.all = C0_csa2_1 ) 
+                and ( AV2_csa2_1.all = C2_csa2_1 ) 
+                and ( AV0_csa3_1.all = C0_csa3_1 ) 
+                and ( AV2_csa3_1.all = C2_csa3_1 )) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00521"
+      severity NOTE;
+    assert  (   ( AV0_usa2_1.all = C0_csa2_1 ) 
+                and ( AV2_usa2_1.all = C2_csa2_1 ) 
+                and ( AV0_usa3_1.all = C0_csa3_1 ) 
+                and ( AV2_usa3_1.all = C2_csa3_1 ) 
+                and ( AV0_usa4_1.all = C0_csa4_1 ) 
+                and ( AV2_usa4_1.all = C2_csa4_1 ) 
+                and ( AV0_csa2_1.all = C0_csa2_1 ) 
+                and ( AV2_csa2_1.all = C2_csa2_1 ) 
+                and ( AV0_csa3_1.all = C0_csa3_1 ) 
+                and ( AV2_csa3_1.all = C2_csa3_1 )) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00521 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00521arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd
new file mode 100644
index 0000000..1226d5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd
@@ -0,0 +1,217 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc522.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n01i00522ent IS
+END c03s03b00x00p03n01i00522ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00522arch OF c03s03b00x00p03n01i00522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare access types and access objects everywhere.
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    AC1 is access SWITCH_LEVEL;
+
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    AC2 is access LOGIC_SWITCH;
+
+    -- Access types.
+    type    AC3 is access AC2;
+
+    -- array types.  Constrained.
+    type WORD   is array(0 to 31) of BIT;
+    type    AC4 is access WORD;
+
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type AC5 is access DATE;
+
+    -- INTEGER types.
+    type AC6 is access INTEGER;
+    
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type AC7 is access POSITIVE;
+    
+    -- Physical types.
+    type AC8 is access TIME;
+    
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type AC10 is access DISTANCE;
+    
+    -- floating point types.
+    type AC11 is access REAL;
+    
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type AC12 is access POSITIVE_R;
+    -- Predefined enumerated types.
+    type AC13 is access BIT;
+    
+    type AC14 is access SEVERITY_LEVEL;
+    
+    type AC15 is access BOOLEAN;
+    
+    type AC16 is access CHARACTER;
+    
+    -- Other predefined types.
+    type AC17 is access NATURAL;
+    
+    type AC18 is access STRING;
+    
+    type AC19 is access BIT_VECTOR;
+    
+    type MEMORY is array(0 to 64) of WORD;
+    type AC20 is access MEMORY;
+    
+    -- Declare all the variables.
+    variable VAR1 : AC1;
+    variable VAR2 : AC2;
+    variable VAR3 : AC3;
+    variable VAR4 : AC4;
+    variable VAR5 : AC5;
+    variable VAR6 : AC6;
+    variable VAR7 : AC7;
+    variable VAR8 : AC8;
+    variable VAR10: AC10;
+    variable VAR11: AC11;
+    variable VAR12: AC12;
+    variable VAR13: AC13;
+    variable VAR14: AC14;
+    variable VAR15: AC15;
+    variable VAR16: AC16;
+    variable VAR17: AC17;
+    variable VAR18: AC18;
+    variable VAR19: AC19;
+    variable VAR20: AC20;
+  BEGIN
+    -- Assert that all variables are initially NULL.
+    assert (VAR1 = null)
+      report "VAR1 has not been set to NULL.";
+    assert (VAR2 = null)
+      report "VAR2 has not been set to NULL.";
+    assert (VAR3 = null)
+      report "VAR3 has not been set to NULL.";
+    assert (VAR4 = null)
+      report "VAR4 has not been set to NULL.";
+    assert (VAR5 = null)
+      report "VAR5 has not been set to NULL.";
+    assert (VAR6 = null)
+      report "VAR6 has not been set to NULL.";
+    assert (VAR7 = null)
+      report "VAR7 has not been set to NULL.";
+    assert (VAR8 = null)
+      report "VAR8 has not been set to NULL.";
+    assert (VAR10 = null)
+      report "VAR10 has not been set to NULL.";
+    assert (VAR11 = null)
+      report "VAR11 has not been set to NULL.";
+    assert (VAR12 = null)
+      report "VAR12 has not been set to NULL.";
+    assert (VAR13 = null)
+      report "VAR13 has not been set to NULL.";
+    assert (VAR14 = null)
+      report "VAR14 has not been set to NULL.";
+    assert (VAR15 = null)
+      report "VAR15 has not been set to NULL.";
+    assert (VAR16 = null)
+      report "VAR16 has not been set to NULL.";
+    assert (VAR17 = null)
+      report "VAR17 has not been set to NULL.";
+    assert (VAR18 = null)
+      report "VAR18 has not been set to NULL.";
+    assert (VAR19 = null)
+      report "VAR19 has not been set to NULL.";
+    assert (VAR20 = null)
+      report "VAR20 has not been set to NULL.";
+    assert   NOT(      (VAR1 = null)
+                       and (VAR2 = null)
+                       and (VAR3 = null)
+                       and (VAR4 = null)
+                       and (VAR5 = null)
+                       and (VAR6 = null)
+                       and (VAR7 = null)
+                       and (VAR8 = null)
+                       and (VAR10 = null)
+                       and (VAR11 = null)
+                       and (VAR12 = null)
+                       and (VAR13 = null)
+                       and (VAR14 = null)
+                       and (VAR15 = null)
+                       and (VAR16 = null)
+                       and (VAR17 = null)
+                       and (VAR18 = null)
+                       and (VAR19 = null)
+                       and (VAR20 = null))
+      report "***PASSED TEST: c03s03b00x00p03n01i00522"
+      severity NOTE;
+    assert   (      (VAR1 = null)
+                    and (VAR2 = null)
+                    and (VAR3 = null)
+                    and (VAR4 = null)
+                    and (VAR5 = null)
+                    and (VAR6 = null)
+                    and (VAR7 = null)
+                    and (VAR8 = null)
+                    and (VAR10 = null)
+                    and (VAR11 = null)
+                    and (VAR12 = null)
+                    and (VAR13 = null)
+                    and (VAR14 = null)
+                    and (VAR15 = null)
+                    and (VAR16 = null)
+                    and (VAR17 = null)
+                    and (VAR18 = null)
+                    and (VAR19 = null)
+                    and (VAR20 = null))
+      report "***FAILED TEST: c03s03b00x00p03n01i00522 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd
new file mode 100644
index 0000000..3f4d14d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc523.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c03s03b00x00p03n03i00523pkg is
+  type udf_int       is range -500 to 500;
+  type udf_real       is range -2000.0 to 2000.0;
+  type udf_int_ptr    is access udf_int;
+  type udf_real_ptr    is access udf_real;
+end c03s03b00x00p03n03i00523pkg;
+
+use work.c03s03b00x00p03n03i00523pkg.all;
+
+ENTITY c03s03b00x00p03n03i00523ent IS
+END c03s03b00x00p03n03i00523ent;
+
+ARCHITECTURE c03s03b00x00p03n03i00523arch OF c03s03b00x00p03n03i00523ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype int_ptr is udf_int_ptr;
+    
+    variable v_int_ptr1: int_ptr    := new udf_int'(365);
+    variable v_int_ptr2: int_ptr;
+    variable v_int_ptr3: int_ptr    := v_int_ptr1;
+    variable v_int_ptr4: int_ptr    := new udf_int'(-365);
+    
+    subtype real_ptr is udf_real_ptr;
+    
+    variable v_real_ptr1: real_ptr    := new udf_real'(365.12);
+    variable v_real_ptr2: real_ptr;
+    variable v_real_ptr3: real_ptr    := v_real_ptr1;
+    variable v_real_ptr4: real_ptr    := new udf_real'(-365.12);
+    constant epislon: udf_real    := 0.00001;
+
+  BEGIN
+
+    assert v_int_ptr1.all    = 365;
+    assert v_int_ptr2    = null;
+    assert v_int_ptr3.all    = 365;
+    assert v_int_ptr4.all    = -365;
+    
+    v_int_ptr2 := new udf_int'(100);
+    
+    assert v_int_ptr2.all    = 100;
+    
+    assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
+    assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
+    assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
+    assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
+    assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
+    assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
+
+    assert v_real_ptr1.all    = 365.12;
+    assert v_real_ptr2    = null;
+    assert v_real_ptr3.all    = 365.12;
+    assert v_real_ptr4.all    = -365.12;
+    
+    v_real_ptr2 := new udf_real'(100.0);
+    
+    assert v_real_ptr2.all    = 100.0;
+    
+    assert (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon);
+    assert (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon);
+    assert (v_real_ptr1.all + v_real_ptr4.all < epislon);
+    assert (v_real_ptr1.all - v_real_ptr3.all < epislon);
+    assert (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon);
+    assert (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon);
+
+    assert NOT(((v_int_ptr1.all + v_int_ptr3.all) = 730)   and
+               (  (v_int_ptr2.all + v_int_ptr3.all) = 465)   and
+               (  (v_int_ptr1.all + v_int_ptr4.all) = 0)   and
+               (  (v_int_ptr1.all - v_int_ptr3.all) = 0)   and
+               (  (v_int_ptr3.all * v_int_ptr1.all) = 133225)   and
+               (  (v_int_ptr3.all / v_int_ptr1.all) = 1)   and
+               (  (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon))   and
+               (  (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon))   and
+               (  (v_real_ptr1.all + v_real_ptr4.all < epislon))      and
+               (  (v_real_ptr1.all - v_real_ptr3.all < epislon))      and
+               (  (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon))and
+               (  (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon)))   
+      report "***PASSED TEST: c03s03b00x00p03n03i00523"
+      severity NOTE;
+    assert   (( (v_int_ptr1.all + v_int_ptr3.all) = 730)   and
+              (  (v_int_ptr2.all + v_int_ptr3.all) = 465)   and
+              (  (v_int_ptr1.all + v_int_ptr4.all) = 0)   and
+              (  (v_int_ptr1.all - v_int_ptr3.all) = 0)   and
+              (  (v_int_ptr3.all * v_int_ptr1.all) = 133225)   and
+              (  (v_int_ptr3.all / v_int_ptr1.all) = 1)   and
+              (  (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon))   and
+              (  (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon))   and
+              (  (v_real_ptr1.all + v_real_ptr4.all < epislon))      and
+              (  (v_real_ptr1.all - v_real_ptr3.all < epislon))      and
+              (  (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon))and
+              (  (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon)))   
+      report "***FAILED TEST: c03s03b00x00p03n03i00523 - User defined integer and floating point types to test for user defined integer and floating point using as base for access type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n03i00523arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd
new file mode 100644
index 0000000..15fc8fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00524ent IS
+END c03s03b00x00p03n04i00524ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type integer_ptr is access integer;
+    variable v_integer_ptr1: integer_ptr := new integer'(365);
+    variable v_integer_ptr2: integer_ptr;
+    variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
+
+
+    type int is range -500 to 500;
+    type int_ptr is access int;
+    variable v_int_ptr1: int_ptr := new int'(365);
+    variable v_int_ptr2: int_ptr;
+    variable v_int_ptr3: int_ptr := v_int_ptr1;
+    variable v_int_ptr4: int_ptr := new int'(-365);
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_integer_ptr1.all = 365;
+    if (v_integer_ptr1.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_integer_ptr2     = null;
+    if (v_integer_ptr2     = null) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_integer_ptr3.all = 365;
+    if (v_integer_ptr3.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
+    if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
+    if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
+    if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
+    if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
+      Oktest := OKtest + 1;
+    end if;
+
+    deallocate(v_integer_ptr2);
+    deallocate(v_integer_ptr1);
+
+    assert v_int_ptr1.all = 365;
+    if (v_int_ptr1.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr2 = null;
+    if (v_int_ptr2 = null) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr3.all = 365;
+    if (v_int_ptr3.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr4.all = -365;
+    if (v_int_ptr4.all = -365) then
+      Oktest := OKtest + 1;
+    end if;
+
+    v_int_ptr2 := new int'(100);
+
+    assert v_int_ptr2.all = 100;
+    if (v_int_ptr2.all = 100) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
+    if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
+    if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
+    if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
+    if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
+    if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
+    if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert NOT(OKtest = 18) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00524"
+      severity NOTE;
+    assert (OKtest = 18) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd
new file mode 100644
index 0000000..86ea8c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00525ent IS
+END c03s03b00x00p03n04i00525ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type bit_ptr is access bit;
+    variable v_bit_ptr1: bit_ptr := new bit'('1');
+    variable v_bit_ptr2: bit_ptr;
+    variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
+    variable v_bit_ptr4: bit_ptr := new bit'('0');
+    variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bit_ptr1.all = '1';
+    if (v_bit_ptr1.all = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr2 = null;
+    if (v_bit_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr3.all = '1';
+    if (v_bit_ptr3.all = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr4.all = '0';
+    if (v_bit_ptr4.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr5.all = '0';
+    if (v_bit_ptr5.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_bit_ptr2 := new bit'('0');
+
+    assert v_bit_ptr2.all = '0';
+    if (v_bit_ptr2.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
+    if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
+    if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
+    if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
+    if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
+      OKtest := OKtest + 1;
+    end if;
+
+    deallocate(v_bit_ptr1);
+    deallocate(v_bit_ptr2);
+    deallocate(v_bit_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00525" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00525arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd
new file mode 100644
index 0000000..2f81a82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc526.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00526ent IS
+END c03s03b00x00p03n04i00526ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00526arch OF c03s03b00x00p03n04i00526ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type beta is range 1000 downto 0
+      units
+        b1;
+        b2  =  5 b1;
+        b3  =  7 b2;
+        b4  =  1 b3;
+      end units;
+
+    type phys_ptr is access beta;
+    variable v_phys_ptr1: phys_ptr := new beta'(6 b1);
+    variable v_phys_ptr2: phys_ptr;
+    variable v_phys_ptr3: phys_ptr := v_phys_ptr1;
+    variable v_phys_ptr4: phys_ptr := new beta'(1 b3);
+    variable v_phys_ptr5: phys_ptr := v_phys_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_phys_ptr1.all = 6 b1;
+    if (v_phys_ptr1.all = 6 b1) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr2 = null;
+    if (v_phys_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr3.all = 6 b1;
+    if (v_phys_ptr3.all = 6 b1) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr4.all = 1 b3;
+    if (v_phys_ptr4.all = 1 b3) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr5.all = b4;
+    if (v_phys_ptr5.all = b4) then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_phys_ptr2 := new beta'(7 b2);
+
+    assert v_phys_ptr2.all = b3;
+    if (v_phys_ptr2.all = b3) then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4);
+    if (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all = 1 b2 + 6 b2);
+    if (v_phys_ptr5.all = 1 b2 + 6 b2) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4);
+    if (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all > v_phys_ptr1.all) = true;
+    if ((v_phys_ptr5.all > v_phys_ptr1.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_phys_ptr1);
+    deallocate(v_phys_ptr2);
+    deallocate(v_phys_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00526" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00526 - Physical type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00526arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd
new file mode 100644
index 0000000..9dd0f8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00527ent IS
+END c03s03b00x00p03n04i00527ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    -- first index constraint method
+    type bv_ptr is access bit_vector(0 to 7);
+    variable v_bv_ptr1: bv_ptr    := new bit_vector'("00000001");
+    variable v_bv_ptr2: bv_ptr;
+    variable v_bv_ptr3: bv_ptr    := v_bv_ptr1;
+    
+    
+    -- second index constraint method
+    subtype tbus is bit_vector(1 to 8);
+    type bus_ptr is access tbus;
+    variable v_bv_ptr4: bus_ptr    := new tbus'("10000000");
+    
+    
+    -- third index constraint method
+    type bus_ptr2 is access bit_vector;
+    variable v_bv_ptr5: bus_ptr2    := new bit_vector'("1111");
+    variable v_bv_ptr6: bus_ptr2    := new bit_vector(1 to 4);
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bv_ptr1.all = "00000001";
+    if (v_bv_ptr1.all = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr2 = null;
+    if (v_bv_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr3.all = "00000001";
+    if (v_bv_ptr3.all = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr4.all = "10000000";
+    if (v_bv_ptr4.all = "10000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr5.all = "1111";
+    if (v_bv_ptr5.all = "1111") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr6.all = "0000";
+    if (v_bv_ptr6.all = "0000") then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_bv_ptr2 := new bit_vector'("00110011");
+    
+    assert v_bv_ptr2.all = "00110011";
+    if (v_bv_ptr6.all = "0000") then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
+    if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
+    if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
+    if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
+    if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
+    if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_bv_ptr1);
+    deallocate(v_bv_ptr2);
+    deallocate(v_bv_ptr4);
+    deallocate(v_bv_ptr5);
+    deallocate(v_bv_ptr6);
+
+    assert NOT(OKtest = 12) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00527" 
+      severity NOTE;
+    assert (OKtest = 12) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00527arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd
new file mode 100644
index 0000000..1bb64fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00528ent IS
+END c03s03b00x00p03n04i00528ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type char_ptr is access character;
+
+    variable v_char_ptr1: char_ptr := new character'('a');
+    variable v_char_ptr2: char_ptr;
+    variable v_char_ptr3: char_ptr := v_char_ptr1;
+    variable v_char_ptr4: char_ptr := new character'('|');
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_char_ptr1.all = 'a';
+    if (v_char_ptr1.all = 'a') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr2 = null;
+    if (v_char_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr3.all = 'a';
+    if (v_char_ptr3.all = 'a') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr4.all = '|';
+    if (v_char_ptr4.all = '|') then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_char_ptr2 := new character'('K');
+
+    assert v_char_ptr2.all = 'K';
+    if (v_char_ptr2.all = 'K') then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
+    if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
+    if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
+    if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
+    if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_char_ptr1);
+    deallocate(v_char_ptr2);
+    deallocate(v_char_ptr4);
+
+    assert NOT(OKtest = 9) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00528" 
+      severity NOTE;
+    assert (OKtest = 9) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00528arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd
new file mode 100644
index 0000000..e642312
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc529.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00529ent IS
+END c03s03b00x00p03n04i00529ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00529arch OF c03s03b00x00p03n04i00529ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type string_ptr is access string(1 to 8);
+
+    variable v_string_ptr1: string_ptr := new string'("abcd0123");
+    variable v_string_ptr2: string_ptr;
+    variable v_string_ptr3: string_ptr := v_string_ptr1;
+    variable v_string_ptr4: string_ptr := new string'("=>*/&^!)");
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_string_ptr1(1 to 8) = "abcd0123";
+    if (v_string_ptr1(1 to 8) = "abcd0123") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr2 = null;
+    if (v_string_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(1 to 8) = "abcd0123";
+    if (v_string_ptr3(1 to 8) = "abcd0123") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(2 to 7) = "bcd012";
+    if (v_string_ptr3(2 to 7) = "bcd012") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(6) = '1';
+    if (v_string_ptr3(6) = '1') then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_string_ptr2 := new string'("ABCD----");
+    
+    assert v_string_ptr2(6) = '-';
+    if (v_string_ptr3(6) = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    
+    assert (v_string_ptr1(1 to 8) & v_string_ptr4(1 to 8)) = "abcd0123=>*/&^!)";        
+    if ((v_string_ptr1(1 to 8) & v_string_ptr4(1 to 8)) = "abcd0123=>*/&^!)") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1 to 8) & v_string_ptr2(1 to 8)) = "abcd0123ABCD----";        
+    if ((v_string_ptr1(1 to 8) & v_string_ptr2(1 to 8)) = "abcd0123ABCD----") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1 to 8) /= v_string_ptr4(1 to 8)) = true;
+    if ((v_string_ptr1(1 to 8) /= v_string_ptr4(1 to 8)) = true) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1) /= v_string_ptr1(2)) = true;
+    if ((v_string_ptr1(1) /= v_string_ptr1(2)) = true) then
+      OKtest := OKtest + 1;
+    end if;
+    
+    deallocate(v_string_ptr1);
+    deallocate(v_string_ptr2);
+    deallocate(v_string_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00529" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00529 - String type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd
new file mode 100644
index 0000000..4d61dbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc53.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n03i00053pkg is
+  constant C1 : Bit ;
+  constant C2 : Integer ;
+end c04s03b01x01p04n03i00053pkg;
+
+package body c04s03b01x01p04n03i00053pkg is
+  constant C1 : Bit    := '1';
+  constant C2 : Integer    := 20;
+end c04s03b01x01p04n03i00053pkg;  -- Failure_here
+
+
+use work.c04s03b01x01p04n03i00053pkg.all;
+ENTITY c04s03b01x01p04n03i00053ent IS
+END c04s03b01x01p04n03i00053ent;
+
+ARCHITECTURE c04s03b01x01p04n03i00053arch OF c04s03b01x01p04n03i00053ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = '1' and C2 = 20 ) 
+      report "***PASSED TEST:c04s03b01x01p04n03i00053" 
+      severity NOTE;
+    assert ( C1 = '1' and C2 = 20 ) 
+      report "***FAILED TEST: c04s03b01x01p04n03i00053 - Full constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n03i00053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd
new file mode 100644
index 0000000..f6afe5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd
@@ -0,0 +1,307 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc530.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00530ent IS
+END c03s03b00x00p03n04i00530ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00530arch OF c03s03b00x00p03n04i00530ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type small is
+      record
+        bt : bit;
+        bv : bit_vector (11 downto 0);
+        r  : real range 0.0 to real'high;
+        bb : boolean;
+        i  : integer range 1 to 20;
+      end record;
+    type color    is (red, green, blue);
+    type two_d    is array (color, 1 to 3) of bit;
+    type smar    is array (1 to 3) of small;
+    
+    type record_ptr is access small;
+    type smar_ptr    is access smar;
+    type two_d_ptr    is access two_d;
+
+    variable v_record_ptr1: record_ptr := new small'(bt => '1',
+                                                     bv => "010101010101",
+                                                     r  => 0.1234,
+                                                     bb => true,
+                                                     i  => 20);
+    variable v_record_ptr2: record_ptr;
+    variable v_record_ptr3: record_ptr := v_record_ptr1;
+    variable v_record_ptr4: record_ptr := new small'(bt => '0',
+                                                     bv => "010101010101",
+                                                     r  => 0.9999,
+                                                     bb => false,
+                                                     i  => 1);
+    
+    variable v_smar_ptr1: smar_ptr := new smar'(others => (bt => '1',
+                                                           bv => "010101010101",
+                                                           r  => 0.1234,
+                                                           bb => true,
+                                                           i  => 20));
+    variable v_smar_ptr2: smar_ptr;
+    variable v_smar_ptr3: smar_ptr := v_smar_ptr1;
+    variable v_smar_ptr4: smar_ptr := new smar'(1 => (bt => '1',
+                                                      bv => "010101010101",
+                                                      r  => 0.1234,
+                                                      bb => true,
+                                                      i  => 20),
+                                                others => (bt => '0',
+                                                           bv => "010101010101",
+                                                           r  => 0.9999,
+                                                           bb => false,
+                                                           i  => 1));
+    
+    variable v_two_d_ptr1: two_d_ptr := new two_d'(others => (others => '1'));
+    variable v_two_d_ptr2: two_d_ptr;
+    variable v_two_d_ptr3: two_d_ptr := v_two_d_ptr1;
+    variable v_two_d_ptr4: two_d_ptr := new two_d'(red   => "111",
+                                                   green => "000",
+                                                   blue  => "101");
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+
+    assert v_record_ptr1.bt = '1';
+    if (v_record_ptr1.bt = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.bv = "010101010101";
+    if (v_record_ptr1.bv = "010101010101") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.r = 0.1234;
+    if (v_record_ptr1.r = 0.1234) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.bb = true;
+    if (v_record_ptr1.bb = true) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.i = 20;
+    if (v_record_ptr1.i = 20) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr2 = null;
+    if (v_record_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    
+    v_record_ptr2 := new small'(bt => '0',
+                                bv => "010101010101",
+                                r  => 0.1234,
+                                bb => true,
+                                i  => 10);
+    
+    assert v_record_ptr2.bt = '0';
+    if (v_record_ptr2.bt = '0') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.bv = "010101010101";
+    if (v_record_ptr2.bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.r = 0.1234;
+    if (v_record_ptr2.r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.bb = true;
+    if (v_record_ptr2.bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.i = 10;
+    if (v_record_ptr2.i = 10) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2 /= null;
+    if (v_record_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert v_record_ptr1.all = v_record_ptr3.all;
+    if (v_record_ptr1.all = v_record_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr1.all /= v_record_ptr4.all;
+    if (v_record_ptr1.all /= v_record_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_record_ptr1.bt & v_record_ptr4.bt) = "10";
+    if ((v_record_ptr1.bt & v_record_ptr4.bt) = "10") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_record_ptr1.i - v_record_ptr4.i) = 19;
+    if ((v_record_ptr1.i - v_record_ptr4.i) = 19) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_record_ptr1);
+    deallocate(v_record_ptr2);
+    deallocate(v_record_ptr4);
+    
+    assert v_smar_ptr1(1).bt = '1';
+    if (v_smar_ptr1(1).bt = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).bv = "010101010101";
+    if (v_smar_ptr1(1).bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).r = 0.1234;
+    if (v_smar_ptr1(1).r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).bb = true;
+    if (v_smar_ptr1(1).bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).i = 20;
+    if (v_smar_ptr1(1).i = 20) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2 = null;
+    if (v_smar_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_smar_ptr2 := new smar'(others => (bt => '1',
+                                        bv => "010101010101",
+                                        r  => 0.1234,
+                                        bb => true,
+                                        i  => 10));
+    
+    assert v_smar_ptr2(1).bt = '1';
+    if (v_smar_ptr2(1).bt = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).bv = "010101010101";
+    if (v_smar_ptr2(1).bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).r = 0.1234;
+    if (v_smar_ptr2(1).r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).bb = true;
+    if (v_smar_ptr2(1).bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).i = 10;
+    if (v_smar_ptr2(1).i = 10) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2 /= null;
+    if (v_smar_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert v_smar_ptr1.all = v_smar_ptr3.all;
+    if (v_smar_ptr1.all = v_smar_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1) /= v_smar_ptr4(2);
+    if (v_smar_ptr1(1) /= v_smar_ptr4(2)) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1) = v_smar_ptr4(1);
+    if (v_smar_ptr1(1) = v_smar_ptr4(1)) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_smar_ptr1(1).bt & v_smar_ptr4(1).bt) = "11";
+    if ((v_smar_ptr1(1).bt & v_smar_ptr4(1).bt) = "11") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_smar_ptr1(1).i - v_smar_ptr4(1).i) = 0;
+    if ((v_smar_ptr1(1).i - v_smar_ptr4(1).i) = 0) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_smar_ptr1);
+    deallocate(v_smar_ptr2);
+    deallocate(v_smar_ptr4);
+    
+    assert v_two_d_ptr1.all = v_two_d_ptr3.all;
+    if (v_two_d_ptr1.all = v_two_d_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr1.all /= v_two_d_ptr4.all;
+    if (v_two_d_ptr1.all /= v_two_d_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr2 = null;
+    if (v_two_d_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr3(blue, 2) = '1';
+    if (v_two_d_ptr3(blue, 2) = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_two_d_ptr2 := new two_d'(red   => "111",
+                               green => "000",
+                               blue  => "101");
+    
+    assert v_two_d_ptr2.all = v_two_d_ptr4.all;
+    if (v_two_d_ptr2.all = v_two_d_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr2 /= null;
+    if (v_two_d_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_two_d_ptr1(red, 1) & v_two_d_ptr4(blue, 2)) = "10";
+    if ((v_two_d_ptr1(red, 1) & v_two_d_ptr4(blue, 2)) = "10") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_two_d_ptr1(red, 1) /= v_two_d_ptr4(blue,2));
+    if ((v_two_d_ptr1(red, 1) /= v_two_d_ptr4(blue,2))) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_two_d_ptr1);
+    deallocate(v_two_d_ptr2);
+    deallocate(v_two_d_ptr4);
+
+    assert NOT(OKtest = 41) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00530" 
+      severity NOTE;
+    assert (OKtest = 41) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00530 - Composite type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd
new file mode 100644
index 0000000..77d7a61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc531.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00531ent IS
+END c03s03b00x00p03n04i00531ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00531arch OF c03s03b00x00p03n04i00531ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type bool_ptr is access boolean;
+    variable v_bool_ptr1: bool_ptr := new boolean'(true);
+    variable v_bool_ptr2: bool_ptr;
+    variable v_bool_ptr3: bool_ptr := v_bool_ptr1;
+    variable v_bool_ptr4: bool_ptr := new boolean'(false);
+    variable v_bool_ptr5: bool_ptr := v_bool_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bool_ptr1.all = true;
+    if (v_bool_ptr1.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr2 = null;
+    if (v_bool_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr3.all = true;
+    if (v_bool_ptr3.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr4.all = false;
+    if (v_bool_ptr4.all = false) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr5.all = false;
+    if (v_bool_ptr5.all = false) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_bool_ptr2 := new boolean'(true);
+    
+    assert v_bool_ptr2.all = true;
+    if (v_bool_ptr2.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_bool_ptr1.all and v_bool_ptr5.all) = false;
+    if ((v_bool_ptr1.all and v_bool_ptr5.all) = false) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr1.all and v_bool_ptr2.all) = true;
+    if ((v_bool_ptr1.all and v_bool_ptr2.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr3.all or v_bool_ptr5.all) = true;
+    if ((v_bool_ptr3.all or v_bool_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr3.all > v_bool_ptr5.all) = true;
+    if ((v_bool_ptr3.all > v_bool_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (not v_bool_ptr3.all) = false;
+    if ((not v_bool_ptr3.all) = false) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_bool_ptr1);
+    deallocate(v_bool_ptr2);
+    deallocate(v_bool_ptr4);
+
+    assert NOT(OKtest = 11) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00531" 
+      severity NOTE;
+    assert (OKtest = 11) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00531 - Boolean type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd
new file mode 100644
index 0000000..126f325
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc534.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p04n02i00534ent IS
+END c03s03b00x00p04n02i00534ent;
+
+ARCHITECTURE c03s03b00x00p04n02i00534arch OF c03s03b00x00p04n02i00534ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- The access type we will use.
+    type ACT  is access BIT;
+
+    -- Declare a variable of this type.  Initialize it.
+    variable VAR : ACT := NEW BIT'( '0' );
+  BEGIN
+    -- Attempt to assign a value to it.
+    VAR.all := '1';
+    assert NOT( VAR.all = '1' )
+      report "***PASSED TEST: c03s03b00x00p04n02i00534"
+      severity NOTE;
+    assert ( VAR.all = '1' )
+      report "***FAILED TEST: c03s03b00x00p04n02i00534 - Object designated by an access value is always an object of class variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p04n02i00534arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd
new file mode 100644
index 0000000..d310731
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc535.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n01i00535ent IS
+END c03s03b00x00p05n01i00535ent;
+
+ARCHITECTURE c03s03b00x00p05n01i00535arch OF c03s03b00x00p05n01i00535ent IS
+  type b is access BIT_VECTOR(0 to 10);   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : b; 
+  BEGIN
+    assert NOT(k=null)
+      report "***PASSED TEST: c03s03b00x00p05n01i00535"
+      severity NOTE;
+    assert ( k=null )
+      report "***FAILED TEST: c03s03b00x00p05n01i00535 - The only form of constraint that is allowed after the name of an access type in a subtype indication is an index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n01i00535arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd
new file mode 100644
index 0000000..696aa53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc537.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n02i00537ent IS
+END c03s03b00x00p05n02i00537ent;
+
+ARCHITECTURE c03s03b00x00p05n02i00537arch OF c03s03b00x00p05n02i00537ent IS
+  type ARR is access BIT_VECTOR ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : ARR := null ;
+    variable V2 : ARR(0 to 3) := new BIT_VECTOR'("1111") ; -- no_failure_here
+  BEGIN
+    V1 := V2;
+    assert NOT(V1(0 to 3)="1111")
+      report "***PASSED TEST: c03s03b00x00p05n02i00537"
+      severity NOTE;
+    assert (V1(0 to 3)="1111")
+      report "***FAILED TEST: c03s03b00x00p05n02i00537 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n02i00537arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd
new file mode 100644
index 0000000..38da705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc538.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n02i00538ent IS
+END c03s03b00x00p05n02i00538ent;
+
+ARCHITECTURE c03s03b00x00p05n02i00538arch OF c03s03b00x00p05n02i00538ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype byte is bit_vector (7 downto 0);
+    type byte_mem is array (0 to 15) of byte;
+
+    type ar_bv_ptr is access byte_mem;
+    variable v_ar_bv_ptr1: ar_bv_ptr := new byte_mem'(0 => "10000000",
+                                                      1 => "00000001",
+                                                      others => "00000000");
+    variable v_ar_bv_ptr2: ar_bv_ptr;
+    variable v_ar_bv_ptr3: ar_bv_ptr := v_ar_bv_ptr1;
+    variable   OKtest : integer := 0;
+  BEGIN
+    assert v_ar_bv_ptr1(1)    = "00000001";
+    if (v_ar_bv_ptr1(1)  = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr2    = null;
+    if (v_ar_bv_ptr2     = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(0)    = "10000000";
+    if (v_ar_bv_ptr3(0)  = "10000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(15) = "00000000";
+    if (v_ar_bv_ptr3(15) = "00000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(1)(0)    = '1';        -- (7 downto 0)
+    if (v_ar_bv_ptr3(1)(0)       = '1') then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_ar_bv_ptr2 := new byte_mem'(0 => "10000000",
+                                  1 => "00000001",
+                                  others => "00000000");
+
+    assert v_ar_bv_ptr2(0)(7) = '1';        -- (7 downto 0)
+    if (v_ar_bv_ptr2(0)(7) = '1') then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000";
+    if ((v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000";
+    if ((v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true;
+    if ((v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert NOT(OKtest = 9)
+      report "***PASSED TEST: c03s03b00x00p05n02i00538" 
+      severity NOTE;
+    assert (OKtest = 9)
+      report "***FAILED TEST: c03s03b00x00p05n02i00538 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n02i00538arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd
new file mode 100644
index 0000000..b90a4c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc539.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b01x00p01n02i00539ent IS
+END c03s03b01x00p01n02i00539ent;
+
+ARCHITECTURE c03s03b01x00p01n02i00539arch OF c03s03b01x00p01n02i00539ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type a;
+    type a is access a;
+
+    variable k : a;
+  BEGIN
+    assert NOT( k=null )
+      report "***PASSED TEST: c03s03b01x00p01n02i00539"
+      severity NOTE;
+    assert ( k=null)
+      report "***FAILED TEST: c03s03b01x00p01n02i00539 - The type of an element of the designated type can be another access type, or even the same access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b01x00p01n02i00539arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd
new file mode 100644
index 0000000..66639b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc54.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n01i00054pkg is
+  constant DC : STRING;               -- unconstrainted deferred constant
+end c04s03b01x01p04n01i00054pkg;
+
+package body c04s03b01x01p04n01i00054pkg is
+  constant DC : STRING := "Hello";    -- constant completion
+end c04s03b01x01p04n01i00054pkg;
+
+
+use work.c04s03b01x01p04n01i00054pkg.all;
+ENTITY c04s03b01x01p04n01i00054ent IS
+END c04s03b01x01p04n01i00054ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00054arch OF c04s03b01x01p04n01i00054ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( DC'LENGTH = 5 and DC(1) = 'H' and DC(5) = 'o' )
+      report "***PASSED TEST:c04s03b01x01p04n01i00054"
+      severity NOTE;
+    assert ( DC'LENGTH = 5 and DC(1) = 'H' and DC(5) = 'o' )
+      report "***FAILED TEST:c04s03b01x01p04n01i00054 - A deferred constant declaration appear in a package declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n01i00054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd
new file mode 100644
index 0000000..2db7fda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc541.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b02x00p06n01i00541ent IS
+END c03s03b02x00p06n01i00541ent;
+
+ARCHITECTURE c03s03b02x00p06n01i00541arch OF c03s03b02x00p06n01i00541ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    AC1 is access SWITCH_LEVEL;
+
+    -- Declare a variable.
+    variable VAR : AC1;
+  BEGIN
+    -- Perform the test.
+    assert( VAR = NULL );
+    DEALLOCATE( VAR );
+    assert NOT( VAR = NULL )
+      report "***PASSED TEST: c03s03b02x00p06n01i00541"
+      severity NOTE;
+    assert ( VAR = NULL )
+      report "***FAILED TEST: c03s03b02x00p06n01i00541 - DEALLOCATE operation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b02x00p06n01i00541arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd
new file mode 100644
index 0000000..eb780e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc542.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b02x00p06n01i00542ent IS
+END c03s03b02x00p06n01i00542ent;
+
+ARCHITECTURE c03s03b02x00p06n01i00542arch OF c03s03b02x00p06n01i00542ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type int_ptr is access integer;
+    variable var1: int_ptr := new integer;
+  BEGIN
+    var1:= null;
+    Deallocate(var1);
+    assert NOT(var1 = null) 
+      report "***PASSED TEST: c03s03b02x00p06n01i00542"
+      severity NOTE;
+    assert (var1 = null) 
+      report "***FAILED TEST: c03s03b02x00p06n01i00542 - DEALLOCATE operation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b02x00p06n01i00542arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd
new file mode 100644
index 0000000..96519ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00544ent IS
+END c03s04b00x00p03n01i00544ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
+  type L is                           -- constrained array decl
+    array (1 to 1023, 31 downto 0) of Bit;
+
+  type M is                           -- record type decl
+    record
+      A: Integer;
+      B: L;
+    end record;
+
+  type O is                           -- file decl
+    file of M;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00544"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00544arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd
new file mode 100644
index 0000000..871982b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc545.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00545ent IS
+END c03s04b00x00p03n01i00545ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00545arch OF c03s04b00x00p03n01i00545ent IS
+  type TM is                             -- unconstrained array decl
+    array (Integer range <>) of Integer;     -- No_failure_here
+
+  type FT is                             -- file decl
+    file of TM;                              -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00545"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00545arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd
new file mode 100644
index 0000000..4d08111
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc546.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00546ent IS
+END c03s04b00x00p03n01i00546ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00546arch OF c03s04b00x00p03n01i00546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    FT1 is file of SWITCH_LEVEL;
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT2 is file of SWITCH_LEVEL;
+
+    -- array types.  Unconstrained.
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type    FT3 is file of MEMORY;
+
+    -- array types.  Constrained.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT4 is file of WORD;
+
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT5 is file of DATE;
+    
+    -- INTEGER types.
+    type FT6 is file of INTEGER;
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT7 is file of POSITIVE;
+    
+    -- Physical types.
+    type FT8 is file of TIME;
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FT10 is file of DISTANCE;
+    
+    -- floating point types.
+    type FT11 is file of REAL;
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT12 is file of POSITIVE_R;
+
+    -- Predefined enumerated types.
+    type FT13 is file of BIT;
+    type FT14 is file of SEVERITY_LEVEL;
+    type FT15 is file of BOOLEAN;
+    type FT16 is file of CHARACTER;
+    
+    -- Other predefined types.
+    type FT17 is file of NATURAL;
+    type FT18 is file of STRING;
+    type FT19 is file of BIT_VECTOR;
+
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00546"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd
new file mode 100644
index 0000000..6df12c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc554.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:28 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00554ent IS
+END c03s04b01x00p01n01i00554ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00554arch OF c03s04b01x00p01n01i00554ent IS
+  type boolean_file is file of boolean;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_file open read_mode is "iofile.10";
+    variable  v : boolean;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= true) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00554"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00554 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00554arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd
new file mode 100644
index 0000000..ebe086c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc555.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:28 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00555ent IS
+END c03s04b01x00p01n01i00555ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00555arch OF c03s04b01x00p01n01i00555ent IS
+  type boolean_file is file of boolean;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_file open write_mode is "iofile.10";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,true);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00555 - The output file will be verified by test s010202.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00555arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd
new file mode 100644
index 0000000..f18ef73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc556.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:29 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00556ent IS
+END c03s04b01x00p01n01i00556ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00556arch OF c03s04b01x00p01n01i00556ent IS
+  type natural_vector  is array (natural range <>) of natural;
+  type natural_vector_file is file of natural_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00556 - The output file will be verified by test s010234.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00556arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd
new file mode 100644
index 0000000..04f9146
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc557.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:29 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00557ent IS
+END c03s04b01x00p01n01i00557ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00557arch OF c03s04b01x00p01n01i00557ent IS
+  type bit_file is file of bit;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_file open write_mode is "iofile.08";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,'1');
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00557 - The output file will be verified by test s010204.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00557arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd
new file mode 100644
index 0000000..2c85c1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc558.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:30 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00558ent IS
+END c03s04b01x00p01n01i00558ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00558arch OF c03s04b01x00p01n01i00558ent IS
+  type bit_file is file of bit;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_file open read_mode is "iofile.08";
+    variable  v : bit;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= '1') then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00558"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00558 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd
new file mode 100644
index 0000000..a3b2076
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:30 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00559ent IS
+END c03s04b01x00p01n01i00559ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
+  type natural_vector      is array (natural range <>) of natural;
+  type natural_vector_file is file of natural_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_vector_file open read_mode is "iofile.25";
+    variable  v    : natural_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00559"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00559arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd
new file mode 100644
index 0000000..b76d638
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc56.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n01i00056ent IS
+END c04s03b01x01p05n01i00056ent;
+
+ARCHITECTURE c04s03b01x01p05n01i00056arch OF c04s03b01x01p05n01i00056ent IS
+  procedure PRO (constant C1 : in BIT := '1') is  --- No_failure_here
+  begin
+    assert NOT( C1= '1' )
+      report "***PASSED TEST:c04s03b01x01p05n01i00056"
+      severity NOTE;
+    assert ( C1= '1' )
+      report "***FAILED TEST: c04s03b01x01p05n01i00056 - The formal parameters of subprogram are of mode in may be constant."
+      severity ERROR;
+  end;
+BEGIN
+  PRO;
+END c04s03b01x01p05n01i00056arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd
new file mode 100644
index 0000000..d2eaa84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc560.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00560ent IS
+END c03s04b01x00p01n01i00560ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00560arch OF c03s04b01x00p01n01i00560ent IS
+  type character_file is file of character;
+BEGIN
+  TESTING: PROCESS
+    file filein : character_file open write_mode is "iofile.16";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,'s');
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00560 - The output file will be verified by test s010206.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00560arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd
new file mode 100644
index 0000000..41284d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc561.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:28 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00561ent IS
+END c03s04b01x00p01n01i00561ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00561arch OF c03s04b01x00p01n01i00561ent IS
+  type character_file is file of character;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : character_file open read_mode is "iofile.16";
+    variable  v : character;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 's') then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00561"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00561 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00561arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd
new file mode 100644
index 0000000..1ff7ae4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc562.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:28 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00562ent IS
+END c03s04b01x00p01n01i00562ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00562arch OF c03s04b01x00p01n01i00562ent IS
+  type integer_cons_vector  is array (15 downto 0) of integer;
+  type integer_cons_vector_file is file of integer_cons_vector;
+  constant C19 : integer_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00562 - The output file will be verified by test s010242.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00562arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd
new file mode 100644
index 0000000..2f1acc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc563.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00563ent IS
+END c03s04b01x00p01n01i00563ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00563arch OF c03s04b01x00p01n01i00563ent IS
+  type severity_level_file is file of severity_level;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_file open write_mode is "iofile.17";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,note);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00563 - The output file will be verified by test s010208.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00563arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd
new file mode 100644
index 0000000..2c7693c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc564.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00564ent IS
+END c03s04b01x00p01n01i00564ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00564arch OF c03s04b01x00p01n01i00564ent IS
+  type severity_level_file is file of severity_level;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_file open read_mode is "iofile.17";
+    variable  v : severity_level;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= note) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00564"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00564 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00564arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd
new file mode 100644
index 0000000..ace2c51
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc565.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00565ent IS
+END c03s04b01x00p01n01i00565ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00565arch OF c03s04b01x00p01n01i00565ent IS
+  type positive_vector  is array (positive range <>) of positive;
+  type positive_vector_file is file of positive_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00565 - The output file will be verified by test s010236.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd
new file mode 100644
index 0000000..a5eec4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc566.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00566ent IS
+END c03s04b01x00p01n01i00566ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00566arch OF c03s04b01x00p01n01i00566ent IS
+  type integer_file is file of integer;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00566 - The output file will be verified by test s010210.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd
new file mode 100644
index 0000000..e7e300b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc567.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00567ent IS
+END c03s04b01x00p01n01i00567ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00567arch OF c03s04b01x00p01n01i00567ent IS
+  type integer_file is file of integer;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_file open read_mode is "iofile.18";
+    variable  v : integer;
+  BEGIN
+    for i in 1 to 100 loop
+      assert (endfile(filein) = false) 
+        report"end of file reached before expected"
+        severity error;
+      read(filein,v);
+      if (v /= 3) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 50 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00567"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00567 - Implicitly declared procedure READ test failed. It may cause by procedure WRITE failed also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd
new file mode 100644
index 0000000..7ed7af4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc568.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00568ent IS
+END c03s04b01x00p01n01i00568ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00568arch OF c03s04b01x00p01n01i00568ent IS
+  type positive_vector      is array (natural range <>) of positive;
+  type positive_vector_file is file of positive_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_vector_file open read_mode is "iofile.25";
+    variable  v    : positive_vector(0 to 3);
+    variable  len   : positive;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00568"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00568 - File reading operation (positive_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00568arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd
new file mode 100644
index 0000000..fd9c5ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc569.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00569ent IS
+END c03s04b01x00p01n01i00569ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00569arch OF c03s04b01x00p01n01i00569ent IS
+  type real_file is file of real;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_file open write_mode is "iofile.19";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3.0);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00569 - The output file will be verified by test s010212.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd
new file mode 100644
index 0000000..d1af4cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc570.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00570ent IS
+END c03s04b01x00p01n01i00570ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00570arch OF c03s04b01x00p01n01i00570ent IS
+  type real_file is file of real;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_file open read_mode is "iofile.19";
+    variable  v : real;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3.0) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00570"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00570 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd
new file mode 100644
index 0000000..65e1454
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc571.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00571ent IS
+END c03s04b01x00p01n01i00571ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00571arch OF c03s04b01x00p01n01i00571ent IS
+  type integer_cons_vector      is array (15 downto 0) of integer;
+  type integer_cons_vector_file is file of integer_cons_vector;
+  constant C19 : integer_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : integer_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00571"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00571 - File reading operation (integer_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00571arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd
new file mode 100644
index 0000000..0346705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc572.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+--major mess!
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00572ent IS
+END c03s04b01x00p01n01i00572ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00572arch OF c03s04b01x00p01n01i00572ent IS
+  type time_file is file of time;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_file open write_mode is "iofile.20";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3 ns);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: ENTITY c03s04b01x00p01n01i00572"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+  
+
+
+end c03s04b01x00p01n01i00572arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd
new file mode 100644
index 0000000..8546c76
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc573.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00573ent IS
+END c03s04b01x00p01n01i00573ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00573arch OF c03s04b01x00p01n01i00573ent IS
+  type time_file is file of time;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_file open read_mode is "iofile.20";
+    variable  v : time;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ns) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00573"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00573 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd
new file mode 100644
index 0000000..eedfb34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc574.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00574ent IS
+END c03s04b01x00p01n01i00574ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00574arch OF c03s04b01x00p01n01i00574ent IS
+  type boolean_cons_vector  is array (15 downto 0) of boolean;
+  type boolean_cons_vector_file is file of boolean_cons_vector;
+  constant C19 : boolean_cons_vector := (others => true);
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_cons_vector_file open write_mode is "iofile.28";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00574 - The output file will be verified by test s010238.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00574arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd
new file mode 100644
index 0000000..f674ff2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc575.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00575ent IS
+END c03s04b01x00p01n01i00575ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00575arch OF c03s04b01x00p01n01i00575ent IS
+  type natural_file is file of natural;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00575 - The output file will be verified by test s010216.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00575arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd
new file mode 100644
index 0000000..1c9c6a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:35 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00576ent IS
+END c03s04b01x00p01n01i00576ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
+  type natural_file is file of natural;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_file open read_mode is "iofile.18";
+    variable  v : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00576"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00576arch;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd
new file mode 100644
index 0000000..40059c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc577.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:48 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:12 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00577ent IS
+END c03s04b01x00p01n01i00577ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00577arch OF c03s04b01x00p01n01i00577ent IS
+  type boolean_cons_vector      is array (15 downto 0) of boolean;
+  type boolean_cons_vector_file is file of boolean_cons_vector;
+  constant C19 : boolean_cons_vector := (others => true);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_cons_vector_file open read_mode is "iofile.28";
+    variable  v    : boolean_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00577"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00577 - File reading operation (boolean_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00577arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd
new file mode 100644
index 0000000..c78b5cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc578.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:49 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:13 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00578ent IS
+END c03s04b01x00p01n01i00578ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00578arch OF c03s04b01x00p01n01i00578ent IS
+  type positive_file is file of positive;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00578 - The output file will be verified by test s010218.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00578arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd
new file mode 100644
index 0000000..3dd7799
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc579.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:49 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:13 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00579ent IS
+END c03s04b01x00p01n01i00579ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00579arch OF c03s04b01x00p01n01i00579ent IS
+  type positive_file is file of positive;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_file open read_mode is "iofile.18";
+    variable  v : positive;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00579"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00579 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00579arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd
new file mode 100644
index 0000000..08ae432
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc580.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00580ent IS
+END c03s04b01x00p01n01i00580ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00580arch OF c03s04b01x00p01n01i00580ent IS
+  constant C1 : boolean    := true;
+  type boolean_vector       is array (natural range <>) of boolean;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  type boolean_vector_st_file    is file of boolean_vector_st;
+  constant C27 : boolean_vector_st := (others => C1);
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_st_file open write_mode is "iofile.28";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00580 - The output file will be verified by test s010256.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00580arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd
new file mode 100644
index 0000000..8a93ecf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00581ent IS
+END c03s04b01x00p01n01i00581ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
+  type string_file is file of string;
+BEGIN
+  TESTING: PROCESS
+    file filein : string_file open write_mode is "iofile.21";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,"shishir");
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00581arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd
new file mode 100644
index 0000000..2242c7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc582.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:50 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00582ent IS
+END c03s04b01x00p01n01i00582ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00582arch OF c03s04b01x00p01n01i00582ent IS
+  type string_file is file of string;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : string_file open read_mode is "iofile.21";
+    variable  v    : string(1 to 7);
+    variable  len    : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 7) report "wrong length passed during read operation";
+      if (v /= "shishir" or len /= 7) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00582"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00582 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00582arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd
new file mode 100644
index 0000000..a9f3e73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc583.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00583ent IS
+END c03s04b01x00p01n01i00583ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00583arch OF c03s04b01x00p01n01i00583ent IS
+  type severity_level_cons_vector  is array (15 downto 0) of severity_level;
+  type severity_level_cons_vector_file is file of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vector := (others => note);
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_cons_vector_file open write_mode is "iofile.29";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00583 - The output file will be verified by test s010240.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00583arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd
new file mode 100644
index 0000000..278c124
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc584.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:51 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00584ent IS
+END c03s04b01x00p01n01i00584ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00584arch OF c03s04b01x00p01n01i00584ent IS
+  type bit_vector_file is file of bit_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_vector_file open write_mode is "iofile.22";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,B"0011");
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00584 - The output file will be verified by test s010222.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00584arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd
new file mode 100644
index 0000000..5355724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc585.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:51 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00585ent IS
+END c03s04b01x00p01n01i00585ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00585arch OF c03s04b01x00p01n01i00585ent IS
+  type bit_vector_file is file of bit_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : bit_vector_file open read_mode is "iofile.22";
+    variable  v    : bit_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= B"0011") then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00585"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00585 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00585arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd
new file mode 100644
index 0000000..bc85add
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc586.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:52 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00586ent IS
+END c03s04b01x00p01n01i00586ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00586arch OF c03s04b01x00p01n01i00586ent IS
+  type real_cons_vector  is array (15 downto 0) of real;
+  type real_cons_vector_file is file of real_cons_vector;
+  constant C19 : real_cons_vector := (others => 3.0);
+BEGIN
+  TESTING: PROCESS
+    file filein : real_cons_vector_file open write_mode is "iofile.31";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00586 - The output file will be verified by test s010244.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00586arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd
new file mode 100644
index 0000000..658a610
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc587.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00587ent IS
+END c03s04b01x00p01n01i00587ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00587arch OF c03s04b01x00p01n01i00587ent IS
+  type boolean_vector       is array (natural range <>) of boolean;
+  type boolean_vector_file is file of boolean_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_file open write_mode is "iofile.23";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(true,false));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00587 - The output file will be verified by test s010224.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00587arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd
new file mode 100644
index 0000000..6d22054
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc588.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:53 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00588ent IS
+END c03s04b01x00p01n01i00588ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00588arch OF c03s04b01x00p01n01i00588ent IS
+  type boolean_vector      is array (natural range <>) of boolean;
+  type boolean_vector_file is file of boolean_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_file open read_mode is "iofile.23";
+    variable  v    : boolean_vector(0 to 1);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 2) report "wrong length passed during read operation";
+      if (v /= (true,false)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00588"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00588 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00588arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd
new file mode 100644
index 0000000..e52cf75
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc589.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:53 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00589ent IS
+END c03s04b01x00p01n01i00589ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00589arch OF c03s04b01x00p01n01i00589ent IS
+  type real_cons_vector      is array (15 downto 0) of real;
+  type real_cons_vector_file is file of real_cons_vector;
+  constant C19 : real_cons_vector := (others => 3.0);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_cons_vector_file open read_mode is "iofile.31";
+    variable  v    : real_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00589"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00589 - File reading operation (real_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00589arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd
new file mode 100644
index 0000000..408ddc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc590.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00590ent IS
+END c03s04b01x00p01n01i00590ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00590arch OF c03s04b01x00p01n01i00590ent IS
+  type severity_level_vector  is array (natural range <>) of severity_level;
+  type severity_level_vector_file is file of severity_level_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_file open write_mode is "iofile.24";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(note,error));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00590 - The output file will be verified by test s010226.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00590arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd
new file mode 100644
index 0000000..f03720b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc591.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:54 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:16 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00591ent IS
+END c03s04b01x00p01n01i00591ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00591arch OF c03s04b01x00p01n01i00591ent IS
+  type severity_level_vector      is array (natural range <>) of severity_level;
+  type severity_level_vector_file is file of severity_level_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_vector_file open read_mode is "iofile.24";
+    variable  v    : severity_level_vector(0 to 1);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 2) report "wrong length passed during read operation";
+      if (v /= (note,error)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00591"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00591 - File reading operation (severity_level_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00591arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd
new file mode 100644
index 0000000..40f416e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc592.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:55 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:16 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00592ent IS
+END c03s04b01x00p01n01i00592ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00592arch OF c03s04b01x00p01n01i00592ent IS
+  type severity_level_cons_vector      is array (15 downto 0) of severity_level;
+  type severity_level_cons_vector_file is file of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vector := (others => note);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_cons_vector_file open read_mode is "iofile.29";
+    variable  v    : severity_level_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00592"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00592 - File reading operation (severity_level_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00592arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd
new file mode 100644
index 0000000..3e3ce84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc593.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00593ent IS
+END c03s04b01x00p01n01i00593ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00593arch OF c03s04b01x00p01n01i00593ent IS
+  type integer_vector  is array (natural range <>) of integer;
+  type integer_vector_file is file of integer_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00593 - The output file will be verified by test s010228.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00593arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd
new file mode 100644
index 0000000..b00c1f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:17 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00594ent IS
+END c03s04b01x00p01n01i00594ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
+  type integer_vector      is array (natural range <>) of integer;
+  type integer_vector_file is file of integer_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_vector_file open read_mode is "iofile.25";
+    variable  v    : integer_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00594"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00594arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd
new file mode 100644
index 0000000..843cfaa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc595.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:17 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00595ent IS
+END c03s04b01x00p01n01i00595ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00595arch OF c03s04b01x00p01n01i00595ent IS
+  constant C1 : boolean   := true;
+  type boolean_vector             is array (natural range <>) of boolean;
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  type boolean_vector_st_file    is file of boolean_vector_st;
+  constant C27 : boolean_vector_st := (others => C1);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_st_file open read_mode is "iofile.28";
+    variable  v    : boolean_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00595"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00595 - File reading operation (boolean_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00595arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd
new file mode 100644
index 0000000..dd26cad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc596.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00596ent IS
+END c03s04b01x00p01n01i00596ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00596arch OF c03s04b01x00p01n01i00596ent IS
+  type real_vector  is array (natural range <>) of real;
+  type real_vector_file is file of real_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_file open write_mode is "iofile.26";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1.0,2.0,3.0,4.0));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00596 - The output file will be verified by test s010230.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00596arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd
new file mode 100644
index 0000000..5cb59fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc597.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:57 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:18 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00597ent IS
+END c03s04b01x00p01n01i00597ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00597arch OF c03s04b01x00p01n01i00597ent IS
+  type real_vector      is array (natural range <>) of real;
+  type real_vector_file is file of real_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_vector_file open read_mode is "iofile.26";
+    variable  v    : real_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1.0,2.0,3.0,4.0)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00597"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00597 - File reading operation (real_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00597arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd
new file mode 100644
index 0000000..ce9920a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc598.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00598ent IS
+END c03s04b01x00p01n01i00598ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00598arch OF c03s04b01x00p01n01i00598ent IS
+  type time_cons_vector  is array (15 downto 0) of time;
+  type time_cons_vector_file is file of time_cons_vector;
+  constant C19 : time_cons_vector := (others => 3 ns);
+BEGIN
+  TESTING: PROCESS
+    file filein : time_cons_vector_file open write_mode is "iofile.32";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00598 - The output file will be verified by test s010246.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00598arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd
new file mode 100644
index 0000000..a8e923e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00599ent IS
+END c03s04b01x00p01n01i00599ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
+  type time_vector  is array (natural range <>) of time;
+  type time_vector_file is file of time_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_file open write_mode is "iofile.27";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1 ns,2 ns,3 ns,4 ns));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00599arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd
new file mode 100644
index 0000000..2deafd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc600.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:58 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:18 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00600ent IS
+END c03s04b01x00p01n01i00600ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00600arch OF c03s04b01x00p01n01i00600ent IS
+  type time_vector      is array (natural range <>) of time;
+  type time_vector_file is file of time_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_vector_file open read_mode is "iofile.27";
+    variable  v    : time_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1 ns,2 ns,3 ns,4 ns)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00600"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00600 - File reading operation (time_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00600arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd
new file mode 100644
index 0000000..8da71e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:58 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:19 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00601ent IS
+END c03s04b01x00p01n01i00601ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
+  type time_cons_vector      is array (15 downto 0) of time;
+  type time_cons_vector_file is file of time_cons_vector;
+  constant C19 : time_cons_vector := (others => 3 ns);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_cons_vector_file open read_mode is "iofile.32";
+    variable  v    : time_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00601"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00601arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd
new file mode 100644
index 0000000..e549a25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc602.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00602ent IS
+END c03s04b01x00p01n01i00602ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00602arch OF c03s04b01x00p01n01i00602ent IS
+  constant C4 : time    := 3 ns;
+  type    time_vector    is array (natural range <>) of time;
+  subtype time_vector_st    is time_vector(0 to 15);
+  type    time_vector_st_file    is file of time_vector_st;
+  constant C27 : time_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_st_file open write_mode is "iofile.32";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00602 - The output file will be verified by test s010264.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00602arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd
new file mode 100644
index 0000000..5c70ba0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc603.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00603ent IS
+END c03s04b01x00p01n01i00603ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00603arch OF c03s04b01x00p01n01i00603ent IS
+  type natural_cons_vector  is array (15 downto 0) of natural;
+  type natural_cons_vector_file is file of natural_cons_vector;
+  constant C19 : natural_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00603 - The output file will be verified by test s010248.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00603arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd
new file mode 100644
index 0000000..bae2fc3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc604.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:00 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:19 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00604ent IS
+END c03s04b01x00p01n01i00604ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00604arch OF c03s04b01x00p01n01i00604ent IS
+  type natural_cons_vector      is array (15 downto 0) of natural;
+  type natural_cons_vector_file is file of natural_cons_vector;
+  constant C19 : natural_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : natural_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00604"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00604 - File reading operation (natural_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00604arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd
new file mode 100644
index 0000000..aeeabef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc605.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00605ent IS
+END c03s04b01x00p01n01i00605ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00605arch OF c03s04b01x00p01n01i00605ent IS
+  constant C4 : severity_level    := note;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  subtype severity_level_vector_st is severity_level_vector(0 to 15);
+  type severity_level_vector_st_file    is file of severity_level_vector_st;
+  constant C27 : severity_level_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_st_file open write_mode is "iofile.29";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00605 - The output file will be verified by test s010258.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00605arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd
new file mode 100644
index 0000000..4bffe74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc606.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00606ent IS
+END c03s04b01x00p01n01i00606ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00606arch OF c03s04b01x00p01n01i00606ent IS
+  type positive_cons_vector  is array (15 downto 0) of positive;
+  type positive_cons_vector_file is file of positive_cons_vector;
+  constant C19 : positive_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00606 - The output file will be verified by test s010250.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00606arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd
new file mode 100644
index 0000000..50a1d4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc607.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:01 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:20 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00607ent IS
+END c03s04b01x00p01n01i00607ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00607arch OF c03s04b01x00p01n01i00607ent IS
+  type positive_cons_vector      is array (15 downto 0) of positive;
+  type positive_cons_vector_file is file of positive_cons_vector;
+  constant C19 : positive_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : positive_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00607"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00607 - File reading operation (positive_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00607arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd
new file mode 100644
index 0000000..275bae5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc608.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:01 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:20 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00608ent IS
+END c03s04b01x00p01n01i00608ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00608arch OF c03s04b01x00p01n01i00608ent IS
+  constant C4 : severity_level    := note;
+  type severity_level_vector      is array (natural range <>) of severity_level;
+  subtype severity_level_vector_st is severity_level_vector(0 to 15);
+  type severity_level_vector_st_file      is file of severity_level_vector_st;
+  constant C27 : severity_level_vector_st := (others => C4);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_vector_st_file open read_mode is "iofile.29";
+    variable  v    : severity_level_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00608"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00608 - File reading operation (severity_level_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00608arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd
new file mode 100644
index 0000000..bfd7a2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc609.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00609ent IS
+END c03s04b01x00p01n01i00609ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00609arch OF c03s04b01x00p01n01i00609ent IS
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                             end record;
+  type record_std_package_file is file of record_std_package;
+  constant C19 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3); 
+BEGIN
+  TESTING: PROCESS
+    file filein : record_std_package_file open write_mode is "iofile.33";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00609 - The output file will be verified by test s010252.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00609arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd
new file mode 100644
index 0000000..4aa6586
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc610.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:02 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:21 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00610ent IS
+END c03s04b01x00p01n01i00610ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00610arch OF c03s04b01x00p01n01i00610ent IS
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                             end record;
+  type record_std_package_file is file of record_std_package;
+  constant C19 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_std_package_file open read_mode is "iofile.33";
+    variable  v    : record_std_package;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00610"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00610 - File reading operation (record_std_package file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00610arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd
new file mode 100644
index 0000000..bfaa7e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc611.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:03 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:21 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00611ent IS
+END c03s04b01x00p01n01i00611ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00611arch OF c03s04b01x00p01n01i00611ent IS
+  constant C4 : time   := 3 ns;
+  type    time_vector        is array (natural range <>) of time;
+  subtype time_vector_st       is time_vector(0 to 15);
+  type    time_vector_st_file     is file of time_vector_st;
+  constant    C27    : time_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_vector_st_file open read_mode is "iofile.32";
+    variable  v    : time_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00611"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00611 - File reading operation (time_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00611arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd
new file mode 100644
index 0000000..8777ef9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc612.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00612ent IS
+END c03s04b01x00p01n01i00612ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00612arch OF c03s04b01x00p01n01i00612ent IS
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_array_file is file of record_cons_array;
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+BEGIN
+  TESTING: PROCESS
+    file filein : record_cons_array_file open write_mode is "iofile.34";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00612 - The output file will be verified by test s010254.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00612arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd
new file mode 100644
index 0000000..155b42f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:03 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:22 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00613ent IS
+END c03s04b01x00p01n01i00613ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector       := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_array_file is file of record_cons_array;
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_cons_array_file open read_mode is "iofile.34";
+    variable  v    : record_cons_array;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00613"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00613arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd
new file mode 100644
index 0000000..f09bcec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc614.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00614ent IS
+END c03s04b01x00p01n01i00614ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00614arch OF c03s04b01x00p01n01i00614ent IS
+  constant    C4 : integer    := 3;
+  type       integer_vector       is array (natural range <>) of integer;
+  subtype    integer_vector_st    is integer_vector(0 to 15);
+  type       integer_vector_st_file    is file of integer_vector_st;
+  constant    C27 : integer_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00614 - The output file will be verified by test s010260.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00614arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd
new file mode 100644
index 0000000..6bc03b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc615.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:04 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:22 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00615ent IS
+END c03s04b01x00p01n01i00615ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00615arch OF c03s04b01x00p01n01i00615ent IS
+  constant C4 : integer   := 3;
+  type integer_vector     is array (natural range <>) of integer;
+  subtype integer_vector_st is integer_vector(0 to 15);
+  type integer_vector_st_file     is file of integer_vector_st;
+  constant C27 : integer_vector_st := (others => C4);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_vector_st_file open read_mode is "iofile.30";
+    variable  v    : integer_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00615"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00615 - File reading operation (integer_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00615arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd
new file mode 100644
index 0000000..41f378d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc616.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00616ent IS
+END c03s04b01x00p01n01i00616ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00616arch OF c03s04b01x00p01n01i00616ent IS
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_array_st_file is file of record_array_st;
+
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+
+  constant C28 : boolean_vector_st    :=(others => C1);
+  constant C29 : severity_level_vector_st   :=(others => C4);
+  constant C30 : integer_vector_st   :=(others => C5);
+  constant C31 : real_vector_st      :=(others => C6);
+  constant C32 : time_vector_st      :=(others => C7);
+  constant C33 : natural_vector_st   :=(others => C8);
+  constant C34 : positive_vector_st   :=(others => C9);
+
+  constant C35 : record_array_st    := (C28,C29,C30,C31,C32,C33,C34);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : record_array_st_file open write_mode is "iofile.34";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C35);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00616 - The output file will be verified by test s010270.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00616arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd
new file mode 100644
index 0000000..3be4b58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc617.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00617ent IS
+END c03s04b01x00p01n01i00617ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00617arch OF c03s04b01x00p01n01i00617ent IS
+  constant C4 : real    := 3.0;
+  type    real_vector    is array (natural range <>) of real;
+  subtype real_vector_st is real_vector(0 to 15);
+  type    real_vector_st_file    is file of real_vector_st;
+  constant C27 : real_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_st_file open write_mode is "iofile.31";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00617 - The output file will be verified by test s010262.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00617arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd
new file mode 100644
index 0000000..27e282e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:06 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:23 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00618ent IS
+END c03s04b01x00p01n01i00618ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
+  constant    C4    : real   := 3.0;
+  type    real_vector        is array (natural range <>) of real;
+  subtype real_vector_st       is real_vector(0 to 15);
+  type    real_vector_st_file     is file of real_vector_st;
+  constant    C27    : real_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_vector_st_file open read_mode is "iofile.31";
+    variable  v    : real_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00618"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00618arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd
new file mode 100644
index 0000000..37580c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc619.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00619ent IS
+END c03s04b01x00p01n01i00619ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00619arch OF c03s04b01x00p01n01i00619ent IS
+  constant C4 : natural    := 3 ;
+  type    natural_vector       is array (natural range <>) of natural;
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  type    natural_vector_st_file    is file of natural_vector_st;
+  constant C27 : natural_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00619 - The output file will be verified by test s010266.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00619arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd
new file mode 100644
index 0000000..e2bc086
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc620.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:06 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00620ent IS
+END c03s04b01x00p01n01i00620ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00620arch OF c03s04b01x00p01n01i00620ent IS
+  constant C4 : natural   := 3 ;
+  type    natural_vector        is array (natural range <>) of natural;
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  type    natural_vector_st_file  is file of natural_vector_st;
+  constant    C27    : natural_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_vector_st_file open read_mode is "iofile.30";
+    variable  v    : natural_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00620"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00620 - File reading operation (natural_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00620arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd
new file mode 100644
index 0000000..02c858a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc621.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:07 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00621ent IS
+END c03s04b01x00p01n01i00621ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00621arch OF c03s04b01x00p01n01i00621ent IS
+  type boolean_vector     is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector     is array (natural range <>) of integer;
+  type real_vector        is array (natural range <>) of real;
+  type time_vector        is array (natural range <>) of time;
+  type natural_vector     is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st      is  positive_vector(0 to 15);
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_array_st_file is file of record_array_st;
+  
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  
+  constant C28 : boolean_vector_st        :=(others => C1);
+  constant C29 : severity_level_vector_st :=(others => C4);
+  constant C30 : integer_vector_st        :=(others => C5);
+  constant C31 : real_vector_st           :=(others => C6);
+  constant C32 : time_vector_st           :=(others => C7);
+  constant C33 : natural_vector_st        :=(others => C8);
+  constant C34 : positive_vector_st       :=(others => C9);
+  
+  constant C35 : record_array_st  := (C28,C29,C30,C31,C32,C33,C34);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_array_st_file open read_mode is "iofile.34";
+    variable  v    : record_array_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C35) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00621"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00621 - File reading operation (record_array_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00621arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd
new file mode 100644
index 0000000..241256b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc622.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00622ent IS
+END c03s04b01x00p01n01i00622ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00622arch OF c03s04b01x00p01n01i00622ent IS
+  constant C4 : positive    := 3 ;
+  type    positive_vector       is array (natural range <>) of positive;
+  subtype positive_vector_st       is positive_vector(0 to 15);
+  type    positive_vector_st_file    is file of positive_vector_st;
+  constant C27 : positive_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00622 - The output file will be verified by test s010268.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00622arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd
new file mode 100644
index 0000000..048936d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc623.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:08 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00623ent IS
+END c03s04b01x00p01n01i00623ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00623arch OF c03s04b01x00p01n01i00623ent IS
+  constant C4 : positive   := 3 ;
+  type    positive_vector        is array (natural range <>) of positive;
+  subtype positive_vector_st    is positive_vector(0 to 15);
+  type    positive_vector_st_file is file of positive_vector_st;
+  constant    C27    : positive_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_vector_st_file open read_mode is "iofile.30";
+    variable  v    : positive_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00623"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00623 - File reading operation (positive_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00623arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd
new file mode 100644
index 0000000..18e6641
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc624.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+
+ENTITY c03s04b01x00p01n01i00624ent IS
+END c03s04b01x00p01n01i00624ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00624arch OF c03s04b01x00p01n01i00624ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type    four_value_file is file of four_value;
+  constant C38 : four_value := 'X';
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_file open write_mode is "iofile.36";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00624 - The output file will be verified by test s010274.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00624arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd
new file mode 100644
index 0000000..4f17c28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd
@@ -0,0 +1,164 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc625.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00625ent IS
+END c03s04b01x00p01n01i00625ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00625arch OF c03s04b01x00p01n01i00625ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+
+  type record_of_records_file is file of record_of_records;
+
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 3;
+  constant C9 : positive := 3;
+
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+
+  constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+
+  constant C28 : boolean_vector_st :=(others => C1);
+  constant C29 : severity_level_vector_st:= (others => C4);
+  constant C30 : integer_vector_st:=(others => C5);
+  constant C31 : real_vector_st:=(others => C6);
+  constant C32 : time_vector_st:=(others => C7);
+  constant C33 : natural_vector_st:=(others => C8);
+  constant C34 : positive_vector_st:=(others => C9);
+
+  constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
+
+  constant C37 : record_of_records := (C26,C27,C35);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : record_of_records_file open write_mode is "iofile.35";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C37);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00625 - The output file will be verified by test s010272.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00625arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd
new file mode 100644
index 0000000..946e5ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc626.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:09 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:25 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00626ent IS
+END c03s04b01x00p01n01i00626ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00626arch OF c03s04b01x00p01n01i00626ent IS
+  type boolean_vector  is array (natural range <>) of boolean;
+  type severity_level_vector   is array (natural range <>) of severity_level;
+  type integer_vector  is array (natural range <>) of integer;
+  type real_vector     is array (natural range <>) of real;
+  type time_vector     is array (natural range <>) of time;
+  type natural_vector  is array (natural range <>) of natural;
+  type positive_vector         is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st     is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st   is  positive_vector(0 to 15);
+
+  type boolean_cons_vector     is array (15 downto 0) of boolean;
+  type severity_level_cons_vector      is array (15 downto 0) of severity_level;
+  type integer_cons_vector     is array (15 downto 0) of integer;
+  type real_cons_vector        is array (15 downto 0) of real;
+  type time_cons_vector        is array (15 downto 0) of time;
+  type natural_cons_vector     is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+  
+  type record_of_records_file is file of record_of_records;
+  
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 3;
+  constant C9 : positive := 3;
+  
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  
+  constant C28 : boolean_vector_st :=(others => C1);
+  constant C29 : severity_level_vector_st:= (others => C4);
+  constant C30 : integer_vector_st:=(others => C5);
+  constant C31 : real_vector_st:=(others => C6);
+  constant C32 : time_vector_st:=(others => C7);
+  constant C33 : natural_vector_st:=(others => C8);
+  constant C34 : positive_vector_st:=(others => C9);
+  
+  constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
+  
+  constant C37 : record_of_records := (C26,C27,C35);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_of_records_file open read_mode is "iofile.35";
+    variable  v    : record_of_records;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C37) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00626"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00626 - File reading operation (record_of_records file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00626arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd
new file mode 100644
index 0000000..eba7a2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc627.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:09 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:25 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00627ent IS
+END c03s04b01x00p01n01i00627ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00627arch OF c03s04b01x00p01n01i00627ent IS
+
+  type   four_value is ('Z','0','1','X');
+  type    four_value_file is file of four_value;
+  constant C38 : four_value := 'X';
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_file open read_mode is "iofile.36";
+    variable  v    : four_value;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00627"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00627 - File reading operation (four_value file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00627arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd
new file mode 100644
index 0000000..7342217
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc628.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00628ent IS
+END c03s04b01x00p01n01i00628ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00628arch OF c03s04b01x00p01n01i00628ent IS
+
+  type   byte   is array(0 to 7) of bit;
+  type    byte_file    is file of byte;
+  constant C38 : byte := (others => '1');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : byte_file open write_mode is "iofile.40";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00628 - The output file will be verified by test s010282.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00628arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd
new file mode 100644
index 0000000..2df0930
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc629.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:47 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00629ent IS
+END c03s04b01x00p01n01i00629ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00629arch OF c03s04b01x00p01n01i00629ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type   four_value_map    is array (four_value) of boolean;
+  type    four_value_map_file is file of four_value_map;
+  constant C38 : four_value_map := (true,true,true,true);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_map_file open write_mode is "iofile.37";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00629 - The output file will be verified by test s010276.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00629arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd
new file mode 100644
index 0000000..08e68c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd
@@ -0,0 +1,580 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc63.vhd,v 1.2 2001-10-26 16:29:57 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p01n01i00063ent IS
+END c04s03b01x02p01n01i00063ent;
+
+ARCHITECTURE c04s03b01x02p01n01i00063arch OF c04s03b01x02p01n01i00063ent IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+  
+----------------------------------------------------------------------------------------------------------
+--
+--          SIGNAL declarations
+--
+  
+  SIGNAL     STRING_con_0 :     STRING (1 TO 7);
+  SIGNAL     STRING_con_1 :     STRING (1 TO 7) := "sailing";
+  SIGNAL     STRING_con_2 :     STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+  
+  SIGNAL BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
+  SIGNAL BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
+  SIGNAL BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
+  
+  SIGNAL   ut_chary_con_0 :   ut_chary (NUL TO ENQ);
+  SIGNAL   ut_chary_con_1 :   ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
+  
+  SIGNAL    ct_word_con_0 :    ct_word;
+  SIGNAL    ct_word_con_1 :    ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
+                                            '1', '1', '1', '1', '1', '1', '1', '1');
+  
+  SIGNAL  cst_str10_con_0 :  cst_str10;
+  SIGNAL  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+  SIGNAL  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
+  
+  SIGNAL  cst_digit_con_0 :  cst_digit;
+  SIGNAL  cst_digit_con_1 :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+  
+  SIGNAL    rt_date_con_0 :    rt_date;
+  SIGNAL    rt_date_con_1 :    rt_date := (1, Jan, 1989);
+  
+  SIGNAL   rst_date_con_0 :   rst_date;
+  SIGNAL   rst_date_con_1 :   rst_date := (1, Apr, 2000);
+
+----------------------------------------------------------------------------------------------------------
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+    ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_0.day   = 0    REPORT " rt_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.month = Jan  REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.year  = 0    REPORT " rt_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_1.day   = 1    REPORT " rt_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.month = Jan  REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.year  = 1989 REPORT " rt_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_0.day   = 0    REPORT "rst_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.month = Jan  REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.year  = 0    REPORT "rst_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_1.day   = 1    REPORT "rst_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.month = Apr  REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.year  = 2000 REPORT "rst_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+
+-------------------------------------------------------------------------------------------------------------
+
+    assert NOT(   STRING_con_0(1) = NUL       and 
+                  STRING_con_0(2) = NUL       and 
+                  STRING_con_0(3) = NUL       and 
+                  STRING_con_0(4) = NUL       and 
+                  STRING_con_0(5) = NUL       and 
+                  STRING_con_0(6) = NUL       and 
+                  STRING_con_0(7) = NUL       and 
+                  STRING_con_1(1) = 's'       and 
+                  STRING_con_1(2) = 'a'       and 
+                  STRING_con_1(3) = 'i'       and 
+                  STRING_con_1(4) = 'l'       and 
+                  STRING_con_1(5) = 'i'       and 
+                  STRING_con_1(6) = 'n'       and 
+                  STRING_con_1(7) = 'g'       and 
+                  STRING_con_2(1) = 's'       and 
+                  STRING_con_2(2) = 'a'       and 
+                  STRING_con_2(3) = 'i'       and 
+                  STRING_con_2(4) = 'l'       and 
+                  STRING_con_2(5) = 'i'       and 
+                  STRING_con_2(6) = 'n'       and 
+                  STRING_con_2(7) = 'g'       and 
+                  BIT_VECTOR_con_0(0) = '0'    and 
+                  BIT_VECTOR_con_0(1) = '0'    and 
+                  BIT_VECTOR_con_0(2) = '0'    and 
+                  BIT_VECTOR_con_0(3) = '0'    and 
+                  BIT_VECTOR_con_0(4) = '0'    and 
+                  BIT_VECTOR_con_0(5) = '0'    and 
+                  BIT_VECTOR_con_0(6) = '0'    and 
+                  BIT_VECTOR_con_0(7) = '0'    and 
+                  BIT_VECTOR_con_1(0) = '1'    and 
+                  BIT_VECTOR_con_1(1) = '0'    and 
+                  BIT_VECTOR_con_1(2) = '1'    and 
+                  BIT_VECTOR_con_1(3) = '0'    and 
+                  BIT_VECTOR_con_1(4) = '1'    and 
+                  BIT_VECTOR_con_1(5) = '1'    and 
+                  BIT_VECTOR_con_1(6) = '1'    and 
+                  BIT_VECTOR_con_1(7) = '0'    and 
+                  BIT_VECTOR_con_2(0) = '1'    and 
+                  BIT_VECTOR_con_2(1) = '0'    and 
+                  BIT_VECTOR_con_2(2) = '1'    and 
+                  BIT_VECTOR_con_2(3) = '0'    and 
+                  BIT_VECTOR_con_2(4) = '1'    and 
+                  BIT_VECTOR_con_2(5) = '1'    and 
+                  BIT_VECTOR_con_2(6) = '1'    and 
+                  BIT_VECTOR_con_2(7) = '0'    and 
+                  ut_chary_con_0(NUL) = INTEGER'LEFT and 
+                  ut_chary_con_0(SOH) = INTEGER'LEFT and 
+                  ut_chary_con_0(STX) = INTEGER'LEFT and 
+                  ut_chary_con_0(ETX) = INTEGER'LEFT and 
+                  ut_chary_con_0(EOT) = INTEGER'LEFT and 
+                  ut_chary_con_0(ENQ) = INTEGER'LEFT and 
+                  ut_chary_con_1(NUL) = 1    and 
+                  ut_chary_con_1(SOH) = 2    and 
+                  ut_chary_con_1(STX) = 3    and 
+                  ut_chary_con_1(ETX) = 9    and 
+                  ut_chary_con_1(EOT) = 8    and 
+                  ut_chary_con_1(ENQ) = 7    and 
+                  ct_word_con_0(0) = '0'       and 
+                  ct_word_con_0(1) = '0'       and 
+                  ct_word_con_0(2) = '0'       and 
+                  ct_word_con_0(3) = '0'       and 
+                  ct_word_con_0(4) = '0'       and 
+                  ct_word_con_0(5) = '0'       and 
+                  ct_word_con_0(6) = '0'       and 
+                  ct_word_con_0(7) = '0'       and 
+                  ct_word_con_0(8) = '0'       and 
+                  ct_word_con_0(9) = '0'       and 
+                  ct_word_con_0(10) = '0'    and 
+                  ct_word_con_0(11) = '0'    and 
+                  ct_word_con_0(12) = '0'    and 
+                  ct_word_con_0(13) = '0'    and 
+                  ct_word_con_0(14) = '0'    and 
+                  ct_word_con_0(15) = '0'    and 
+                  ct_word_con_1(0) = '1'       and 
+                  ct_word_con_1(1) = '1'       and 
+                  ct_word_con_1(2) = '1'       and 
+                  ct_word_con_1(3) = '1'       and 
+                  ct_word_con_1(4) = '1'       and 
+                  ct_word_con_1(5) = '1'       and 
+                  ct_word_con_1(6) = '1'       and 
+                  ct_word_con_1(7) = '1'       and 
+                  ct_word_con_1(8) = '1'       and 
+                  ct_word_con_1(9) = '1'       and 
+                  ct_word_con_1(10) = '1'    and 
+                  ct_word_con_1(11) = '1'    and 
+                  ct_word_con_1(12) = '1'    and 
+                  ct_word_con_1(13) = '1'    and 
+                  ct_word_con_1(14) = '1'    and 
+                  ct_word_con_1(15) = '1'    and 
+                  cst_str10_con_0(1) = NUL    and 
+                  cst_str10_con_0(2) = NUL    and 
+                  cst_str10_con_0(3) = NUL    and 
+                  cst_str10_con_0(4) = NUL    and 
+                  cst_str10_con_0(5) = NUL    and 
+                  cst_str10_con_0(6) = NUL    and 
+                  cst_str10_con_0(7) = NUL    and 
+                  cst_str10_con_0(8) = NUL    and 
+                  cst_str10_con_0(9) = NUL    and 
+                  cst_str10_con_0(10) = NUL    and 
+                  cst_str10_con_1(1) = 'a'    and
+                  cst_str10_con_1(2) = 'b'    and
+                  cst_str10_con_1(3) = 'c'    and
+                  cst_str10_con_1(4) = 'd'    and
+                  cst_str10_con_1(5) = 'e'    and
+                  cst_str10_con_1(6) = 'f'    and
+                  cst_str10_con_1(7) = 'g'    and
+                  cst_str10_con_1(8) = 'h'    and
+                  cst_str10_con_1(9) = 'i'    and
+                  cst_str10_con_1(10)= 'j'    and
+                  cst_str10_con_2(1) = 'a'    and
+                  cst_str10_con_2(2) = 'b'    and
+                  cst_str10_con_2(3) = 'c'    and
+                  cst_str10_con_2(4) = 'd'    and
+                  cst_str10_con_2(5) = 'e'    and
+                  cst_str10_con_2(6) = 'f'    and
+                  cst_str10_con_2(7) = 'g'    and
+                  cst_str10_con_2(8) = 'h'    and
+                  cst_str10_con_2(9) = 'i'    and
+                  cst_str10_con_2(10)= 'j'    and
+                  cst_digit_con_0('0') = INTEGER'LEFT    and
+                  cst_digit_con_0('1') = INTEGER'LEFT    and
+                  cst_digit_con_0('2') = INTEGER'LEFT    and
+                  cst_digit_con_0('3') = INTEGER'LEFT    and
+                  cst_digit_con_0('4') = INTEGER'LEFT    and
+                  cst_digit_con_0('5') = INTEGER'LEFT    and
+                  cst_digit_con_0('6') = INTEGER'LEFT    and
+                  cst_digit_con_0('7') = INTEGER'LEFT    and
+                  cst_digit_con_0('8') = INTEGER'LEFT    and
+                  cst_digit_con_0('9') = INTEGER'LEFT    and
+                  cst_digit_con_1('0') = 0    and
+                  cst_digit_con_1('1') = 1    and
+                  cst_digit_con_1('2') = 2    and
+                  cst_digit_con_1('3') = 3    and
+                  cst_digit_con_1('4') = 4    and
+                  cst_digit_con_1('5') = 5    and
+                  cst_digit_con_1('6') = 6    and
+                  cst_digit_con_1('7') = 7    and
+                  cst_digit_con_1('8') = 8    and
+                  cst_digit_con_1('9') = 9    and
+                  rt_date_con_0.day   = 0       and
+                  rt_date_con_0.month = Jan     and
+                  rt_date_con_0.year  = 0       and
+                  rt_date_con_1.day   = 1       and
+                  rt_date_con_1.month = Jan     and
+                  rt_date_con_1.year  = 1989    and
+                  rst_date_con_0.day   = 0       and
+                  rst_date_con_0.month = Jan     and
+                  rst_date_con_0.year  = 0       and
+                  rst_date_con_1.day   = 1       and
+                  rst_date_con_1.month = Apr     and
+                  rst_date_con_1.year  = 2000    )
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss02/p001/s010101.vhd"
+      severity NOTE;
+    assert (   STRING_con_0(1) = NUL       and 
+               STRING_con_0(2) = NUL       and 
+               STRING_con_0(3) = NUL       and 
+               STRING_con_0(4) = NUL       and 
+               STRING_con_0(5) = NUL       and 
+               STRING_con_0(6) = NUL       and 
+               STRING_con_0(7) = NUL       and 
+               STRING_con_1(1) = 's'       and 
+               STRING_con_1(2) = 'a'       and 
+               STRING_con_1(3) = 'i'       and 
+               STRING_con_1(4) = 'l'       and 
+               STRING_con_1(5) = 'i'       and 
+               STRING_con_1(6) = 'n'       and 
+               STRING_con_1(7) = 'g'       and 
+               STRING_con_2(1) = 's'       and 
+               STRING_con_2(2) = 'a'       and 
+               STRING_con_2(3) = 'i'       and 
+               STRING_con_2(4) = 'l'       and 
+               STRING_con_2(5) = 'i'       and 
+               STRING_con_2(6) = 'n'       and 
+               STRING_con_2(7) = 'g'       and 
+               BIT_VECTOR_con_0(0) = '0'    and 
+               BIT_VECTOR_con_0(1) = '0'    and 
+               BIT_VECTOR_con_0(2) = '0'    and 
+               BIT_VECTOR_con_0(3) = '0'    and 
+               BIT_VECTOR_con_0(4) = '0'    and 
+               BIT_VECTOR_con_0(5) = '0'    and 
+               BIT_VECTOR_con_0(6) = '0'    and 
+               BIT_VECTOR_con_0(7) = '0'    and 
+               BIT_VECTOR_con_1(0) = '1'    and 
+               BIT_VECTOR_con_1(1) = '0'    and 
+               BIT_VECTOR_con_1(2) = '1'    and 
+               BIT_VECTOR_con_1(3) = '0'    and 
+               BIT_VECTOR_con_1(4) = '1'    and 
+               BIT_VECTOR_con_1(5) = '1'    and 
+               BIT_VECTOR_con_1(6) = '1'    and 
+               BIT_VECTOR_con_1(7) = '0'    and 
+               BIT_VECTOR_con_2(0) = '1'    and 
+               BIT_VECTOR_con_2(1) = '0'    and 
+               BIT_VECTOR_con_2(2) = '1'    and 
+               BIT_VECTOR_con_2(3) = '0'    and 
+               BIT_VECTOR_con_2(4) = '1'    and 
+               BIT_VECTOR_con_2(5) = '1'    and 
+               BIT_VECTOR_con_2(6) = '1'    and 
+               BIT_VECTOR_con_2(7) = '0'    and 
+               ut_chary_con_0(NUL) = INTEGER'LEFT and 
+               ut_chary_con_0(SOH) = INTEGER'LEFT and 
+               ut_chary_con_0(STX) = INTEGER'LEFT and 
+               ut_chary_con_0(ETX) = INTEGER'LEFT and 
+               ut_chary_con_0(EOT) = INTEGER'LEFT and 
+               ut_chary_con_0(ENQ) = INTEGER'LEFT and 
+               ut_chary_con_1(NUL) = 1    and 
+               ut_chary_con_1(SOH) = 2    and 
+               ut_chary_con_1(STX) = 3    and 
+               ut_chary_con_1(ETX) = 9    and 
+               ut_chary_con_1(EOT) = 8    and 
+               ut_chary_con_1(ENQ) = 7    and 
+               ct_word_con_0(0) = '0'       and 
+               ct_word_con_0(1) = '0'       and 
+               ct_word_con_0(2) = '0'       and 
+               ct_word_con_0(3) = '0'       and 
+               ct_word_con_0(4) = '0'       and 
+               ct_word_con_0(5) = '0'       and 
+               ct_word_con_0(6) = '0'       and 
+               ct_word_con_0(7) = '0'       and 
+               ct_word_con_0(8) = '0'       and 
+               ct_word_con_0(9) = '0'       and 
+               ct_word_con_0(10) = '0'    and 
+               ct_word_con_0(11) = '0'    and 
+               ct_word_con_0(12) = '0'    and 
+               ct_word_con_0(13) = '0'    and 
+               ct_word_con_0(14) = '0'    and 
+               ct_word_con_0(15) = '0'    and 
+               ct_word_con_1(0) = '1'       and 
+               ct_word_con_1(1) = '1'       and 
+               ct_word_con_1(2) = '1'       and 
+               ct_word_con_1(3) = '1'       and 
+               ct_word_con_1(4) = '1'       and 
+               ct_word_con_1(5) = '1'       and 
+               ct_word_con_1(6) = '1'       and 
+               ct_word_con_1(7) = '1'       and 
+               ct_word_con_1(8) = '1'       and 
+               ct_word_con_1(9) = '1'       and 
+               ct_word_con_1(10) = '1'    and 
+               ct_word_con_1(11) = '1'    and 
+               ct_word_con_1(12) = '1'    and 
+               ct_word_con_1(13) = '1'    and 
+               ct_word_con_1(14) = '1'    and 
+               ct_word_con_1(15) = '1'    and 
+               cst_str10_con_0(1) = NUL    and 
+               cst_str10_con_0(2) = NUL    and 
+               cst_str10_con_0(3) = NUL    and 
+               cst_str10_con_0(4) = NUL    and 
+               cst_str10_con_0(5) = NUL    and 
+               cst_str10_con_0(6) = NUL    and 
+               cst_str10_con_0(7) = NUL    and 
+               cst_str10_con_0(8) = NUL    and 
+               cst_str10_con_0(9) = NUL    and 
+               cst_str10_con_0(10) = NUL    and 
+               cst_str10_con_1(1) = 'a'    and
+               cst_str10_con_1(2) = 'b'    and
+               cst_str10_con_1(3) = 'c'    and
+               cst_str10_con_1(4) = 'd'    and
+               cst_str10_con_1(5) = 'e'    and
+               cst_str10_con_1(6) = 'f'    and
+               cst_str10_con_1(7) = 'g'    and
+               cst_str10_con_1(8) = 'h'    and
+               cst_str10_con_1(9) = 'i'    and
+               cst_str10_con_1(10)= 'j'    and
+               cst_str10_con_2(1) = 'a'    and
+               cst_str10_con_2(2) = 'b'    and
+               cst_str10_con_2(3) = 'c'    and
+               cst_str10_con_2(4) = 'd'    and
+               cst_str10_con_2(5) = 'e'    and
+               cst_str10_con_2(6) = 'f'    and
+               cst_str10_con_2(7) = 'g'    and
+               cst_str10_con_2(8) = 'h'    and
+               cst_str10_con_2(9) = 'i'    and
+               cst_str10_con_2(10)= 'j'    and
+               cst_digit_con_0('0') = INTEGER'LEFT    and
+               cst_digit_con_0('1') = INTEGER'LEFT    and
+               cst_digit_con_0('2') = INTEGER'LEFT    and
+               cst_digit_con_0('3') = INTEGER'LEFT    and
+               cst_digit_con_0('4') = INTEGER'LEFT    and
+               cst_digit_con_0('5') = INTEGER'LEFT    and
+               cst_digit_con_0('6') = INTEGER'LEFT    and
+               cst_digit_con_0('7') = INTEGER'LEFT    and
+               cst_digit_con_0('8') = INTEGER'LEFT    and
+               cst_digit_con_0('9') = INTEGER'LEFT    and
+               cst_digit_con_1('0') = 0    and
+               cst_digit_con_1('1') = 1    and
+               cst_digit_con_1('2') = 2    and
+               cst_digit_con_1('3') = 3    and
+               cst_digit_con_1('4') = 4    and
+               cst_digit_con_1('5') = 5    and
+               cst_digit_con_1('6') = 6    and
+               cst_digit_con_1('7') = 7    and
+               cst_digit_con_1('8') = 8    and
+               cst_digit_con_1('9') = 9    and
+               rt_date_con_0.day   = 0       and
+               rt_date_con_0.month = Jan     and
+               rt_date_con_0.year  = 0       and
+               rt_date_con_1.day   = 1       and
+               rt_date_con_1.month = Jan     and
+               rt_date_con_1.year  = 1989    and
+               rst_date_con_0.day   = 0       and
+               rst_date_con_0.month = Jan     and
+               rst_date_con_0.year  = 0       and
+               rst_date_con_1.day   = 1       and
+               rst_date_con_1.month = Apr     and
+               rst_date_con_1.year  = 2000    )
+      report "***FAILED TEST: c04s03b01x02p01n01i00063 - A signal declared a signal of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p01n01i00063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd
new file mode 100644
index 0000000..3e29762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:47 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:11 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:26 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00630ent IS
+END c03s04b01x00p01n01i00630ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
+
+  type   four_value is ('Z','0','1','X');
+  type   four_value_map is array (four_value) of boolean;
+  type    four_value_map_file is file of four_value_map;
+  constant C38 : four_value_map := (true,true,true,true);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_map_file open read_mode is "iofile.37";
+    variable  v    : four_value_map;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00630"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00630arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd
new file mode 100644
index 0000000..2034913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc631.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:11 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:26 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00631ent IS
+END c03s04b01x00p01n01i00631ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00631arch OF c03s04b01x00p01n01i00631ent IS
+
+  type   byte       is array (0 to 7) of bit;
+  type    byte_file    is file of byte;
+  constant C38 : byte := (others => '1');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : byte_file open read_mode is "iofile.40";
+    variable  v    : byte;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00631"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00631 - File reading operation (byte file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00631arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd
new file mode 100644
index 0000000..705fa6f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc632.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p01n01i00632ent IS
+END c03s04b01x00p01n01i00632ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00632arch OF c03s04b01x00p01n01i00632ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  subtype   binary       is four_value range '0' to '1';
+  type    binary_file    is file of binary;
+  constant C38 : binary    := '0';
+
+BEGIN
+  TESTING: PROCESS
+    file filein : binary_file open write_mode is "iofile.38";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00632 - The output file will be verified by test s010278.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00632arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd
new file mode 100644
index 0000000..f0e6f49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc633.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:12 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:27 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00633ent IS
+END c03s04b01x00p01n01i00633ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00633arch OF c03s04b01x00p01n01i00633ent IS
+
+  type   four_value    is ('Z','0','1','X');
+  subtype   binary       is four_value range '0' to '1';
+  type    binary_file    is file of binary;
+  constant C38 : binary := '0';
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : binary_file open read_mode is "iofile.38";
+    variable  v    : binary;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00633"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00633 - File reading operation (binary file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00633arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd
new file mode 100644
index 0000000..25f86f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc634.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00634ent IS
+END c03s04b01x00p01n01i00634ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00634arch OF c03s04b01x00p01n01i00634ent IS
+
+  type      four_value    is ('Z','0','1','X');
+  subtype      binary      is four_value range '0' to '1';
+  subtype      word      is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type      primary_memory   is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable      : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type    primary_memory_module_file    is file of primary_memory_module;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : primary_memory_module_file open write_mode is "iofile.43";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C45);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00634 - The output file will be verified by test s010288.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00634arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd
new file mode 100644
index 0000000..ecc8e7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc635.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:49 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00635ent IS
+END c03s04b01x00p01n01i00635ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00635arch OF c03s04b01x00p01n01i00635ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type   four_value_vector    is array (natural range <>) of four_value;
+  type    four_value_vector_file    is file of four_value_vector;
+  constant C38 : four_value_vector    := ('1','0','1','0');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_vector_file open write_mode is "iofile.39";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00635 - The output file will be verified by test s010280.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00635arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd
new file mode 100644
index 0000000..2c129f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc636.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:49 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:13 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00636ent IS
+END c03s04b01x00p01n01i00636ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00636arch OF c03s04b01x00p01n01i00636ent IS
+
+  type   four_value    is ('Z','0','1','X');
+  type   four_value_vector    is array (natural range <>) of four_value;
+  type    four_value_vector_file    is file of four_value_vector;
+  constant C38 : four_value_vector := ('1','0','1','0');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_vector_file open read_mode is "iofile.39";
+    variable  v    : four_value_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00636"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00636 - File reading operation (four_value_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00636arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd
new file mode 100644
index 0000000..aa0643d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc637.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:50 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00637ent IS
+END c03s04b01x00p01n01i00637ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00637arch OF c03s04b01x00p01n01i00637ent IS
+
+  subtype      word   is bit_vector(0 to 15);
+  type    word_file    is file of word;
+  constant C38 : word := (others => '1');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : word_file open write_mode is "iofile.41";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00637 - The output file will be verified by test s010284.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00637arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd
new file mode 100644
index 0000000..e53ae92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc638.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:50 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:14 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00638ent IS
+END c03s04b01x00p01n01i00638ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00638arch OF c03s04b01x00p01n01i00638ent IS
+
+  subtype   word       is bit_vector(0 to 15);
+  type    word_file    is file of word;
+  constant C38 : word := (others => '1');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : word_file open read_mode is "iofile.41";
+    variable  v    : word;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00638"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00638 - File reading operation (word file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00638arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd
new file mode 100644
index 0000000..55c9c4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:14 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00639ent IS
+END c03s04b01x00p01n01i00639ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
+
+  type            four_value    is ('Z','0','1','X');
+  subtype         binary          is four_value range '0' to '1';
+  subtype      word       is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type       primary_memory  is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable          : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type       primary_memory_module_file     is file of primary_memory_module;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : primary_memory_module_file open read_mode is "iofile.43";
+    variable  v    : primary_memory_module;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C45) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00639"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00639arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd
new file mode 100644
index 0000000..2e30878
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc64.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p02n01i00064ent IS
+END c04s03b01x02p02n01i00064ent;
+
+ARCHITECTURE c04s03b01x02p02n01i00064arch OF c04s03b01x02p02n01i00064ent IS
+  signal C1 : Boolean      := TRUE;          -- No_failure_here
+  signal C2 : bit          := '1';          -- No_failure_here
+  signal C3 : integer      := 12345;          -- No_failure_here
+  signal C4 : positive     := 54321;          -- No_failure_here
+  signal C5 : natural      := 12121;          -- No_failure_here
+  signal C6 : real         := 1.345;          -- No_failure_here
+  signal C7 : character    := 'N';          -- No_failure_here
+  signal C8 : time         := 100 ns;          -- No_failure_here
+  signal C9 : String    (1 to 8)    := "AAAAAAAA";  -- No_failure_here
+  signal C10 : bit_vector(0 to 7)    := "11111111";  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    C1   = TRUE   and
+                   C2   = '1'   and
+                   C3   = 12345   and
+                   C4   = 54321   and
+                   C5   = 12121   and
+                   C6   = 1.345   and
+                   C7   = 'N'   and
+                   C8   = 100 ns   and
+                   C9   = "AAAAAAAA"   and
+                   C10   = "11111111"   ) 
+      report "***PASSED TEST:c04s03b01x02p02n01i00064"
+      severity NOTE;
+    assert (    C1   = TRUE   and
+                C2   = '1'   and
+                C3   = 12345   and
+                C4   = 54321   and
+                C5   = 12121   and
+                C6   = 1.345   and
+                C7   = 'N'   and
+                C8   = 100 ns   and
+                C9   = "AAAAAAAA"   and
+                C10   = "11111111"   ) 
+      report "***FAILED TEST: c04s03b01x02p02n01i00064 - Syntactic test for signal assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p02n01i00064arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd
new file mode 100644
index 0000000..a0a8a35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc640.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00640ent IS
+END c03s04b01x00p01n01i00640ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00640arch OF c03s04b01x00p01n01i00640ent IS
+
+  subtype      word   is bit_vector(0 to 15);
+  constant   size   : integer := 7;
+  type   primary_memory   is array(0 to size) of word;
+  type    primary_memory_file    is file of primary_memory;
+  constant C38 : word := (others => '1');
+  constant C44 : primary_memory := (others => C38);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : primary_memory_file open write_mode is "iofile.42";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C44);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00640 - The output file will be verified by test s010286.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00640arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd
new file mode 100644
index 0000000..bef8906
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc641.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:15 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:29 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00641ent IS
+END c03s04b01x00p01n01i00641ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00641arch OF c03s04b01x00p01n01i00641ent IS
+
+  subtype   word       is bit_vector(0 to 15);
+  constant   size   : integer := 7;
+  type    primary_memory  is array(0 to size) of word;
+  type    primary_memory_file     is file of primary_memory;
+  constant C38 : word := (others => '1');
+  constant C44 : primary_memory := (others => C38);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : primary_memory_file open read_mode is "iofile.42";
+    variable  v    : primary_memory;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C44) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00641"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00641 - File reading operation (primary_memory file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00641arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd
new file mode 100644
index 0000000..76291b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc642.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00642ent IS
+END c03s04b01x00p01n01i00642ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00642arch OF c03s04b01x00p01n01i00642ent IS
+
+  type      four_value    is ('Z','0','1','X');
+  subtype      binary      is four_value range '0' to '1';
+  subtype      word      is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type      primary_memory   is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable      : binary;
+      memory_number   : primary_memory;
+    end record;
+  
+  type   whole_memory   is array (0 to size) of primary_memory_module;
+
+  type    whole_memory_file    is file of whole_memory;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+  constant C46 : whole_memory      := (others => C45);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : whole_memory_file open write_mode is "iofile.44";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C46);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00642 - The output file will be verified by test s010290.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd
new file mode 100644
index 0000000..9e1e40e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00643ent IS
+END c03s04b01x00p01n01i00643ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       boolean_vector    is array (natural range <>) of boolean;
+  subtype    boolean_vector_range is boolean_vector(hi_to_low_range);
+
+  constant   C1 : boolean         := true;
+  constant   C2 : boolean_vector_range    := (others => C1);
+
+  type       boolean_vector_range_file is file of boolean_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_range_file open write_mode is "iofile.46";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C2);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd
new file mode 100644
index 0000000..7665345
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc644.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:16 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:30 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00644ent IS
+END c03s04b01x00p01n01i00644ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00644arch OF c03s04b01x00p01n01i00644ent IS
+
+  type            four_value    is ('Z','0','1','X');
+  subtype         binary          is four_value range '0' to '1';
+  subtype      word       is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type       primary_memory  is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable          : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type    whole_memory    is array (0 to size) of primary_memory_module;
+
+  type      whole_memory_file     is file of whole_memory;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+  constant C46 : whole_memory             := (others => C45);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : whole_memory_file open read_mode is "iofile.44";
+    variable  v    : whole_memory;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C46) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00644"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00644 - File reading operation (whole_memory_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00644arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd
new file mode 100644
index 0000000..b65dba2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc645.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:17 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:30 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00645ent IS
+END c03s04b01x00p01n01i00645ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00645arch OF c03s04b01x00p01n01i00645ent IS
+  
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            boolean_vector  is array (natural range <>) of boolean;
+  subtype         boolean_vector_range is boolean_vector(hi_to_low_range);
+  
+  constant        C1 : boolean                    := true;
+  constant        C2 : boolean_vector_range       := (others => C1);
+  
+  type            boolean_vector_range_file is file of boolean_vector_range;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_range_file open read_mode is "iofile.46";
+    variable  v    : boolean_vector_range;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C2) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00645"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00645 - File reading operation (boolean_vector_range_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00645arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd
new file mode 100644
index 0000000..3e9c7c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00646ent IS
+END c03s04b01x00p01n01i00646ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00646arch OF c03s04b01x00p01n01i00646ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  type current_file is file of current;
+
+  constant C47 : current := 1 A;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : current_file open write_mode is "iofile.62";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00646 - The output file will be verified by test s010292.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00646arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd
new file mode 100644
index 0000000..6e47b87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00647ent IS
+END c03s04b01x00p01n01i00647ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00647arch OF c03s04b01x00p01n01i00647ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  type current_file is file of current;
+  constant C47 : current := 1 A;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : current_file open read_mode is "iofile.62";
+    variable  v    : current;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00647"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00647 - File reading operation (current_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00647arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd
new file mode 100644
index 0000000..fee7575
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc648.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:53 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00648ent IS
+END c03s04b01x00p01n01i00648ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00648arch OF c03s04b01x00p01n01i00648ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       severity_level_vector       is array (natural range <>) of severity_level;
+  subtype    severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  constant   C1 : severity_level_vector_range := (others => note);
+
+  type       severity_level_vector_range_file is file of severity_level_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_range_file open write_mode is "iofile.01";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00648 - The output file will be verified by test s010102.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00648arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd
new file mode 100644
index 0000000..85657a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00649ent IS
+END c03s04b01x00p01n01i00649ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  type resistance_file is file of resistance;
+
+  constant C47 : resistance := 1 Ohm;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : resistance_file open write_mode is "iofile.63";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00649arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd
new file mode 100644
index 0000000..1d1ea35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00650ent IS
+END c03s04b01x00p01n01i00650ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00650arch OF c03s04b01x00p01n01i00650ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  type resistance_file is file of resistance;
+  constant C47 : resistance := 1 Ohm;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : resistance_file open read_mode is "iofile.63";
+    variable  v    : resistance;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00650"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00650 - File reading operation (resistance_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00650arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd
new file mode 100644
index 0000000..e62058f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc651.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:19 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:32 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00651ent IS
+END c03s04b01x00p01n01i00651ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00651arch OF c03s04b01x00p01n01i00651ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            severity_level_vector is array (natural range <>) of severity_level;       
+  subtype         severity_level_vector_range is severity_level_vector(hi_to_low_range);     
+  constant        C1 : severity_level_vector_range := (others => note);
+  
+  type            severity_level_vector_range_file is file of severity_level_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_range_file open read_mode is "iofile.01";
+    variable   v : severity_level_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00651"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00651 - File reading of severity_level_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00651arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd
new file mode 100644
index 0000000..c8d538e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc652.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00652ent IS
+END c03s04b01x00p01n01i00652ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00652arch OF c03s04b01x00p01n01i00652ent IS
+
+  subtype   delay   is integer range 1 to 10;
+
+  type    delay_file is file of delay;
+
+  constant C47 : delay := 2;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : delay_file open write_mode is "iofile.45";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00652 - The output file will be verified by test s010296.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00652arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd
new file mode 100644
index 0000000..e3366fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc653.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:20 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:33 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00653ent IS
+END c03s04b01x00p01n01i00653ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00653arch OF c03s04b01x00p01n01i00653ent IS
+
+  subtype   delay   is integer range 1 to 10;
+  
+  type    delay_file is file of delay;
+  constant C47 : delay := 2;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : delay_file open read_mode is "iofile.45";
+    variable  v    : delay;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00653"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00653 - File reading operation (delay_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00653arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd
new file mode 100644
index 0000000..6d1d0fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc654.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00654ent IS
+END c03s04b01x00p01n01i00654ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00654arch OF c03s04b01x00p01n01i00654ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       integer_vector is array (natural range <>) of integer;
+  subtype    integer_vector_range is integer_vector(hi_to_low_range);
+  constant   C1 : integer_vector_range := (others => 3);
+
+  type       integer_vector_range_file is file of integer_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00654 - The output file will be verified by test s010104.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00654arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd
new file mode 100644
index 0000000..ef01182
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc655.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:21 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:33 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00655ent IS
+END c03s04b01x00p01n01i00655ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00655arch OF c03s04b01x00p01n01i00655ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            integer_vector is array (natural range <>) of integer;       
+  subtype         integer_vector_range is integer_vector(hi_to_low_range);     
+  constant        C1 : integer_vector_range := (others => 3);
+  
+  type            integer_vector_range_file is file of integer_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_range_file open read_mode is "iofile.03";
+    variable   v : integer_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00655"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00655 - File reading of integer_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00655arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd
new file mode 100644
index 0000000..9a61767
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc656.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00656ent IS
+END c03s04b01x00p01n01i00656ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00656arch OF c03s04b01x00p01n01i00656ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       real_vector is array (natural range <>) of real;
+  subtype    real_vector_range is real_vector(hi_to_low_range);
+  constant   C1 : real_vector_range := (others => 3.0);
+
+  type       real_vector_range_file is file of real_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_range_file open write_mode is "iofile.05";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00656 - The output file will be verified by test s010106.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00656arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd
new file mode 100644
index 0000000..3999acf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc657.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:22 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:34 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00657ent IS
+END c03s04b01x00p01n01i00657ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00657arch OF c03s04b01x00p01n01i00657ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            real_vector is array (natural range <>) of real;       
+  subtype         real_vector_range is real_vector(hi_to_low_range);     
+  constant        C1 : real_vector_range := (others => 3.0);
+  
+  type            real_vector_range_file is file of real_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_range_file open read_mode is "iofile.05";
+    variable   v : real_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00657"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00657 - File reading of real_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00657arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd
new file mode 100644
index 0000000..50a9894
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc658.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00658ent IS
+END c03s04b01x00p01n01i00658ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00658arch OF c03s04b01x00p01n01i00658ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       time_vector is array (natural range <>) of time;
+  subtype    time_vector_range is time_vector(hi_to_low_range);
+  constant   C1 : time_vector_range := (others => 3 ns);
+
+  type       time_vector_range_file is file of time_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_range_file open write_mode is "iofile.07";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00658 - The output file will be verified by test s010108.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00658arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd
new file mode 100644
index 0000000..d00b1e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc659.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:23 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:34 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00659ent IS
+END c03s04b01x00p01n01i00659ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00659arch OF c03s04b01x00p01n01i00659ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            time_vector is array (natural range <>) of time;       
+  subtype         time_vector_range is time_vector(hi_to_low_range);     
+  constant        C1 : time_vector_range := (others => 3 ns);
+  
+  type            time_vector_range_file is file of time_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_range_file open read_mode is "iofile.07";
+    variable   v : time_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00659"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00659 - File reading of time_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00659arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd
new file mode 100644
index 0000000..c06b86a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc66.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n01i00066ent IS
+END c04s03b01x02p07n01i00066ent;
+
+ARCHITECTURE c04s03b01x02p07n01i00066arch OF c04s03b01x02p07n01i00066ent IS
+  signal C1 : Boolean   := true;  -- No_failure_here
+  signal C2 : bit       := '0';   -- No_failure_here
+  signal C3 : integer   := 123;   -- No_failure_here
+  signal C4 : positive  := 34;    -- No_failure_here
+  signal C5 : natural   := 12;    -- No_failure_here
+  signal C6 : real      := 1.20;  -- No_failure_here
+  signal C7 : character := 'C';   -- No_failure_here
+  signal C8 : time      := 0 ns;  -- No_failure_here
+  signal INDEX : INTEGER range 0 to 99 := 0; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    C1   = true   and
+                   C2   = '0'   and
+                   C3   = 123   and
+                   C4   = 34   and
+                   C5   = 12   and
+                   C6   = 1.20   and
+                   C7   = 'C'   and
+                   C8   = 0 ns   and
+                   INDEX   = 0   )
+      report "***PASSED TEST: c04s03b01x02p07n01i00066"
+      severity NOTE;
+    assert (    C1   = true   and
+                C2   = '0'   and
+                C3   = 123   and
+                C4   = 34   and
+                C5   = 12   and
+                C6   = 1.20   and
+                C7   = 'C'   and
+                C8   = 0 ns   and
+                INDEX   = 0   )
+      report "***FAILED TEST: c04s03b01x02p07n01i00066 - Signal expression must be as the same type as the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n01i00066arch;
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd
new file mode 100644
index 0000000..1378b7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc660.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00660ent IS
+END c03s04b01x00p01n01i00660ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00660arch OF c03s04b01x00p01n01i00660ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       natural_vector is array (natural range <>) of natural;
+  subtype    natural_vector_range is natural_vector(hi_to_low_range);
+  constant   C1 : natural_vector_range := (others => 3);
+
+  type       natural_vector_range_file is file of natural_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00660 - The output file will be verified by test s010110.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00660arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd
new file mode 100644
index 0000000..de13b12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc661.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:24 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:35 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00661ent IS
+END c03s04b01x00p01n01i00661ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00661arch OF c03s04b01x00p01n01i00661ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            natural_vector is array (natural range <>) of natural;       
+  subtype         natural_vector_range is natural_vector(hi_to_low_range);     
+  constant        C1 : natural_vector_range := (others => 3);
+  
+  type            natural_vector_range_file is file of natural_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_range_file open read_mode is "iofile.03";
+    variable   v : natural_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00661"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00661 - File reading of natural_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00661arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd
new file mode 100644
index 0000000..f263220
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc662.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00662ent IS
+END c03s04b01x00p01n01i00662ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00662arch OF c03s04b01x00p01n01i00662ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       positive_vector is array (natural range <>) of positive;
+  subtype    positive_vector_range is positive_vector(hi_to_low_range);
+  constant   C1 : positive_vector_range := (others => 3);
+
+  type       positive_vector_range_file is file of positive_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00662 - The output file will be verified by test s010112.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00662arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd
new file mode 100644
index 0000000..53242ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc663.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:35 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00663ent IS
+END c03s04b01x00p01n01i00663ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00663arch OF c03s04b01x00p01n01i00663ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            positive_vector is array (natural range <>) of positive;       
+  subtype         positive_vector_range is positive_vector(hi_to_low_range);     
+  constant        C1 : positive_vector_range := (others => 3);
+  
+  type            positive_vector_range_file is file of positive_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_range_file open read_mode is "iofile.03";
+    variable   v : positive_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00663"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00663 - File reading of positive_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00663arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd
new file mode 100644
index 0000000..1e66d8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc664.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00664ent IS
+END c03s04b01x00p01n01i00664ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00664arch OF c03s04b01x00p01n01i00664ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type    array_rec_std       is array (integer range <>) of record_std_package;
+  type    array_rec_std_file    is file of array_rec_std;
+
+  constant   C26 : record_std_package    := (true,'1','s',note,3,3.0,3 ns,3,3);
+  constant   C57 : array_rec_std(0 to 7)    := (others => C26);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_std_file open write_mode is "iofile.11";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C57);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00664 - The output file will be verified by test s010114.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00664arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd
new file mode 100644
index 0000000..07d5594
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc665.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00665ent IS
+END c03s04b01x00p01n01i00665ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00665arch OF c03s04b01x00p01n01i00665ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type    array_rec_std           is array (integer range <>) of record_std_package;
+  type    array_rec_std_file      is file of array_rec_std;
+  
+  constant        C26 : record_std_package        := (true,'1','s',note,3,3.0,3 ns,3,3);     
+  constant        C57 : array_rec_std(0 to 7)     := (others => C26);
+
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_std_file open read_mode is "iofile.11";
+    variable   v    : array_rec_std(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C57) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00665"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00665 - File reading of array_rec_std_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00665arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd
new file mode 100644
index 0000000..b4d524c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc666.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00666ent IS
+END c03s04b01x00p01n01i00666ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00666arch OF c03s04b01x00p01n01i00666ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant C27 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+
+  constant C58 : array_rec_cons (0 to 7)    := (others => C27);
+
+  type    array_rec_cons_file    is file of array_rec_cons;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_cons_file open write_mode is "iofile.13";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C58);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00666 - The output file will be verified by test s010116.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00666arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd
new file mode 100644
index 0000000..6f49dff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc667.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00667ent IS
+END c03s04b01x00p01n01i00667ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00667arch OF c03s04b01x00p01n01i00667ent IS
+
+  type boolean_cons_vector        is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector        is array (15 downto 0) of integer;
+  type real_cons_vector           is array (15 downto 0) of real;
+  type time_cons_vector           is array (15 downto 0) of time;
+  type natural_cons_vector        is array (15 downto 0) of natural;
+  type positive_cons_vector       is array (15 downto 0) of positive;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  
+  constant C27 : record_cons_array        := (C19,C20,C21,C22,C23,C24,C25);
+  
+  constant C58 : array_rec_cons (0 to 7)  := (others => C27);
+  
+  type    array_rec_cons_file     is file of array_rec_cons;
+
+  signal     k : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_cons_file open read_mode is "iofile.13";
+    variable   v    : array_rec_cons(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C58) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00667"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00667 - File reading of array_rec_cons_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00667arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd
new file mode 100644
index 0000000..f0b47d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd
@@ -0,0 +1,160 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc668.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00668ent IS
+END c03s04b01x00p01n01i00668ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00668arch OF c03s04b01x00p01n01i00668ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+
+  type    array_rec_rec       is array (integer range <>) of record_of_records;
+  type    array_rec_rec_file    is file of array_rec_rec;
+
+  constant C1 : boolean       := true;
+  constant C2 : bit       := '1';
+  constant C3 : character    := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer       := 3;
+  constant C6 : real       := 3.0;
+  constant C7 : time       := 3 ns;
+  constant C8 : natural       := 3;
+  constant C9 : positive       := 3;
+  constant C10 : string       := "shishir";
+  constant C11 : bit_vector       := B"0011";
+  constant C12 : boolean_vector       := (true,false);
+  constant C13 : severity_level_vector    := (note,error);
+  constant C14 : integer_vector       := (1,2,3,4);
+  constant C15 : real_vector       := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector       := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector       := (1,2,3,4);
+  constant C18 : positive_vector       := (1,2,3,4);
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  constant C26 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C27 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C28 : boolean_vector_st    := (others => C1);
+  constant C29 : severity_level_vector_st   := (others => C4);
+  constant C30 : integer_vector_st   := (others => C5);
+  constant C31 : real_vector_st      := (others => C6);
+  constant C32 : time_vector_st      := (others => C7);
+  constant C33 : natural_vector_st   := (others => C8);
+  constant C34 : positive_vector_st   := (others => C9);
+  constant C35 : record_array_st       := (C28,C29,C30,C31,C32,C33,C34);
+
+  constant C37 : record_of_records    := (C26,C27,C35);
+
+  constant C59: array_rec_rec(0 to 7)    :=(others => C37);
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_rec_file open write_mode is "iofile.15";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C59);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00668 - The output file will be verified by test s010118.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00668arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd
new file mode 100644
index 0000000..8b6fba0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc669.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:37 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00669ent IS
+END c03s04b01x00p01n01i00669ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00669arch OF c03s04b01x00p01n01i00669ent IS
+
+  type boolean_vector     is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector     is array (natural range <>) of integer;
+  type real_vector        is array (natural range <>) of real;
+  type time_vector        is array (natural range <>) of time;
+  type natural_vector     is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st      is  positive_vector(0 to 15);
+  
+  type boolean_cons_vector        is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector        is array (15 downto 0) of integer;
+  type real_cons_vector           is array (15 downto 0) of real;
+  type time_cons_vector           is array (15 downto 0) of time;
+  type natural_cons_vector        is array (15 downto 0) of natural;
+  type positive_cons_vector       is array (15 downto 0) of positive;
+  
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+  
+  type    array_rec_rec           is array (integer range <>) of record_of_records;
+  type    array_rec_rec_file      is file of array_rec_rec;
+  
+  constant C1 : boolean           := true;
+  constant C2 : bit               := '1';
+  constant C3 : character         := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer           := 3;
+  constant C6 : real              := 3.0;
+  constant C7 : time              := 3 ns;
+  constant C8 : natural           := 3;
+  constant C9 : positive          := 3;
+  constant C10 : string           := "shishir";
+  constant C11 : bit_vector               := B"0011";
+  constant C12 : boolean_vector           := (true,false);
+  constant C13 : severity_level_vector    := (note,error);
+  constant C14 : integer_vector           := (1,2,3,4);
+  constant C15 : real_vector              := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector              := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector           := (1,2,3,4);
+  constant C18 : positive_vector          := (1,2,3,4);
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  constant C26 : record_std_package       := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C27 : record_cons_array        := (C19,C20,C21,C22,C23,C24,C25);
+  constant C28 : boolean_vector_st        := (others => C1);
+  constant C29 : severity_level_vector_st := (others => C4);
+  constant C30 : integer_vector_st        := (others => C5);
+  constant C31 : real_vector_st           := (others => C6);
+  constant C32 : time_vector_st           := (others => C7);
+  constant C33 : natural_vector_st        := (others => C8);
+  constant C34 : positive_vector_st       := (others => C9);
+  constant C35 : record_array_st          := (C28,C29,C30,C31,C32,C33,C34);
+  
+  constant C37 : record_of_records        := (C26,C27,C35);
+  
+  constant C59: array_rec_rec(0 to 7)     :=(others => C37);
+
+  signal     k : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_rec_file open read_mode is "iofile.15";
+    variable   v    : array_rec_rec(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C59) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00669"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00669 - File reading of array_rec_rec_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00669arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd
new file mode 100644
index 0000000..adb3cd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc670.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00670ent IS
+END c03s04b01x00p23n01i00670ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00670arch OF c03s04b01x00p23n01i00670ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type       SWITCH_LEVEL is ('0', '1', 'X');
+    type       FT is file of SWITCH_LEVEL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.48";
+
+    -- Declare a variable.
+    constant CON : SWITCH_LEVEL := '1';
+    variable VAR : SWITCH_LEVEL := CON;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00670 - The output file will tested by test file s010404.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00670arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd
new file mode 100644
index 0000000..59fcee3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc671.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00671ent IS
+END c03s04b01x00p23n01i00671ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00671arch OF c03s04b01x00p23n01i00671ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT is file of DATE;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.51";
+
+    -- Declare a variable.
+    constant CON : DATE := (1,1,1);
+    variable VAR : DATE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00671 - The output file will tested by test file s010410.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00671arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd
new file mode 100644
index 0000000..b65a2e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc672.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00672ent IS
+END c03s04b01x00p23n01i00672ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00672arch OF c03s04b01x00p23n01i00672ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type       SWITCH_LEVEL is ('0', '1', 'X');
+    type       FT is file of SWITCH_LEVEL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.48";
+    
+    -- Declare a variable into which we will read.
+    constant CON : SWITCH_LEVEL := '1';
+    variable VAR : SWITCH_LEVEL ;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00672"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00672 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00672arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd
new file mode 100644
index 0000000..8137829
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc673.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00673ent IS
+END c03s04b01x00p23n01i00673ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00673arch OF c03s04b01x00p23n01i00673ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT is file of DATE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.51";
+    
+    -- Declare a variable into which we will read.
+    constant CON : DATE := ( 1,1,1 );
+    variable VAR : DATE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00673"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00673 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00673arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd
new file mode 100644
index 0000000..8301784
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc674.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00674ent IS
+END c03s04b01x00p23n01i00674ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00674arch OF c03s04b01x00p23n01i00674ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type SWITCH_LEVEL is ( '0', '1', 'Z' );
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT is file of LOGIC_SWITCH;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.49";
+
+    -- Declare a variable.
+    constant CON : LOGIC_SWITCH := '1';
+    variable VAR : LOGIC_SWITCH := CON;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00674 - The output file will tested by test file s010406.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00674arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd
new file mode 100644
index 0000000..0c6dbeb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00675ent IS
+END c03s04b01x00p23n01i00675ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type SWITCH_LEVEL is ( '0', '1', 'Z' );
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT is file of LOGIC_SWITCH;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.49";
+    
+    -- Declare a variable into which we will read.
+    constant CON : LOGIC_SWITCH := '1';
+    variable VAR : LOGIC_SWITCH ;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00675"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00675arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd
new file mode 100644
index 0000000..de22af7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc676.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00676ent IS
+END c03s04b01x00p23n01i00676ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00676arch OF c03s04b01x00p23n01i00676ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT is file of POSITIVE_R;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.54";
+
+    -- Declare a variable.
+    constant CON : POSITIVE_R := 1.0;
+    variable VAR : POSITIVE_R := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00676 - The output file will tested by test file s010422.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00676arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd
new file mode 100644
index 0000000..5f12a7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc677.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00677ent IS
+END c03s04b01x00p23n01i00677ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00677arch OF c03s04b01x00p23n01i00677ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT is file of WORD;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.50";
+
+    -- Declare a variable.
+    constant CON : WORD := B"11111111111111111111111111111111";
+    variable VAR : WORD := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00677 - The output file will tested by test file s010408.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd
new file mode 100644
index 0000000..8c47c52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc678.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:39 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00678ent IS
+END c03s04b01x00p23n01i00678ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00678arch OF c03s04b01x00p23n01i00678ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT is file of WORD;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.50";
+    
+    -- Declare a variable into which we will read.
+    constant CON : WORD := B"11111111111111111111111111111111";
+    variable VAR : WORD;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00678"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00678 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00678arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd
new file mode 100644
index 0000000..e93b2e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc679.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00679ent IS
+END c03s04b01x00p23n01i00679ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00679arch OF c03s04b01x00p23n01i00679ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of INTEGER;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : INTEGER := 1;
+    variable VAR : INTEGER := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00679 - The output file will tested by test file s010412.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd
new file mode 100644
index 0000000..cae1740
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc68.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n04i00068ent IS
+END c04s03b01x02p07n04i00068ent;
+
+ARCHITECTURE c04s03b01x02p07n04i00068arch OF c04s03b01x02p07n04i00068ent IS
+  signal S1 : Integer := (10 *2 *4 +9 -3);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( S1 = 86 )
+      report "***PASSED TEST: c04s03b01x02p07n04i00068"
+      severity NOTE;
+    assert ( S1 = 86 )
+      report "***FAILED TEST: c04s03b01x02p07n04i00068 - The value of the default expression is the default value of the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n04i00068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd
new file mode 100644
index 0000000..92708f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc680.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00680ent IS
+END c03s04b01x00p23n01i00680ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00680arch OF c03s04b01x00p23n01i00680ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of INTEGER;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : INTEGER := 1;
+    variable VAR : INTEGER;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00680"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00680 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00680arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd
new file mode 100644
index 0000000..2527301
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00681ent IS
+END c03s04b01x00p23n01i00681ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
+
+  type FT is file of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    file S1: FT open write_mode is "iofile.47";   
+  BEGIN
+    WRITE(S1,3);
+    WRITE(S1,2);
+    WRITE(S1,1);
+    wait for 10 ns;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00681arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd
new file mode 100644
index 0000000..3664b1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00682ent IS
+END c03s04b01x00p23n01i00682ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
+  type FT is file of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    variable i3, i2, i1: INTEGER;
+    file S1: FT open read_mode is "iofile.47";
+  BEGIN
+    wait for 10 ns;
+    READ(S1,i3);
+    READ(S1,i2);
+    READ(S1,i1);
+    wait for 10 ns;
+    assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
+      report "***PASSED TEST: c03s04b01x00p23n01i00682"
+      severity NOTE;
+    assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
+      report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00682arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd
new file mode 100644
index 0000000..38632f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00683ent IS
+END c03s04b01x00p23n01i00683ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT is file of POSITIVE_R;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.54";
+    
+    -- Declare a variable into which we will read.
+    constant CON : POSITIVE_R := 1.0;
+    variable VAR : POSITIVE_R;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00683"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00683arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd
new file mode 100644
index 0000000..b8ce797
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc684.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00684ent IS
+END c03s04b01x00p23n01i00684ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00684arch OF c03s04b01x00p23n01i00684ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT is file of POSITIVE;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : POSITIVE := 1;
+    variable VAR : POSITIVE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00684 - The output file will tested by test file s010414.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00684arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd
new file mode 100644
index 0000000..5cba64d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc685.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:41 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00685ent IS
+END c03s04b01x00p23n01i00685ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00685arch OF c03s04b01x00p23n01i00685ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT is file of POSITIVE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : POSITIVE := 1;
+    variable VAR : POSITIVE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00685"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00685 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00685arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd
new file mode 100644
index 0000000..237ac8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc686.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00686ent IS
+END c03s04b01x00p23n01i00686ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00686arch OF c03s04b01x00p23n01i00686ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BOOLEAN;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.10";
+
+    -- Declare a variable.
+    constant CON : BOOLEAN := TRUE;
+    variable VAR : BOOLEAN := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00686 - The output file will tested by test file s010428.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00686arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd
new file mode 100644
index 0000000..3a02212
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc687.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00687ent IS
+END c03s04b01x00p23n01i00687ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00687arch OF c03s04b01x00p23n01i00687ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of TIME;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.52";
+
+    -- Declare a variable.
+    constant CON : TIME := 1 ns;
+    variable VAR : TIME := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00687 - The output file will tested by test file s010416.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00687arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd
new file mode 100644
index 0000000..33c1810
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:35 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:42 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00688ent IS
+END c03s04b01x00p23n01i00688ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of TIME;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.52";
+    
+    -- Declare a variable into which we will read.
+    constant CON : TIME := 1 ns;
+    variable VAR : TIME;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00688"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00688arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd
new file mode 100644
index 0000000..0ab97a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc689.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00689ent IS
+END c03s04b01x00p23n01i00689ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00689arch OF c03s04b01x00p23n01i00689ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BIT;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : BIT := '1';
+    variable VAR : BIT := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00689 - The output file will tested by test file s010424.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00689arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd
new file mode 100644
index 0000000..08ccfeb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n05i00069ent IS
+END c04s03b01x02p07n05i00069ent;
+
+ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
+  signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    S1(0)   = '0'   and
+                   S1(1)   = '1'   and
+                   S1(2)   = '0'   and
+                   S1(3)   = '1'   )
+      report "***PASSED TEST: c04s03b01x02p07n05i00069"
+      severity NOTE;
+    assert (    S1(0)   = '0'   and
+                S1(1)   = '1'   and
+                S1(2)   = '0'   and
+                S1(3)   = '1'   )
+      report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n05i00069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd
new file mode 100644
index 0000000..2b93ec7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00690ent IS
+END c03s04b01x00p23n01i00690ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FilT is file of DISTANCE;
+
+    -- Declare the actual file to write.
+    file FILEV : FilT open write_mode is "iofile.53";
+
+    -- Declare a variable.
+    constant CON : DISTANCE := 1 nm;
+    variable VAR : DISTANCE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd
new file mode 100644
index 0000000..678a323
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc691.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:37 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:42 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00691ent IS
+END c03s04b01x00p23n01i00691ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00691arch OF c03s04b01x00p23n01i00691ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FilT is file of DISTANCE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FilT open read_mode is "iofile.53";
+    
+    -- Declare a variable into which we will read.
+    constant CON : DISTANCE := 1 nm;
+    variable VAR : DISTANCE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00691"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00691 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00691arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd
new file mode 100644
index 0000000..4aac090
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc692.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:38 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00692ent IS
+END c03s04b01x00p23n01i00692ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00692arch OF c03s04b01x00p23n01i00692ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BIT;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BIT := '1';
+    variable VAR : BIT;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00692"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00692 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00692arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd
new file mode 100644
index 0000000..783df55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc693.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:38 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00693ent IS
+END c03s04b01x00p23n01i00693ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00693arch OF c03s04b01x00p23n01i00693ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of REAL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.54";
+    
+    -- Declare a variable into which we will read.
+    constant CON : REAL := 1.0;
+    variable VAR : REAL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00693"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00693 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00693arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd
new file mode 100644
index 0000000..063545c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc694.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00694ent IS
+END c03s04b01x00p23n01i00694ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00694arch OF c03s04b01x00p23n01i00694ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of REAL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.54";
+
+    -- Declare a variable.
+    constant CON : REAL := 1.0;
+    variable VAR : REAL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00694 - The output file will tested by test file s010420.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00694arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd
new file mode 100644
index 0000000..0701828
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:39 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00695ent IS
+END c03s04b01x00p23n01i00695ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BOOLEAN;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.10";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BOOLEAN := TRUE;
+    variable VAR : BOOLEAN;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00695"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00695arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd
new file mode 100644
index 0000000..9bb52ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc696.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:39 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:44 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00696ent IS
+END c03s04b01x00p23n01i00696ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00696arch OF c03s04b01x00p23n01i00696ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of SEVERITY_LEVEL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.55";
+    
+    -- Declare a variable into which we will read.
+    constant CON : SEVERITY_LEVEL := WARNING;
+    variable VAR : SEVERITY_LEVEL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00696"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00696 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00696arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd
new file mode 100644
index 0000000..5a0760e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc697.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00697ent IS
+END c03s04b01x00p23n01i00697ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00697arch OF c03s04b01x00p23n01i00697ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of SEVERITY_LEVEL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.55";
+
+    -- Declare a variable.
+    constant CON : SEVERITY_LEVEL := WARNING;
+    variable VAR : SEVERITY_LEVEL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00697 - The output file will tested by test file s010426.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00697arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd
new file mode 100644
index 0000000..f796267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc698.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00698ent IS
+END c03s04b01x00p23n01i00698ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00698arch OF c03s04b01x00p23n01i00698ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of CHARACTER;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : CHARACTER := '1';
+    variable VAR : CHARACTER := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00698 - The output file will tested by test file s010430.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd
new file mode 100644
index 0000000..8afad7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc699.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:40 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:44 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00699ent IS
+END c03s04b01x00p23n01i00699ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00699arch OF c03s04b01x00p23n01i00699ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of CHARACTER;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : CHARACTER := '1';
+    variable VAR : CHARACTER;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00699"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00699 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00699arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd
new file mode 100644
index 0000000..5723753
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc70.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p08n02i00070ent IS
+END c04s03b01x02p08n02i00070ent;
+
+ARCHITECTURE c04s03b01x02p08n02i00070arch OF c04s03b01x02p08n02i00070ent IS
+  type    A is array (1 to 10) of integer;
+  subtype    B is integer range a'range;
+  signal    c :  b;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( c=1 )
+      report "***PASSED TEST:c04s03b01x02p08n02i00070"
+      severity NOTE;
+    assert ( c=1 )
+      report "***FAILED TEST:c04s03b01x02p08n02i00070 - Implicit default value test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p08n02i00070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd
new file mode 100644
index 0000000..9c26e42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc700.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00700ent IS
+END c03s04b01x00p23n01i00700ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00700arch OF c03s04b01x00p23n01i00700ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of NATURAL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : NATURAL := 1;
+    variable VAR : NATURAL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00700 - The output file will tested by test file s010432.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00700arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd
new file mode 100644
index 0000000..7622968
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:41 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:45 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00701ent IS
+END c03s04b01x00p23n01i00701ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of NATURAL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : NATURAL := 1;
+    variable VAR : NATURAL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00701"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00701arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd
new file mode 100644
index 0000000..a5a0d9d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc702.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00702ent IS
+END c03s04b01x00p23n01i00702ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00702arch OF c03s04b01x00p23n01i00702ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype STRING12 is STRING( 1 to 12 );
+    type FT is file of STRING12;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.56";
+
+    -- Declare a variable.
+    constant CON : STRING12 := "hello, world";
+    variable VAR : STRING12 := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00702 - The output file will tested by test file s010434.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00702arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd
new file mode 100644
index 0000000..2e1ea8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc703.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:42 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:45 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00703ent IS
+END c03s04b01x00p23n01i00703ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00703arch OF c03s04b01x00p23n01i00703ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype STRING12 is STRING( 1 to 12 );
+    type FT is file of STRING12;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.56";
+    
+    -- Declare a variable into which we will read.
+    constant CON : STRING12 := "hello, world";
+    variable VAR : STRING12;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00703"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00703 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd
new file mode 100644
index 0000000..80b6267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc704.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00704ent IS
+END c03s04b01x00p23n01i00704ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00704arch OF c03s04b01x00p23n01i00704ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
+    type FT is file of BIT_VECTOR5;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.57";
+
+    -- Declare a variable.
+    constant CON : BIT_VECTOR5 := B"10101";
+    variable VAR : BIT_VECTOR5 := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00704 - The output file will tested by test file s010436.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd
new file mode 100644
index 0000000..a648909
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc705.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:43 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:46 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00705ent IS
+END c03s04b01x00p23n01i00705ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00705arch OF c03s04b01x00p23n01i00705ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
+    type FT is file of BIT_VECTOR5;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.57";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BIT_VECTOR5 := B"10101";
+    variable VAR : BIT_VECTOR5;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00705"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00705 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd
new file mode 100644
index 0000000..6c67dab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc706.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+package c03s04b01x00p23n01i00706pkg is
+
+  type Waveform_element is record
+                             Value:     Bit;
+                             At:        Time;
+                           end record;
+  
+  type Signal_history is file of Waveform_element;
+
+end c03s04b01x00p23n01i00706pkg;
+
+use work.c03s04b01x00p23n01i00706pkg.all;
+ENTITY c03s04b01x00p23n01i00706ent IS
+END c03s04b01x00p23n01i00706ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00706arch OF c03s04b01x00p23n01i00706ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : Signal_history open write_mode is "iofile.58";
+
+    -- Declare a variable.
+    variable VAR : Waveform_element    := ('1',10 ns);
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00706 - The output file will tested by test file s010438.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00706arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd
new file mode 100644
index 0000000..3274e47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc707.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:44 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:46 1996  --
+--                 ****************************               --
+
+
+package c03s04b01x00p23n01i00707pkg is
+
+  type Waveform_element is record
+                             Value:     Bit;
+                             At:        Time;
+                           end record;
+  
+  type Signal_history is file of Waveform_element;
+
+end c03s04b01x00p23n01i00707pkg;
+
+use work.c03s04b01x00p23n01i00707pkg.all;
+ENTITY c03s04b01x00p23n01i00707ent IS
+END c03s04b01x00p23n01i00707ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00707arch OF c03s04b01x00p23n01i00707ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : Signal_history open read_mode is "iofile.58";
+    
+    -- Declare a variable into which we will read.
+    constant con : Waveform_element := ('1',10 ns);
+    variable VAR : Waveform_element;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00707"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00707 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00707arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd
new file mode 100644
index 0000000..39cd65a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc708.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00708ent IS
+END c03s04b01x00p23n01i00708ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00708arch OF c03s04b01x00p23n01i00708ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type t1 is record
+               number:      NATURAL;
+               string:      STR16;
+             end record;
+
+  type string_table is array (1 to NumOfStrings) of STR16;
+  
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft1 is file of t1;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft1 open write_mode is "iofile.59";
+
+    -- Declare a variable.
+    variable VAR : t1;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to NumOfStrings  loop
+      VAR.number := i;
+      VAR.string := string_array(i);
+      write(FILEV, VAR);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00708 - The output file will tested by test file s010440.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00708arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd
new file mode 100644
index 0000000..b5f0d39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc709.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:45 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:47 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00709ent IS
+END c03s04b01x00p23n01i00709ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00709arch OF c03s04b01x00p23n01i00709ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type t1 is record
+               number:      NATURAL;
+               string:      STR16;
+             end record;
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft1 is file of t1;
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : ft1 open read_mode is "iofile.59";
+    
+    -- Declare a variable into which we will read.
+    variable VAR : t1;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to NumofStrings loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if ((VAR.number /= i) or (VAR.string /= string_array(i))) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00709"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00709 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd
new file mode 100644
index 0000000..e94f66f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc710.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00710ent IS
+END c03s04b01x00p23n01i00710ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00710arch OF c03s04b01x00p23n01i00710ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  type t2 is array(1 to 5) of INTEGER;
+  type t3 is array(INTEGER range <>) of t2;
+  
+  -- Objects...
+  constant integer_array: t3(1 to 8) :=
+    ( (0, 1, 2, 3, 4),    (2, 4, 6, 8, 10),
+      (-2, -1, 0, 1, 2),    (13, 2, -45, 6, 1),
+      (1, 4, 16, 64, 256),    (1, 4, 9, 16, 25),
+      (1, 2, 4, 8, 16),    (5, 4, 3, 2, 1) );
+
+  type    ft3 is file of t3;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open write_mode is "iofile.60";
+
+    -- Declare a variable.
+    variable VAR : t3(3 downto 0);
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 2  loop
+      VAR := integer_array((i-1)*4+1 to i*4);
+      write(FILEV, VAR);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00710 - The output file will tested by test file s010442.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00710arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd
new file mode 100644
index 0000000..7a15d8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc711.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00711ent IS
+END c03s04b01x00p23n01i00711ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00711arch OF c03s04b01x00p23n01i00711ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  type t2 is array(1 to 5) of INTEGER;
+  type t3 is array(INTEGER range <>) of t2;
+  type ft3 is file of t3;
+
+  -- Objects...
+  constant integer_array: t3(1 to 8) :=
+    ( (0, 1, 2, 3, 4),    (2, 4, 6, 8, 10),
+      (-2, -1, 0, 1, 2),    (13, 2, -45, 6, 1),
+      (1, 4, 16, 64, 256),    (1, 4, 9, 16, 25),
+      (1, 2, 4, 8, 16),    (5, 4, 3, 2, 1) );
+
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : ft3 open read_mode is "iofile.60";
+    
+    -- Declare a variable into which we will read.
+    variable VAR    : t3(3 downto 0);
+    variable k      : integer   := 0;   
+    variable count    : integer;
+    variable length   : integer;
+  BEGIN
+    -- Read in the file.
+    count := 1;
+    while not endfile(FILEV) loop
+      read(FILEV, VAR, length);
+      assert length = 4
+        report "Wrong length returned from READ"
+        severity ERROR;
+      if (length /= 4) then
+        k := 1;
+      end if;
+      assert VAR(1 to length) = integer_array((count-1)*4+1 to count*4)
+        report "Read of array of integer arrays failed."
+        severity ERROR;
+      if (VAR(1 to length) /= integer_array((count-1)*4+1 to count*4)) then
+        k := 1;
+      end if;
+      count := count + 1;
+    end loop;
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00711"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00711 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd
new file mode 100644
index 0000000..20218cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc712.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p24n01i00712ent IS
+END c03s04b01x00p24n01i00712ent;
+
+ARCHITECTURE c03s04b01x00p24n01i00712arch OF c03s04b01x00p24n01i00712ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft3 is file of STRING;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open write_mode is "iofile.01";
+  BEGIN
+    for i in 1 to NumOfStrings loop
+      write(FILEV, string_array(i));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p24n01i00712 - This test should produce an output file iofile.01 and tested by s010102.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p24n01i00712arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd
new file mode 100644
index 0000000..dab5fe5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc713.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:46 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:48 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p24n01i00713ent IS
+END c03s04b01x00p24n01i00713ent;
+
+ARCHITECTURE c03s04b01x00p24n01i00713arch OF c03s04b01x00p24n01i00713ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    (  "This is string 1"
+       ,"__Hello  World__"
+       ,"This is string " & "3"
+       ,"_Bird is a word_"
+       ,"_Goodbye (ciao)_"
+       );
+
+  type ft3 is file of STRING;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open read_mode is "iofile.02";
+    variable length   : INTEGER;
+    variable str   : STR16;
+    variable count    : integer := 0;
+    variable ok   : integer := 1;
+  BEGIN
+    count := 1;
+    while not endfile(FILEV) loop
+      read(FILEV, str, length);
+      if (length /= 16) then
+        ok := 0;
+      end if;
+      if (str /= string_array(count)) then
+        ok := 0;
+      end if;
+      assert str = string_array(count)
+        report "'string' is incorrect"
+        severity ERROR;
+      count := count + 1;
+    end loop;
+    assert NOT(ok = 1)
+      report "***PASSED TEST: c03s04b01x00p24n01i00713" 
+      severity NOTE;
+    assert (ok = 1)
+      report "***FAILED TEST: c03s04b01x00p24n01i00713 - READ operation for unconstrained array type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p24n01i00713arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd
new file mode 100644
index 0000000..b529fe7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc717.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p02n01i00717ent IS
+begin
+  assert false
+    report "First entity NOT overwritten -- test FAILS."
+    severity note ;
+END c01s01b00x00p02n01i00717ent;
+
+
+-- legal. identifier has already been defined - this causes the
+--        first entity to be over-written.
+ENTITY c01s01b00x00p02n01i00717ent IS                         -- second use of name
+begin
+  assert false
+    report "First entity overwritten -- test passes."
+    severity note ;
+END c01s01b00x00p02n01i00717ent;
+
+ARCHITECTURE c01s01b00x00p02n01i00717arch OF c01s01b00x00p02n01i00717ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b00x00p02n01i00717 - This test needs manual check." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p02n01i00717arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd
new file mode 100644
index 0000000..9185d9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc719.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p04n01i00719ent IS
+BEGIN
+END;            -- No_Failure_Here
+
+ENTITY c01s01b00x00p04n01i00719ent IS
+END c01s01b00x00p04n01i00719ent;
+
+ARCHITECTURE c01s01b00x00p04n01i00719arch OF c01s01b00x00p04n01i00719ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b00x00p04n01i00719"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p04n01i00719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd
new file mode 100644
index 0000000..a602d07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00731ent IS
+  -- A basic entity with a port
+  port ( signal s : bit);
+END c01s01b01x00p04n01i00731ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x00p04n01i00731"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00731arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd
new file mode 100644
index 0000000..a4fe42e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n02i00740pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer; 
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1 : boolean := true; 
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note; 
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false); 
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4); 
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0); 
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+
+end c01s01b01x01p04n02i00740pkg;
+
+use work.c01s01b01x01p04n02i00740pkg.all;
+ENTITY c01s01b01x01p04n02i00740ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    Cgen1 : boolean := true;
+    Cgen2 : bit := '1';
+    Cgen3 : character := 's';
+    Cgen4 : severity_level := note;
+    Cgen5 : integer := 3;
+    Cgen6 : real := 3.0;
+    Cgen7 : time := 3 ns;
+    Cgen8 : natural := 1;
+    Cgen9 : positive := 1;
+    Cgen10 : string := "shishir";
+    Cgen11 : bit_vector := B"0011";
+    Cgen12 : boolean_vector := (true,false);
+    Cgen13 : severity_level_vector := (note,error);
+    Cgne14 : integer_vector := (1,2,3,4);
+    Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17 : natural_vector := (1,2,3,4);
+    Cgen18 : positive_vector := (1,2,3,4));
+END c01s01b01x01p04n02i00740ent;
+
+ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable Vgen1 : boolean := true;
+    variable Vgen2 : bit := '1';
+    variable Vgen3 : character := 's';
+    variable Vgen4 : severity_level := note;
+    variable Vgen5 : integer := 3;
+    variable Vgen6 : real := 3.0;
+    variable Vgen7 : time := 3 ns;
+    variable Vgen8 : natural := 1;
+    variable Vgen9 : positive := 1;
+    variable Vgen10 : string (one to seven):= "shishir";
+    variable Vgen11 : bit_vector(zero to three) := B"0011";
+    variable Vgen12 : boolean_vector(zero to one) := (true,false);
+    variable Vgen13 : severity_level_vector(zero to one) := (note,error);
+    variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
+    variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
+    variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
+    variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
+    variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
+
+  BEGIN
+    assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
+    assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
+    assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
+    assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
+    assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
+    assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
+    assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
+    assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
+    assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
+    assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
+    assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
+    assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
+    assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
+    assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
+    assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
+    assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
+    assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
+    assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
+    assert NOT( 
+      Vgen1 = C1    and
+      Vgen2 = C2    and
+      Vgen3 = C3    and
+      Vgen4 = C4    and
+      Vgen5 = C5    and
+      Vgen6 = C6    and
+      Vgen7 = C7    and
+      Vgen8 = C8    and
+      Vgen9 = C9    and
+      Vgen10 = C10    and
+      Vgen11 = C11    and
+      Vgen12 = C12    and
+      Vgen13 = C13    and
+      Vgen14 = C14    and
+      Vgen15 = C15    and
+      Vgen16 = C16    and
+      Vgen17 = C17    and
+      Vgen18 = C18    )
+      report "***PASSED TEST: c01s01b01x01p04n02i00740"
+      severity NOTE;
+    assert ( 
+      Vgen1 = C1    and
+      Vgen2 = C2    and
+      Vgen3 = C3    and
+      Vgen4 = C4    and
+      Vgen5 = C5    and
+      Vgen6 = C6    and
+      Vgen7 = C7    and
+      Vgen8 = C8    and
+      Vgen9 = C9    and
+      Vgen10 = C10    and
+      Vgen11 = C11    and
+      Vgen12 = C12    and
+      Vgen13 = C13    and
+      Vgen14 = C14    and
+      Vgen15 = C15    and
+      Vgen16 = C16    and
+      Vgen17 = C17    and
+      Vgen18 = C18    )
+      report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p04n02i00740arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd
new file mode 100644
index 0000000..f6cb9da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc741.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x01p04n01i00741ent_a is
+  generic (
+    constant gc1 : in integer;
+    constant gc2 : in real;
+    constant gc3 : in boolean
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n01i00741ent_a;
+
+architecture c01s01b01x01p04n01i00741arch_a of c01s01b01x01p04n01i00741ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00741"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00741 - Simple generic association in component instantiation failed."
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00741arch_a;
+
+
+ENTITY c01s01b01x01p04n01i00741ent IS
+  generic ( constant gen_con : integer := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n01i00741ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00741arch OF c01s01b01x01p04n01i00741ent IS
+  constant    c1 : integer    := 33;
+  constant    c2 : real    := 1.23557;
+  constant    c3 : boolean    := FALSE;
+  signal       s1 : integer;
+  signal       s2 : integer;
+  signal       s3 : integer;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : real;
+      constant dgc3 : boolean
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+  
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00741ent_a(c01s01b01x01p04n01i00741arch_a)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+  
+  u1 : comp1
+    generic map (5, 0.1234, TRUE)
+    port map (ee1,ee2);
+
+END c01s01b01x01p04n01i00741arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd
new file mode 100644
index 0000000..17c1be2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd
@@ -0,0 +1,131 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n01i00742pkg is
+  type arrtype is array (1 to 5) of integer;
+  type rectype is record
+-- 'a',33,0.1234,TRUE
+                    ch : character;
+                    int : integer;
+                    re : real;
+                    bo : boolean;
+                  end record;
+end c01s01b01x01p04n01i00742pkg;
+
+use work.c01s01b01x01p04n01i00742pkg.all;
+entity c01s01b01x01p04n01i00742ent_a is
+  generic (
+    constant gc1 : arrtype;
+    constant gc2 : rectype;
+    constant gc3 : boolean
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n01i00742ent_a;
+
+architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo)  AND (gc3) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00742"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed." 
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00742arch_a;
+
+use work.c01s01b01x01p04n01i00742pkg.all;
+ENTITY c01s01b01x01p04n01i00742ent IS
+  generic ( constant gen_con : integer := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n01i00742ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
+  signal       s1 : integer;
+  signal       s2 : integer;
+  signal       s3 : integer;
+
+  component comp1
+    generic (
+      constant dgc1 : arrtype;
+      constant dgc2 : rectype;
+      constant dgc3 : boolean
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+  
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+  function BoolToArr(bin : boolean) return arrtype is
+  begin
+    if bin then
+      return (1,2,3,4,5);
+    else
+      return (9,8,7,6,5);
+    end if;
+  end;
+  
+  function IntegerToRec(iin : integer) return rectype is
+  begin
+    return ('a',33,0.1234,TRUE);
+  end;
+  
+  function BitToBool(bin : bit) return boolean is
+  begin
+    if (bin = '1') then
+      return TRUE;
+    else
+      return FALSE;
+    end if;
+  end;
+
+BEGIN
+  
+  u1 : comp1
+    generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
+    port map (ee1,ee2);
+
+END c01s01b01x01p04n01i00742arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd
new file mode 100644
index 0000000..840378a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n01i00743pkg is
+  type arrtype is array (1 to 5) of bit;
+  constant defcon1 : bit;
+  constant defcon2 : integer;
+  constant defcon3 : arrtype;
+  constant defcon4 : boolean;
+  component comp1
+    generic (
+      constant dgc1 : bit := defcon1;
+      constant dgc2 : integer := defcon2;
+      constant dgc3 : arrtype := defcon3;
+      constant dgc4 : boolean := defcon4
+      );
+    port ( signal dcent1 : inout bit := dgc1;
+           signal dcent2 : inout integer := dgc2;
+           signal dcent3 : inout arrtype := dgc3;
+           signal dcent4 : inout boolean := dgc4
+           );
+  end component;
+end c01s01b01x01p04n01i00743pkg;
+
+package body c01s01b01x01p04n01i00743pkg is
+  constant defcon1 : bit := '1';
+  constant defcon2 : integer := 113;
+  constant defcon3 : arrtype := ('1','0','1','0','1');
+  constant defcon4 : boolean := TRUE;
+end c01s01b01x01p04n01i00743pkg;
+
+use work.c01s01b01x01p04n01i00743pkg.all;
+entity c01s01b01x01p04n01i00743ent_a is
+  generic (
+    constant gc1 : bit;
+    constant gc2 : integer;
+    constant gc3 : arrtype;
+    constant gc4 : boolean
+    );
+  port (       signal cent1 : inout bit;
+               signal cent2 : inout integer;
+               signal cent3 : inout arrtype;
+               signal cent4 : inout boolean
+               );
+end c01s01b01x01p04n01i00743ent_a;
+
+architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00743"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants." 
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00743arch_a;
+
+use work.c01s01b01x01p04n01i00743pkg.all;
+ENTITY c01s01b01x01p04n01i00743ent IS
+  generic    (    constant gen_con : integer := 1334 );
+  port    (    signal ee1 : inout boolean := TRUE;
+               signal ee2 : inout bit;
+               signal ee3 : inout integer;
+               signal ee4 : inout arrtype
+               );
+END c01s01b01x01p04n01i00743ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
+    generic map ( dgc1, dgc2, dgc3, dgc4 )
+    port map ( dcent1, dcent2, dcent3, dcent4 );
+BEGIN
+
+  u1 : comp1; 
+
+END c01s01b01x01p04n01i00743arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd
new file mode 100644
index 0000000..e47c7da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd
@@ -0,0 +1,170 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc744.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00744pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                               j: string(1 to 7);
+                               k: bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+end c01s01b01x01p05n02i00744pkg;
+
+use work.c01s01b01x01p05n02i00744pkg.all;
+ENTITY c01s01b01x01p05n02i00744ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "shishir";
+    C11 : bit_vector    := B"0011"
+    );
+  port(
+    S1 : inout boolean_vector      (zero to fifteen);
+    S2 : inout severity_level_vector   (zero to fifteen);
+    S3 : inout integer_vector      (zero to fifteen);
+    S4 : inout real_vector         (zero to fifteen);
+    S5 : inout time_vector       (zero to fifteen);
+    S6 : inout natural_vector      (zero to fifteen);
+    S7 : inout positive_vector      (zero to fifteen);
+    S48: inout array_rec_std      (zero to seven)
+    );
+END c01s01b01x01p05n02i00744ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00744arch OF c01s01b01x01p05n02i00744ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    for i in S1'range loop
+      S1(i) <= C1;
+    end loop;
+    for i in S2'range loop
+      S2(i) <= C4;
+    end loop;
+    for i in S3'range loop
+      S3(i) <= C5;
+    end loop;
+    for i in S4'range loop
+      S4(i) <= C6;
+    end loop;
+    for i in S5'range loop
+      S5(i) <= C7;
+    end loop;
+    for i in S6'range loop
+      S6(i) <= C8;
+    end loop;
+    for i in S7'range loop
+      S7(i) <= C9;
+    end loop;
+    for i in S48'range loop
+      S48(i) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+    end loop;
+    wait for 10 ns;
+    for i in zero to 7 loop
+      if (S1(i) /= true) then
+        k := 1;
+      end if;
+      assert S1(i) = true report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S2(i) /= note) then
+        k := 1;
+      end if;
+      assert S2(i) = note report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S3(i) /= 3) then
+        k := 1;
+      end if;
+      assert S3(i) = 3 report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S4(i) /= 3.0) then
+        k := 1;
+      end if;
+      assert S4(i) = 3.0 report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S5(i) /= 3 ns) then
+        k := 1;
+      end if;
+      assert S5(i) = 3 ns report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+      if (S6(i) /= 1) then
+        k := 1;
+      end if;
+      assert S6(i) = 1 report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S7(i) /= 1) then
+        k := 1;
+      end if;
+      assert S7(i) = 1 report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S48(i) /= (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011")) then
+        k := 1;
+      end if;
+      assert S48(i) = (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011") report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00744"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00744 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd
new file mode 100644
index 0000000..771b627
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd
@@ -0,0 +1,250 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc745.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00745pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                               j: string(1 to 7);
+                               k: bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  function F1(inp : boolean_vector)    return boolean ;
+  function F2(inp : bit_vector)    return bit ;
+  function F3(inp : string)       return character ;
+  function F4(inp : severity_level_vector)    return severity_level ;
+  function F5(inp : integer_vector)    return integer ;
+  function F6(inp : real_vector)    return real ;
+  function F7(inp : time_vector)    return time ;
+  function F8(inp : natural_vector)    return natural ;
+  function F9(inp : positive_vector)    return positive ;
+  function F10(inp : array_rec_std)    return record_std_package ;
+
+end c01s01b01x01p05n02i00745pkg;
+
+package body c01s01b01x01p05n02i00745pkg is
+  function F1(inp : boolean_vector) return boolean is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    return false;
+  end F1;
+  function F2(inp : bit_vector) return bit is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    return '0';
+  end F2;
+  function F3(inp : string) return character is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    return 'h';
+  end F3;
+  function F4(inp : severity_level_vector) return severity_level is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    return error;
+  end F4;
+  function F5(inp : integer_vector) return integer is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    return 6;
+  end F5;
+  function F6(inp : real_vector) return real is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    return 6.0;
+  end F6;
+  function F7(inp : time_vector) return time is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    return 6 ns;
+  end F7;
+  function F8(inp : natural_vector) return natural is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    return 6;
+  end F8;
+  function F9(inp : positive_vector) return positive is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    return 6;
+  end F9;
+  function F10(inp : array_rec_std) return record_std_package is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end F10;
+end c01s01b01x01p05n02i00745pkg;
+
+
+use work.c01s01b01x01p05n02i00745pkg.all;
+ENTITY c01s01b01x01p05n02i00745ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00745ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00745arch OF c01s01b01x01p05n02i00745ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    var1 := F1(S1);
+    var2 := F2(S9);
+    var3 := F3(S8);
+    var4 := F4(S2);
+    var5 := F5(S3);
+    var6 := F6(S4);
+    var7 := F7(S5);
+    var8 := F8(S6);
+    var9 := F9(S7);
+    var48 := F10(S48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = F1(S1)   and
+                   var2    = F2(S9)   and
+                   var3    = F3(S8)   and
+                   var4    = F4(S2)   and
+                   var5    = F5(S3)   and
+                   var6    = F6(S4)   and
+                   var7    = F7(S5)   and
+                   var8    = F8(S6)   and
+                   var9    = F9(S7)   and
+                   var48    = F10(S48)   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00745"
+      severity NOTE;
+    assert (    var1    = F1(S1)   and
+                var2    = F2(S9)   and
+                var3    = F3(S8)   and
+                var4    = F4(S2)   and
+                var5    = F5(S3)   and
+                var6    = F6(S4)   and
+                var7    = F7(S5)   and
+                var8    = F8(S6)   and
+                var9    = F9(S7)   and
+                var48    = F10(S48)   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00745 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd
new file mode 100644
index 0000000..07ed72d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd
@@ -0,0 +1,249 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00746pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  function F1(inp : boolean_vector(0 to 15))    return boolean ;
+  function F2(inp : bit_vector(0 to 3))    return bit ;
+  function F3(inp : string(1 to 7))       return character ;
+  function F4(inp : severity_level_vector(0 to 15))    return severity_level ;
+  function F5(inp : integer_vector(0 to 15))    return integer ;
+  function F6(inp : real_vector(0 to 15))    return real ;
+  function F7(inp : time_vector(0 to 15))    return time ;
+  function F8(inp : natural_vector(0 to 15))    return natural ;
+  function F9(inp : positive_vector(0 to 15)) return positive ;
+  function F10(inp: array_rec_std(0 to 7))    return record_std_package ;
+
+end c01s01b01x01p05n02i00746pkg;
+
+package body c01s01b01x01p05n02i00746pkg is
+  function F1(inp : boolean_vector(0 to 15)) return boolean is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    return false;
+  end F1;
+  function F2(inp : bit_vector(0 to 3)) return bit is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    return '0';
+  end F2;
+  function F3(inp : string(1 to 7)) return character is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    return 'h';
+  end F3;
+  function F4(inp : severity_level_vector(0 to 15)) return severity_level is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    return error;
+  end F4;
+  function F5(inp : integer_vector(0 to 15)) return integer is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    return 6;
+  end F5;
+  function F6(inp : real_vector(0 to 15)) return real is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    return 6.0;
+  end F6;
+  function F7(inp : time_vector(0 to 15)) return time is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    return 6 ns;
+  end F7;
+  function F8(inp : natural_vector(0 to 15)) return natural is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    return 6;
+  end F8;
+  function F9(inp : positive_vector(0 to 15)) return positive is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    return 6;
+  end F9;
+  function F10(inp : array_rec_std(0 to 7)) return record_std_package is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end F10;
+end c01s01b01x01p05n02i00746pkg;
+
+use work.c01s01b01x01p05n02i00746pkg.all;
+ENTITY c01s01b01x01p05n02i00746ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00746ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    var1 := F1(S1);
+    var2 := F2(S9);
+    var3 := F3(S8);
+    var4 := F4(S2);
+    var5 := F5(S3);
+    var6 := F6(S4);
+    var7 := F7(S5);
+    var8 := F8(S6);
+    var9 := F9(S7);
+    var48 := F10(S48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = F1(S1)   and
+                   var2    = F2(S9)   and
+                   var3    = F3(S8)   and
+                   var4    = F4(S2)   and
+                   var5    = F5(S3)   and
+                   var6    = F6(S4)   and
+                   var7    = F7(S5)   and
+                   var8    = F8(S6)   and
+                   var9    = F9(S7)   and
+                   var48    = F10(S48)   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00746"
+      severity NOTE;
+    assert (    var1    = F1(S1)   and
+                var2    = F2(S9)   and
+                var3    = F3(S8)   and
+                var4    = F4(S2)   and
+                var5    = F5(S3)   and
+                var6    = F6(S4)   and
+                var7    = F7(S5)   and
+                var8    = F8(S6)   and
+                var9    = F9(S7)   and
+                var48    = F10(S48)   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00746arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd
new file mode 100644
index 0000000..3ff5063
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd
@@ -0,0 +1,249 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc747.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00747pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  procedure P1(inp : boolean_vector;ot:out boolean) ;
+  procedure P2(inp : bit_vector;ot:out bit) ;
+  procedure P3(inp : string; ot:out character);
+  procedure P4(inp : severity_level_vector;ot:out severity_level);
+  procedure P5(inp : integer_vector; ot:out integer) ;
+  procedure P6(inp : real_vector; ot:out real) ;
+  procedure P7(inp : time_vector; ot:out time) ;
+  procedure P8(inp : natural_vector;ot:out natural) ;
+  procedure P9(inp : positive_vector;ot:out positive) ;
+  procedure P10(inp : array_rec_std;ot:out record_std_package) ;
+
+end c01s01b01x01p05n02i00747pkg;
+
+package body c01s01b01x01p05n02i00747pkg is
+  procedure P1(inp : boolean_vector;ot:out boolean) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    ot :=  false;
+  end P1;
+  procedure P2(inp : bit_vector;ot:out bit) is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    ot :=  '0';
+  end P2;
+  procedure P3(inp : string; ot:out character) is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    ot :=  'h';
+  end P3;
+  procedure P4(inp : severity_level_vector;ot:out severity_level) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    ot :=  error;
+  end P4;
+  procedure P5(inp : integer_vector; ot:out integer) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    ot :=  6;
+  end P5;
+  procedure P6(inp : real_vector; ot:out real) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    ot :=  6.0;
+  end P6;
+  procedure P7(inp : time_vector; ot:out time) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    ot :=  6 ns;
+  end P7;
+  procedure P8(inp : natural_vector;ot:out natural) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    ot :=  6;
+  end P8;
+  procedure P9(inp : positive_vector;ot:out positive) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    ot :=  6;
+  end P9;
+  procedure P10(inp : array_rec_std;ot:out record_std_package) is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    ot :=  (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end P10;
+end c01s01b01x01p05n02i00747pkg;
+
+use work.c01s01b01x01p05n02i00747pkg.all;
+ENTITY c01s01b01x01p05n02i00747ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00747ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00747arch OF c01s01b01x01p05n02i00747ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    P1(S1,var1);
+    P2(S9,var2);
+    P3(S8,var3);
+    P4(S2,var4);
+    P5(S3,var5);
+    P6(S4,var6);
+    P7(S5,var7);
+    P8(S6,var8);
+    P9(S7,var9);
+    P10(S48,var48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = false      and
+                   var2    = '0'      and
+                   var3    = 'h'      and
+                   var4    = error      and
+                   var5    = 6      and
+                   var6    = 6.0      and
+                   var7    = 6 ns      and
+                   var8    = 6      and
+                   var9    = 6      and
+                   var48    = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00747"
+      severity NOTE;
+    assert (    var1    = false      and
+                var2    = '0'      and
+                var3    = 'h'      and
+                var4    = error      and
+                var5    = 6      and
+                var6    = 6.0      and
+                var7    = 6 ns      and
+                var8    = 6      and
+                var9    = 6      and
+                var48    = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00747 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd
new file mode 100644
index 0000000..44247a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd
@@ -0,0 +1,247 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc748.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00748pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) ;
+  procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) ;
+  procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string);
+  procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector);
+  procedure P5(inp : integer_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out integer_vector) ;
+  procedure P6(inp : real_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out real_vector) ;
+  procedure P7(inp : time_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out time_vector) ;
+  procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) ;
+  procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) ;
+  procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) ;
+end c01s01b01x01p05n02i00748pkg;
+
+package body c01s01b01x01p05n02i00748pkg is
+  procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) is
+  begin 
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    ot := inp;
+  end P1;   
+  procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    ot := inp;
+  end P2;
+  procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string) is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    ot := inp;
+  end P3;
+  procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    ot := inp;
+  end P4;
+  procedure P5(inp : integer_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out integer_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    ot := inp;
+  end P5;
+  procedure P6(inp : real_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out real_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    ot := inp;
+  end P6;
+  procedure P7(inp : time_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out time_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    ot := inp;
+  end P7;
+  procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    ot :=  inp;
+  end P8;
+  procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    ot := inp;
+  end P9;
+  procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    ot :=  inp;
+  end P10;
+end c01s01b01x01p05n02i00748pkg;
+
+use work.c01s01b01x01p05n02i00748pkg.all;
+ENTITY c01s01b01x01p05n02i00748ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00748ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00748arch OF c01s01b01x01p05n02i00748ent IS
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean_vector(zero to fifteen);
+    variable var4 : severity_level_vector(zero to fifteen);
+    variable var5 : integer_vector(zero to fifteen);
+    variable var6 : real_vector(zero to fifteen);
+    variable var7 : time_vector(zero to fifteen);
+    variable var8 : natural_vector(zero to fifteen);
+    variable var9 : positive_vector(zero to fifteen);
+    variable var2 : bit_vector(zero to three);
+    variable var3 : string(one to seven);
+    variable var48: array_rec_std(zero to seven);
+
+  BEGIN
+    P1(S1,zero,one,three,seven,fifteen,var1);
+    P2(S9,zero,one,three,seven,fifteen,var2);
+    P3(S8,zero,one,three,seven,fifteen,var3);
+    P4(S2,zero,one,three,seven,fifteen,var4);
+    P5(S3,zero,one,three,seven,fifteen,var5);
+    P6(S4,zero,one,three,seven,fifteen,var6);
+    P7(S5,zero,one,three,seven,fifteen,var7);
+    P8(S6,zero,one,three,seven,fifteen,var8);
+    P9(S7,zero,one,three,seven,fifteen,var9);
+    P10(S48,zero,one,three,seven,fifteen,var48);
+    wait for 1 ns;
+
+    assert(var1(0) = true)    report"wrong assignment of S1" severity error;
+    assert(var2(0) = '0')    report"wrong assignment of S2" severity error;
+    assert(var3(1) = 's')    report"wrong assignment of S3" severity error;
+    assert(var4(0) = note)    report"wrong assignment of S4" severity error;
+    assert(var5(0) = 3)    report"wrong assignment of S5" severity error;
+    assert(var6(0) = 3.0)    report"wrong assignment of S6" severity error;
+    assert(var7(0) = 3 ns)    report"wrong assignment of S7" severity error;
+    assert(var8(0) = 1)    report"wrong assignment of S8" severity error;
+    assert(var9(0) = 1)    report"wrong assignment of S9" severity error;
+    assert(var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000"))    report"wrong assignment of S10" severity error;
+
+    assert NOT(    (var1(0) = true)   and
+                   (var2(0) = '0')    and
+                   (var3(1) = 's')    and
+                   (var4(0) = note)    and
+                   (var5(0) = 3)       and
+                   (var6(0) = 3.0)    and
+                   (var7(0) = 3 ns)    and
+                   (var8(0) = 1)       and
+                   (var9(0) = 1)       and
+                   (var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
+      report "***PASSED TEST: c01s01b01x01p05n02i00748"
+      severity NOTE;
+    assert (    (var1(0) = true)   and
+                (var2(0) = '0')    and
+                (var3(1) = 's')    and
+                (var4(0) = note)    and
+                (var5(0) = 3)       and
+                (var6(0) = 3.0)    and
+                (var7(0) = 3 ns)    and
+                (var8(0) = 1)       and
+                (var9(0) = 1)       and
+                (var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
+      report "***FAILED TEST: c01s01b01x01p05n02i00748 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00748arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd
new file mode 100644
index 0000000..099d1fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd
@@ -0,0 +1,527 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00749ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "shishir";
+    C11 : bit_vector    := B"0011"
+    );
+END c01s01b01x01p05n02i00749ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00749arch OF c01s01b01x01p05n02i00749ent IS
+  subtype hi_to_low_range    is integer range zero to seven;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st    is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st    is  integer_vector(zero to fifteen);
+  subtype real_vector_st    is  real_vector(zero to fifteen);
+  subtype time_vector_st    is  time_vector(zero to fifteen);
+  subtype natural_vector_st    is  natural_vector(zero to fifteen);
+  subtype positive_vector_st    is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector    is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector    is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector    is array (fifteen downto zero) of integer;
+  type real_cons_vector    is array (fifteen downto zero) of real;
+  type time_cons_vector    is array (fifteen downto zero) of time;
+  type natural_cons_vector    is array (fifteen downto zero) of natural;
+  type positive_cons_vector    is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector    is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector    is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector    is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector    is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector    is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range    is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range    is integer_vector(hi_to_low_range);
+  subtype real_vector_range       is real_vector(hi_to_low_range);
+  subtype time_vector_range       is time_vector(hi_to_low_range);
+  subtype natural_vector_range    is natural_vector(hi_to_low_range);
+  subtype positive_vector_range    is positive_vector(hi_to_low_range);
+
+  type array_rec_std    is array (integer range <>) of record_std_package;
+  type array_rec_cons    is array (integer range <>) of record_cons_array;
+  type array_rec_rec    is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st    is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st    is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st    is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector    := (C1,false);
+  constant C13 : severity_level_vector    := (C4,error);
+  constant C14 : integer_vector    := (one,two,three,four);
+  constant C15 : real_vector    := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector    := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector    := (one,2,3,4);
+  constant C18 : positive_vector    := (one,2,3,4);
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    :=  (others => C7);
+  constant C24 : natural_cons_vector    :=  (others => C8);
+  constant C25 : positive_cons_vector    :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector    :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 : severity_level_vector_st   := (others => C4);
+  constant C72 : integer_vector_st:=(others => C5);
+  constant C73 : real_vector_st   :=(others => C6);
+  constant C74 : time_vector_st   :=(others => C7);
+  constant C75 : natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a :record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new   := (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
+  constant C60 : byte       := (others => '0');
+  constant C61 : word       := (others =>'0' );
+  constant C64 : primary_memory    := (others => C61);
+  constant C65 : primary_memory_module    := ('1',C64);
+  constant C66 : whole_memory    := (others => C65);
+  constant C67 : current       := 1 A;
+  constant C68 : resistance    := 1 Ohm;
+  constant C69 : delay       := 2;
+  constant C78: boolean_vector_range    := (others => C1);
+  constant C79: severity_level_vector_range    := (others => C4) ;
+  constant C80: integer_vector_range    :=(others => C5) ;
+  constant C81: real_vector_range    :=(others => C6);
+  constant C82: time_vector_range    :=(others => C7);
+  constant C83: natural_vector_range    :=(others => C8);
+  constant C84: positive_vector_range    :=(others => C9);
+  constant C85: array_rec_std(0 to 7)    :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7)    :=(others => C51);
+  constant C88: array_rec_rec(0 to 7)    :=(others => C55);
+  constant C102: record_of_arr_of_record   := (C85,C86,C88);
+
+  signal V1    : boolean_vector(zero to fifteen) ;
+  signal V2    : severity_level_vector(zero to fifteen);
+  signal V3    : integer_vector(zero to fifteen) ;
+  signal V4    : real_vector(zero to fifteen) ;
+  signal V5    : time_vector (zero to fifteen);
+  signal V6    : natural_vector(zero to fifteen);
+  signal V7    : positive_vector(zero to fifteen);
+  signal V8    : boolean_cons_vector;
+  signal V9    : severity_level_cons_vector ;
+  signal V10    : integer_cons_vector;
+  signal V11    : real_cons_vector;
+  signal V12    : time_cons_vector ;
+  signal V13    : natural_cons_vector ;
+  signal V14    : positive_cons_vector ;
+  signal V15    : boolean_cons_vectorofvector ;
+  signal V16    : severity_level_cons_vectorofvector;
+  signal V17    : integer_cons_vectorofvector;
+  signal V18    : real_cons_vectorofvector;
+  signal V19    : time_cons_vectorofvector;
+  signal V20    : natural_cons_vectorofvector;
+  signal V21    : positive_cons_vectorofvector;
+  signal V22    : record_std_package;
+  signal V23    : record_cons_array ;
+  signal V24    : record_cons_arrayofarray ;
+  signal V25    : boolean_vector_st ;
+  signal V26    : severity_level_vector_st ;
+  signal V27    : integer_vector_st ;
+  signal V28    : real_vector_st ;
+  signal V29    : time_vector_st ;
+  signal V30    : natural_vector_st ;
+  signal V31    : positive_vector_st ;
+  signal V32    : record_array_st ;
+  signal V33    : record_array_st ;
+  signal V34   : record_array_new ;
+  signal V35    : record_of_records ;
+  signal V36    : byte ;
+  signal V37    : word ;
+  signal V41   : boolean_vector_range ;
+  signal V42   : severity_level_vector_range  ;
+  signal V43   : integer_vector_range  ;
+  signal V44   : real_vector_range ;
+  signal V45   : time_vector_range  ;
+  signal V46   : natural_vector_range  ;
+  signal V47   : positive_vector_range  ;
+  signal V48   : array_rec_std(zero to seven) ;
+  signal V49   : array_rec_cons(zero to seven) ;
+  signal V50   : array_rec_rec(zero to seven) ;
+  signal V51   : record_of_arr_of_record ;
+
+BEGIN
+  V1     <= (zero to fifteen => C1);
+  V2     <= (zero to fifteen => C4);
+  V3     <= (zero to fifteen => C5);
+  V4     <= (zero to fifteen => C6);
+  V5     <= (zero to fifteen => C7);
+  V6     <= (zero to fifteen => C8);
+  V7     <= (zero to fifteen => C9);
+  V8     <= C19;
+  V9     <= C20;
+  V10     <= C21;
+  V11     <= C22;
+  V12     <= C23;
+  V13     <= C24;
+  V14     <= C25;
+  V15     <= C26;
+  V16     <= C27;
+  V17     <= C28;
+  V18     <= C29;
+  V19     <= C30;
+  V20     <= C31;
+  V21     <= C32;
+  V22     <= C50;
+  V23     <= C51;
+  V24     <= C53;
+  V25     <= C70;
+  V26     <= C71;
+  V27     <= C72;
+  V28     <= C73;
+  V29     <= C74;
+  V30     <= C75;
+  V31     <= C76;
+  V32     <= C54a;
+  V33     <= C54a;
+  V34    <= C54b;
+  V35     <= C55;
+  V36     <= C60;
+  V37     <= C61;
+  V41    <= C78;
+  V42    <= C79;
+  V43    <= C80;
+  V44    <= C81;
+  V45    <= C82;
+  V46    <= C83;
+  V47    <= C84;
+  V48    <= C85;
+  V49    <= C86;
+  V50    <= C88;
+  V51    <= C102;
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and
+                   V22 = C50    and
+                   V23 = C51    and
+                   V24 = C53     and
+                   V25 = C70     and
+                   V26 = C71    and
+                   V27 = C72    and
+                   V28 = C73    and
+                   V29 = C74    and
+                   V30 = C75    and
+                   V31 = C76    and
+                   V32 = C54a    and
+                   V33 = C54a    and
+                   V34= C54b    and
+                   V35 = C55    and
+                   V36 = C60    and
+                   V37 = C61    and
+                   V41= C78    and
+                   V42= C79    and
+                   V43= C80    and
+                   V44= C81     and
+                   V45= C82    and
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    )   
+      report "***PASSED TEST: c01s01b01x01p05n02i00749"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and
+                V22 = C50    and
+                V23 = C51    and
+                V24 = C53     and
+                V25 = C70     and
+                V26 = C71    and
+                V27 = C72    and
+                V28 = C73    and
+                V29 = C74    and
+                V30 = C75    and
+                V31 = C76    and
+                V32 = C54a    and
+                V33 = C54a    and
+                V34= C54b    and
+                V35 = C55    and
+                V36 = C60    and
+                V37 = C61    and
+                V41= C78    and
+                V42= C79    and
+                V43= C80    and
+                V44= C81     and
+                V45= C82    and
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    )   
+      report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00749arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd
new file mode 100644
index 0000000..9afa1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd
@@ -0,0 +1,479 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00750ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive :=1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00750ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+  signal V1    : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+  signal V2    : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+  signal V3    : integer_vector(zero to fifteen) := (zero to fifteen => C5);
+  signal V4    : real_vector(zero to fifteen)    := (zero to fifteen => C6);
+  signal V5    : time_vector (zero to fifteen)   := (zero to fifteen => C7);
+  signal V6    : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+  signal V7    : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+  signal V8    : boolean_cons_vector:= C19;
+  signal V9    : severity_level_cons_vector:= C20;
+  signal V10    : integer_cons_vector:= C21;
+  signal V11    : real_cons_vector:= C22;
+  signal V12    : time_cons_vector:= C23;
+  signal V13    : natural_cons_vector := C24;
+  signal V14    : positive_cons_vector := C25;
+  signal V15    : boolean_cons_vectorofvector := C26;
+  signal V16    : severity_level_cons_vectorofvector:= C27;
+  signal V17    : integer_cons_vectorofvector:= C28;
+  signal V18    : real_cons_vectorofvector:= C29;
+  signal V19    : time_cons_vectorofvector:= C30;
+  signal V20    : natural_cons_vectorofvector:= C31;
+  signal V21    : positive_cons_vectorofvector:= C32;
+  signal V22    : record_std_package:= C50;
+  signal V23    : record_cons_array := C51;
+  signal V24    : record_cons_arrayofarray := C53 ;
+  signal V25    : boolean_vector_st := C70 ;
+  signal V26    : severity_level_vector_st:= C71;
+  signal V27    : integer_vector_st := C72;
+  signal V28    : real_vector_st := C73;
+  signal V29    : time_vector_st := C74;
+  signal V30    : natural_vector_st := C75;
+  signal V31    : positive_vector_st := C76;
+  signal V32    : record_array_st := C54a;
+  signal V33    : record_array_st := C54a;
+  signal V34   : record_array_new:= C54b;
+  signal V35    : record_of_records := C55;
+  signal V36    : byte    := C60;
+  signal V37    : word    := C61;
+  signal V41   : boolean_vector_range    := C78;
+  signal V42   : severity_level_vector_range := C79;
+  signal V43   : integer_vector_range  := C80;
+  signal V44   : real_vector_range:= C81 ;
+  signal V45   : time_vector_range  := C82;
+  signal V46   : natural_vector_range  := C83;
+  signal V47   : positive_vector_range  := C84;
+  signal V48   : array_rec_std(zero to seven)    := C85;
+  signal V49   : array_rec_cons(zero to seven) := C86;
+  signal V50   : array_rec_rec(zero to seven)    := C88;
+  signal V51   : record_of_arr_of_record    := C102;
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00750"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00750arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd
new file mode 100644
index 0000000..e3f8134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd
@@ -0,0 +1,526 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc751.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00751ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00751ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00751arch OF c01s01b01x01p05n02i00751ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+BEGIN
+
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen) ;
+    variable V2    : severity_level_vector(zero to fifteen);
+    variable V3    : integer_vector(zero to fifteen) ;
+    variable V4    : real_vector(zero to fifteen) ;
+    variable V5    : time_vector (zero to fifteen);
+    variable V6    : natural_vector(zero to fifteen);
+    variable V7    : positive_vector(zero to fifteen);
+    variable V8    : boolean_cons_vector;
+    variable V9    : severity_level_cons_vector ;
+    variable V10    : integer_cons_vector;
+    variable V11    : real_cons_vector;
+    variable V12    : time_cons_vector ;
+    variable V13    : natural_cons_vector ;
+    variable V14    : positive_cons_vector ;
+    variable V15    : boolean_cons_vectorofvector ;
+    variable V16    : severity_level_cons_vectorofvector;
+    variable V17    : integer_cons_vectorofvector;
+    variable V18    : real_cons_vectorofvector;
+    variable V19    : time_cons_vectorofvector;
+    variable V20    : natural_cons_vectorofvector;
+    variable V21    : positive_cons_vectorofvector;
+    variable V22    : record_std_package;
+    variable V23    : record_cons_array ;
+    variable V24    : record_cons_arrayofarray ;
+    variable V25    : boolean_vector_st ;
+    variable V26    : severity_level_vector_st ;
+    variable V27    : integer_vector_st ;
+    variable V28    : real_vector_st ;
+    variable V29    : time_vector_st ;
+    variable V30    : natural_vector_st ;
+    variable V31    : positive_vector_st ;
+    variable V32    : record_array_st ;
+    variable V33    : record_array_st ;
+    variable V34   : record_array_new ;
+    variable V35    : record_of_records ;
+    variable V36    : byte ;
+    variable V37    : word ;
+    variable V41   : boolean_vector_range ;
+    variable V42   : severity_level_vector_range  ;
+    variable V43   : integer_vector_range  ;
+    variable V44   : real_vector_range ;
+    variable V45   : time_vector_range  ;
+    variable V46   : natural_vector_range  ;
+    variable V47   : positive_vector_range  ;
+    variable V48   : array_rec_std(zero to seven) ;
+    variable V49   : array_rec_cons(zero to seven) ;
+    variable V50   : array_rec_rec(zero to seven) ;
+    variable V51   : record_of_arr_of_record ;
+
+  BEGIN
+
+    V1     := (zero to fifteen => C1);
+    V2     := (zero to fifteen => C4);
+    V3     := (zero to fifteen => C5);
+    V4     := (zero to fifteen => C6);
+    V5     := (zero to fifteen => C7);
+    V6     := (zero to fifteen => C8);
+    V7     := (zero to fifteen => C9);
+    V8     := C19;
+    V9     := C20;
+    V10     := C21;
+    V11     := C22;
+    V12     := C23;
+    V13     := C24;
+    V14     := C25;
+    V15     := C26;
+    V16     := C27;
+    V17     := C28;
+    V18     := C29;
+    V19     := C30;
+    V20     := C31;
+    V21     := C32;
+    V22     := C50;
+    V23     := C51;
+    V24     := C53;
+    V25     := C70;
+    V26     := C71;
+    V27     := C72;
+    V28     := C73;
+    V29     := C74;
+    V30     := C75;
+    V31     := C76;
+    V32     := C54a;
+    V33     := C54a;
+    V34    := C54b;
+    V35     := C55;
+    V36     := C60;
+    V37     := C61;
+    V41    := C78;
+    V42    := C79;
+    V43    := C80;
+    V44    := C81;
+    V45    := C82;
+    V46    := C83;
+    V47    := C84;
+    V48    := C85;
+    V49    := C86;
+    V50    := C88;
+    V51    := C102;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00751"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00751 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00751arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd
new file mode 100644
index 0000000..8d5ddb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd
@@ -0,0 +1,476 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00752ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00752ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+BEGIN
+
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+    variable V2    : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+    variable V3    : integer_vector(zero to fifteen) := (zero to fifteen => C5);
+    variable V4    : real_vector(zero to fifteen)    := (zero to fifteen => C6);
+    variable V5    : time_vector (zero to fifteen)   := (zero to fifteen => C7);
+    variable V6    : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+    variable V7    : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+    variable V8    : boolean_cons_vector:= C19;
+    variable V9    : severity_level_cons_vector := C20;
+    variable V10    : integer_cons_vector:= C21;
+    variable V11    : real_cons_vector:= C22;
+    variable V12    : time_cons_vector := C23;
+    variable V13    : natural_cons_vector := C24;
+    variable V14    : positive_cons_vector := C25;
+    variable V15    : boolean_cons_vectorofvector := C26;
+    variable V16    : severity_level_cons_vectorofvector:= C27;
+    variable V17    : integer_cons_vectorofvector:= C28;
+    variable V18    : real_cons_vectorofvector:= C29;
+    variable V19    : time_cons_vectorofvector:= C30;
+    variable V20    : natural_cons_vectorofvector:= C31;
+    variable V21    : positive_cons_vectorofvector:= C32;
+    variable V22    : record_std_package:= C50;
+    variable V23    : record_cons_array := C51;
+    variable V24    : record_cons_arrayofarray := C53 ;
+    variable V25    : boolean_vector_st:= C70 ;
+    variable V26    :  severity_level_vector_st := C71;
+    variable V27    :  integer_vector_st:= C72;
+    variable V28    :  real_vector_st := C73;
+    variable V29    :  time_vector_st := C74;
+    variable V30    :  natural_vector_st:= C75;
+    variable V31    : positive_vector_st := C76;
+    variable V32    : record_array_st := C54a;
+    variable V33    : record_array_st := C54a;
+    variable V34   : record_array_new:= C54b;
+    variable V35    : record_of_records := C55;
+    variable V36    : byte    := C60;
+    variable V37    : word    := C61;
+    variable V41   : boolean_vector_range    := C78;
+    variable V42   : severity_level_vector_range     := C79;
+    variable V43   : integer_vector_range  := C80;
+    variable V44   : real_vector_range:= C81 ;
+    variable V45   : time_vector_range := C82;
+    variable V46   : natural_vector_range    := C83;
+    variable V47   : positive_vector_range  := C84;
+    variable V48   : array_rec_std(zero to seven)    := C85;
+    variable V49   : array_rec_cons(zero to seven) := C86;
+    variable V50   : array_rec_rec(zero to seven)    := C88;
+    variable V51   : record_of_arr_of_record    := C102;
+  BEGIN
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34 = C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00752"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00752arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd
new file mode 100644
index 0000000..5877e63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd
@@ -0,0 +1,370 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc753.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00753pkg is
+  subtype hi_to_low_range    is integer range 0 to 7;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is integer_vector(0 to 15);
+  subtype real_vector_st    is real_vector(0 to 15);
+  subtype time_vector_st    is time_vector(0 to 15);
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  subtype positive_vector_st    is positive_vector(0 to 15);
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  type record_array_new is record
+                             a:boolean_vector(0 to 15);
+                             b:severity_level_vector(0 to 15);
+                             c:integer_vector(0 to 15);
+                             d:real_vector(0 to 15);
+                             e:time_vector(0 to 15);
+                             f:natural_vector(0 to 15);
+                             g:positive_vector(0 to 15);
+                           end record;
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(0 to 7);
+                                    b: array_rec_cons(0 to 7);
+                                    c: array_rec_rec(0 to 7);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(0 to 7) of bit;
+  
+  subtype word is bit_vector(0 to 15);                                 --constrained array
+  
+  constant size :integer := 7;
+  
+  type primary_memory is array(0 to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range 1 to 10;
+  
+end c01s01b01x01p05n02i00753pkg;
+
+
+use work.c01s01b01x01p05n02i00753pkg.all;
+ENTITY c01s01b01x01p05n02i00753ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+    S2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+    S3 : integer_vector(zero to fifteen):= (zero to fifteen => C5);
+    S4 : real_vector(zero to fifteen):= (zero to fifteen => C6);
+    S5 : time_vector (zero to fifteen):= (zero to fifteen => C7);
+    S6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+    S7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+    S8 : boolean_cons_vector:= (zero to fifteen => C1);
+    S9 : severity_level_cons_vector := (zero to fifteen => C4);
+    S10 : integer_cons_vector:= (zero to fifteen => C5);
+    S11 : real_cons_vector:= (zero to fifteen => C6);
+    S12 : time_cons_vector := (zero to fifteen => C7);
+    S13 : natural_cons_vector := (zero to fifteen => C8);
+    S14 : positive_cons_vector := (zero to fifteen => C9);
+    S15 : boolean_cons_vectorofvector:= (zero to fifteen =>(others=> C1));
+    S16 : severity_level_cons_vectorofvector := (zero to fifteen =>(others=> C4));
+    S17 : integer_cons_vectorofvector := (zero to fifteen =>(others=> C5));
+    S18 : real_cons_vectorofvector := (zero to fifteen =>(others=> C6));
+    S19 : time_cons_vectorofvector := (zero to fifteen =>(others=> C7));
+    S20 : natural_cons_vectorofvector := (zero to fifteen =>(others=> C8));
+    S21 : positive_cons_vectorofvector := (zero to fifteen =>(others=> C9));
+    S22 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+    S25 : boolean_vector_st := (zero to fifteen => C1);
+    S26 : severity_level_vector_st:= (zero to fifteen => C4);
+    S27 : integer_vector_st:= (zero to fifteen => C5);
+    S28 : real_vector_st:= (zero to fifteen => C6);
+    S29 : time_vector_st:= (zero to fifteen => C7);
+    S30 : natural_vector_st:= (zero to fifteen => C8);
+    S31 : positive_vector_st:= (zero to fifteen => C9)
+    );
+END c01s01b01x01p05n02i00753ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00753arch OF c01s01b01x01p05n02i00753ent IS
+
+BEGIN
+  assert (S1(0) = C1) report " error in initializing S1" severity error;
+  assert (S2(0) = C4) report " error in initializing S2" severity error;
+  assert (S3(0) = C5) report " error in initializing S3" severity error;
+  assert (S4(0) = C6) report " error in initializing S4" severity error;
+  assert (S5(0) = C7) report " error in initializing S5" severity error;
+  assert (S6(0) = C8) report " error in initializing S6" severity error;
+  assert (S7(0) = C9) report " error in initializing S7" severity error;
+  assert (S8(0) = C1) report " error in initializing S8" severity error;
+  assert (S9(0) = C4) report " error in initializing S9" severity error;
+  assert (S10(0) = C5) report " error in initializing S10" severity error;
+  assert (S11(0) = C6) report " error in initializing S11" severity error;
+  assert (S12(0) = C7) report " error in initializing S12" severity error;
+  assert (S13(0) = C8) report " error in initializing S13" severity error;
+  assert (S14(0) = C9) report " error in initializing S14" severity error;
+  assert (S15(0)(0) = C1) report " error in initializing S15" severity error;
+  assert (S16(0)(0) = C4) report " error in initializing S16" severity error;
+  assert (S17(0)(0) = C5) report " error in initializing S17" severity error;
+  assert (S18(0)(0) = C6) report " error in initializing S18" severity error;
+  assert (S19(0)(0) = C7) report " error in initializing S19" severity error;
+  assert (S20(0)(0) = C8) report " error in initializing S20" severity error;
+  assert (S21(0)(0) = C9) report " error in initializing S21" severity error;
+  assert (S22.a = C1) report " error in initializing S21" severity error;
+  assert (S22.b = C2) report " error in initializing S21" severity error;
+  assert (S22.c = C3) report " error in initializing S21" severity error;
+  assert (S22.d = C4) report " error in initializing S21" severity error;
+  assert (S22.e = C5) report " error in initializing S21" severity error;
+  assert (S22.f = C6) report " error in initializing S21" severity error;
+  assert (S22.g = C7) report " error in initializing S21" severity error;
+  assert (S22.h = C8) report " error in initializing S21" severity error;
+  assert (S22.i = C9) report " error in initializing S21" severity error;
+  assert (S22.j = C10) report " error in initializing S21" severity error;
+  assert (S22.k = C11) report " error in initializing S21" severity error;
+  assert (S25(0) = C1) report " error in initializing S25" severity error;
+  assert (S26(0) = C4) report " error in initializing S26" severity error;
+  assert (S27(0) = C5) report " error in initializing S27" severity error;
+  assert (S28(0) = C6) report " error in initializing S28" severity error;
+  assert (S29(0) = C7) report " error in initializing S29" severity error;
+  assert (S30(0) = C8) report " error in initializing S30" severity error;
+  assert (S31(0) = C9) report " error in initializing S31" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(    (S1(0) = C1)    and 
+                   (S2(0) = C4)    and 
+                   (S3(0) = C5)    and 
+                   (S4(0) = C6)    and 
+                   (S5(0) = C7)    and 
+                   (S6(0) = C8)    and 
+                   (S7(0) = C9)    and 
+                   (S8(0) = C1)    and 
+                   (S9(0) = C4)    and 
+                   (S10(0) = C5)    and 
+                   (S11(0) = C6)    and 
+                   (S12(0) = C7)    and 
+                   (S13(0) = C8)    and 
+                   (S14(0) = C9)    and 
+                   (S15(0)(0) = C1) and 
+                   (S16(0)(0) = C4) and 
+                   (S17(0)(0) = C5) and 
+                   (S18(0)(0) = C6) and 
+                   (S19(0)(0) = C7) and 
+                   (S20(0)(0) = C8) and 
+                   (S21(0)(0) = C9) and 
+                   (S22.a = C1)    and 
+                   (S22.b = C2)    and 
+                   (S22.c = C3)    and 
+                   (S22.d = C4)    and 
+                   (S22.e = C5)    and 
+                   (S22.f = C6)    and 
+                   (S22.g = C7)    and 
+                   (S22.h = C8)    and 
+                   (S22.i = C9)    and 
+                   (S22.j = C10)    and 
+                   (S22.k = C11)    and 
+                   (S25(0) = C1)    and 
+                   (S26(0) = C4)    and 
+                   (S27(0) = C5)    and 
+                   (S28(0) = C6)    and 
+                   (S29(0) = C7)    and 
+                   (S30(0) = C8)    and 
+                   (S31(0) = C9)    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00753"
+      severity NOTE;
+    assert (    (S1(0) = C1)    and 
+                (S2(0) = C4)    and 
+                (S3(0) = C5)    and 
+                (S4(0) = C6)    and 
+                (S5(0) = C7)    and 
+                (S6(0) = C8)    and 
+                (S7(0) = C9)    and 
+                (S8(0) = C1)    and 
+                (S9(0) = C4)    and 
+                (S10(0) = C5)    and 
+                (S11(0) = C6)    and 
+                (S12(0) = C7)    and 
+                (S13(0) = C8)    and 
+                (S14(0) = C9)    and 
+                (S15(0)(0) = C1) and 
+                (S16(0)(0) = C4) and 
+                (S17(0)(0) = C5) and 
+                (S18(0)(0) = C6) and 
+                (S19(0)(0) = C7) and 
+                (S20(0)(0) = C8) and 
+                (S21(0)(0) = C9) and 
+                (S22.a = C1)    and 
+                (S22.b = C2)    and 
+                (S22.c = C3)    and 
+                (S22.d = C4)    and 
+                (S22.e = C5)    and 
+                (S22.f = C6)    and 
+                (S22.g = C7)    and 
+                (S22.h = C8)    and 
+                (S22.i = C9)    and 
+                (S22.j = C10)    and 
+                (S22.k = C11)    and 
+                (S25(0) = C1)    and 
+                (S26(0) = C4)    and 
+                (S27(0) = C5)    and 
+                (S28(0) = C6)    and 
+                (S29(0) = C7)    and 
+                (S30(0) = C8)    and 
+                (S31(0) = C9)    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00753 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00753arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd
new file mode 100644
index 0000000..5cb4386
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd
@@ -0,0 +1,1025 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc754.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00754pkg is
+  subtype hi_to_low_range    is integer range 0 to 7;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  type boolean_cons_vectorofvector       is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  type record_array_new is record
+                             a:boolean_vector(0 to 15);
+                             b:severity_level_vector(0 to 15);
+                             c:integer_vector(0 to 15);
+                             d:real_vector(0 to 15);
+                             e:time_vector(0 to 15);
+                             f:natural_vector(0 to 15);
+                             g:positive_vector(0 to 15);
+                           end record;
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range    is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range    is integer_vector(hi_to_low_range);
+  subtype real_vector_range       is real_vector(hi_to_low_range);
+  subtype time_vector_range       is time_vector(hi_to_low_range);
+  subtype natural_vector_range    is natural_vector(hi_to_low_range);
+  subtype positive_vector_range    is positive_vector(hi_to_low_range);
+  type array_rec_std       is array (integer range <>) of record_std_package;
+  type array_rec_cons       is array (integer range <>) of record_cons_array;
+  type array_rec_rec       is array (integer range <>) of record_of_records;
+  subtype array_rec_std_st    is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st    is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st    is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(0 to 7);
+                                    b: array_rec_cons(0 to 7);
+                                    c: array_rec_rec(0 to 7);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(0 to 7) of bit;
+  
+  subtype word is bit_vector(0 to 15);                                 --constrained array
+  
+  constant size :integer := 7;
+  
+  type primary_memory is array(0 to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range 1 to 10;
+  
+  constant C1    : boolean := true;
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note;
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C10    : string := "shishir";
+  constant C11    : bit_vector := B"0011";
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (1,2,3,4);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (1,2,3,4);
+  constant C18    : positive_vector := (1,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+
+end c01s01b01x01p05n02i00754pkg;
+
+
+use work.c01s01b01x01p05n02i00754pkg.all;
+ENTITY c01s01b01x01p05n02i00754ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+  port(
+    S1    : boolean_vector(zero to fifteen);
+    S2    : severity_level_vector(zero to fifteen);
+    S3    : integer_vector(zero to fifteen);
+    S4    : real_vector(zero to fifteen);
+    S5    : time_vector (zero to fifteen);
+    S6    : natural_vector(zero to fifteen);
+    S7    : positive_vector(zero to fifteen);
+    S8    : boolean_cons_vector;
+    S9    : severity_level_cons_vector ;
+    S10    : integer_cons_vector;
+    S11    : real_cons_vector;
+    S12    : time_cons_vector ;
+    S13    : natural_cons_vector ;
+    S14    : positive_cons_vector ;
+    S15    : boolean_cons_vectorofvector;
+    S16    : severity_level_cons_vectorofvector;
+    S17    : integer_cons_vectorofvector;
+    S18    : real_cons_vectorofvector;
+    S19    : time_cons_vectorofvector;
+    S20    : natural_cons_vectorofvector;
+    S21    : positive_cons_vectorofvector;
+    S22    : record_std_package;
+    S23    : record_cons_array;
+    S24    : record_cons_arrayofarray ;
+    S25    : boolean_vector_st;
+    S26    : severity_level_vector_st;
+    S27    : integer_vector_st;
+    S28    : real_vector_st;
+    S29    : time_vector_st;
+    S30    : natural_vector_st;
+    S31    : positive_vector_st;
+    S32    : record_array_st;
+    S33    : record_array_st;
+    S34   : record_array_new;
+    S35    : record_of_records;
+    S36    : byte;
+    S37    : word;
+    S38    : current_vector(zero to three);
+    S39    : resistance_vector(zero to three);
+    S40    : delay;
+    S41   : boolean_vector_range;
+    S42   : severity_level_vector_range ;
+    S43   : integer_vector_range ;
+    S44   : real_vector_range ;
+    S45   : time_vector_range ;
+    S46   : natural_vector_range ;
+    S47   : positive_vector_range ;
+    S48   : array_rec_std(zero to seven);
+    S49   : array_rec_cons(zero to seven);
+    S50   : array_rec_rec(zero to seven);
+    S51   : record_of_arr_of_record
+    );
+END c01s01b01x01p05n02i00754ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00754arch OF c01s01b01x01p05n02i00754ent IS
+
+BEGIN
+  assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+  assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+  assert (S9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+  assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+  assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+  assert (S12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+  assert (S13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+  assert (S14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+  assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+  assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+  assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+  assert (S26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+  assert (S27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+  assert (S28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+  assert (S29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+  assert (S30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+  assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+  assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S36'left = 0) report " byte error in the left generic value" severity  error;
+  assert (S37'left = 0) report " word error in the left generic value" severity  error;
+  assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+  assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (S40'left = 1) report " delay error in the left generic value" severity  error;
+  assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+  assert (S42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+  assert (S43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+  assert (S44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+  assert (S45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+  assert (S46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+  assert (S47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+  assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+  assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+  assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+  assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  
+  assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+  assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+  assert (S9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+  assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+  assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+  assert (S12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+  assert (S13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+  assert (S14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+  assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+  assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+  assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+  assert (S26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+  assert (S27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+  assert (S28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+  assert (S29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+  assert (S30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+  assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+  assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S36'right = 7) report " byte error in the right generic value" severity  error;
+  assert (S37'right = 15) report " word error in the right generic value" severity  error;
+  assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+  assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (S40'right = 1) report " delay error in the right generic value" severity  error;
+  assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+  assert (S42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+  assert (S43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+  assert (S44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+  assert (S45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+  assert (S46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+  assert (S47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+  assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+  assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+  assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+  assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+  assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+  assert (S9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+  assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+  assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+  assert (S12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+  assert (S13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+  assert (S14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+  assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+  assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+  assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+  assert (S26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+  assert (S27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+  assert (S28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+  assert (S29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+  assert (S30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+  assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+  assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S36'length = 8) report " byte error in the length generic value" severity  error;
+  assert (S37'length = 16) report " word error in the length generic value" severity  error;
+  assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+  assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (S40'length = 1) report " delay error in the length generic value" severity  error;
+  assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+  assert (S42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+  assert (S43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+  assert (S44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+  assert (S45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+  assert (S46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+  assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+  assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+  assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert   NOT(    (S1'left = 0)    and 
+                     (S2'left = 0)    and 
+                     (S3'left = 0)    and 
+                     (S4'left = 0)    and 
+                     (S5'left = 0)    and 
+                     (S6'left = 0)    and 
+                     (S7'left = 0)    and 
+                     (S8'left = 15) and 
+                     (S9'left = 15) and 
+                     (S10'left = 15) and 
+                     (S11'left = 15) and 
+                     (S12'left = 15) and 
+                     (S13'left = 15) and 
+                     (S14'left = 15) and 
+                     (S15'left = 0) and 
+                     (S16'left = 0) and 
+                     (S17'left = 0) and 
+                     (S18'left = 0) and 
+                     (S19'left = 0) and 
+                     (S20'left = 0) and 
+                     (S21'left = 0) and 
+                     (S22.j'left = 1) and 
+                     (S22.k'left = 0) and 
+                     (S23.a'left = 15) and 
+                     (S23.b'left = 15) and 
+                     (S23.c'left = 15) and 
+                     (S23.d'left = 15) and 
+                     (S23.e'left = 15) and 
+                     (S23.f'left = 15) and 
+                     (S23.g'left = 15) and 
+                     (S24.a'left = 0) and 
+                     (S24.b'left = 0) and 
+                     (S24.c'left = 0) and 
+                     (S24.d'left = 0) and 
+                     (S24.e'left = 0) and 
+                     (S24.f'left = 0) and 
+                     (S24.g'left = 0) and 
+                     (S25'left = 0) and 
+                     (S26'left = 0) and 
+                     (S27'left = 0) and 
+                     (S28'left = 0) and 
+                     (S29'left = 0) and 
+                     (S30'left = 0) and 
+                     (S31'left = 0) and 
+                     (S32.a'left = 0) and 
+                     (S32.b'left = 0) and 
+                     (S32.c'left = 0) and 
+                     (S32.d'left = 0) and 
+                     (S32.e'left = 0) and 
+                     (S32.f'left = 0) and 
+                     (S32.g'left = 0) and 
+                     (S34.a'left = 0) and 
+                     (S34.b'left = 0) and 
+                     (S34.c'left = 0) and 
+                     (S34.d'left = 0) and 
+                     (S34.e'left = 0) and 
+                     (S34.f'left = 0) and 
+                     (S34.g'left = 0) and 
+                     (S36'left = 0) and 
+                     (S37'left = 0) and 
+                     (S38'left = 0) and 
+                     (S39'left = 0) and 
+--          (S40'left = 1) and 
+                     (S42'left = 0) and 
+                     (S43'left = 0) and 
+                     (S44'left = 0) and 
+                     (S45'left = 0) and 
+                     (S46'left = 0) and 
+                     (S47'left = 0) and 
+                     (S48'left = 0) and 
+                     (S49'left = 0) and 
+                     (S50'left = 0) and 
+                     (S51.a'left = 0) and 
+                     (S51.b'left = 0) and 
+                     (S51.c'left = 0) and 
+                     (S1'right = 15) and 
+                     (S2'right = 15) and 
+                     (S3'right = 15) and 
+                     (S4'right = 15) and 
+                     (S5'right = 15) and 
+                     (S6'right = 15) and 
+                     (S7'right = 15) and 
+                     (S8'right = 0) and 
+                     (S9'right = 0) and 
+                     (S10'right = 0)and 
+                     (S11'right = 0) and 
+                     (S12'right = 0) and 
+                     (S13'right = 0) and 
+                     (S14'right = 0) and 
+                     (S15'right = 15) and 
+                     (S16'right = 15) and 
+                     (S17'right = 15) and 
+                     (S18'right = 15) and 
+                     (S19'right = 15) and 
+                     (S20'right = 15) and 
+                     (S21'right = 15) and 
+                     (S22.j'right = 7) and 
+                     (S22.k'right = 3) and 
+                     (S23.a'right = 0) and 
+                     (S23.b'right = 0) and 
+                     (S23.c'right = 0) and 
+                     (S23.d'right = 0) and 
+                     (S23.e'right = 0) and 
+                     (S23.f'right = 0) and 
+                     (S23.g'right = 0) and 
+                     (S24.a'right = 15) and 
+                     (S24.b'right = 15) and 
+                     (S24.c'right = 15) and 
+                     (S24.d'right = 15) and 
+                     (S24.e'right = 15) and 
+                     (S24.f'right = 15) and 
+                     (S24.g'right = 15) and 
+                     (S25'right = 15) and 
+                     (S26'right = 15) and 
+                     (S27'right = 15) and 
+                     (S28'right = 15) and 
+                     (S29'right = 15) and 
+                     (S30'right = 15) and 
+                     (S31'right = 15) and 
+                     (S32.a'right = 15) and 
+                     (S32.b'right = 15) and 
+                     (S32.c'right = 15) and 
+                     (S32.d'right = 15) and 
+                     (S32.e'right = 15) and 
+                     (S32.f'right = 15) and 
+                     (S32.g'right = 15) and 
+                     (S34.a'right = 15) and 
+                     (S34.b'right = 15) and 
+                     (S34.c'right = 15) and 
+                     (S34.d'right = 15) and 
+                     (S34.e'right = 15) and 
+                     (S34.f'right = 15) and 
+                     (S34.g'right = 15) and 
+                     (S36'right = 7) and 
+                     (S37'right = 15) and  
+                     (S38'right = 3) and 
+                     (S39'right = 3) and 
+--          (S40'right = 1) and 
+                     (S41'right = 7) and 
+                     (S42'right = 7) and 
+                     (S43'right = 7) and 
+                     (S44'right = 7) and 
+                     (S45'right = 7) and 
+                     (S46'right = 7) and 
+                     (S47'right = 7) and 
+                     (S48'right = 7) and 
+                     (S49'right = 7) and 
+                     (S50'right = 7) and 
+                     (S51.a'right = 7) and 
+                     (S51.b'right = 7) and 
+                     (S51.c'right = 7) and 
+                     (S1'length = 16) and 
+                     (S2'length = 16) and 
+                     (S3'length = 16) and 
+                     (S4'length = 16) and 
+                     (S5'length = 16) and 
+                     (S6'length = 16) and 
+                     (S7'length = 16) and 
+                     (S8'length = 16) and 
+                     (S9'length = 16) and 
+                     (S10'length = 16) and 
+                     (S11'length = 16) and 
+                     (S12'length = 16) and 
+                     (S13'length = 16) and 
+                     (S14'length = 16) and 
+                     (S15'length = 16) and 
+                     (S16'length = 16) and 
+                     (S17'length = 16) and 
+                     (S18'length = 16) and 
+                     (S19'length = 16) and 
+                     (S20'length = 16) and 
+                     (S21'length = 16) and 
+                     (S22.j'length = 7)and 
+                     (S22.k'length = 4) and 
+                     (S23.a'length = 16) and 
+                     (S23.b'length = 16) and 
+                     (S23.c'length = 16) and 
+                     (S23.d'length = 16) and 
+                     (S23.e'length = 16) and 
+                     (S23.f'length = 16) and 
+                     (S23.g'length = 16) and 
+                     (S24.a'length = 16) and 
+                     (S24.b'length = 16) and 
+                     (S24.c'length = 16) and 
+                     (S24.d'length = 16) and 
+                     (S24.e'length = 16) and 
+                     (S24.f'length = 16) and 
+                     (S24.g'length = 16) and 
+                     (S25'length = 16) and 
+                     (S26'length = 16) and 
+                     (S27'length = 16) and 
+                     (S28'length = 16) and 
+                     (S29'length = 16) and 
+                     (S30'length = 16) and 
+                     (S31'length = 16) and 
+                     (S32.a'length = 16) and 
+                     (S32.b'length = 16) and 
+                     (S32.c'length = 16) and 
+                     (S32.d'length = 16) and 
+                     (S32.e'length = 16) and 
+                     (S32.f'length = 16) and 
+                     (S32.g'length = 16) and 
+                     (S34.a'length = 16) and 
+                     (S34.b'length = 16) and 
+                     (S34.c'length = 16) and 
+                     (S34.d'length = 16) and 
+                     (S34.e'length = 16) and 
+                     (S34.f'length = 16) and 
+                     (S34.g'length = 16) and 
+                     (S36'length = 8) and 
+                     (S37'length = 16) and 
+                     (S38'length = 4) and 
+                     (S39'length = 4) and 
+--          (S40'length = 1) and 
+                     (S41'length = 8) and 
+                     (S42'length = 8) and 
+                     (S43'length = 8) and 
+                     (S44'length = 8) and 
+                     (S45'length = 8) and 
+                     (S46'length = 8) and 
+                     (S48'length = 8) and 
+                     (S48'length = 8) and 
+                     (S49'length = 8) and 
+                     (S50'length = 8) and 
+                     (S51.a'length = 8) and 
+                     (S51.b'length = 8) and 
+                     (S51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00754"
+      severity NOTE;
+    assert   ((S1'left = 0)    and 
+              (S2'left = 0)    and 
+              (S3'left = 0)    and 
+              (S4'left = 0)    and 
+              (S5'left = 0)    and 
+              (S6'left = 0)    and 
+              (S7'left = 0)    and 
+              (S8'left = 15) and 
+              (S9'left = 15) and 
+              (S10'left = 15) and 
+              (S11'left = 15) and 
+              (S12'left = 15) and 
+              (S13'left = 15) and 
+              (S14'left = 15) and 
+              (S15'left = 0) and 
+              (S16'left = 0) and 
+              (S17'left = 0) and 
+              (S18'left = 0) and 
+              (S19'left = 0) and 
+              (S20'left = 0) and 
+              (S21'left = 0) and 
+              (S22.j'left = 1) and 
+              (S22.k'left = 0) and 
+              (S23.a'left = 15) and 
+              (S23.b'left = 15) and 
+              (S23.c'left = 15) and 
+              (S23.d'left = 15) and 
+              (S23.e'left = 15) and 
+              (S23.f'left = 15) and 
+              (S23.g'left = 15) and 
+              (S24.a'left = 0) and 
+              (S24.b'left = 0) and 
+              (S24.c'left = 0) and 
+              (S24.d'left = 0) and 
+              (S24.e'left = 0) and 
+              (S24.f'left = 0) and 
+              (S24.g'left = 0) and 
+              (S25'left = 0) and 
+              (S26'left = 0) and 
+              (S27'left = 0) and 
+              (S28'left = 0) and 
+              (S29'left = 0) and 
+              (S30'left = 0) and 
+              (S31'left = 0) and 
+              (S32.a'left = 0) and 
+              (S32.b'left = 0) and 
+              (S32.c'left = 0) and 
+              (S32.d'left = 0) and 
+              (S32.e'left = 0) and 
+              (S32.f'left = 0) and 
+              (S32.g'left = 0) and 
+              (S34.a'left = 0) and 
+              (S34.b'left = 0) and 
+              (S34.c'left = 0) and 
+              (S34.d'left = 0) and 
+              (S34.e'left = 0) and 
+              (S34.f'left = 0) and 
+              (S34.g'left = 0) and 
+              (S36'left = 0) and 
+              (S37'left = 0) and 
+              (S38'left = 0) and 
+              (S39'left = 0) and 
+--          (S40'left = 1) and 
+              (S42'left = 0) and 
+              (S43'left = 0) and 
+              (S44'left = 0) and 
+              (S45'left = 0) and 
+              (S46'left = 0) and 
+              (S47'left = 0) and 
+              (S48'left = 0) and 
+              (S49'left = 0) and 
+              (S50'left = 0) and 
+              (S51.a'left = 0) and 
+              (S51.b'left = 0) and 
+              (S51.c'left = 0) and 
+              (S1'right = 15) and 
+              (S2'right = 15) and 
+              (S3'right = 15) and 
+              (S4'right = 15) and 
+              (S5'right = 15) and 
+              (S6'right = 15) and 
+              (S7'right = 15) and 
+              (S8'right = 0) and 
+              (S9'right = 0) and 
+              (S10'right = 0)and 
+              (S11'right = 0) and 
+              (S12'right = 0) and 
+              (S13'right = 0) and 
+              (S14'right = 0) and 
+              (S15'right = 15) and 
+              (S16'right = 15) and 
+              (S17'right = 15) and 
+              (S18'right = 15) and 
+              (S19'right = 15) and 
+              (S20'right = 15) and 
+              (S21'right = 15) and 
+              (S22.j'right = 7) and 
+              (S22.k'right = 3) and 
+              (S23.a'right = 0) and 
+              (S23.b'right = 0) and 
+              (S23.c'right = 0) and 
+              (S23.d'right = 0) and 
+              (S23.e'right = 0) and 
+              (S23.f'right = 0) and 
+              (S23.g'right = 0) and 
+              (S24.a'right = 15) and 
+              (S24.b'right = 15) and 
+              (S24.c'right = 15) and 
+              (S24.d'right = 15) and 
+              (S24.e'right = 15) and 
+              (S24.f'right = 15) and 
+              (S24.g'right = 15) and 
+              (S25'right = 15) and 
+              (S26'right = 15) and 
+              (S27'right = 15) and 
+              (S28'right = 15) and 
+              (S29'right = 15) and 
+              (S30'right = 15) and 
+              (S31'right = 15) and 
+              (S32.a'right = 15) and 
+              (S32.b'right = 15) and 
+              (S32.c'right = 15) and 
+              (S32.d'right = 15) and 
+              (S32.e'right = 15) and 
+              (S32.f'right = 15) and 
+              (S32.g'right = 15) and 
+              (S34.a'right = 15) and 
+              (S34.b'right = 15) and 
+              (S34.c'right = 15) and 
+              (S34.d'right = 15) and 
+              (S34.e'right = 15) and 
+              (S34.f'right = 15) and 
+              (S34.g'right = 15) and 
+              (S36'right = 7) and 
+              (S37'right = 15) and  
+              (S38'right = 3) and 
+              (S39'right = 3) and 
+--          (S40'right = 1) and 
+              (S41'right = 7) and 
+              (S42'right = 7) and 
+              (S43'right = 7) and 
+              (S44'right = 7) and 
+              (S45'right = 7) and 
+              (S46'right = 7) and 
+              (S47'right = 7) and 
+              (S48'right = 7) and 
+              (S49'right = 7) and 
+              (S50'right = 7) and 
+              (S51.a'right = 7) and 
+              (S51.b'right = 7) and 
+              (S51.c'right = 7) and 
+              (S1'length = 16) and 
+              (S2'length = 16) and 
+              (S3'length = 16) and 
+              (S4'length = 16) and 
+              (S5'length = 16) and 
+              (S6'length = 16) and 
+              (S7'length = 16) and 
+              (S8'length = 16) and 
+              (S9'length = 16) and 
+              (S10'length = 16) and 
+              (S11'length = 16) and 
+              (S12'length = 16) and 
+              (S13'length = 16) and 
+              (S14'length = 16) and 
+              (S15'length = 16) and 
+              (S16'length = 16) and 
+              (S17'length = 16) and 
+              (S18'length = 16) and 
+              (S19'length = 16) and 
+              (S20'length = 16) and 
+              (S21'length = 16) and 
+              (S22.j'length = 7)and 
+              (S22.k'length = 4) and 
+              (S23.a'length = 16) and 
+              (S23.b'length = 16) and 
+              (S23.c'length = 16) and 
+              (S23.d'length = 16) and 
+              (S23.e'length = 16) and 
+              (S23.f'length = 16) and 
+              (S23.g'length = 16) and 
+              (S24.a'length = 16) and 
+              (S24.b'length = 16) and 
+              (S24.c'length = 16) and 
+              (S24.d'length = 16) and 
+              (S24.e'length = 16) and 
+              (S24.f'length = 16) and 
+              (S24.g'length = 16) and 
+              (S25'length = 16) and 
+              (S26'length = 16) and 
+              (S27'length = 16) and 
+              (S28'length = 16) and 
+              (S29'length = 16) and 
+              (S30'length = 16) and 
+              (S31'length = 16) and 
+              (S32.a'length = 16) and 
+              (S32.b'length = 16) and 
+              (S32.c'length = 16) and 
+              (S32.d'length = 16) and 
+              (S32.e'length = 16) and 
+              (S32.f'length = 16) and 
+              (S32.g'length = 16) and 
+              (S34.a'length = 16) and 
+              (S34.b'length = 16) and 
+              (S34.c'length = 16) and 
+              (S34.d'length = 16) and 
+              (S34.e'length = 16) and 
+              (S34.f'length = 16) and 
+              (S34.g'length = 16) and 
+              (S36'length = 8) and 
+              (S37'length = 16) and 
+              (S38'length = 4) and 
+              (S39'length = 4) and 
+--          (S40'length = 1) and 
+              (S41'length = 8) and 
+              (S42'length = 8) and 
+              (S43'length = 8) and 
+              (S44'length = 8) and 
+              (S45'length = 8) and 
+              (S46'length = 8) and 
+              (S48'length = 8) and 
+              (S48'length = 8) and 
+              (S49'length = 8) and 
+              (S50'length = 8) and 
+              (S51.a'length = 8) and 
+              (S51.b'length = 8) and 
+              (S51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00754 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00754arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd
new file mode 100644
index 0000000..5079776
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd
@@ -0,0 +1,1018 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc755.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00755ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00755ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00755arch OF c01s01b01x01p05n02i00755ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (one,two,three,four);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (one,2,3,4);
+  constant C18    : positive_vector := (one,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+  
+  signal S1    : boolean_vector(zero to fifteen);
+  signal S2    : severity_level_vector(zero to fifteen);
+  signal S3    : integer_vector(zero to fifteen);
+  signal S4    : real_vector(zero to fifteen);
+  signal S5    : time_vector (zero to fifteen);
+  signal S6    : natural_vector(zero to fifteen);
+  signal S7    : positive_vector(zero to fifteen);
+  signal S8    : boolean_cons_vector;
+  signal S9    : severity_level_cons_vector ;
+  signal S10    : integer_cons_vector;
+  signal S11    : real_cons_vector;
+  signal S12    : time_cons_vector ;
+  signal S13    : natural_cons_vector ;
+  signal S14    : positive_cons_vector ;
+  signal S15    : boolean_cons_vectorofvector;
+  signal S16    : severity_level_cons_vectorofvector;
+  signal S17    : integer_cons_vectorofvector;
+  signal S18    : real_cons_vectorofvector;
+  signal S19    : time_cons_vectorofvector;
+  signal S20    : natural_cons_vectorofvector;
+  signal S21    : positive_cons_vectorofvector;
+  signal S22    : record_std_package;
+  signal S23    : record_cons_array;
+  signal S24    : record_cons_arrayofarray ;
+  signal S25    : boolean_vector_st;
+  signal S26    : severity_level_vector_st;
+  signal S27    : integer_vector_st;
+  signal S28    : real_vector_st;
+  signal S29    : time_vector_st;
+  signal S30    : natural_vector_st;
+  signal S31    : positive_vector_st;
+  signal S32    : record_array_st;
+  signal S33    : record_array_st;
+  signal S34   : record_array_new;
+  signal S35    : record_of_records;
+  signal S36    : byte;
+  signal S37    : word;
+  signal S38    : current_vector(zero to three);
+  signal S39    : resistance_vector(zero to three);
+  signal S40    : delay;
+  signal S41   : boolean_vector_range;
+  signal S42   : severity_level_vector_range ;
+  signal S43   : integer_vector_range ;
+  signal S44   : real_vector_range ;
+  signal S45   : time_vector_range ;
+  signal S46   : natural_vector_range ;
+  signal S47   : positive_vector_range ;
+  signal S48   : array_rec_std(zero to seven);
+  signal S49   : array_rec_cons(zero to seven);
+  signal S50   : array_rec_rec(zero to seven);
+  signal S51   : record_of_arr_of_record;
+
+BEGIN
+  assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+  assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+  assert (S9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+  assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+  assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+  assert (S12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+  assert (S13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+  assert (S14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+  assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+  assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+  assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+  assert (S26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+  assert (S27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+  assert (S28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+  assert (S29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+  assert (S30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+  assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+  assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S36'left = 0) report " byte error in the left generic value" severity  error;
+  assert (S37'left = 0) report " word error in the left generic value" severity  error;
+  assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+  assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (S40'left = 1) report " delay error in the left generic value" severity  error;
+  assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+  assert (S42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+  assert (S43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+  assert (S44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+  assert (S45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+  assert (S46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+  assert (S47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+  assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+  assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+  assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+  assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  
+  assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+  assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+  assert (S9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+  assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+  assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+  assert (S12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+  assert (S13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+  assert (S14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+  assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+  assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+  assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+  assert (S26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+  assert (S27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+  assert (S28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+  assert (S29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+  assert (S30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+  assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+  assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S36'right = 7) report " byte error in the right generic value" severity  error;
+  assert (S37'right = 15) report " word error in the right generic value" severity  error;
+  assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+  assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (S40'right = 1) report " delay error in the right generic value" severity  error;
+  assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+  assert (S42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+  assert (S43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+  assert (S44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+  assert (S45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+  assert (S46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+  assert (S47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+  assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+  assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+  assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+  assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+  assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+  assert (S9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+  assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+  assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+  assert (S12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+  assert (S13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+  assert (S14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+  assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+  assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+  assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+  assert (S26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+  assert (S27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+  assert (S28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+  assert (S29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+  assert (S30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+  assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+  assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S36'length = 8) report " byte error in the length generic value" severity  error;
+  assert (S37'length = 16) report " word error in the length generic value" severity  error;
+  assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+  assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (S40'length = 1) report " delay error in the length generic value" severity  error;
+  assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+  assert (S42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+  assert (S43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+  assert (S44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+  assert (S45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+  assert (S46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+  assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+  assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+  assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert   NOT(    (S1'left = 0)    and 
+                     (S2'left = 0)    and 
+                     (S3'left = 0)    and 
+                     (S4'left = 0)    and 
+                     (S5'left = 0)    and 
+                     (S6'left = 0)    and 
+                     (S7'left = 0)    and 
+                     (S8'left = 15) and 
+                     (S9'left = 15) and 
+                     (S10'left = 15) and 
+                     (S11'left = 15) and 
+                     (S12'left = 15) and 
+                     (S13'left = 15) and 
+                     (S14'left = 15) and 
+                     (S15'left = 0) and 
+                     (S16'left = 0) and 
+                     (S17'left = 0) and 
+                     (S18'left = 0) and 
+                     (S19'left = 0) and 
+                     (S20'left = 0) and 
+                     (S21'left = 0) and 
+                     (S22.j'left = 1) and 
+                     (S22.k'left = 0) and 
+                     (S23.a'left = 15) and 
+                     (S23.b'left = 15) and 
+                     (S23.c'left = 15) and 
+                     (S23.d'left = 15) and 
+                     (S23.e'left = 15) and 
+                     (S23.f'left = 15) and 
+                     (S23.g'left = 15) and 
+                     (S24.a'left = 0) and 
+                     (S24.b'left = 0) and 
+                     (S24.c'left = 0) and 
+                     (S24.d'left = 0) and 
+                     (S24.e'left = 0) and 
+                     (S24.f'left = 0) and 
+                     (S24.g'left = 0) and 
+                     (S25'left = 0) and 
+                     (S26'left = 0) and 
+                     (S27'left = 0) and 
+                     (S28'left = 0) and 
+                     (S29'left = 0) and 
+                     (S30'left = 0) and 
+                     (S31'left = 0) and 
+                     (S32.a'left = 0) and 
+                     (S32.b'left = 0) and 
+                     (S32.c'left = 0) and 
+                     (S32.d'left = 0) and 
+                     (S32.e'left = 0) and 
+                     (S32.f'left = 0) and 
+                     (S32.g'left = 0) and 
+                     (S34.a'left = 0) and 
+                     (S34.b'left = 0) and 
+                     (S34.c'left = 0) and 
+                     (S34.d'left = 0) and 
+                     (S34.e'left = 0) and 
+                     (S34.f'left = 0) and 
+                     (S34.g'left = 0) and 
+                     (S36'left = 0) and 
+                     (S37'left = 0) and 
+                     (S38'left = 0) and 
+                     (S39'left = 0) and 
+--          (S40'left = 1) and 
+                     (S42'left = 0) and 
+                     (S43'left = 0) and 
+                     (S44'left = 0) and 
+                     (S45'left = 0) and 
+                     (S46'left = 0) and 
+                     (S47'left = 0) and 
+                     (S48'left = 0) and 
+                     (S49'left = 0) and 
+                     (S50'left = 0) and 
+                     (S51.a'left = 0) and 
+                     (S51.b'left = 0) and 
+                     (S51.c'left = 0) and 
+                     (S1'right = 15) and 
+                     (S2'right = 15) and 
+                     (S3'right = 15) and 
+                     (S4'right = 15) and 
+                     (S5'right = 15) and 
+                     (S6'right = 15) and 
+                     (S7'right = 15) and 
+                     (S8'right = 0) and 
+                     (S9'right = 0) and 
+                     (S10'right = 0)and 
+                     (S11'right = 0) and 
+                     (S12'right = 0) and 
+                     (S13'right = 0) and 
+                     (S14'right = 0) and 
+                     (S15'right = 15) and 
+                     (S16'right = 15) and 
+                     (S17'right = 15) and 
+                     (S18'right = 15) and 
+                     (S19'right = 15) and 
+                     (S20'right = 15) and 
+                     (S21'right = 15) and 
+                     (S22.j'right = 7) and 
+                     (S22.k'right = 3) and 
+                     (S23.a'right = 0) and 
+                     (S23.b'right = 0) and 
+                     (S23.c'right = 0) and 
+                     (S23.d'right = 0) and 
+                     (S23.e'right = 0) and 
+                     (S23.f'right = 0) and 
+                     (S23.g'right = 0) and 
+                     (S24.a'right = 15) and 
+                     (S24.b'right = 15) and 
+                     (S24.c'right = 15) and 
+                     (S24.d'right = 15) and 
+                     (S24.e'right = 15) and 
+                     (S24.f'right = 15) and 
+                     (S24.g'right = 15) and 
+                     (S25'right = 15) and 
+                     (S26'right = 15) and 
+                     (S27'right = 15) and 
+                     (S28'right = 15) and 
+                     (S29'right = 15) and 
+                     (S30'right = 15) and 
+                     (S31'right = 15) and 
+                     (S32.a'right = 15) and 
+                     (S32.b'right = 15) and 
+                     (S32.c'right = 15) and 
+                     (S32.d'right = 15) and 
+                     (S32.e'right = 15) and 
+                     (S32.f'right = 15) and 
+                     (S32.g'right = 15) and 
+                     (S34.a'right = 15) and 
+                     (S34.b'right = 15) and 
+                     (S34.c'right = 15) and 
+                     (S34.d'right = 15) and 
+                     (S34.e'right = 15) and 
+                     (S34.f'right = 15) and 
+                     (S34.g'right = 15) and 
+                     (S36'right = 7) and 
+                     (S37'right = 15) and  
+                     (S38'right = 3) and 
+                     (S39'right = 3) and 
+--          (S40'right = 1) and 
+                     (S41'right = 7) and 
+                     (S42'right = 7) and 
+                     (S43'right = 7) and 
+                     (S44'right = 7) and 
+                     (S45'right = 7) and 
+                     (S46'right = 7) and 
+                     (S47'right = 7) and 
+                     (S48'right = 7) and 
+                     (S49'right = 7) and 
+                     (S50'right = 7) and 
+                     (S51.a'right = 7) and 
+                     (S51.b'right = 7) and 
+                     (S51.c'right = 7) and 
+                     (S1'length = 16) and 
+                     (S2'length = 16) and 
+                     (S3'length = 16) and 
+                     (S4'length = 16) and 
+                     (S5'length = 16) and 
+                     (S6'length = 16) and 
+                     (S7'length = 16) and 
+                     (S8'length = 16) and 
+                     (S9'length = 16) and 
+                     (S10'length = 16) and 
+                     (S11'length = 16) and 
+                     (S12'length = 16) and 
+                     (S13'length = 16) and 
+                     (S14'length = 16) and 
+                     (S15'length = 16) and 
+                     (S16'length = 16) and 
+                     (S17'length = 16) and 
+                     (S18'length = 16) and 
+                     (S19'length = 16) and 
+                     (S20'length = 16) and 
+                     (S21'length = 16) and 
+                     (S22.j'length = 7)and 
+                     (S22.k'length = 4) and 
+                     (S23.a'length = 16) and 
+                     (S23.b'length = 16) and 
+                     (S23.c'length = 16) and 
+                     (S23.d'length = 16) and 
+                     (S23.e'length = 16) and 
+                     (S23.f'length = 16) and 
+                     (S23.g'length = 16) and 
+                     (S24.a'length = 16) and 
+                     (S24.b'length = 16) and 
+                     (S24.c'length = 16) and 
+                     (S24.d'length = 16) and 
+                     (S24.e'length = 16) and 
+                     (S24.f'length = 16) and 
+                     (S24.g'length = 16) and 
+                     (S25'length = 16) and 
+                     (S26'length = 16) and 
+                     (S27'length = 16) and 
+                     (S28'length = 16) and 
+                     (S29'length = 16) and 
+                     (S30'length = 16) and 
+                     (S31'length = 16) and 
+                     (S32.a'length = 16) and 
+                     (S32.b'length = 16) and 
+                     (S32.c'length = 16) and 
+                     (S32.d'length = 16) and 
+                     (S32.e'length = 16) and 
+                     (S32.f'length = 16) and 
+                     (S32.g'length = 16) and 
+                     (S34.a'length = 16) and 
+                     (S34.b'length = 16) and 
+                     (S34.c'length = 16) and 
+                     (S34.d'length = 16) and 
+                     (S34.e'length = 16) and 
+                     (S34.f'length = 16) and 
+                     (S34.g'length = 16) and 
+                     (S36'length = 8) and 
+                     (S37'length = 16) and 
+                     (S38'length = 4) and 
+                     (S39'length = 4) and 
+--          (S40'length = 1) and 
+                     (S41'length = 8) and 
+                     (S42'length = 8) and 
+                     (S43'length = 8) and 
+                     (S44'length = 8) and 
+                     (S45'length = 8) and 
+                     (S46'length = 8) and 
+                     (S48'length = 8) and 
+                     (S48'length = 8) and 
+                     (S49'length = 8) and 
+                     (S50'length = 8) and 
+                     (S51.a'length = 8) and 
+                     (S51.b'length = 8) and 
+                     (S51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00755"
+      severity NOTE;
+    assert   ((S1'left = 0)    and 
+              (S2'left = 0)    and 
+              (S3'left = 0)    and 
+              (S4'left = 0)    and 
+              (S5'left = 0)    and 
+              (S6'left = 0)    and 
+              (S7'left = 0)    and 
+              (S8'left = 15) and 
+              (S9'left = 15) and 
+              (S10'left = 15) and 
+              (S11'left = 15) and 
+              (S12'left = 15) and 
+              (S13'left = 15) and 
+              (S14'left = 15) and 
+              (S15'left = 0) and 
+              (S16'left = 0) and 
+              (S17'left = 0) and 
+              (S18'left = 0) and 
+              (S19'left = 0) and 
+              (S20'left = 0) and 
+              (S21'left = 0) and 
+              (S22.j'left = 1) and 
+              (S22.k'left = 0) and 
+              (S23.a'left = 15) and 
+              (S23.b'left = 15) and 
+              (S23.c'left = 15) and 
+              (S23.d'left = 15) and 
+              (S23.e'left = 15) and 
+              (S23.f'left = 15) and 
+              (S23.g'left = 15) and 
+              (S24.a'left = 0) and 
+              (S24.b'left = 0) and 
+              (S24.c'left = 0) and 
+              (S24.d'left = 0) and 
+              (S24.e'left = 0) and 
+              (S24.f'left = 0) and 
+              (S24.g'left = 0) and 
+              (S25'left = 0) and 
+              (S26'left = 0) and 
+              (S27'left = 0) and 
+              (S28'left = 0) and 
+              (S29'left = 0) and 
+              (S30'left = 0) and 
+              (S31'left = 0) and 
+              (S32.a'left = 0) and 
+              (S32.b'left = 0) and 
+              (S32.c'left = 0) and 
+              (S32.d'left = 0) and 
+              (S32.e'left = 0) and 
+              (S32.f'left = 0) and 
+              (S32.g'left = 0) and 
+              (S34.a'left = 0) and 
+              (S34.b'left = 0) and 
+              (S34.c'left = 0) and 
+              (S34.d'left = 0) and 
+              (S34.e'left = 0) and 
+              (S34.f'left = 0) and 
+              (S34.g'left = 0) and 
+              (S36'left = 0) and 
+              (S37'left = 0) and 
+              (S38'left = 0) and 
+              (S39'left = 0) and 
+--          (S40'left = 1) and 
+              (S42'left = 0) and 
+              (S43'left = 0) and 
+              (S44'left = 0) and 
+              (S45'left = 0) and 
+              (S46'left = 0) and 
+              (S47'left = 0) and 
+              (S48'left = 0) and 
+              (S49'left = 0) and 
+              (S50'left = 0) and 
+              (S51.a'left = 0) and 
+              (S51.b'left = 0) and 
+              (S51.c'left = 0) and 
+              (S1'right = 15) and 
+              (S2'right = 15) and 
+              (S3'right = 15) and 
+              (S4'right = 15) and 
+              (S5'right = 15) and 
+              (S6'right = 15) and 
+              (S7'right = 15) and 
+              (S8'right = 0) and 
+              (S9'right = 0) and 
+              (S10'right = 0)and 
+              (S11'right = 0) and 
+              (S12'right = 0) and 
+              (S13'right = 0) and 
+              (S14'right = 0) and 
+              (S15'right = 15) and 
+              (S16'right = 15) and 
+              (S17'right = 15) and 
+              (S18'right = 15) and 
+              (S19'right = 15) and 
+              (S20'right = 15) and 
+              (S21'right = 15) and 
+              (S22.j'right = 7) and 
+              (S22.k'right = 3) and 
+              (S23.a'right = 0) and 
+              (S23.b'right = 0) and 
+              (S23.c'right = 0) and 
+              (S23.d'right = 0) and 
+              (S23.e'right = 0) and 
+              (S23.f'right = 0) and 
+              (S23.g'right = 0) and 
+              (S24.a'right = 15) and 
+              (S24.b'right = 15) and 
+              (S24.c'right = 15) and 
+              (S24.d'right = 15) and 
+              (S24.e'right = 15) and 
+              (S24.f'right = 15) and 
+              (S24.g'right = 15) and 
+              (S25'right = 15) and 
+              (S26'right = 15) and 
+              (S27'right = 15) and 
+              (S28'right = 15) and 
+              (S29'right = 15) and 
+              (S30'right = 15) and 
+              (S31'right = 15) and 
+              (S32.a'right = 15) and 
+              (S32.b'right = 15) and 
+              (S32.c'right = 15) and 
+              (S32.d'right = 15) and 
+              (S32.e'right = 15) and 
+              (S32.f'right = 15) and 
+              (S32.g'right = 15) and 
+              (S34.a'right = 15) and 
+              (S34.b'right = 15) and 
+              (S34.c'right = 15) and 
+              (S34.d'right = 15) and 
+              (S34.e'right = 15) and 
+              (S34.f'right = 15) and 
+              (S34.g'right = 15) and 
+              (S36'right = 7) and 
+              (S37'right = 15) and  
+              (S38'right = 3) and 
+              (S39'right = 3) and 
+--          (S40'right = 1) and 
+              (S41'right = 7) and 
+              (S42'right = 7) and 
+              (S43'right = 7) and 
+              (S44'right = 7) and 
+              (S45'right = 7) and 
+              (S46'right = 7) and 
+              (S47'right = 7) and 
+              (S48'right = 7) and 
+              (S49'right = 7) and 
+              (S50'right = 7) and 
+              (S51.a'right = 7) and 
+              (S51.b'right = 7) and 
+              (S51.c'right = 7) and 
+              (S1'length = 16) and 
+              (S2'length = 16) and 
+              (S3'length = 16) and 
+              (S4'length = 16) and 
+              (S5'length = 16) and 
+              (S6'length = 16) and 
+              (S7'length = 16) and 
+              (S8'length = 16) and 
+              (S9'length = 16) and 
+              (S10'length = 16) and 
+              (S11'length = 16) and 
+              (S12'length = 16) and 
+              (S13'length = 16) and 
+              (S14'length = 16) and 
+              (S15'length = 16) and 
+              (S16'length = 16) and 
+              (S17'length = 16) and 
+              (S18'length = 16) and 
+              (S19'length = 16) and 
+              (S20'length = 16) and 
+              (S21'length = 16) and 
+              (S22.j'length = 7)and 
+              (S22.k'length = 4) and 
+              (S23.a'length = 16) and 
+              (S23.b'length = 16) and 
+              (S23.c'length = 16) and 
+              (S23.d'length = 16) and 
+              (S23.e'length = 16) and 
+              (S23.f'length = 16) and 
+              (S23.g'length = 16) and 
+              (S24.a'length = 16) and 
+              (S24.b'length = 16) and 
+              (S24.c'length = 16) and 
+              (S24.d'length = 16) and 
+              (S24.e'length = 16) and 
+              (S24.f'length = 16) and 
+              (S24.g'length = 16) and 
+              (S25'length = 16) and 
+              (S26'length = 16) and 
+              (S27'length = 16) and 
+              (S28'length = 16) and 
+              (S29'length = 16) and 
+              (S30'length = 16) and 
+              (S31'length = 16) and 
+              (S32.a'length = 16) and 
+              (S32.b'length = 16) and 
+              (S32.c'length = 16) and 
+              (S32.d'length = 16) and 
+              (S32.e'length = 16) and 
+              (S32.f'length = 16) and 
+              (S32.g'length = 16) and 
+              (S34.a'length = 16) and 
+              (S34.b'length = 16) and 
+              (S34.c'length = 16) and 
+              (S34.d'length = 16) and 
+              (S34.e'length = 16) and 
+              (S34.f'length = 16) and 
+              (S34.g'length = 16) and 
+              (S36'length = 8) and 
+              (S37'length = 16) and 
+              (S38'length = 4) and 
+              (S39'length = 4) and 
+--          (S40'length = 1) and 
+              (S41'length = 8) and 
+              (S42'length = 8) and 
+              (S43'length = 8) and 
+              (S44'length = 8) and 
+              (S45'length = 8) and 
+              (S46'length = 8) and 
+              (S48'length = 8) and 
+              (S48'length = 8) and 
+              (S49'length = 8) and 
+              (S50'length = 8) and 
+              (S51.a'length = 8) and 
+              (S51.b'length = 8) and 
+              (S51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00755 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00755arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd
new file mode 100644
index 0000000..c3c199c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd
@@ -0,0 +1,1018 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc756.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00756ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00756ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00756arch OF c01s01b01x01p05n02i00756ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (one,two,three,four);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (one,2,3,4);
+  constant C18    : positive_vector := (one,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+  
+BEGIN
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen);
+    variable V2    : severity_level_vector(zero to fifteen);
+    variable V3    : integer_vector(zero to fifteen);
+    variable V4    : real_vector(zero to fifteen);
+    variable V5    : time_vector (zero to fifteen);
+    variable V6    : natural_vector(zero to fifteen);
+    variable V7    : positive_vector(zero to fifteen);
+    variable V8    : boolean_cons_vector;
+    variable V9    : severity_level_cons_vector ;
+    variable V10    : integer_cons_vector;
+    variable V11    : real_cons_vector;
+    variable V12    : time_cons_vector ;
+    variable V13    : natural_cons_vector ;
+    variable V14    : positive_cons_vector ;
+    variable V15    : boolean_cons_vectorofvector;
+    variable V16    : severity_level_cons_vectorofvector;
+    variable V17    : integer_cons_vectorofvector;
+    variable V18    : real_cons_vectorofvector;
+    variable V19    : time_cons_vectorofvector;
+    variable V20    : natural_cons_vectorofvector;
+    variable V21    : positive_cons_vectorofvector;
+    variable V22    : record_std_package;
+    variable V23    : record_cons_array;
+    variable V24    : record_cons_arrayofarray ;
+    variable V25    : boolean_vector_st;
+    variable V26    : severity_level_vector_st;
+    variable V27    : integer_vector_st;
+    variable V28    : real_vector_st;
+    variable V29    : time_vector_st;
+    variable V30    : natural_vector_st;
+    variable V31    : positive_vector_st;
+    variable V32    : record_array_st;
+    variable V33    : record_array_st;
+    variable V34   : record_array_new;
+    variable V35    : record_of_records;
+    variable V36    : byte;
+    variable V37    : word;
+    variable V38    : current_vector(zero to three);
+    variable V39    : resistance_vector(zero to three);
+    variable V40    : delay;
+    variable V41   : boolean_vector_range;
+    variable V42   : severity_level_vector_range ;
+    variable V43   : integer_vector_range ;
+    variable V44   : real_vector_range ;
+    variable V45   : time_vector_range ;
+    variable V46   : natural_vector_range ;
+    variable V47   : positive_vector_range ;
+    variable V48   : array_rec_std(zero to seven);
+    variable V49   : array_rec_cons(zero to seven);
+    variable V50   : array_rec_rec(zero to seven);
+    variable V51   : record_of_arr_of_record;
+
+  BEGIN
+    assert (V1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+    assert (V6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+    assert (V9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+    assert (V10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+    assert (V11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+    assert (V12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+    assert (V13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+    assert (V14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+    assert (V15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+    assert (V22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+    assert (V23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+    assert (V26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+    assert (V27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+    assert (V28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+    assert (V29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+    assert (V30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+    assert (V31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+    assert (V32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V36'left = 0) report " byte error in the left generic value" severity  error;
+    assert (V37'left = 0) report " word error in the left generic value" severity  error;
+    assert (V38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+    assert (V39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (V40'left = 1) report " delay error in the left generic value" severity  error;
+    assert (V41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+    assert (V42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+    assert (V43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+    assert (V44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+    assert (V45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+    assert (V46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+    assert (V47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+    assert (V48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+    assert (V49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+    assert (V50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+    assert (V51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    assert (V51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    assert (V51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    
+    assert (V1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+    assert (V6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+    assert (V9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+    assert (V10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+    assert (V11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+    assert (V12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+    assert (V13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+    assert (V14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+    assert (V15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+    assert (V22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+    assert (V23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+    assert (V26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+    assert (V27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+    assert (V28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+    assert (V29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+    assert (V30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+    assert (V31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+    assert (V32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V36'right = 7) report " byte error in the right generic value" severity  error;
+    assert (V37'right = 15) report " word error in the right generic value" severity  error;
+    assert (V38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+    assert (V39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (V40'right = 1) report " delay error in the right generic value" severity  error;
+    assert (V41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+    assert (V42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+    assert (V43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+    assert (V44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+    assert (V45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+    assert (V46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+    assert (V47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+    assert (V48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+    assert (V49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+    assert (V50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+    assert (V51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+    assert (V6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+    assert (V9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+    assert (V10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+    assert (V11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+    assert (V12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+    assert (V13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+    assert (V14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+    assert (V15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+    assert (V22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+    assert (V23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+    assert (V26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+    assert (V27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+    assert (V28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+    assert (V29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+    assert (V30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+    assert (V31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+    assert (V32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V36'length = 8) report " byte error in the length generic value" severity  error;
+    assert (V37'length = 16) report " word error in the length generic value" severity  error;
+    assert (V38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+    assert (V39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (V40'length = 1) report " delay error in the length generic value" severity  error;
+    assert (V41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+    assert (V42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+    assert (V43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+    assert (V44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+    assert (V45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+    assert (V46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+    assert (V48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+    assert (V48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+    assert (V49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+    assert (V50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+    assert (V51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+    assert (V51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+    assert (V51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+
+    assert   NOT(    (V1'left = 0)    and 
+                     (V2'left = 0)    and 
+                     (V3'left = 0)    and 
+                     (V4'left = 0)    and 
+                     (V5'left = 0)    and 
+                     (V6'left = 0)    and 
+                     (V7'left = 0)    and 
+                     (V8'left = 15) and 
+                     (V9'left = 15) and 
+                     (V10'left = 15) and 
+                     (V11'left = 15) and 
+                     (V12'left = 15) and 
+                     (V13'left = 15) and 
+                     (V14'left = 15) and 
+                     (V15'left = 0) and 
+                     (V16'left = 0) and 
+                     (V17'left = 0) and 
+                     (V18'left = 0) and 
+                     (V19'left = 0) and 
+                     (V20'left = 0) and 
+                     (V21'left = 0) and 
+                     (V22.j'left = 1) and 
+                     (V22.k'left = 0) and 
+                     (V23.a'left = 15) and 
+                     (V23.b'left = 15) and 
+                     (V23.c'left = 15) and 
+                     (V23.d'left = 15) and 
+                     (V23.e'left = 15) and 
+                     (V23.f'left = 15) and 
+                     (V23.g'left = 15) and 
+                     (V24.a'left = 0) and 
+                     (V24.b'left = 0) and 
+                     (V24.c'left = 0) and 
+                     (V24.d'left = 0) and 
+                     (V24.e'left = 0) and 
+                     (V24.f'left = 0) and 
+                     (V24.g'left = 0) and 
+                     (V25'left = 0) and 
+                     (V26'left = 0) and 
+                     (V27'left = 0) and 
+                     (V28'left = 0) and 
+                     (V29'left = 0) and 
+                     (V30'left = 0) and 
+                     (V31'left = 0) and 
+                     (V32.a'left = 0) and 
+                     (V32.b'left = 0) and 
+                     (V32.c'left = 0) and 
+                     (V32.d'left = 0) and 
+                     (V32.e'left = 0) and 
+                     (V32.f'left = 0) and 
+                     (V32.g'left = 0) and 
+                     (V34.a'left = 0) and 
+                     (V34.b'left = 0) and 
+                     (V34.c'left = 0) and 
+                     (V34.d'left = 0) and 
+                     (V34.e'left = 0) and 
+                     (V34.f'left = 0) and 
+                     (V34.g'left = 0) and 
+                     (V36'left = 0) and 
+                     (V37'left = 0) and 
+                     (V38'left = 0) and 
+                     (V39'left = 0) and 
+--          (V40'left = 1) and 
+                     (V42'left = 0) and 
+                     (V43'left = 0) and 
+                     (V44'left = 0) and 
+                     (V45'left = 0) and 
+                     (V46'left = 0) and 
+                     (V47'left = 0) and 
+                     (V48'left = 0) and 
+                     (V49'left = 0) and 
+                     (V50'left = 0) and 
+                     (V51.a'left = 0) and 
+                     (V51.b'left = 0) and 
+                     (V51.c'left = 0) and 
+                     (V1'right = 15) and 
+                     (V2'right = 15) and 
+                     (V3'right = 15) and 
+                     (V4'right = 15) and 
+                     (V5'right = 15) and 
+                     (V6'right = 15) and 
+                     (V7'right = 15) and 
+                     (V8'right = 0) and 
+                     (V9'right = 0) and 
+                     (V10'right = 0)and 
+                     (V11'right = 0) and 
+                     (V12'right = 0) and 
+                     (V13'right = 0) and 
+                     (V14'right = 0) and 
+                     (V15'right = 15) and 
+                     (V16'right = 15) and 
+                     (V17'right = 15) and 
+                     (V18'right = 15) and 
+                     (V19'right = 15) and 
+                     (V20'right = 15) and 
+                     (V21'right = 15) and 
+                     (V22.j'right = 7) and 
+                     (V22.k'right = 3) and 
+                     (V23.a'right = 0) and 
+                     (V23.b'right = 0) and 
+                     (V23.c'right = 0) and 
+                     (V23.d'right = 0) and 
+                     (V23.e'right = 0) and 
+                     (V23.f'right = 0) and 
+                     (V23.g'right = 0) and 
+                     (V24.a'right = 15) and 
+                     (V24.b'right = 15) and 
+                     (V24.c'right = 15) and 
+                     (V24.d'right = 15) and 
+                     (V24.e'right = 15) and 
+                     (V24.f'right = 15) and 
+                     (V24.g'right = 15) and 
+                     (V25'right = 15) and 
+                     (V26'right = 15) and 
+                     (V27'right = 15) and 
+                     (V28'right = 15) and 
+                     (V29'right = 15) and 
+                     (V30'right = 15) and 
+                     (V31'right = 15) and 
+                     (V32.a'right = 15) and 
+                     (V32.b'right = 15) and 
+                     (V32.c'right = 15) and 
+                     (V32.d'right = 15) and 
+                     (V32.e'right = 15) and 
+                     (V32.f'right = 15) and 
+                     (V32.g'right = 15) and 
+                     (V34.a'right = 15) and 
+                     (V34.b'right = 15) and 
+                     (V34.c'right = 15) and 
+                     (V34.d'right = 15) and 
+                     (V34.e'right = 15) and 
+                     (V34.f'right = 15) and 
+                     (V34.g'right = 15) and 
+                     (V36'right = 7) and 
+                     (V37'right = 15) and  
+                     (V38'right = 3) and 
+                     (V39'right = 3) and 
+--          (V40'right = 1) and 
+                     (V41'right = 7) and 
+                     (V42'right = 7) and 
+                     (V43'right = 7) and 
+                     (V44'right = 7) and 
+                     (V45'right = 7) and 
+                     (V46'right = 7) and 
+                     (V47'right = 7) and 
+                     (V48'right = 7) and 
+                     (V49'right = 7) and 
+                     (V50'right = 7) and 
+                     (V51.a'right = 7) and 
+                     (V51.b'right = 7) and 
+                     (V51.c'right = 7) and 
+                     (V1'length = 16) and 
+                     (V2'length = 16) and 
+                     (V3'length = 16) and 
+                     (V4'length = 16) and 
+                     (V5'length = 16) and 
+                     (V6'length = 16) and 
+                     (V7'length = 16) and 
+                     (V8'length = 16) and 
+                     (V9'length = 16) and 
+                     (V10'length = 16) and 
+                     (V11'length = 16) and 
+                     (V12'length = 16) and 
+                     (V13'length = 16) and 
+                     (V14'length = 16) and 
+                     (V15'length = 16) and 
+                     (V16'length = 16) and 
+                     (V17'length = 16) and 
+                     (V18'length = 16) and 
+                     (V19'length = 16) and 
+                     (V20'length = 16) and 
+                     (V21'length = 16) and 
+                     (V22.j'length = 7)and 
+                     (V22.k'length = 4) and 
+                     (V23.a'length = 16) and 
+                     (V23.b'length = 16) and 
+                     (V23.c'length = 16) and 
+                     (V23.d'length = 16) and 
+                     (V23.e'length = 16) and 
+                     (V23.f'length = 16) and 
+                     (V23.g'length = 16) and 
+                     (V24.a'length = 16) and 
+                     (V24.b'length = 16) and 
+                     (V24.c'length = 16) and 
+                     (V24.d'length = 16) and 
+                     (V24.e'length = 16) and 
+                     (V24.f'length = 16) and 
+                     (V24.g'length = 16) and 
+                     (V25'length = 16) and 
+                     (V26'length = 16) and 
+                     (V27'length = 16) and 
+                     (V28'length = 16) and 
+                     (V29'length = 16) and 
+                     (V30'length = 16) and 
+                     (V31'length = 16) and 
+                     (V32.a'length = 16) and 
+                     (V32.b'length = 16) and 
+                     (V32.c'length = 16) and 
+                     (V32.d'length = 16) and 
+                     (V32.e'length = 16) and 
+                     (V32.f'length = 16) and 
+                     (V32.g'length = 16) and 
+                     (V34.a'length = 16) and 
+                     (V34.b'length = 16) and 
+                     (V34.c'length = 16) and 
+                     (V34.d'length = 16) and 
+                     (V34.e'length = 16) and 
+                     (V34.f'length = 16) and 
+                     (V34.g'length = 16) and 
+                     (V36'length = 8) and 
+                     (V37'length = 16) and 
+                     (V38'length = 4) and 
+                     (V39'length = 4) and 
+--          (V40'length = 1) and 
+                     (V41'length = 8) and 
+                     (V42'length = 8) and 
+                     (V43'length = 8) and 
+                     (V44'length = 8) and 
+                     (V45'length = 8) and 
+                     (V46'length = 8) and 
+                     (V48'length = 8) and 
+                     (V48'length = 8) and 
+                     (V49'length = 8) and 
+                     (V50'length = 8) and 
+                     (V51.a'length = 8) and 
+                     (V51.b'length = 8) and 
+                     (V51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00756"
+      severity NOTE;
+    assert   ((V1'left = 0)    and 
+              (V2'left = 0)    and 
+              (V3'left = 0)    and 
+              (V4'left = 0)    and 
+              (V5'left = 0)    and 
+              (V6'left = 0)    and 
+              (V7'left = 0)    and 
+              (V8'left = 15) and 
+              (V9'left = 15) and 
+              (V10'left = 15) and 
+              (V11'left = 15) and 
+              (V12'left = 15) and 
+              (V13'left = 15) and 
+              (V14'left = 15) and 
+              (V15'left = 0) and 
+              (V16'left = 0) and 
+              (V17'left = 0) and 
+              (V18'left = 0) and 
+              (V19'left = 0) and 
+              (V20'left = 0) and 
+              (V21'left = 0) and 
+              (V22.j'left = 1) and 
+              (V22.k'left = 0) and 
+              (V23.a'left = 15) and 
+              (V23.b'left = 15) and 
+              (V23.c'left = 15) and 
+              (V23.d'left = 15) and 
+              (V23.e'left = 15) and 
+              (V23.f'left = 15) and 
+              (V23.g'left = 15) and 
+              (V24.a'left = 0) and 
+              (V24.b'left = 0) and 
+              (V24.c'left = 0) and 
+              (V24.d'left = 0) and 
+              (V24.e'left = 0) and 
+              (V24.f'left = 0) and 
+              (V24.g'left = 0) and 
+              (V25'left = 0) and 
+              (V26'left = 0) and 
+              (V27'left = 0) and 
+              (V28'left = 0) and 
+              (V29'left = 0) and 
+              (V30'left = 0) and 
+              (V31'left = 0) and 
+              (V32.a'left = 0) and 
+              (V32.b'left = 0) and 
+              (V32.c'left = 0) and 
+              (V32.d'left = 0) and 
+              (V32.e'left = 0) and 
+              (V32.f'left = 0) and 
+              (V32.g'left = 0) and 
+              (V34.a'left = 0) and 
+              (V34.b'left = 0) and 
+              (V34.c'left = 0) and 
+              (V34.d'left = 0) and 
+              (V34.e'left = 0) and 
+              (V34.f'left = 0) and 
+              (V34.g'left = 0) and 
+              (V36'left = 0) and 
+              (V37'left = 0) and 
+              (V38'left = 0) and 
+              (V39'left = 0) and 
+--          (V40'left = 1) and 
+              (V42'left = 0) and 
+              (V43'left = 0) and 
+              (V44'left = 0) and 
+              (V45'left = 0) and 
+              (V46'left = 0) and 
+              (V47'left = 0) and 
+              (V48'left = 0) and 
+              (V49'left = 0) and 
+              (V50'left = 0) and 
+              (V51.a'left = 0) and 
+              (V51.b'left = 0) and 
+              (V51.c'left = 0) and 
+              (V1'right = 15) and 
+              (V2'right = 15) and 
+              (V3'right = 15) and 
+              (V4'right = 15) and 
+              (V5'right = 15) and 
+              (V6'right = 15) and 
+              (V7'right = 15) and 
+              (V8'right = 0) and 
+              (V9'right = 0) and 
+              (V10'right = 0)and 
+              (V11'right = 0) and 
+              (V12'right = 0) and 
+              (V13'right = 0) and 
+              (V14'right = 0) and 
+              (V15'right = 15) and 
+              (V16'right = 15) and 
+              (V17'right = 15) and 
+              (V18'right = 15) and 
+              (V19'right = 15) and 
+              (V20'right = 15) and 
+              (V21'right = 15) and 
+              (V22.j'right = 7) and 
+              (V22.k'right = 3) and 
+              (V23.a'right = 0) and 
+              (V23.b'right = 0) and 
+              (V23.c'right = 0) and 
+              (V23.d'right = 0) and 
+              (V23.e'right = 0) and 
+              (V23.f'right = 0) and 
+              (V23.g'right = 0) and 
+              (V24.a'right = 15) and 
+              (V24.b'right = 15) and 
+              (V24.c'right = 15) and 
+              (V24.d'right = 15) and 
+              (V24.e'right = 15) and 
+              (V24.f'right = 15) and 
+              (V24.g'right = 15) and 
+              (V25'right = 15) and 
+              (V26'right = 15) and 
+              (V27'right = 15) and 
+              (V28'right = 15) and 
+              (V29'right = 15) and 
+              (V30'right = 15) and 
+              (V31'right = 15) and 
+              (V32.a'right = 15) and 
+              (V32.b'right = 15) and 
+              (V32.c'right = 15) and 
+              (V32.d'right = 15) and 
+              (V32.e'right = 15) and 
+              (V32.f'right = 15) and 
+              (V32.g'right = 15) and 
+              (V34.a'right = 15) and 
+              (V34.b'right = 15) and 
+              (V34.c'right = 15) and 
+              (V34.d'right = 15) and 
+              (V34.e'right = 15) and 
+              (V34.f'right = 15) and 
+              (V34.g'right = 15) and 
+              (V36'right = 7) and 
+              (V37'right = 15) and  
+              (V38'right = 3) and 
+              (V39'right = 3) and 
+--          (V40'right = 1) and 
+              (V41'right = 7) and 
+              (V42'right = 7) and 
+              (V43'right = 7) and 
+              (V44'right = 7) and 
+              (V45'right = 7) and 
+              (V46'right = 7) and 
+              (V47'right = 7) and 
+              (V48'right = 7) and 
+              (V49'right = 7) and 
+              (V50'right = 7) and 
+              (V51.a'right = 7) and 
+              (V51.b'right = 7) and 
+              (V51.c'right = 7) and 
+              (V1'length = 16) and 
+              (V2'length = 16) and 
+              (V3'length = 16) and 
+              (V4'length = 16) and 
+              (V5'length = 16) and 
+              (V6'length = 16) and 
+              (V7'length = 16) and 
+              (V8'length = 16) and 
+              (V9'length = 16) and 
+              (V10'length = 16) and 
+              (V11'length = 16) and 
+              (V12'length = 16) and 
+              (V13'length = 16) and 
+              (V14'length = 16) and 
+              (V15'length = 16) and 
+              (V16'length = 16) and 
+              (V17'length = 16) and 
+              (V18'length = 16) and 
+              (V19'length = 16) and 
+              (V20'length = 16) and 
+              (V21'length = 16) and 
+              (V22.j'length = 7)and 
+              (V22.k'length = 4) and 
+              (V23.a'length = 16) and 
+              (V23.b'length = 16) and 
+              (V23.c'length = 16) and 
+              (V23.d'length = 16) and 
+              (V23.e'length = 16) and 
+              (V23.f'length = 16) and 
+              (V23.g'length = 16) and 
+              (V24.a'length = 16) and 
+              (V24.b'length = 16) and 
+              (V24.c'length = 16) and 
+              (V24.d'length = 16) and 
+              (V24.e'length = 16) and 
+              (V24.f'length = 16) and 
+              (V24.g'length = 16) and 
+              (V25'length = 16) and 
+              (V26'length = 16) and 
+              (V27'length = 16) and 
+              (V28'length = 16) and 
+              (V29'length = 16) and 
+              (V30'length = 16) and 
+              (V31'length = 16) and 
+              (V32.a'length = 16) and 
+              (V32.b'length = 16) and 
+              (V32.c'length = 16) and 
+              (V32.d'length = 16) and 
+              (V32.e'length = 16) and 
+              (V32.f'length = 16) and 
+              (V32.g'length = 16) and 
+              (V34.a'length = 16) and 
+              (V34.b'length = 16) and 
+              (V34.c'length = 16) and 
+              (V34.d'length = 16) and 
+              (V34.e'length = 16) and 
+              (V34.f'length = 16) and 
+              (V34.g'length = 16) and 
+              (V36'length = 8) and 
+              (V37'length = 16) and 
+              (V38'length = 4) and 
+              (V39'length = 4) and 
+--          (V40'length = 1) and 
+              (V41'length = 8) and 
+              (V42'length = 8) and 
+              (V43'length = 8) and 
+              (V44'length = 8) and 
+              (V45'length = 8) and 
+              (V46'length = 8) and 
+              (V48'length = 8) and 
+              (V48'length = 8) and 
+              (V49'length = 8) and 
+              (V50'length = 8) and 
+              (V51.a'length = 8) and 
+              (V51.b'length = 8) and 
+              (V51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00756 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00756arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd
new file mode 100644
index 0000000..eb76c0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd
@@ -0,0 +1,382 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc757.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00757ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00757ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00757arch OF c01s01b01x01p05n02i00757ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  subtype column is integer range one to two;
+  subtype row is integer range one to eight;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_2cons is array (integer range <>) of record_2cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_2cons_st is  array_rec_2cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_2cons(zero to seven);
+                                    d: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_vector is array (natural range <>) of four_value;
+  subtype four_value_vector_range is four_value_vector(hi_to_low_range);
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+--   function resolution14(i:in four_value_vector) return four_value;        --bus resolution
+--   subtype four_value_state is resolution14 four_value;                    --function type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type byte is array(zero to seven) of bit;
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  constant size :integer := seven;
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  
+  constant     C12 : boolean_vector := (C1,false);
+  constant     C13 : severity_level_vector := (C4,error);
+  constant     C14 : integer_vector := (one,two,three,four);
+  constant     C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant     C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant     C17 : natural_vector := (one,2,3,4);
+  constant     C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  
+BEGIN
+  assert (hi_to_low_range'left = 0) report "generic for left bound of hi_to_low_range not working" severity failure;
+  assert (hi_to_low_range'right = 7) report "generic for right bound of hi_to_low_range not working" severity failure;
+  assert (row'left = 1) report "generic constrained for left bound of row not working" severity failure;
+  assert (row'right = 8) report "generic constrained for right bound of row not working" severity failure;
+  assert (column'left = 1) report "generic constrained for left bound of column not working" severity failure;
+  assert (column'right = 2) report "generic constrained for right bound of column not working" severity failure;
+  assert (boolean_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (severity_level_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (integer_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (real_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (time_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (natural_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (positive_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (boolean_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (severity_level_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (integer_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (real_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (time_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (natural_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (positive_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert  (boolean_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (severity_level_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (integer_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (real_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (time_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (natural_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (positive_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (boolean_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (severity_level_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (integer_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (real_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (time_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (natural_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (positive_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert    NOT(    (hi_to_low_range'left = 0) and 
+                      (hi_to_low_range'right = 7) and 
+                      (row'left = 1) and 
+                      (row'right = 8) and 
+                      (column'left = 1) and 
+                      (column'right = 2) and 
+                      (boolean_cons_vector'left = 15) and 
+                      (severity_level_cons_vector'left = 15)   and 
+                      (integer_cons_vector'left = 15) and 
+                      (real_cons_vector'left = 15)    and 
+                      (time_cons_vector'left = 15)    and 
+                      (natural_cons_vector'left = 15) and 
+                      (positive_cons_vector'left = 15) and 
+                      (boolean_cons_vector'right = 0) and 
+                      (severity_level_cons_vector'right = 0)   and 
+                      (integer_cons_vector'right = 0) and 
+                      (real_cons_vector'right = 0)    and 
+                      (time_cons_vector'right = 0)    and 
+                      (natural_cons_vector'right = 0) and 
+                      (positive_cons_vector'right = 0) and 
+                      (boolean_cons_vectorofvector'left = 0) and 
+                      (severity_level_cons_vectorofvector'left = 0) and 
+                      (integer_cons_vectorofvector'left = 0) and 
+                      (real_cons_vectorofvector'left = 0)    and 
+                      (time_cons_vectorofvector'left = 0)    and 
+                      (natural_cons_vectorofvector'left = 0) and 
+                      (positive_cons_vectorofvector'left = 0) and 
+                      (boolean_cons_vectorofvector'right = 15) and 
+                      (severity_level_cons_vectorofvector'right = 15) and 
+                      (integer_cons_vectorofvector'right = 15) and 
+                      (real_cons_vectorofvector'right = 15)    and 
+                      (time_cons_vectorofvector'right = 15)    and 
+                      (natural_cons_vectorofvector'right = 15) and 
+                      (positive_cons_vectorofvector'right = 15)    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00757"
+      severity NOTE;
+    assert    (    (hi_to_low_range'left = 0) and 
+                   (hi_to_low_range'right = 7) and 
+                   (row'left = 1) and 
+                   (row'right = 8) and 
+                   (column'left = 1) and 
+                   (column'right = 2) and 
+                   (boolean_cons_vector'left = 15) and 
+                   (severity_level_cons_vector'left = 15)   and 
+                   (integer_cons_vector'left = 15) and 
+                   (real_cons_vector'left = 15)    and 
+                   (time_cons_vector'left = 15)    and 
+                   (natural_cons_vector'left = 15) and 
+                   (positive_cons_vector'left = 15) and 
+                   (boolean_cons_vector'right = 0) and 
+                   (severity_level_cons_vector'right = 0)   and 
+                   (integer_cons_vector'right = 0) and 
+                   (real_cons_vector'right = 0)    and 
+                   (time_cons_vector'right = 0)    and 
+                   (natural_cons_vector'right = 0) and 
+                   (positive_cons_vector'right = 0) and 
+                   (boolean_cons_vectorofvector'left = 0) and 
+                   (severity_level_cons_vectorofvector'left = 0) and 
+                   (integer_cons_vectorofvector'left = 0) and 
+                   (real_cons_vectorofvector'left = 0)    and 
+                   (time_cons_vectorofvector'left = 0)    and 
+                   (natural_cons_vectorofvector'left = 0) and 
+                   (positive_cons_vectorofvector'left = 0) and 
+                   (boolean_cons_vectorofvector'right = 15) and 
+                   (severity_level_cons_vectorofvector'right = 15) and 
+                   (integer_cons_vectorofvector'right = 15) and 
+                   (real_cons_vectorofvector'right = 15)    and 
+                   (time_cons_vectorofvector'right = 15)    and 
+                   (natural_cons_vectorofvector'right = 15) and 
+                   (positive_cons_vectorofvector'right = 15)    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00757 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00757arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd
new file mode 100644
index 0000000..b693afb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc759.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00759pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer; 
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1    : boolean := true; 
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note; 
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C10    : string := "shishir";
+  constant C11    : bit_vector := B"0011";
+  constant C12    : boolean_vector := (true,false); 
+  constant C13    : severity_level_vector := (note,error);
+  constant C14    : integer_vector := (1,2,3,4); 
+  constant C15    : real_vector := (1.0,2.0,3.0,4.0); 
+  constant C16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17    : natural_vector := (1,2,3,4);
+  constant C18    : positive_vector := (1,2,3,4);
+
+end c01s01b01x01p05n02i00759pkg;
+
+
+use   work.c01s01b01x01p05n02i00759pkg.ALL;
+ENTITY c01s01b01x01p05n02i00759ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen10    : string := "shishir";
+    Cgen11    : bit_vector := B"0011";
+    Cgen12    : boolean_vector := (true,false);
+    Cgen13    : severity_level_vector := (note,error);
+    Cgen14    : integer_vector := (1,2,3,4);
+    Cgen15    : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17    : natural_vector := (1,2,3,4);
+    Cgen18    : positive_vector := (1,2,3,4) );
+END c01s01b01x01p05n02i00759ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00759arch OF c01s01b01x01p05n02i00759ent IS
+  constant Vgen1       : boolean := true;
+  constant Vgen2       : bit := '1';
+  constant Vgen3       : character := 's';
+  constant Vgen4       : severity_level := note;
+  constant Vgen5       : integer := 3;
+  constant Vgen6       : real := 3.0;
+  constant Vgen7       : time := 3 ns;
+  constant Vgen8       : natural := 1;
+  constant Vgen9       : positive := 1;
+  constant Vgen10    : string (one to seven):= "shishir";
+  constant Vgen11    : bit_vector(zero to three) := B"0011";
+  constant Vgen12    : boolean_vector(zero to one) := (true,false);
+  constant Vgen13    : severity_level_vector(zero to one) := (note,error);
+  constant Vgen14    : integer_vector(zero to three) := (1,2,3,4);
+  constant Vgen15    : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
+  constant Vgen16    : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant Vgen17    : natural_vector(zero to three) := (1,2,3,4);
+  constant Vgen18    : positive_vector(zero to three) := (1,2,3,4);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
+  assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
+  assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
+  assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
+  assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
+  assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
+  assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
+  assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
+  assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen10 = C10 and 
+                    Vgen11 = C11 and 
+                    Vgen12 = C12 and 
+                    Vgen13 = C13 and 
+                    Vgen14 = C14 and 
+                    Vgen15 = C15 and 
+                    Vgen16 = C16 and 
+                    Vgen17 = C17 and 
+                    Vgen18 = C18 ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00759"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen10 = C10 and 
+                   Vgen11 = C11 and 
+                   Vgen12 = C12 and 
+                   Vgen13 = C13 and 
+                   Vgen14 = C14 and 
+                   Vgen15 = C15 and 
+                   Vgen16 = C16 and 
+                   Vgen17 = C17 and 
+                   Vgen18 = C18 ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00759 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00759arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd
new file mode 100644
index 0000000..d5dffd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc76.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p10n04i00076ent IS
+END c04s03b01x02p10n04i00076ent;
+
+ARCHITECTURE c04s03b01x02p10n04i00076arch OF c04s03b01x02p10n04i00076ent IS
+  function F (constant S : BIT_VECTOR) return bit;
+  function F (constant S : BIT_VECTOR) return bit is
+    variable res_bit : bit := bit'('0');
+  begin
+    for I in S'LOW to S'HIGH loop
+      if S(I) = bit'('1') then
+        res_bit := bit'('1');
+        exit;
+      end if;
+    end loop;
+    return res_bit;
+  end;
+  signal X : F bit;       -- X is a resolved signal.
+  signal P,Q : bit := '1';
+BEGIN
+  TESTING: PROCESS(P)
+  BEGIN
+    X <= P;
+  END PROCESS TESTING;
+
+  TESTING1: PROCESS(Q)
+  BEGIN
+    X <= Q;      --NO_Failure Here
+  END PROCESS TESTING1;
+
+  TEST: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(X='1') 
+      report "***PASSED TEST: c04s03b01x02p10n04i00076" 
+      severity NOTE;
+    assert (X='1') 
+      report "***FAILED TEST:c04s03b01x02p10n04i00076 - A signal with multiple source should be a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TEST;
+
+END c04s03b01x02p10n04i00076arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd
new file mode 100644
index 0000000..0665348
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd
@@ -0,0 +1,185 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc760.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00760pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C10    : string    := "shishir";
+  constant C11    : bit_vector    := B"0011";
+  constant C12    : boolean_vector:= (true,false); 
+  constant C13    : severity_level_vector    := (note,error);
+  constant C14    : integer_vector:= (1,2,3,4); 
+  constant C15    : real_vector    := (1.0,2.0,3.0,4.0); 
+  constant C16    : time_vector    := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17    : natural_vector:= (1,2,3,4);
+  constant C18    : positive_vector:= (1,2,3,4);
+
+end c01s01b01x01p05n02i00760pkg;
+
+use   work.c01s01b01x01p05n02i00760pkg.ALL;
+ENTITY c01s01b01x01p05n02i00760ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen10    : string := "shishir";
+    Cgen11    : bit_vector := B"0011";
+    Cgen12    : boolean_vector := (true,false);
+    Cgen13    : severity_level_vector := (note,error);
+    Cgen14    : integer_vector := (1,2,3,4);
+    Cgen15    : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17    : natural_vector := (1,2,3,4);
+    Cgen18    : positive_vector := (1,2,3,4) 
+    );
+END c01s01b01x01p05n02i00760ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00760arch OF c01s01b01x01p05n02i00760ent IS
+  signal Vgen1    : boolean    := true;
+  signal Vgen2    : bit       := '1';
+  signal Vgen3    : character    := 's';
+  signal Vgen4    : severity_level:= note;
+  signal Vgen5    : integer    := 3;
+  signal Vgen6    : real       := 3.0;
+  signal Vgen7    : time       := 3 ns;
+  signal Vgen8    : natural    := 1;
+  signal Vgen9    : positive    := 1;
+  signal Vgen10    : string (one to seven)      := "shishir";
+  signal Vgen11    : bit_vector(zero to three)    := B"0011";
+  signal Vgen12    : boolean_vector(zero to one)    := (true,false);
+  signal Vgen13    : severity_level_vector(zero to one)    := (note,error);
+  signal Vgen14    : integer_vector(zero to three) := (1,2,3,4);
+  signal Vgen15    : real_vector(zero to three)    := (1.0,2.0,3.0,4.0);
+  signal Vgen16    : time_vector(zero to three)    := (1 ns, 2 ns, 3 ns, 4 ns);
+  signal Vgen17    : natural_vector(zero to three) := (1,2,3,4);
+  signal Vgen18    : positive_vector(zero to three) := (1,2,3,4);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
+  assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
+  assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
+  assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
+  assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
+  assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
+  assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
+  assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
+  assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen10 = C10 and 
+                    Vgen11 = C11 and 
+                    Vgen12 = C12 and 
+                    Vgen13 = C13 and 
+                    Vgen14 = C14 and 
+                    Vgen15 = C15 and 
+                    Vgen16 = C16 and 
+                    Vgen17 = C17 and 
+                    Vgen18 = C18 ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00760"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen10 = C10 and 
+                   Vgen11 = C11 and 
+                   Vgen12 = C12 and 
+                   Vgen13 = C13 and 
+                   Vgen14 = C14 and 
+                   Vgen15 = C15 and 
+                   Vgen16 = C16 and 
+                   Vgen17 = C17 and 
+                   Vgen18 = C18 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00760 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00760arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd
new file mode 100644
index 0000000..9871cd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00761pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer; 
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00761pkg;
+
+use   work.c01s01b01x01p05n02i00761pkg.ALL;
+ENTITY c01s01b01x01p05n02i00761ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   : integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+  port(
+    Vgen1    : boolean    := true;
+    Vgen2    : bit       := '1';
+    Vgen3    : character    := 's';
+    Vgen4    : severity_level:= note;
+    Vgen5    : integer    := 3;
+    Vgen6    : real       := 3.0;
+    Vgen7    : time       := 3 ns;
+    Vgen8    : natural    := 1;
+    Vgen9    : positive    := 1;
+    Vgen70  : boolean_vector_st       :=(others => true);
+    Vgen71  : severity_level_vector_st   :=(others => note);
+    Vgen72  : integer_vector_st      :=(others => 3);
+    Vgen73  : real_vector_st      :=(others => 3.0);
+    Vgen74  : time_vector_st      :=(others => 3 ns);
+    Vgen75  : natural_vector_st      :=(others => 1);
+    Vgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00761ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00761"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd
new file mode 100644
index 0000000..3fd73b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd
@@ -0,0 +1,183 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc762.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00762pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer; 
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean := true; 
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note; 
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00762pkg;
+
+
+use   work.c01s01b01x01p05n02i00762pkg.ALL;
+ENTITY c01s01b01x01p05n02i00762ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00762ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00762arch OF c01s01b01x01p05n02i00762ent IS
+  constant Vgen1       : boolean := true;
+  constant Vgen2       : bit := '1';
+  constant Vgen3       : character := 's';
+  constant Vgen4       : severity_level := note;
+  constant Vgen5       : integer := 3;
+  constant Vgen6       : real := 3.0;
+  constant Vgen7       : time := 3 ns;
+  constant Vgen8       : natural := 1;
+  constant Vgen9       : positive := 1;
+  constant Vgen70         : boolean_vector_st       :=(others => Cgen1);
+  constant Vgen71         : severity_level_vector_st   :=(others => Cgen4);
+  constant Vgen72         : integer_vector_st      :=(others => Cgen5);
+  constant Vgen73         : real_vector_st      :=(others => Cgen6);
+  constant Vgen74         : time_vector_st      :=(others => Cgen7);
+  constant Vgen75         : natural_vector_st      :=(others => Cgen8);
+  constant Vgen76         : positive_vector_st      :=(others => Cgen9);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00762"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00762 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00762arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd
new file mode 100644
index 0000000..20a45e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd
@@ -0,0 +1,183 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00763pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00763pkg;
+
+use   work.c01s01b01x01p05n02i00763pkg.ALL;
+ENTITY c01s01b01x01p05n02i00763ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00763ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
+  signal Vgen1    : boolean    := true;
+  signal Vgen2    : bit       := '1';
+  signal Vgen3    : character    := 's';
+  signal Vgen4    : severity_level:= note;
+  signal Vgen5    : integer    := 3;
+  signal Vgen6    : real       := 3.0;
+  signal Vgen7    : time       := 3 ns;
+  signal Vgen8    : natural    := 1;
+  signal Vgen9    : positive    := 1;
+  signal Vgen70   : boolean_vector_st       :=(others => Cgen1);
+  signal Vgen71   : severity_level_vector_st   :=(others => Cgen4);
+  signal Vgen72   : integer_vector_st      :=(others => Cgen5);
+  signal Vgen73   : real_vector_st      :=(others => Cgen6);
+  signal Vgen74   : time_vector_st      :=(others => Cgen7);
+  signal Vgen75   : natural_vector_st      :=(others => Cgen8);
+  signal Vgen76   : positive_vector_st      :=(others => Cgen9);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00763"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00763arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd
new file mode 100644
index 0000000..fa3a0ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc765.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p06n01i00765ent_a IS
+  port ( c1 : in  integer ;
+         c2 : out integer );
+END c01s01b01x02p06n01i00765ent_a;
+
+ARCHITECTURE c01s01b01x02p06n01i00765arch_a OF c01s01b01x02p06n01i00765ent_a IS
+
+BEGIN
+  c2   <=    c1;
+END c01s01b01x02p06n01i00765arch_a;
+
+
+ENTITY c01s01b01x02p06n01i00765ent IS
+  port ( p1 : in  integer ;
+         p2 : out integer );
+END c01s01b01x02p06n01i00765ent;
+
+ARCHITECTURE c01s01b01x02p06n01i00765arch OF c01s01b01x02p06n01i00765ent IS
+  component c01s01b01x02p06n01i00765ent_b
+    port (    c1 : in  integer ;
+              c2 : out integer );
+  end component;
+  for L : c01s01b01x02p06n01i00765ent_b use entity work.c01s01b01x02p06n01i00765ent_a(c01s01b01x02p06n01i00765arch_a);
+BEGIN
+  L: c01s01b01x02p06n01i00765ent_b
+    port map (p1, p2);    -- Success_here
+  -- The formal c1 is of mode in and
+  -- The corresponding actual p1 is of
+  -- mode in which is legal.
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b01x02p06n01i00765"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p06n01i00765arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd
new file mode 100644
index 0000000..ad26eb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc768.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p07n01i00768ent_a IS
+  port ( c1 : in    integer ;
+         c2 : out    integer );
+END c01s01b01x02p07n01i00768ent_a;
+
+ARCHITECTURE c01s01b01x02p07n01i00768arch_a OF c01s01b01x02p07n01i00768ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p07n01i00768arch_a;
+
+
+
+ENTITY c01s01b01x02p07n01i00768ent IS
+  port ( p1 : in    integer ;
+         p2 : out    integer );
+END c01s01b01x02p07n01i00768ent;
+
+ARCHITECTURE c01s01b01x02p07n01i00768arch OF c01s01b01x02p07n01i00768ent IS
+  component c01s01b01x02p07n01i00768ent_b
+    port ( c1 : in integer ;
+           c2 : out integer );
+  end component;
+  for L : c01s01b01x02p07n01i00768ent_b use entity work.c01s01b01x02p07n01i00768ent_a(c01s01b01x02p07n01i00768arch_a);
+BEGIN
+  L : c01s01b01x02p07n01i00768ent_b port map (p1, p2);
+  -- Success_here
+    -- The formal c2 is of mode out .
+      -- The corresponding actual p2 is of
+        -- mode out which is legal
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p07n01i00768"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p07n01i00768arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd
new file mode 100644
index 0000000..81b3350
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc772.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p08n01i00772ent_a IS
+  port ( C1 : inout    Bit ;
+         C2 : out    Bit );
+END c01s01b01x02p08n01i00772ent_a;
+
+ARCHITECTURE c01s01b01x02p08n01i00772arch_a OF c01s01b01x02p08n01i00772ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p08n01i00772arch_a;
+
+
+
+ENTITY c01s01b01x02p08n01i00772ent IS
+  port ( P1 : inout    Bit ;
+         P2 : out    Bit );
+END c01s01b01x02p08n01i00772ent;
+
+ARCHITECTURE c01s01b01x02p08n01i00772arch OF c01s01b01x02p08n01i00772ent IS
+  component c01s01b01x02p08n01i00772ent_b
+    port ( C1 : inout    Bit ;
+           C2 : out    Bit );
+  end component ;
+  for L : c01s01b01x02p08n01i00772ent_b use entity work.c01s01b01x02p08n01i00772ent_a(c01s01b01x02p08n01i00772arch_a);
+BEGIN
+  L : c01s01b01x02p08n01i00772ent_b port map (p1, p2);
+  --Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p08n01i00772" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p08n01i00772arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd
new file mode 100644
index 0000000..ff0c49f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc776.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p09n01i00776ent_a IS
+  port ( C1 : inout    Bit ;
+         C2 : buffer    Bit );
+END c01s01b01x02p09n01i00776ent_a;
+
+ARCHITECTURE c01s01b01x02p09n01i00776arch_a OF c01s01b01x02p09n01i00776ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p09n01i00776arch_a;
+
+
+ENTITY c01s01b01x02p09n01i00776ent IS
+  port ( p1 : inout    Bit ;
+         p2 : buffer    Bit );
+END c01s01b01x02p09n01i00776ent;
+
+ARCHITECTURE c01s01b01x02p09n01i00776arch OF c01s01b01x02p09n01i00776ent IS
+  component c01s01b01x02p09n01i00776ent_b
+    port (    C1 : inout    Bit ;
+              C2 : buffer    Bit );
+  end component;
+  for L : c01s01b01x02p09n01i00776ent_b use entity work.c01s01b01x02p09n01i00776ent_a(c01s01b01x02p09n01i00776arch_a);
+BEGIN
+  L : c01s01b01x02p09n01i00776ent_b port map (p1, p2);
+  --Success here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p09n01i00776" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p09n01i00776arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd
new file mode 100644
index 0000000..5841fcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc777.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p10n01i00777ent_a IS
+  port      (A : linkage integer;
+             B : linkage integer;
+             C : linkage integer;
+             D : linkage integer);
+END c01s01b01x02p10n01i00777ent_a;
+
+ARCHITECTURE c01s01b01x02p10n01i00777arch_a OF c01s01b01x02p10n01i00777ent_a IS
+
+BEGIN
+  test : process
+  begin
+    wait;
+  end process test;
+END c01s01b01x02p10n01i00777arch_a;
+
+
+
+ENTITY c01s01b01x02p10n01i00777ent IS
+  port (X : linkage    integer;
+        Y : buffer    integer;
+        Z : inout    integer);
+END c01s01b01x02p10n01i00777ent;
+
+ARCHITECTURE c01s01b01x02p10n01i00777arch OF c01s01b01x02p10n01i00777ent IS
+  component c01s01b01x02p10n01i00777ent_b
+    port      (A : linkage integer;
+               B : linkage integer;
+               C : linkage integer;
+               D : linkage integer);
+  end component;
+  for L : c01s01b01x02p10n01i00777ent_b use entity work.c01s01b01x02p10n01i00777ent_a(c01s01b01x02p10n01i00777arch_a);
+
+  signal M : integer;
+
+BEGIN
+  L:c01s01b01x02p10n01i00777ent_b port map 
+    ( A => M,
+      B => X,
+      C => Y,
+      D => Z);
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p10n01i00777"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p10n01i00777arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd
new file mode 100644
index 0000000..8891fa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p10n01i00778ent_a IS
+  port (  c1 : linkage integer;
+          c2 : linkage integer;
+          c3 : linkage integer;
+          c4 : linkage integer;
+          c5 : linkage integer);
+END c01s01b01x02p10n01i00778ent_a;
+
+ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
+
+BEGIN
+  test : process
+  begin
+    wait;
+  end process test;
+END c01s01b01x02p10n01i00778arch_a;
+
+
+
+ENTITY c01s01b01x02p10n01i00778ent IS
+  port (p1 : in      integer;
+        p2 : out     integer;
+        p3 : inout   integer;
+        p4 : buffer  integer;
+        p5 : linkage integer);
+END c01s01b01x02p10n01i00778ent;
+
+ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
+  component c01s01b01x02p10n01i00778ent_b
+    port (  c1 : linkage integer;
+            c2 : linkage integer;
+            c3 : linkage integer;
+            c4 : linkage integer;
+            c5 : linkage integer);
+  end component;
+  for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
+BEGIN
+  L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p10n01i00778"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p10n01i00778arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd
new file mode 100644
index 0000000..6e13a5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc782.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00782ent_a IS
+  port (
+    C2 : inout      Bit;
+    C3 : linkage    Bit;
+    C4 : out        Bit;
+    C5 : Buffer     Bit
+    );
+END c01s01b01x02p12n04i00782ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00782arch_a OF c01s01b01x02p12n04i00782ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00782arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00782ent IS
+  port (
+    A2 : inout      Bit;
+    A3 : linkage    Bit;
+    A4 : out        Bit;
+    A5 : Buffer     Bit
+    ) ;
+END c01s01b01x02p12n04i00782ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00782arch OF c01s01b01x02p12n04i00782ent IS
+  component c01s01b01x02p12n04i00782ent_b
+    port (
+      C2 : inout      Bit;
+      C3 : linkage    Bit;
+      C4 : out        Bit;
+      C5 : Buffer     Bit
+      );
+  end component;
+  for L : c01s01b01x02p12n04i00782ent_b use entity work.c01s01b01x02p12n04i00782ent_a(c01s01b01x02p12n04i00782arch_a);
+BEGIN
+  L : c01s01b01x02p12n04i00782ent_b port map ( C2 => open, C3 => open, C4 => open, C5 => open );
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p12n04i00782"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00782arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd
new file mode 100644
index 0000000..a5ea38c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc784.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00784ent_a IS
+  port (   C1 : in      bit_vector;
+           C2 : out     bit_vector;
+           C3 : inout   bit_vector;
+           C4 : buffer  bit_vector;
+           C5 : linkage bit_vector);
+END c01s01b01x02p12n04i00784ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00784arch_a OF c01s01b01x02p12n04i00784ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00784arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00784ent IS
+  port (   P1 : in     bit_vector(15 downto 0);
+           P2 : out     bit_vector(15 downto 0);
+           P3 : inout     bit_vector(15 downto 0);
+           P4 : buffer     bit_vector(15 downto 0);
+           P5 : linkage     bit_vector(15 downto 0));
+END c01s01b01x02p12n04i00784ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00784arch OF c01s01b01x02p12n04i00784ent IS
+  component c01s01b01x02p12n04i00784ent_b
+    port (   C1 : in      bit_vector;
+             C2 : out     bit_vector;
+             C3 : inout   bit_vector;
+             C4 : buffer  bit_vector;
+             C5 : linkage bit_vector);
+  end component;
+  for L : c01s01b01x02p12n04i00784ent_b use entity work.c01s01b01x02p12n04i00784ent_a(c01s01b01x02p12n04i00784arch_a);
+BEGIN
+  L : c01s01b01x02p12n04i00784ent_b 
+    port map (C1 => p1, C2 => p2, C3 => p3, C4 => p4, C5 => p5);
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p12n04i00784" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00784arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd
new file mode 100644
index 0000000..102cc10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00791ent_1 IS
+END  ;
+
+-- legal. with entity_simple_name
+ENTITY c01s01b02x00p03n01i00791ent_2 IS
+END c01s01b02x00p03n01i00791ent_2 ;
+
+-- legal. begin with no statements following
+ENTITY c01s01b02x00p03n01i00791ent_3 IS
+begin
+END c01s01b02x00p03n01i00791ent_3;
+
+-- legal. no space before semicolon
+ENTITY c01s01b02x00p03n01i00791ent_4 IS
+END c01s01b02x00p03n01i00791ent_4;
+
+-- legal. NEW line before semicolon
+ENTITY c01s01b02x00p03n01i00791ent_5 IS
+END c01s01b02x00p03n01i00791ent_5
+  ;
+
+--------------------------------
+ENTITY c01s01b02x00p03n01i00791ent IS
+END c01s01b02x00p03n01i00791ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b02x00p03n01i00791" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00791arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd
new file mode 100644
index 0000000..170d0a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b02x00p03n01i00792pkg is
+  constant k : integer := 5;
+  function wired_and (sig : bit_vector) return bit;
+end c01s01b02x00p03n01i00792pkg;
+
+package body c01s01b02x00p03n01i00792pkg is
+  function wired_and (sig : bit_vector) return bit is
+  begin
+    return '0';
+  end wired_and;
+end c01s01b02x00p03n01i00792pkg;
+
+
+ENTITY c01s01b02x00p03n01i00792ent_1 IS
+  GENERIC (CONSTANT a : bit);
+  ALIAS alias_identifier : bit IS a ;
+END    c01s01b02x00p03n01i00792ent_1 ;
+
+ENTITY c01s01b02x00p03n01i00792ent_2 IS
+  GENERIC (CONSTANT a : bit);
+  ATTRIBUTE my_name : integer;
+END    c01s01b02x00p03n01i00792ent_2 ;
+
+ENTITY c01s01b02x00p03n01i00792ent_4 IS
+  GENERIC (CONSTANT a : bit);
+  USE work.c01s01b02x00p03n01i00792pkg.ALL;
+END    c01s01b02x00p03n01i00792ent_4 ;
+
+use work.c01s01b02x00p03n01i00792pkg.all;
+ENTITY c01s01b02x00p03n01i00792ent_5 IS
+  port (signal a : in wired_and bit bus);
+  DISCONNECT a:bit AFTER 100 ns;
+END    c01s01b02x00p03n01i00792ent_5 ;
+
+--------------------------------
+ENTITY c01s01b02x00p03n01i00792ent IS
+END c01s01b02x00p03n01i00792ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b02x00p03n01i00792" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00792arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd
new file mode 100644
index 0000000..ce3c006
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc80.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p12n01i00080ent IS
+END c04s03b01x02p12n01i00080ent;
+
+ARCHITECTURE c04s03b01x02p12n01i00080arch OF c04s03b01x02p12n01i00080ent IS
+  type arrbit    is array (1 to 3) of bit;
+  type comp_vect    is array (positive range <>) of arrbit;
+  
+  function F(BB: comp_vect) return arrbit is
+  begin
+    return "111";
+  end;
+  
+  signal X : F arrbit ;
+  signal P : bit := '1';
+  signal Q : bit := '1';
+  signal R : bit := '1';
+BEGIN
+  TESTING: PROCESS(P,Q,R)
+  BEGIN
+    X(1) <= P;   -- No_failure_here
+    X(2) <= Q;   -- No_failure_here
+    X(3) <= R;   -- No_failure_here
+    assert NOT(X="111") 
+      report "***PASSED TEST: c04s03b01x02p12n01i00080"
+      severity NOTE;
+    assert (X="111") 
+      report "***FAILED TEST:c04s03b01x02p12n01i00080 - All of the subelements of the signal should have a driver in a process."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c04s03b01x02p12n01i00080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd
new file mode 100644
index 0000000..5755b1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc805.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00805ent IS
+  port (CLK: in bit);
+begin
+  assert FALSE
+    report "The test of concurrent assertion statement in entity statement passed when you see this asssertion note."
+    severity note;
+  process
+  begin
+    wait;
+  end process;
+END c01s01b03x00p03n01i00805ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00805arch OF c01s01b03x00p03n01i00805ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b03x00p03n01i00805 - This test needs manual check to make sure that assertion notice appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00805arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd
new file mode 100644
index 0000000..72e2e0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc81.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p13n01i00081ent IS
+END c04s03b01x02p13n01i00081ent;
+
+ARCHITECTURE c04s03b01x02p13n01i00081arch OF c04s03b01x02p13n01i00081ent IS
+  signal S1 : Integer := 1;
+BEGIN
+  TESTING: PROCESS
+    variable T1 : TIME:= NOW;
+  BEGIN
+    assert NOT( S1 = 1 and T1 = NOW )
+      report "***PASSED TEST: c04s03b01x02p13n01i00081"
+      severity NOTE;
+    assert ( S1 = 1 and T1 = NOW )
+      report "***FAILED TEST:c04s03b01x02p13n01i00081 - Default value of the scalar signal is assumed at the start of the simulation."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p13n01i00081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd
new file mode 100644
index 0000000..fe41dac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc817.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00817ent_a IS
+  port (A    : IN BIT);
+END c01s02b01x00p03n01i00817ent_a;
+
+ARCHITECTURE c01s02b01x00p03n01i00817arch_a OF c01s02b01x00p03n01i00817ent_a IS
+
+BEGIN
+  TEST : PROCESS
+  BEGIN
+    if A = '1' then 
+      null;
+    end if;
+    wait;
+  END PROCESS TEST;
+
+END c01s02b01x00p03n01i00817arch_a;
+
+
+package c01s02b01x00p03n01i00817pkg is
+  type BIT is ('0', '1');
+end c01s02b01x00p03n01i00817pkg;
+
+ENTITY c01s02b01x00p03n01i00817ent IS
+  port (A    : BIT;
+        B    : out BIT;
+        C, D    : Boolean) ;
+END c01s02b01x00p03n01i00817ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00817arch OF c01s02b01x00p03n01i00817ent IS
+  
+  procedure P1 is
+  begin
+    return;
+  end P1;
+  
+  function F1 return BIT is
+  begin
+    return '0';
+  end F1;
+  
+  type    Q  is range 10.5 to 11.5;
+  subtype    R  is REAL;
+  constant    C1 : REAL := 1.39;
+  signal    S  : BIT;
+  component E2
+    port (A : in BIT);
+  end component;
+  for TEST : E2 use entity work.c01s02b01x00p03n01i00817ent_a(c01s02b01x00p03n01i00817arch_a);
+  use WORK.c01s02b01x00p03n01i00817pkg.all;
+
+BEGIN
+  TEST : E2 port map (S);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s02b01x00p03n01i00817"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b01x00p03n01i00817arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd
new file mode 100644
index 0000000..1a997e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd
@@ -0,0 +1,576 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p01n01i00082ent IS
+END c04s03b01x03p01n01i00082ent;
+
+ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+  
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE declarations
+--
+    
+    VARIABLE     STRING_con_0 :     STRING (1 TO 7);
+    VARIABLE     STRING_con_1 :     STRING (1 TO 7) := "sailing";
+    VARIABLE     STRING_con_2 :     STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+    
+    VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
+    VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
+    VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
+    
+    VARIABLE   ut_chary_con_0 :   ut_chary (NUL TO ENQ);
+    VARIABLE   ut_chary_con_1 :   ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
+    
+    VARIABLE    ct_word_con_0 :    ct_word;
+    VARIABLE    ct_word_con_1 :    ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
+                                                '1', '1', '1', '1', '1', '1', '1', '1');
+    
+    VARIABLE  cst_str10_con_0 :  cst_str10;
+    VARIABLE  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+    VARIABLE  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j'); 
+    VARIABLE  cst_digit_con_0 :  cst_digit;
+    VARIABLE  cst_digit_con_1 :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+    
+    VARIABLE    rt_date_con_0 :    rt_date;
+    VARIABLE    rt_date_con_1 :    rt_date := (1, Jan, 1989);
+    
+    VARIABLE   rst_date_con_0 :   rst_date;
+    VARIABLE   rst_date_con_1 :   rst_date := (1, Apr, 2000);
+    
+----------------------------------------------------------------------------------------------------------
+  BEGIN
+    ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_0.day   = 0    REPORT " rt_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.month = Jan  REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.year  = 0    REPORT " rt_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_1.day   = 1    REPORT " rt_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.month = Jan  REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.year  = 1989 REPORT " rt_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_0.day   = 0    REPORT "rst_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.month = Jan  REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.year  = 0    REPORT "rst_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_1.day   = 1    REPORT "rst_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.month = Apr  REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.year  = 2000 REPORT "rst_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+
+--------------------------------------------------------------------------------------------------------------
+
+    assert NOT(    STRING_con_0(1) = NUL      and 
+                   STRING_con_0(2) = NUL       and
+                   STRING_con_0(3) = NUL       and
+                   STRING_con_0(4) = NUL       and
+                   STRING_con_0(5) = NUL       and
+                   STRING_con_0(6) = NUL       and
+                   STRING_con_0(7) = NUL       and
+                   STRING_con_1(1) = 's'       and
+                   STRING_con_1(2) = 'a'       and
+                   STRING_con_1(3) = 'i'       and
+                   STRING_con_1(4) = 'l'       and
+                   STRING_con_1(5) = 'i'       and
+                   STRING_con_1(6) = 'n'       and
+                   STRING_con_1(7) = 'g'       and
+                   STRING_con_2(1) = 's'       and
+                   STRING_con_2(2) = 'a'       and
+                   STRING_con_2(3) = 'i'       and
+                   STRING_con_2(4) = 'l'       and
+                   STRING_con_2(5) = 'i'       and
+                   STRING_con_2(6) = 'n'       and
+                   STRING_con_2(7) = 'g'       and
+                   BIT_VECTOR_con_0(0) = '0'    and
+                   BIT_VECTOR_con_0(1) = '0'    and
+                   BIT_VECTOR_con_0(2) = '0'    and
+                   BIT_VECTOR_con_0(3) = '0'    and
+                   BIT_VECTOR_con_0(4) = '0'    and
+                   BIT_VECTOR_con_0(5) = '0'    and
+                   BIT_VECTOR_con_0(6) = '0'    and
+                   BIT_VECTOR_con_0(7) = '0'    and
+                   BIT_VECTOR_con_1(0) = '1'    and
+                   BIT_VECTOR_con_1(1) = '0'    and
+                   BIT_VECTOR_con_1(2) = '1'    and
+                   BIT_VECTOR_con_1(3) = '0'    and
+                   BIT_VECTOR_con_1(4) = '1'    and
+                   BIT_VECTOR_con_1(5) = '1'    and
+                   BIT_VECTOR_con_1(6) = '1'    and
+                   BIT_VECTOR_con_1(7) = '0'    and
+                   BIT_VECTOR_con_2(0) = '1'    and
+                   BIT_VECTOR_con_2(1) = '0'    and
+                   BIT_VECTOR_con_2(2) = '1'    and
+                   BIT_VECTOR_con_2(3) = '0'    and
+                   BIT_VECTOR_con_2(4) = '1'    and
+                   BIT_VECTOR_con_2(5) = '1'    and
+                   BIT_VECTOR_con_2(6) = '1'    and
+                   BIT_VECTOR_con_2(7) = '0'    and
+                   ut_chary_con_0(NUL) = INTEGER'LEFT    and
+                   ut_chary_con_0(SOH) = INTEGER'LEFT    and
+                   ut_chary_con_0(STX) = INTEGER'LEFT    and
+                   ut_chary_con_0(ETX) = INTEGER'LEFT    and
+                   ut_chary_con_0(EOT) = INTEGER'LEFT    and
+                   ut_chary_con_0(ENQ) = INTEGER'LEFT    and
+                   ut_chary_con_1(NUL) = 1    and
+                   ut_chary_con_1(SOH) = 2    and
+                   ut_chary_con_1(STX) = 3    and
+                   ut_chary_con_1(ETX) = 9    and
+                   ut_chary_con_1(EOT) = 8    and
+                   ut_chary_con_1(ENQ) = 7    and
+                   ct_word_con_0(0) = '0'       and
+                   ct_word_con_0(1) = '0'       and
+                   ct_word_con_0(2) = '0'       and
+                   ct_word_con_0(3) = '0'       and
+                   ct_word_con_0(4) = '0'       and
+                   ct_word_con_0(5) = '0'       and
+                   ct_word_con_0(6) = '0'       and
+                   ct_word_con_0(7) = '0'       and
+                   ct_word_con_0(8) = '0'       and
+                   ct_word_con_0(9) = '0'       and
+                   ct_word_con_0(10) = '0'    and
+                   ct_word_con_0(11) = '0'    and
+                   ct_word_con_0(12) = '0'    and
+                   ct_word_con_0(13) = '0'    and
+                   ct_word_con_0(14) = '0'    and
+                   ct_word_con_0(15) = '0'    and
+                   ct_word_con_1(0) = '1'       and
+                   ct_word_con_1(1) = '1'       and
+                   ct_word_con_1(2) = '1'       and
+                   ct_word_con_1(3) = '1'       and
+                   ct_word_con_1(4) = '1'       and
+                   ct_word_con_1(5) = '1'       and
+                   ct_word_con_1(6) = '1'       and
+                   ct_word_con_1(7) = '1'       and
+                   ct_word_con_1(8) = '1'       and
+                   ct_word_con_1(9) = '1'       and
+                   ct_word_con_1(10) = '1'    and
+                   ct_word_con_1(11) = '1'    and
+                   ct_word_con_1(12) = '1'    and
+                   ct_word_con_1(13) = '1'    and
+                   ct_word_con_1(14) = '1'    and
+                   ct_word_con_1(15) = '1'    and
+                   cst_str10_con_0(1) = NUL    and
+                   cst_str10_con_0(2) = NUL    and
+                   cst_str10_con_0(3) = NUL    and
+                   cst_str10_con_0(4) = NUL    and
+                   cst_str10_con_0(5) = NUL    and
+                   cst_str10_con_0(6) = NUL    and
+                   cst_str10_con_0(7) = NUL    and
+                   cst_str10_con_0(8) = NUL    and
+                   cst_str10_con_0(9) = NUL    and
+                   cst_str10_con_0(10) = NUL    and
+                   cst_str10_con_1(1) = 'a'    and
+                   cst_str10_con_1(2) = 'b'    and
+                   cst_str10_con_1(3) = 'c'    and
+                   cst_str10_con_1(4) = 'd'    and
+                   cst_str10_con_1(5) = 'e'    and
+                   cst_str10_con_1(6) = 'f'    and
+                   cst_str10_con_1(7) = 'g'    and
+                   cst_str10_con_1(8) = 'h'    and
+                   cst_str10_con_1(9) = 'i'    and
+                   cst_str10_con_1(10)= 'j'    and
+                   cst_str10_con_2(1) = 'a'    and
+                   cst_str10_con_2(2) = 'b'    and
+                   cst_str10_con_2(3) = 'c'    and
+                   cst_str10_con_2(4) = 'd'    and
+                   cst_str10_con_2(5) = 'e'    and
+                   cst_str10_con_2(6) = 'f'    and
+                   cst_str10_con_2(7) = 'g'    and
+                   cst_str10_con_2(8) = 'h'    and
+                   cst_str10_con_2(9) = 'i'    and
+                   cst_str10_con_2(10)= 'j'    and
+                   cst_digit_con_0('0') = INTEGER'LEFT    and
+                   cst_digit_con_0('1') = INTEGER'LEFT    and
+                   cst_digit_con_0('2') = INTEGER'LEFT    and
+                   cst_digit_con_0('3') = INTEGER'LEFT    and
+                   cst_digit_con_0('4') = INTEGER'LEFT    and
+                   cst_digit_con_0('5') = INTEGER'LEFT    and
+                   cst_digit_con_0('6') = INTEGER'LEFT    and
+                   cst_digit_con_0('7') = INTEGER'LEFT    and
+                   cst_digit_con_0('8') = INTEGER'LEFT    and
+                   cst_digit_con_0('9') = INTEGER'LEFT    and
+                   cst_digit_con_1('0') = 0    and
+                   cst_digit_con_1('1') = 1    and
+                   cst_digit_con_1('2') = 2    and
+                   cst_digit_con_1('3') = 3    and
+                   cst_digit_con_1('4') = 4    and
+                   cst_digit_con_1('5') = 5    and
+                   cst_digit_con_1('6') = 6    and
+                   cst_digit_con_1('7') = 7    and
+                   cst_digit_con_1('8') = 8    and
+                   cst_digit_con_1('9') = 9    and
+                   rt_date_con_0.day   = 0       and
+                   rt_date_con_0.month = Jan     and
+                   rt_date_con_0.year  = 0       and
+                   rt_date_con_1.day   = 1       and
+                   rt_date_con_1.month = Jan     and
+                   rt_date_con_1.year  = 1989    and
+                   rst_date_con_0.day   = 0       and
+                   rst_date_con_0.month = Jan     and
+                   rst_date_con_0.year  = 0       and
+                   rst_date_con_1.day   = 1       and
+                   rst_date_con_1.month = Apr     and
+                   rst_date_con_1.year  = 2000    )   
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
+      severity NOTE;
+    assert (       STRING_con_0(1) = NUL      and 
+                   STRING_con_0(2) = NUL       and
+                   STRING_con_0(3) = NUL       and
+                   STRING_con_0(4) = NUL       and
+                   STRING_con_0(5) = NUL       and
+                   STRING_con_0(6) = NUL       and
+                   STRING_con_0(7) = NUL       and
+                   STRING_con_1(1) = 's'       and
+                   STRING_con_1(2) = 'a'       and
+                   STRING_con_1(3) = 'i'       and
+                   STRING_con_1(4) = 'l'       and
+                   STRING_con_1(5) = 'i'       and
+                   STRING_con_1(6) = 'n'       and
+                   STRING_con_1(7) = 'g'       and
+                   STRING_con_2(1) = 's'       and
+                   STRING_con_2(2) = 'a'       and
+                   STRING_con_2(3) = 'i'       and
+                   STRING_con_2(4) = 'l'       and
+                   STRING_con_2(5) = 'i'       and
+                   STRING_con_2(6) = 'n'       and
+                   STRING_con_2(7) = 'g'       and
+                   BIT_VECTOR_con_0(0) = '0'    and
+                   BIT_VECTOR_con_0(1) = '0'    and
+                   BIT_VECTOR_con_0(2) = '0'    and
+                   BIT_VECTOR_con_0(3) = '0'    and
+                   BIT_VECTOR_con_0(4) = '0'    and
+                   BIT_VECTOR_con_0(5) = '0'    and
+                   BIT_VECTOR_con_0(6) = '0'    and
+                   BIT_VECTOR_con_0(7) = '0'    and
+                   BIT_VECTOR_con_1(0) = '1'    and
+                   BIT_VECTOR_con_1(1) = '0'    and
+                   BIT_VECTOR_con_1(2) = '1'    and
+                   BIT_VECTOR_con_1(3) = '0'    and
+                   BIT_VECTOR_con_1(4) = '1'    and
+                   BIT_VECTOR_con_1(5) = '1'    and
+                   BIT_VECTOR_con_1(6) = '1'    and
+                   BIT_VECTOR_con_1(7) = '0'    and
+                   BIT_VECTOR_con_2(0) = '1'    and
+                   BIT_VECTOR_con_2(1) = '0'    and
+                   BIT_VECTOR_con_2(2) = '1'    and
+                   BIT_VECTOR_con_2(3) = '0'    and
+                   BIT_VECTOR_con_2(4) = '1'    and
+                   BIT_VECTOR_con_2(5) = '1'    and
+                   BIT_VECTOR_con_2(6) = '1'    and
+                   BIT_VECTOR_con_2(7) = '0'    and
+                   ut_chary_con_0(NUL) = INTEGER'LEFT    and
+                   ut_chary_con_0(SOH) = INTEGER'LEFT    and
+                   ut_chary_con_0(STX) = INTEGER'LEFT    and
+                   ut_chary_con_0(ETX) = INTEGER'LEFT    and
+                   ut_chary_con_0(EOT) = INTEGER'LEFT    and
+                   ut_chary_con_0(ENQ) = INTEGER'LEFT    and
+                   ut_chary_con_1(NUL) = 1    and
+                   ut_chary_con_1(SOH) = 2    and
+                   ut_chary_con_1(STX) = 3    and
+                   ut_chary_con_1(ETX) = 9    and
+                   ut_chary_con_1(EOT) = 8    and
+                   ut_chary_con_1(ENQ) = 7    and
+                   ct_word_con_0(0) = '0'       and
+                   ct_word_con_0(1) = '0'       and
+                   ct_word_con_0(2) = '0'       and
+                   ct_word_con_0(3) = '0'       and
+                   ct_word_con_0(4) = '0'       and
+                   ct_word_con_0(5) = '0'       and
+                   ct_word_con_0(6) = '0'       and
+                   ct_word_con_0(7) = '0'       and
+                   ct_word_con_0(8) = '0'       and
+                   ct_word_con_0(9) = '0'       and
+                   ct_word_con_0(10) = '0'    and
+                   ct_word_con_0(11) = '0'    and
+                   ct_word_con_0(12) = '0'    and
+                   ct_word_con_0(13) = '0'    and
+                   ct_word_con_0(14) = '0'    and
+                   ct_word_con_0(15) = '0'    and
+                   ct_word_con_1(0) = '1'       and
+                   ct_word_con_1(1) = '1'       and
+                   ct_word_con_1(2) = '1'       and
+                   ct_word_con_1(3) = '1'       and
+                   ct_word_con_1(4) = '1'       and
+                   ct_word_con_1(5) = '1'       and
+                   ct_word_con_1(6) = '1'       and
+                   ct_word_con_1(7) = '1'       and
+                   ct_word_con_1(8) = '1'       and
+                   ct_word_con_1(9) = '1'       and
+                   ct_word_con_1(10) = '1'    and
+                   ct_word_con_1(11) = '1'    and
+                   ct_word_con_1(12) = '1'    and
+                   ct_word_con_1(13) = '1'    and
+                   ct_word_con_1(14) = '1'    and
+                   ct_word_con_1(15) = '1'    and
+                   cst_str10_con_0(1) = NUL    and
+                   cst_str10_con_0(2) = NUL    and
+                   cst_str10_con_0(3) = NUL    and
+                   cst_str10_con_0(4) = NUL    and
+                   cst_str10_con_0(5) = NUL    and
+                   cst_str10_con_0(6) = NUL    and
+                   cst_str10_con_0(7) = NUL    and
+                   cst_str10_con_0(8) = NUL    and
+                   cst_str10_con_0(9) = NUL    and
+                   cst_str10_con_0(10) = NUL    and
+                   cst_str10_con_1(1) = 'a'    and
+                   cst_str10_con_1(2) = 'b'    and
+                   cst_str10_con_1(3) = 'c'    and
+                   cst_str10_con_1(4) = 'd'    and
+                   cst_str10_con_1(5) = 'e'    and
+                   cst_str10_con_1(6) = 'f'    and
+                   cst_str10_con_1(7) = 'g'    and
+                   cst_str10_con_1(8) = 'h'    and
+                   cst_str10_con_1(9) = 'i'    and
+                   cst_str10_con_1(10)= 'j'    and
+                   cst_str10_con_2(1) = 'a'    and
+                   cst_str10_con_2(2) = 'b'    and
+                   cst_str10_con_2(3) = 'c'    and
+                   cst_str10_con_2(4) = 'd'    and
+                   cst_str10_con_2(5) = 'e'    and
+                   cst_str10_con_2(6) = 'f'    and
+                   cst_str10_con_2(7) = 'g'    and
+                   cst_str10_con_2(8) = 'h'    and
+                   cst_str10_con_2(9) = 'i'    and
+                   cst_str10_con_2(10)= 'j'    and
+                   cst_digit_con_0('0') = INTEGER'LEFT    and
+                   cst_digit_con_0('1') = INTEGER'LEFT    and
+                   cst_digit_con_0('2') = INTEGER'LEFT    and
+                   cst_digit_con_0('3') = INTEGER'LEFT    and
+                   cst_digit_con_0('4') = INTEGER'LEFT    and
+                   cst_digit_con_0('5') = INTEGER'LEFT    and
+                   cst_digit_con_0('6') = INTEGER'LEFT    and
+                   cst_digit_con_0('7') = INTEGER'LEFT    and
+                   cst_digit_con_0('8') = INTEGER'LEFT    and
+                   cst_digit_con_0('9') = INTEGER'LEFT    and
+                   cst_digit_con_1('0') = 0    and
+                   cst_digit_con_1('1') = 1    and
+                   cst_digit_con_1('2') = 2    and
+                   cst_digit_con_1('3') = 3    and
+                   cst_digit_con_1('4') = 4    and
+                   cst_digit_con_1('5') = 5    and
+                   cst_digit_con_1('6') = 6    and
+                   cst_digit_con_1('7') = 7    and
+                   cst_digit_con_1('8') = 8    and
+                   cst_digit_con_1('9') = 9    and
+                   rt_date_con_0.day   = 0       and
+                   rt_date_con_0.month = Jan     and
+                   rt_date_con_0.year  = 0       and
+                   rt_date_con_1.day   = 1       and
+                   rt_date_con_1.month = Jan     and
+                   rt_date_con_1.year  = 1989    and
+                   rst_date_con_0.day   = 0       and
+                   rst_date_con_0.month = Jan     and
+                   rst_date_con_0.year  = 0       and
+                   rst_date_con_1.day   = 1       and
+                   rst_date_con_1.month = Apr     and
+                   rst_date_con_1.year  = 2000    )   
+      report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p01n01i00082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd
new file mode 100644
index 0000000..004ea89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc820.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00820ent IS
+END c01s02b01x00p03n01i00820ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00820arch_empty OF c01s02b01x00p03n01i00820ent IS
+
+BEGIN
+END c01s02b01x00p03n01i00820arch_empty;
+
+
+
+ARCHITECTURE c01s02b01x00p03n01i00820arch OF c01s02b01x00p03n01i00820ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s02b01x00p03n01i00820" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b01x00p03n01i00820arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd
new file mode 100644
index 0000000..eafe359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc83.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p02n01i00083ent IS
+END c04s03b01x03p02n01i00083ent;
+
+ARCHITECTURE c04s03b01x03p02n01i00083arch OF c04s03b01x03p02n01i00083ent IS
+  type x is (a, b, c, d);
+BEGIN
+  TESTING: PROCESS
+    variable x1 : x := a;            -- No_failure_here
+    variable x  : character := 'a';  -- No_failure_here
+    variable x2 : character := 'a';  -- No_failure_here
+  BEGIN
+    assert NOT( x1 = a and x = 'a' and x2 = 'a' )
+      report "***PASSED TEST:c04s03b01x03p02n01i00083"
+      severity NOTE;
+    assert ( x1 = a and x = 'a' and x2 = 'a' )
+      report "***FAILED TEST: c04s03b01x03p02n01i00083- Variable assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p02n01i00083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd
new file mode 100644
index 0000000..bf8f080
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc837.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p02n01i00837ent_a is 
+end c01s03b01x00p02n01i00837ent_a;
+
+architecture c01s03b01x00p02n01i00837arch_a of c01s03b01x00p02n01i00837ent_a is
+  signal S1 : INTEGER;
+begin
+  A2_BLK : block
+  begin
+    S1 <= 2 after 10 ns;
+  end block;
+
+  TESTING: PROCESS(S1)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT(S1 = 2) 
+        report "***PASSED TEST: c01s03b01x00p02n01i00837"
+        severity NOTE;
+      assert (S1 = 2) 
+        report "***FAILED TEST: c01s03b01x00p02n01i00837 - Configuration block syntactic error."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+end c01s03b01x00p02n01i00837arch_a;
+
+ENTITY c01s03b01x00p02n01i00837ent IS
+END c01s03b01x00p02n01i00837ent;
+
+ARCHITECTURE c01s03b01x00p02n01i00837arch OF c01s03b01x00p02n01i00837ent IS
+
+BEGIN
+
+  DBLK : block
+    component FOUR
+    end component;
+  begin
+    LS : FOUR ;
+  end block DBLK;
+
+END c01s03b01x00p02n01i00837arch;
+
+configuration c01s03b01x00p02n01i00837cfg of c01s03b01x00p02n01i00837ent  is
+  for c01s03b01x00p02n01i00837arch
+    for DBLK
+      for LS : FOUR use entity work.c01s03b01x00p02n01i00837ent_a(c01s03b01x00p02n01i00837arch_a);
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p02n01i00837cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd
new file mode 100644
index 0000000..bef10b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc84.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p02n01i00084ent IS
+END c04s03b01x03p02n01i00084ent;
+
+ARCHITECTURE c04s03b01x03p02n01i00084arch OF c04s03b01x03p02n01i00084ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x1 : bit ;                         -- No_failure_here
+    variable x2 : character ;                   -- No_failure_here
+    variable x3 : integer := 1000;                  -- No_failure_here
+    variable x4 : real := 1.001;                    -- No_failure_here
+    variable x5 : boolean ;                     -- No_failure_here
+    variable x6 : time  := 10 ns;                   -- No_failure_here
+    variable x7 : string(1 to 10) := "abcdefghij";    -- No_failure_here
+    variable x8 : bit_vector (10 downto 1);     -- No_failure_here
+  BEGIN
+    assert NOT(    x1 = '0'      and
+                   x2 = NUL      and
+                   x3 = 1000      and
+                   x4 = 1.001      and
+                   x5 = false      and
+                   x6 = 10 ns      and
+                   x7 = "abcdefghij"   and
+                   x8 = "0000000000"   ) 
+      report "***PASSED TEST:c04s03b01x03p02n01i00084"
+      severity NOTE;
+    assert (    x1 = '0'      and
+                x2 = NUL      and
+                x3 = 1000      and
+                x4 = 1.001      and
+                x5 = false      and
+                x6 = 10 ns      and
+                x7 = "abcdefghij"   and
+                x8 = "0000000000"   ) 
+      report "***FAILED TEST: c04s03b01x03p02n01i00084 - Variable assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p02n01i00084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd
new file mode 100644
index 0000000..b6f310a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc840.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p03n01i00840ent_a is
+end c01s03b01x00p03n01i00840ent_a;
+
+architecture c01s03b01x00p03n01i00840arch_a of c01s03b01x00p03n01i00840ent_a is
+begin
+end c01s03b01x00p03n01i00840arch_a;
+
+ENTITY c01s03b01x00p03n01i00840ent IS
+END c01s03b01x00p03n01i00840ent;
+
+ARCHITECTURE c01s03b01x00p03n01i00840arch OF c01s03b01x00p03n01i00840ent IS
+
+BEGIN
+
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+    LR : FOUR;
+    aaa_blk: block
+    begin
+    end block;
+    L1: for I in 1 to 3 generate
+    end generate;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p03n01i00840"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p03n01i00840arch;
+
+configuration c01s03b01x00p03n01i00840cfg of c01s03b01x00p03n01i00840ent is
+  for c01s03b01x00p03n01i00840arch
+    for AA_BLK
+      for LH, LR : FOUR
+        use entity work.c01s03b01x00p03n01i00840ent_a(c01s03b01x00p03n01i00840arch_a);
+      end for;
+      for aaa_blk
+      end for;
+      for l1 (1 to 2)
+      end for;
+      for l1 (3)
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p03n01i00840cfg;
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd
new file mode 100644
index 0000000..35e3847
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc842.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p04n01i00842ent_a is
+end c01s03b01x00p04n01i00842ent_a;
+
+architecture c01s03b01x00p04n01i00842arch_a of c01s03b01x00p04n01i00842ent_a is
+begin
+end c01s03b01x00p04n01i00842arch_a;
+
+ENTITY c01s03b01x00p04n01i00842ent IS
+END c01s03b01x00p04n01i00842ent;
+
+ARCHITECTURE c01s03b01x00p04n01i00842arch OF c01s03b01x00p04n01i00842ent IS
+
+BEGIN
+  
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+    LR : FOUR;
+    aaa_blk: block
+    begin
+    end block;
+    L1: for I in 1 to 3 generate
+    end generate;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p04n01i00842"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p04n01i00842arch;
+
+configuration c01s03b01x00p04n01i00842cfg of c01s03b01x00p04n01i00842ent is
+  for c01s03b01x00p04n01i00842arch
+    for AA_BLK
+      for LH, LR : FOUR
+        use entity work.c01s03b01x00p04n01i00842ent_a(c01s03b01x00p04n01i00842arch_a);
+      end for;
+      for aaa_blk
+      end for;
+      for L1 (1 to 2)                 --- No_failure_here
+      end for;
+      for L1 (3)
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p04n01i00842cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd
new file mode 100644
index 0000000..75d0420
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc843.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p05n01i00843ent_a is 
+end c01s03b01x00p05n01i00843ent_a ;
+
+architecture c01s03b01x00p05n01i00843arch_a of c01s03b01x00p05n01i00843ent_a is
+begin
+  AC_BLK : block
+    signal B : BIT;
+  begin
+    B <= '1';
+  end block;
+end c01s03b01x00p05n01i00843arch_a;
+
+
+ENTITY c01s03b01x00p05n01i00843ent IS
+END c01s03b01x00p05n01i00843ent;
+
+ARCHITECTURE c01s03b01x00p05n01i00843arch OF c01s03b01x00p05n01i00843ent IS
+
+BEGIN
+  A_BLK : block
+    component C
+    end component;
+  begin
+    L1 : C;
+    L2 : C;
+    L3 : C;
+    L4 : C;
+    L5 : C;
+    L6 : C;
+    L7 : C;
+    L8 : C;
+    L9 : C;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p05n01i00843"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p05n01i00843arch;
+
+configuration c01s03b01x00p05n01i00843cfg of c01s03b01x00p05n01i00843ent is
+  for c01s03b01x00p05n01i00843arch
+    for A_BLK
+      for L1 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L2 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L3 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L4 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L5 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L6 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L7 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L8 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L9 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+    end for;
+  end for ;
+end c01s03b01x00p05n01i00843cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd
new file mode 100644
index 0000000..eb2adca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc844.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p05n01i00844ent_a is 
+end c01s03b01x00p05n01i00844ent_a ;
+
+architecture c01s03b01x00p05n01i00844arch_a of c01s03b01x00p05n01i00844ent_a is
+begin
+  A1_BLK : block
+    signal S : INTEGER;
+  begin
+    S <= 1;
+  end block;
+end c01s03b01x00p05n01i00844arch_a;
+
+
+ENTITY c01s03b01x00p05n01i00844ent IS
+END c01s03b01x00p05n01i00844ent;
+
+architecture c01s03b01x00p05n01i00844arch of  c01s03b01x00p05n01i00844ent is
+BEGIN
+
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p05n01i00844"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p05n01i00844arch;
+
+configuration c01s03b01x00p05n01i00844cfg of c01s03b01x00p05n01i00844ent is
+  for c01s03b01x00p05n01i00844arch
+    for AA_BLK
+      for LH : FOUR
+        use
+          entity work.c01s03b01x00p05n01i00844ent_a(c01s03b01x00p05n01i00844arch_a);
+      end for;
+    end for;
+  end for ;
+end c01s03b01x00p05n01i00844cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd
new file mode 100644
index 0000000..95e3d7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc846.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity and2g is
+end and2g;
+
+architecture behavior of and2g is
+begin
+end behavior;
+
+entity full_adder is
+end full_adder;
+
+architecture structural of full_adder is
+  component and2
+  end component;
+begin
+  C1: and2;
+end structural;
+
+ENTITY c01s03b01x00p08n01i00846ent IS
+END c01s03b01x00p08n01i00846ent;
+
+ARCHITECTURE c01s03b01x00p08n01i00846arch OF c01s03b01x00p08n01i00846ent IS
+  
+  component adder
+  end component;
+  
+BEGIN
+  A1 : adder;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p08n01i00846" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p08n01i00846arch;
+
+
+configuration c01s03b01x00p08n01i00846cfg of c01s03b01x00p08n01i00846ent is
+  for c01s03b01x00p08n01i00846arch
+    for A1: adder use                      -- component configuration
+                    entity work.full_adder(structural);
+                  
+                  for structural       -- no_failure_here
+                    for C1: and2 use
+                                   entity work.and2g(behavior);
+                    end for;
+                  end for;
+    end for;
+  end for;
+end c01s03b01x00p08n01i00846cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd
new file mode 100644
index 0000000..1c9997e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd
@@ -0,0 +1,291 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc849.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00849pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00849pkg_b;
+
+package body c01s03b01x00p12n01i00849pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00849pkg_b;
+
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+package c01s03b01x00p12n01i00849pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00849pkg_a;
+
+use work.c01s03b01x00p12n01i00849pkg_a.all;
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00849pkg_a.all;
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+ENTITY c01s03b01x00p12n01i00849ent IS
+END c01s03b01x00p12n01i00849ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00849arch OF c01s03b01x00p12n01i00849ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00849"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00849 - Block configuration apply to implicit blocks generated by that generate statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00849arch;
+
+configuration c01s03b01x00p12n01i00849cfg of c01s03b01x00p12n01i00849ent is
+  for c01s03b01x00p12n01i00849arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd
new file mode 100644
index 0000000..7bdcbe0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc850.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00850pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00850pkg_b;
+
+package body c01s03b01x00p12n01i00850pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00850pkg_b;
+
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+package c01s03b01x00p12n01i00850pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00850pkg_a;
+
+
+use work.c01s03b01x00p12n01i00850pkg_a.all;
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00850pkg_a.all;
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+ENTITY c01s03b01x00p12n01i00850ent IS
+END c01s03b01x00p12n01i00850ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00850arch OF c01s03b01x00p12n01i00850ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00850"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00850 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00850arch;
+
+configuration c01s03b01x00p12n01i00850cfg of c01s03b01x00p12n01i00850ent is
+  for c01s03b01x00p12n01i00850arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd
new file mode 100644
index 0000000..ecae4e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc852.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00852pkg_2 is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00852pkg_2;
+
+package body c01s03b01x00p12n01i00852pkg_2 is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00852pkg_2;
+
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+package c01s03b01x00p12n01i00852pkg is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal dumy : bit_vector(zero to three);
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00852pkg;
+
+use work.c01s03b01x00p12n01i00852pkg.all;
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+entity c01s03b01x00p12n01i00852ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00852ent_a of c01s03b01x00p12n01i00852ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00852ent_abench of c01s03b01x00p12n01i00852ent_a is
+  for c01s03b01x00p12n01i00852ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00852pkg.all;
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+ENTITY c01s03b01x00p12n01i00852ent IS
+END c01s03b01x00p12n01i00852ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00852arch OF c01s03b01x00p12n01i00852ent IS
+  component c01s03b01x00p12n01i00852ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component c01s03b01x00p12n01i00852ent_a
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00852ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00852ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00852"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00852 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00852arch;
+
+configuration c01s03b01x00p12n01i00852cfg of c01s03b01x00p12n01i00852ent is
+  for c01s03b01x00p12n01i00852arch
+    for K
+      for T5:c01s03b01x00p12n01i00852ent_a use configuration work.c01s03b01x00p12n01i00852ent_abench;
+      end for;
+      for G(dumy'range)
+        for T1:c01s03b01x00p12n01i00852ent_a
+          use configuration work.c01s03b01x00p12n01i00852ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd
new file mode 100644
index 0000000..b471197
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc853.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00853pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00853pkg_b;
+
+package body c01s03b01x00p12n01i00853pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00853pkg_b;
+
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+package c01s03b01x00p12n01i00853pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00853pkg_a;
+
+use work.c01s03b01x00p12n01i00853pkg_a.all;
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00853pkg_a.all;
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+ENTITY c01s03b01x00p12n01i00853ent IS
+END c01s03b01x00p12n01i00853ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00853arch OF c01s03b01x00p12n01i00853ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00853"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00853 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00853arch;
+
+configuration c01s03b01x00p12n01i00853cfg of c01s03b01x00p12n01i00853ent is
+  for c01s03b01x00p12n01i00853arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(dumy'reverse_range)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd
new file mode 100644
index 0000000..3744c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc854.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00854pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00854pkg_b;
+
+package body c01s03b01x00p12n01i00854pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00854pkg_b;
+
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+package c01s03b01x00p12n01i00854pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00854pkg_a;
+
+use work.c01s03b01x00p12n01i00854pkg_a.all;
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00854pkg_a.all;
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+ENTITY c01s03b01x00p12n01i00854ent IS
+END c01s03b01x00p12n01i00854ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00854arch OF c01s03b01x00p12n01i00854ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00854"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00854 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00854arch;
+
+configuration c01s03b01x00p12n01i00854cfg of c01s03b01x00p12n01i00854ent is
+  for c01s03b01x00p12n01i00854arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(dumy'reverse_range(1))
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd
new file mode 100644
index 0000000..6c44d39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd
@@ -0,0 +1,291 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc855.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00855pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00855pkg_b;
+
+package body c01s03b01x00p12n01i00855pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00855pkg_b;
+
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+package c01s03b01x00p12n01i00855pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00855pkg_a;
+
+use work.c01s03b01x00p12n01i00855pkg_a.all;
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00855pkg_a.all;
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+ENTITY c01s03b01x00p12n01i00855ent IS
+END c01s03b01x00p12n01i00855ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00855arch OF c01s03b01x00p12n01i00855ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00855"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00855 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00855arch;
+
+configuration c01s03b01x00p12n01i00855cfg of c01s03b01x00p12n01i00855ent is
+  for c01s03b01x00p12n01i00855arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to 3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd
new file mode 100644
index 0000000..6bc98cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc856.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00856pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00856pkg_b;
+
+package body c01s03b01x00p12n01i00856pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00856pkg_b;
+
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+package c01s03b01x00p12n01i00856pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00856pkg_a;
+
+use work.c01s03b01x00p12n01i00856pkg_a.all;
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00856pkg_a.all;
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+ENTITY c01s03b01x00p12n01i00856ent IS
+END c01s03b01x00p12n01i00856ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00856arch OF c01s03b01x00p12n01i00856ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00856"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00856 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00856arch;
+
+configuration c01s03b01x00p12n01i00856cfg of c01s03b01x00p12n01i00856ent is
+  for c01s03b01x00p12n01i00856arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(hi_to_low_range)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd
new file mode 100644
index 0000000..69353ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc857.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00857pkg_2 is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00857pkg_2;
+
+package body c01s03b01x00p12n01i00857pkg_2 is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00857pkg_2;
+
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+package c01s03b01x00p12n01i00857pkg is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00857pkg;
+
+use work.c01s03b01x00p12n01i00857pkg.all;
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+entity c01s03b01x00p12n01i00857ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00857ent_a of c01s03b01x00p12n01i00857ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00857ent_abench of c01s03b01x00p12n01i00857ent_a is
+  for c01s03b01x00p12n01i00857ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00857pkg.all;
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+ENTITY c01s03b01x00p12n01i00857ent IS
+END c01s03b01x00p12n01i00857ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00857arch OF c01s03b01x00p12n01i00857ent IS
+  component c01s03b01x00p12n01i00857ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component c01s03b01x00p12n01i00857ent_a
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00857ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00857ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00857"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00857 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00857arch;
+
+configuration c01s03b01x00p12n01i00857cfg of c01s03b01x00p12n01i00857ent is
+  for c01s03b01x00p12n01i00857arch
+    for K
+      for T5:c01s03b01x00p12n01i00857ent_a use configuration work.c01s03b01x00p12n01i00857ent_abench;
+      end for;
+      for G(dumy'low to 3)
+        for T1:c01s03b01x00p12n01i00857ent_a
+          use configuration work.c01s03b01x00p12n01i00857ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd
new file mode 100644
index 0000000..44bc00d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc858.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00858pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00858pkg_b;
+
+package body c01s03b01x00p12n01i00858pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00858pkg_b;
+
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+package c01s03b01x00p12n01i00858pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00858pkg_a;
+
+use work.c01s03b01x00p12n01i00858pkg_a.all;
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00858pkg_a.all;
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+ENTITY c01s03b01x00p12n01i00858ent IS
+END c01s03b01x00p12n01i00858ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00858arch OF c01s03b01x00p12n01i00858ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00858"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00858 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00858arch;
+
+configuration c01s03b01x00p12n01i00858cfg of c01s03b01x00p12n01i00858ent is
+  for c01s03b01x00p12n01i00858arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd
new file mode 100644
index 0000000..78e1f4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd
@@ -0,0 +1,296 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc859.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00859pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00859pkg_b;
+
+package body c01s03b01x00p12n01i00859pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00859pkg_b;
+
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+package c01s03b01x00p12n01i00859pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00859pkg_a;
+
+use work.c01s03b01x00p12n01i00859pkg_a.all;
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00859pkg_a.all;
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+ENTITY c01s03b01x00p12n01i00859ent IS
+END c01s03b01x00p12n01i00859ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00859arch OF c01s03b01x00p12n01i00859ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00859"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00859 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00859arch;
+
+configuration cc01s03b01x00p12n01i00859cfg of c01s03b01x00p12n01i00859ent is
+  for c01s03b01x00p12n01i00859arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd
new file mode 100644
index 0000000..b9706b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc86.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00086ent IS
+END c04s03b01x03p05n02i00086ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00086arch OF c04s03b01x03p05n02i00086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type some_type is (Sunday,Monday,Tuesday,Wed,Thur,Fri);
+    variable X : some_type;    -- No_failure_here
+    -- no default value declared.
+  BEGIN
+
+    assert NOT( X=Sunday )
+      report "***PASSED TEST: c04s03b01x03p05n02i00086"
+      severity NOTE;
+    assert ( X=Sunday )
+      report "***FAILED TEST: c04s03b01x03p05n02i00086 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd
new file mode 100644
index 0000000..f7abe68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd
@@ -0,0 +1,311 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc860.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00860pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00860pkg_b;
+
+package body c01s03b01x00p12n01i00860pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00860pkg_b;
+
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+package c01s03b01x00p12n01i00860pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00860pkg_a;
+
+use work.c01s03b01x00p12n01i00860pkg_a.all;
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00860pkg_a.all;
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+ENTITY c01s03b01x00p12n01i00860ent IS
+END c01s03b01x00p12n01i00860ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00860arch OF c01s03b01x00p12n01i00860ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00860"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00860 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00860arch;
+
+configuration c01s03b01x00p12n01i00860cfg of c01s03b01x00p12n01i00860ent is
+  for c01s03b01x00p12n01i00860arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(two)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd
new file mode 100644
index 0000000..50e31ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd
@@ -0,0 +1,301 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc861.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00861pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00861pkg_b;
+
+package body c01s03b01x00p12n01i00861pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00861pkg_b;
+
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+package c01s03b01x00p12n01i00861pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00861pkg_a;
+
+use work.c01s03b01x00p12n01i00861pkg_a.all;
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00861pkg_a.all;
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+ENTITY c01s03b01x00p12n01i00861ent IS
+END c01s03b01x00p12n01i00861ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00861arch OF c01s03b01x00p12n01i00861ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00861"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00861 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00861arch;
+
+configuration c01s03b01x00p12n01i00861cfg of c01s03b01x00p12n01i00861ent is
+  for c01s03b01x00p12n01i00861arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero to 1)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd
new file mode 100644
index 0000000..f6747d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd
@@ -0,0 +1,302 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc862.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00862pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00862pkg_b;
+
+package body c01s03b01x00p12n01i00862pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00862pkg_b;
+
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+package c01s03b01x00p12n01i00862pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00862pkg_a;
+
+use work.c01s03b01x00p12n01i00862pkg_a.all;
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00862pkg_a.all;
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+
+ENTITY c01s03b01x00p12n01i00862ent IS
+END c01s03b01x00p12n01i00862ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00862arch OF c01s03b01x00p12n01i00862ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00862"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00862 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00862arch;
+
+configuration c01s03b01x00p12n01i00862cfg of c01s03b01x00p12n01i00862ent is
+  for c01s03b01x00p12n01i00862arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low to 1)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd
new file mode 100644
index 0000000..23ede50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd
@@ -0,0 +1,296 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc863.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00863pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00863pkg_b;
+
+package body c01s03b01x00p12n01i00863pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00863pkg_b;
+
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+package c01s03b01x00p12n01i00863pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00863pkg_a;
+
+use work.c01s03b01x00p12n01i00863pkg_a.all;
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00863pkg_a.all;
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+ENTITY c01s03b01x00p12n01i00863ent IS
+END c01s03b01x00p12n01i00863ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00863arch OF c01s03b01x00p12n01i00863ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00863"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00863 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00863arch;
+
+configuration c01s03b01x00p12n01i00863cfg of c01s03b01x00p12n01i00863ent is
+  for c01s03b01x00p12n01i00863arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(0 to 2)
+        for all:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd
new file mode 100644
index 0000000..e01267a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd
@@ -0,0 +1,273 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc864.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00864pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  signal dumy : bit_vector(0 to 3);
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00864pkg;
+
+use work.c01s03b01x00p12n01i00864pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00864pkg.all;
+ENTITY c01s03b01x00p12n01i00864ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+END c01s03b01x00p12n01i00864ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00864arch OF c01s03b01x00p12n01i00864ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00864"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00864 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00864arch;
+
+configuration c01s03b01x00p12n01i00864cfg of c01s03b01x00p12n01i00864ent is
+  for c01s03b01x00p12n01i00864arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd
new file mode 100644
index 0000000..12f6aff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd
@@ -0,0 +1,288 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc866.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00866pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00866pkg;
+
+use work.c01s03b01x00p12n01i00866pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00866pkg.all;
+ENTITY c01s03b01x00p12n01i00866ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+END c01s03b01x00p12n01i00866ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00866arch OF c01s03b01x00p12n01i00866ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00866"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00866 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00866arch;
+
+configuration c01s03b01x00p12n01i00866cfg of c01s03b01x00p12n01i00866ent is
+  for c01s03b01x00p12n01i00866arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd
new file mode 100644
index 0000000..921262d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd
@@ -0,0 +1,284 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc867.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00867pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00867pkg;
+
+use work.c01s03b01x00p12n01i00867pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00867pkg.all;
+ENTITY c01s03b01x00p12n01i00867ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    dumb : bit_vector(0 to 3) := "1010");
+END c01s03b01x00p12n01i00867ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00867arch OF c01s03b01x00p12n01i00867ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00867"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00867 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00867arch;
+
+configuration c01s03b01x00p12n01i00867cfg of c01s03b01x00p12n01i00867ent is
+  for c01s03b01x00p12n01i00867arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd
new file mode 100644
index 0000000..50de97c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc868.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00868pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00868pkg;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+ENTITY c01s03b01x00p12n01i00868ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00868ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00868arch OF c01s03b01x00p12n01i00868ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00868"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00868 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00868arch;
+
+configuration c01s03b01x00p12n01i00868cfg of c01s03b01x00p12n01i00868ent is
+  for c01s03b01x00p12n01i00868arch
+    for K
+      for T5:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for all :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd
new file mode 100644
index 0000000..30ffda6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc869.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00869pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00869pkg;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+ENTITY c01s03b01x00p12n01i00869ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00869ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00869arch OF c01s03b01x00p12n01i00869ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00869"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00869 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00869arch;
+
+configuration c01s03b01x00p12n01i00869cfg of c01s03b01x00p12n01i00869ent is
+  for c01s03b01x00p12n01i00869arch
+    for K
+      for all:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd
new file mode 100644
index 0000000..36e634f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc87.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00087ent IS
+END c04s03b01x03p05n02i00087ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00087arch OF c04s03b01x03p05n02i00087ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type acc_type is access integer;
+    variable x : acc_type ;           -- No_failure_here
+  BEGIN
+
+    assert NOT( X=Null )
+      report "***PASSED TEST: c04s03b01x03p05n02i00087"
+      severity NOTE;
+    assert ( X=Null )
+      report "***FAILED TEST: c04s03b01x03p05n02i00087 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd
new file mode 100644
index 0000000..6d8899d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00870pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00870pkg;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+ENTITY c01s03b01x00p12n01i00870ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00870ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00870"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00870arch;
+
+configuration c01s03b01x00p12n01i00870cfg of c01s03b01x00p12n01i00870ent is
+  for c01s03b01x00p12n01i00870arch
+    for K
+      for others:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for all :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd
new file mode 100644
index 0000000..245600f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd
@@ -0,0 +1,324 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc871.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00871pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00871pkg;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+ENTITY c01s03b01x00p12n01i00871ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00871ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00871arch OF c01s03b01x00p12n01i00871ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00871"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00871 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00871arch;
+
+configuration c01s03b01x00p12n01i00871cfg of c01s03b01x00p12n01i00871ent is
+  for c01s03b01x00p12n01i00871arch
+    for K
+      for all:test use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd
new file mode 100644
index 0000000..b2aba52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc872.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00872pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00872pkg;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+ENTITY c01s03b01x00p12n01i00872ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00872ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00872arch OF c01s03b01x00p12n01i00872ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00872"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00872 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00872arch;
+
+configuration c01s03b01x00p12n01i00872cfg of c01s03b01x00p12n01i00872ent is
+  for c01s03b01x00p12n01i00872arch
+    for K
+      for all:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for others :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd
new file mode 100644
index 0000000..1ed0a88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd
@@ -0,0 +1,324 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc873.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00873pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00873pkg;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+entity c01s03b01x00p12n01i00873ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00873ent_a of c01s03b01x00p12n01i00873ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00873ent_abench of c01s03b01x00p12n01i00873ent_a is
+  for c01s03b01x00p12n01i00873ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+entity c01s03b01x00p12n01i00873ent_a1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00873ent_a1 of c01s03b01x00p12n01i00873ent_a1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration c01s03b01x00p12n01i00873ent_a1bench of c01s03b01x00p12n01i00873ent_a1 is
+  for c01s03b01x00p12n01i00873ent_a1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+ENTITY c01s03b01x00p12n01i00873ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00873ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00873arch OF c01s03b01x00p12n01i00873ent IS
+  component c01s03b01x00p12n01i00873ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00873ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00873ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00873"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00873 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00873arch;
+
+configuration c01s03b01x00p12n01i00873cfg of c01s03b01x00p12n01i00873ent is
+  for c01s03b01x00p12n01i00873arch
+    for K
+      for others:c01s03b01x00p12n01i00873ent_a use configuration work.c01s03b01x00p12n01i00873ent_a1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :c01s03b01x00p12n01i00873ent_a
+          use configuration work.c01s03b01x00p12n01i00873ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd
new file mode 100644
index 0000000..55b568e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc874.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p17n02i00874ent_a is
+end c01s03b01x00p17n02i00874ent_a;
+
+architecture c01s03b01x00p17n02i00874arch_a of c01s03b01x00p17n02i00874ent_a is
+begin
+end c01s03b01x00p17n02i00874arch_a;
+
+entity c01s03b01x00p17n02i00874ent_b is
+end c01s03b01x00p17n02i00874ent_b;
+
+architecture c01s03b01x00p17n02i00874arch_b of c01s03b01x00p17n02i00874ent_b is
+  component c01s03b01x00p17n02i00874ent_a
+  end component;
+begin
+  C1: c01s03b01x00p17n02i00874ent_a;
+end c01s03b01x00p17n02i00874arch_b;
+
+ENTITY c01s03b01x00p17n02i00874ent IS
+END c01s03b01x00p17n02i00874ent;
+
+ARCHITECTURE c01s03b01x00p17n02i00874arch OF c01s03b01x00p17n02i00874ent IS
+
+  component adder
+  end component;
+  
+BEGIN
+  A1 : adder;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p17n02i00874"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p17n02i00874arch;
+
+configuration c01s03b01x00p17n02i00874cfg of c01s03b01x00p17n02i00874ent is
+  for c01s03b01x00p17n02i00874arch
+    for A1: adder use             -- component configuration
+                    entity work.c01s03b01x00p17n02i00874ent_b(c01s03b01x00p17n02i00874arch_b);
+                  
+                  for c01s03b01x00p17n02i00874arch_b          -- no_failure_here    block configuration
+                    -- implicit component configuration
+                  end for;           -- no_failure_here
+    end for;
+  end for;
+end c01s03b01x00p17n02i00874cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd
new file mode 100644
index 0000000..501d040
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc876.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b02x00p02n01i00876ent_a  is
+  port (   ia, ib : bit;
+           oc, od : out bit) ;
+end c01s03b02x00p02n01i00876ent_a;
+
+architecture c01s03b02x00p02n01i00876arch_a of c01s03b02x00p02n01i00876ent_a is
+begin
+  A1_BLK : block
+    signal S : INTEGER;
+  begin
+    S <= 1;
+  end block;
+end c01s03b02x00p02n01i00876arch_a;
+
+
+ENTITY c01s03b02x00p02n01i00876ent IS
+  port (   P3 : out bit;
+           P4 : out bit) ;
+END c01s03b02x00p02n01i00876ent;
+
+ARCHITECTURE c01s03b02x00p02n01i00876arch OF c01s03b02x00p02n01i00876ent IS
+
+BEGIN
+  BB : block
+    signal S1 : bit;
+    signal S2 : bit;
+    component LOCAL port(   CI, I2  : in BIT;
+                            CO, RES :out BIT);
+    end component ;
+    
+    for all : LOCAL
+      use entity work.c01s03b02x00p02n01i00876ent_a (c01s03b02x00p02n01i00876arch_a)
+      port map (ia => CI, ib => I2, oc => CO, od => RES);
+  begin
+    L : LOCAL
+      port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
+    assert FALSE 
+      report "***PASSED TEST: c01s03b02x00p02n01i00876"
+      severity NOTE;
+  end block BB;
+
+END c01s03b02x00p02n01i00876arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd
new file mode 100644
index 0000000..d7d2d0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc877.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b02x00p02n01i00877ent IS
+END c01s03b02x00p02n01i00877ent;
+
+ARCHITECTURE c01s03b02x00p02n01i00877arch OF c01s03b02x00p02n01i00877ent IS
+
+BEGIN
+  BB : block
+
+    component LOCAL
+    end component;
+  begin
+    CIS : LOCAL;
+
+    assert FALSE 
+      report "***PASSED TEST: c01s03b02x00p02n01i00877"
+      severity NOTE;
+  end block BB;
+
+END c01s03b02x00p02n01i00877arch;
+
+configuration c01s03b02x00p02n01i00877cfg of c01s03b02x00p02n01i00877ent is
+  for  c01s03b02x00p02n01i00877arch
+    for BB
+      for CIS : LOCAL             -- Success_here
+      end for;
+    end for;
+  end for ;
+end c01s03b02x00p02n01i00877cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd
new file mode 100644
index 0000000..aff9317
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p03n01i00878pkg is
+  constant UNIT_DELAY: TIME := 1 ns;
+end c10s01b00x00p03n01i00878pkg;
+
+-- a nand gate
+entity ENT1 is
+  port ( BITIN1, BITIN2 : in  BIT;
+         BITOUT: out BIT );
+end ENT1;
+
+use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
+architecture ARC1 of ENT1 is
+begin
+  BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
+end ARC1;
+
+configuration CON1 of ENT1 is
+  for ARC1
+  end for;
+end CON1;
+
+-- build an inverter from nand-nand logic
+entity ENT2 is
+  port ( GOING_IN: in BIT;
+         COMING_OUT: out BIT );
+end ENT2;
+
+architecture ARC2 of ENT2 is
+  component NAND_BOX
+    port ( IN1, IN2: in BIT; OUT1: out BIT );
+  end component;
+  signal STUCKAT_HIGH: BIT := '1';
+begin
+  NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
+end ARC2;
+
+use WORK.CON1;
+configuration CON2 of ENT2 is
+  for ARC2
+    for NAND_COMP: NAND_BOX
+      use configuration CON1
+        port map ( IN1, IN2, OUT1 );
+    end for;
+  end for;
+end CON2;
+
+-- declare a test bench
+ENTITY c10s01b00x00p03n01i00878ent IS
+END c10s01b00x00p03n01i00878ent;
+
+use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
+ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
+  component INV
+    port ( ENTRA: in BIT; SALE: out BIT );
+  end component;
+  signal SIGIN, SIGOUT: BIT;
+BEGIN
+  INVERTER: INV port map ( SIGIN, SIGOUT );
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    SIGIN <= '0';
+    wait for ( 2 * UNIT_DELAY );
+    if (SIGOUT /= '1') then
+      k := 1;
+    end if;
+    assert ( SIGOUT = '1' )
+      report "didn't invert low to high" severity FAILURE;
+    wait for ( 3 * UNIT_DELAY );
+    SIGIN <= '1';
+    wait for ( 2 * UNIT_DELAY );
+    if (SIGOUT /= '0') then
+      k := 1;
+    end if;
+    assert ( SIGOUT = '0' )
+      report "didn't invert high to low" severity FAILURE;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p03n01i00878"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p03n01i00878arch;
+
+use WORK.CON2;
+configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
+  for c10s01b00x00p03n01i00878arch
+    for INVERTER: INV
+      use configuration CON2
+        port map ( ENTRA, SALE );
+    end for;
+  end for;
+end c10s01b00x00p03n01i00878cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd
new file mode 100644
index 0000000..6c59318
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc879.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p04n01i00879pkg_a is
+  -- define a subtype to be used elsewhere
+  subtype EIGHTIES is INTEGER range 1980 to 1989;
+end c10s01b00x00p04n01i00879pkg_a;
+
+package c10s01b00x00p04n01i00879pkg_b is
+  use WORK.c10s01b00x00p04n01i00879pkg_a.EIGHTIES;
+  function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES;
+end c10s01b00x00p04n01i00879pkg_b;
+
+package body c10s01b00x00p04n01i00879pkg_b is
+  -- map any integer into range 1980 : 1989 based on one's digit
+  function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES is
+    variable RETVAL: EIGHTIES;
+  begin
+    RETVAL := ( ( abs ARG ) mod 10 ) + 1980;
+    return RETVAL;
+  end INTO_EIGHTIES;
+end c10s01b00x00p04n01i00879pkg_b;
+
+
+ENTITY c10s01b00x00p04n01i00879ent IS
+END c10s01b00x00p04n01i00879ent;
+
+use WORK.c10s01b00x00p04n01i00879pkg_a.all;
+use WORK.c10s01b00x00p04n01i00879pkg_b.all;
+ARCHITECTURE c10s01b00x00p04n01i00879arch OF c10s01b00x00p04n01i00879ent IS
+  signal THE_INPUT   : INTEGER;
+  signal THE_OUTPUT   : INTEGER;
+BEGIN
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    for I in 120 to 149 loop
+      THE_INPUT    <= I;
+      THE_OUTPUT    <= INTO_EIGHTIES( I );
+      wait for 1 ns;
+      if ( THE_OUTPUT < 1980 or THE_OUTPUT > 1989 ) then
+        k := 1;
+      end if;
+      assert ( ( THE_OUTPUT >= 1980 ) and ( THE_OUTPUT <= 1989 ) )
+        report "output is out of range" 
+        severity FAILURE;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p04n01i00879"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p04n01i00879 - Declaration is formed by the subprogram declaration together with the corresponding subprogram body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p04n01i00879arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd
new file mode 100644
index 0000000..674ab72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc88.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00088ent IS
+END c04s03b01x03p05n02i00088ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00088arch OF c04s03b01x03p05n02i00088ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        a : bit;
+        b : character;
+        c : boolean;
+      end record;
+    variable x : rec_type ;
+  BEGIN
+
+    assert NOT( x.a = '0' and x.b = Nul and x.c = false ) 
+      report "***PASSED TEST:c04s03b01x03p05n02i00088"
+      severity NOTE;
+    assert ( x.a = '0' and x.b = Nul and x.c = false ) 
+      report "***FAILED TEST:c04s03b01x03p05n02i00088 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd
new file mode 100644
index 0000000..a73930e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc880.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p05n01i00880pkg_1 is
+  subtype LOWERCASE is CHARACTER range 'a' to 'z';
+end c10s01b00x00p05n01i00880pkg_1;
+
+use WORK.c10s01b00x00p05n01i00880pkg_1.LOWERCASE;
+package c10s01b00x00p05n01i00880pkg_2 is
+  function ISLOWER ( TESTCHAR: in CHARACTER ) return BOOLEAN;
+end c10s01b00x00p05n01i00880pkg_2;
+
+package body c10s01b00x00p05n01i00880pkg_2 is
+  function ISLOWER ( TESTCHAR: in CHARACTER ) return BOOLEAN is
+  begin
+    if ( ( TESTCHAR >= LOWERCASE'LOW ) and ( TESTCHAR <= LOWERCASE'HIGH )) then
+      return TRUE;
+    else
+      return FALSE;
+    end if;
+  end ISLOWER;
+end c10s01b00x00p05n01i00880pkg_2;
+
+ENTITY c10s01b00x00p05n01i00880ent IS
+END c10s01b00x00p05n01i00880ent;
+
+-- run through all values of character
+-- and post high if lowercase, low otherwise.  also, if is lowercase,
+-- place value on small_letter.
+use WORK.c10s01b00x00p05n01i00880pkg_1.LOWERCASE;
+use WORK.c10s01b00x00p05n01i00880pkg_2.all;
+ARCHITECTURE c10s01b00x00p05n01i00880arch OF c10s01b00x00p05n01i00880ent IS
+  signal LOWER_TRUTH : BIT := '0';
+  signal SMALL_LETTER: LOWERCASE;
+  signal TEST_LETTER : CHARACTER;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+
+    for CHAR_AT_HAND in CHARACTER'LOW to CHARACTER'HIGH loop
+      -- do the work
+      TEST_LETTER    <= CHAR_AT_HAND;
+      if ISLOWER( CHAR_AT_HAND ) then
+        LOWER_TRUTH    <= '1';
+        SMALL_LETTER    <= CHAR_AT_HAND;
+      else
+        LOWER_TRUTH    <= '0';
+      end if;
+      wait for 1 ns;
+      -- make sure it happened
+      if ( ( CHAR_AT_HAND >= LOWERCASE'LOW ) and ( CHAR_AT_HAND <= LOWERCASE'HIGH ) ) then
+        if (ISLOWER(CHAR_AT_HAND) = false) then
+          k := 1;
+        end if;
+        assert ( ISLOWER( CHAR_AT_HAND ) )
+          report "ISLOWER is wrong"
+          severity FAILURE;
+        if (LOWER_TRUTH /= '1') then
+          k := 1;
+        end if;
+        assert ( LOWER_TRUTH = '1' )
+          report "LOWER_TRUTH is wrong"
+          severity FAILURE;
+        if (CHAR_AT_HAND /= SMALL_LETTER) then
+          k := 1;
+        end if;
+        assert ( CHAR_AT_HAND = SMALL_LETTER )
+          report "SMALL_LETTER is wrong"
+          severity FAILURE;
+      else
+        if (LOWER_TRUTH /= '0') then
+          k := 1;
+        end if;
+        assert ( LOWER_TRUTH = '0' )
+          report "LOWER_TRUTH is wrong"
+          severity FAILURE;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p05n01i00880"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p05n01i00880 - A declaration region is formed by a package declaration together with the corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p05n01i00880arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd
new file mode 100644
index 0000000..20d955f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p06n01i00881PKG is
+-- VAL1 is here a constant
+  constant VAL1 : INTEGER := 65;
+  type DBLINTREC is
+    record
+-- VAL1 is here a record element
+      VAL1  : INTEGER;
+      VAL2  : INTEGER;
+    end record;
+end c10s01b00x00p06n01i00881PKG;
+
+
+use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
+entity c10s01b00x00p06n01i00881ent_a is
+  port (
+    PS1: in  DBLINTREC;
+    PS2: out DBLINTREC
+    );
+end c10s01b00x00p06n01i00881ent_a;
+
+architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is
+begin
+  process
+  begin
+    PS2.VAL1 <= PS1.VAL1 + 1;
+    PS2.VAL2 <= PS1.VAL2 + 2;
+    wait;
+  end process;
+end c10s01b00x00p06n01i00881arch_a;
+
+use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
+use WORK.c10s01b00x00p06n01i00881ent_a;
+ENTITY c10s01b00x00p06n01i00881ent IS
+END c10s01b00x00p06n01i00881ent;
+
+ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS
+
+  component c10s01b00x00p06n01i00881ent_a
+    port ( PS1: in DBLINTREC; PS2: out DBLINTREC );
+  end component;
+  for A1: c10s01b00x00p06n01i00881ent_a
+    use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a );
+  signal S1: DBLINTREC := (3, 9);
+  signal S2: DBLINTREC := (0, 0);
+
+BEGIN
+  
+  A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 );
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns; -- let a time increment go by so init done
+    assert ( S2.VAL1 = 4 )
+      report "didn't add to record element S2.VAL1 correctly"
+      severity FAILURE;
+    assert ( S2.VAL2 = 11 )
+      report "didn't add to record element S2.VAL2 correctly"
+      severity FAILURE;
+
+    assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 )
+      report "***PASSED TEST: c10s01b00x00p06n01i00881"
+      severity NOTE;
+    assert ( S2.VAL1 = 4 and S2.VAL2 =11 )
+      report "***FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p06n01i00881arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd
new file mode 100644
index 0000000..573db95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc883.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p08n01i00883ent IS
+END c10s01b00x00p08n01i00883ent;
+
+ARCHITECTURE c10s01b00x00p08n01i00883arch OF c10s01b00x00p08n01i00883ent IS
+
+  signal S1   : INTEGER;
+  signal S2   : INTEGER;
+  signal GS1   : INTEGER;
+  signal GS2   : INTEGER;
+  signal PS1   : INTEGER;
+  signal PS2   : INTEGER;
+
+BEGIN
+
+  -- initialization block and process
+  ALIST1SUB:
+  block
+    generic (
+      GS1: INTEGER := 3;
+      GS2: INTEGER := 9
+      );
+    generic map ( 3, 9 );
+    port (
+      PS1: out INTEGER;
+      PS2: out INTEGER
+      );
+    port map ( S1, S2 );
+  begin
+    process
+    begin
+      PS1 <= GS1 + 1;
+      PS2 <= GS2 + 2;
+      wait;
+    end process; -- forever, initialization complete
+  end block ALIST1SUB;
+
+  -- verification process
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( S1=4 and S2=11 )
+      report "***PASSED TEST: c10s01b00x00p08n01i00883"
+      severity NOTE;
+    assert ( S1=4 and S2=11 )
+      report "***FAILED TEST: c10s01b00x00p08n01i00883 - A single declaration region is formed by the text of a block statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p08n01i00883arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd
new file mode 100644
index 0000000..c46542f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc884.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p09n01i00884ent IS
+END c10s01b00x00p09n01i00884ent;
+
+ARCHITECTURE c10s01b00x00p09n01i00884arch OF c10s01b00x00p09n01i00884ent IS
+
+  constant GS1: INTEGER := 105;
+  constant GS2: INTEGER := 785;
+  signal PS1: INTEGER := 356;
+  signal PS2: INTEGER := 123;
+
+BEGIN
+  TESTING: PROCESS
+    constant GS1: INTEGER := 3;
+    constant GS2: INTEGER := 9;
+  BEGIN
+    PS1 <= GS1 + 1;
+    PS2 <= GS2 + 2;
+    wait on PS1, PS2;
+    assert NOT( PS1=4 and PS2=11 )
+      report "***PASSED TEST: c10s01b00x00p09n01i00884"
+      severity NOTE;
+    assert ( PS1=4 and PS2=11 )
+      report "***FAILED TEST: c10s01b00x00p09n01i00884 - A declaration region is formed by the text of a process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p09n01i00884arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
new file mode 100644
index 0000000..9152a1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc885.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p10n01i00885ent IS
+END c10s01b00x00p10n01i00885ent;
+
+ARCHITECTURE c10s01b00x00p10n01i00885arch OF c10s01b00x00p10n01i00885ent IS
+  signal S: INTEGER := 356;
+BEGIN
+  TESTING: PROCESS
+    constant I: INTEGER := 105; -- loop parameter has same name
+    variable k: integer := 0;
+  BEGIN
+    -- assign process constant I to S
+    S <= I;
+    wait for 1 ns;
+    assert ( S = 105 )
+      report "constant not properly assigned to signal"
+      severity FAILURE;
+    -- loop parameter has same name as constant declared in process
+    for I in 1 to 5 loop
+      -- assign loop parameter I to S
+      S <= I;
+      wait for 1 ns;
+      if ((S<1) or (S>5)) then
+        k := 1;
+      end if;
+      assert ( ( S >= 1 ) and ( S <= 5 ) )
+        report "loop parameter not properly assigned to signal"
+        severity FAILURE;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p10n01i00885"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p10n01i00885 - A declaration region is formed by the text of a loop statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p10n01i00885arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd
new file mode 100644
index 0000000..d281808
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc886.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p11n01i00886pkg_a is
+  constant x : integer := 1;
+end c10s01b00x00p11n01i00886pkg_a;
+
+package c10s01b00x00p11n01i00886pkg_b is
+  constant x : integer := 1;
+end c10s01b00x00p11n01i00886pkg_b;
+
+
+entity c10s01b00x00p11n01i00886ent_a is
+  generic (    passed_value    : integer := 6; 
+               ignored_value    : integer := 0 );
+end c10s01b00x00p11n01i00886ent_a;
+
+architecture c10s01b00x00p11n01i00886arch_a of c10s01b00x00p11n01i00886ent_a is
+begin
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( passed_value = 1)
+      report "***PASSED TEST: c10s01b00x00p11n01i00886"
+      severity NOTE;
+    assert ( passed_value = 1)
+      report "***FAILED TEST: c10s01b00x00p11n01i00886 - A block configuration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s01b00x00p11n01i00886arch_a;
+
+configuration c10s01b00x00p11n01i00886cfg_a of c10s01b00x00p11n01i00886ent_a is
+  for c10s01b00x00p11n01i00886arch_a
+  end for;
+end c10s01b00x00p11n01i00886cfg_a;
+
+ENTITY c10s01b00x00p11n01i00886ent IS
+END c10s01b00x00p11n01i00886ent;
+
+ARCHITECTURE c10s01b00x00p11n01i00886arch OF c10s01b00x00p11n01i00886ent IS
+  component ic_socket
+    generic (dummy_value : integer := 2);
+  end component;
+BEGIN
+  instance : ic_socket;
+
+END c10s01b00x00p11n01i00886arch;
+
+configuration c10s01b00x00p11n01i00886cfg of c10s01b00x00p11n01i00886ent is
+  for c10s01b00x00p11n01i00886arch    -- block_specification
+    use work.c10s01b00x00p11n01i00886pkg_a.x;    -- creates a declarative item in this region
+    for instance : ic_socket use configuration work.c10s01b00x00p11n01i00886cfg_a
+                               generic map ( passed_value => x, ignored_value => dummy_value );
+    end for;
+  end for;
+end c10s01b00x00p11n01i00886cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd
new file mode 100644
index 0000000..6ebb25c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc887.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p10n01i00887ent IS
+END c10s02b00x00p10n01i00887ent;
+
+ARCHITECTURE c10s02b00x00p10n01i00887arch OF c10s02b00x00p10n01i00887ent IS
+  function i_val ( a : integer ) return integer is
+  begin
+    return ( 2 * a );
+  end i_val;
+  signal i_sig : integer := 1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_val(i_sig) after 10 ns; -- declaration is visible.
+    wait for 11 ns;
+    assert NOT( i_sig = 2 )
+      report "***PASSED TEST: c10s02b00x00p10n01i00887"
+      severity NOTE;
+    assert ( i_sig = 2 )
+      report "***FAILED TEST: c10s02b00x00p10n01i00887 - The scope of the declaration extends to the end of the enclosing declaration when there is an absence of a separate subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p10n01i00887arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd
new file mode 100644
index 0000000..d07c093
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc888.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p10n01i00888ent IS
+END c10s02b00x00p10n01i00888ent;
+
+ARCHITECTURE c10s02b00x00p10n01i00888arch OF c10s02b00x00p10n01i00888ent IS
+  procedure xyz ( a : integer; b : real ) is
+  begin
+    assert NOT( b = 2.0 * real(a) ) 
+      report "***PASSED TEST: c10s02b00x00p10n01i00888"
+      severity NOTE;
+    assert ( b = 2.0 * real(a) ) 
+      report "***FAILED TEST: c10s02b00x00p10n01i00888 - When in the absence of a separate subprogram declaration, the subprogram specification given in the subprogram body acts as the declaration." 
+      severity ERROR;
+  end xyz;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    xyz ( a => 20, b => 40.0 );
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p10n01i00888arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd
new file mode 100644
index 0000000..5c84f60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc889.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c10s02b00x00p12n01i00889pkg IS
+  CONSTANT zero : INTEGER := 0;
+END c10s02b00x00p12n01i00889pkg;
+
+
+USE WORK.c10s02b00x00p12n01i00889pkg.all;
+ENTITY c10s02b00x00p12n01i00889ent_a IS
+  GENERIC ( I : INTEGER );
+END c10s02b00x00p12n01i00889ent_a;
+
+
+ARCHITECTURE c10s02b00x00p12n01i00889arch_a OF c10s02b00x00p12n01i00889ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+    assert NOT( I=0 )
+      report "***PASSED TEST: c10s02b00x00p12n01i00889"
+      severity NOTE;
+    assert ( I=0 )
+      report "***FAILED TEST: c10s02b00x00p12n01i00889"
+      severity ERROR;
+    wait;
+  END PROCESS;
+END;
+
+USE WORK.c10s02b00x00p12n01i00889pkg.all;
+ENTITY c10s02b00x00p12n01i00889ent IS
+END c10s02b00x00p12n01i00889ent;
+
+ARCHITECTURE c10s02b00x00p12n01i00889arch OF c10s02b00x00p12n01i00889ent IS
+
+  COMPONENT c10s02b00x00p12n01i00889ent_a
+  END COMPONENT;
+
+BEGIN
+  comp1 : c10s02b00x00p12n01i00889ent_a;
+
+END c10s02b00x00p12n01i00889arch;
+
+
+CONFIGURATION c10s02b00x00p12n01i00889cfg OF c10s02b00x00p12n01i00889ent IS
+  FOR c10s02b00x00p12n01i00889arch
+    FOR comp1 : c10s02b00x00p12n01i00889ent_a
+      USE ENTITY WORK.c10s02b00x00p12n01i00889ent_a(c10s02b00x00p12n01i00889arch_a) GENERIC MAP ( zero );
+    END FOR;
+  END FOR;
+END c10s02b00x00p12n01i00889cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd
new file mode 100644
index 0000000..45617db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc890.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n01i00890pkg is
+  function gimme_value return integer;
+end c10s02b00x00p02n01i00890pkg;
+
+package body c10s02b00x00p02n01i00890pkg is
+  constant x : integer := 10;    -- should not be visible outside
+  function gimme_value return integer is
+    constant x : integer := 0;    -- should only be visible inside
+  begin
+    return (x);
+  end;
+end c10s02b00x00p02n01i00890pkg;
+
+use work.c10s02b00x00p02n01i00890pkg.all;
+ENTITY c10s02b00x00p02n01i00890ent IS
+END c10s02b00x00p02n01i00890ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00890arch OF c10s02b00x00p02n01i00890ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 0 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00890"
+      severity NOTE;
+    assert ( gimme_value = 0 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00890 - A declaration in a subprogram extends only within the subprogram body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00890arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd
new file mode 100644
index 0000000..852d467
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc891.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00891ent IS
+END c10s02b00x00p02n02i00891ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00891arch OF c10s02b00x00p02n02i00891ent IS
+  type rec_typ is RECORD
+                    -- immediate scope
+                    r,g,b : real;
+                  end record;
+BEGIN
+  TESTING: PROCESS
+    -- extended scope
+    variable electron_gun : rec_typ := ( 0.25, 0.5, 1.0 );
+  BEGIN
+    assert NOT(   electron_gun.r   = 0.25   and
+                  electron_gun.g   = 0.5   and
+                  electron_gun.b   = 1.0   ) 
+      report "***PASSED TEST: c10s02b00x00p02n02i00891"
+      severity NOTE;
+    assert (   electron_gun.r   = 0.25   and
+               electron_gun.g   = 0.5   and
+               electron_gun.b   = 1.0   ) 
+      report "***FAILED TEST: c10s02b00x00p02n02i00891 - The scope of the declaration that occurs immediately within a record type declaration extends beyond the immediate scope"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00891arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd
new file mode 100644
index 0000000..d1201f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc892.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n01i00892pkg is
+  function gimme_value return integer;
+end c10s02b00x00p02n01i00892pkg;
+
+package body c10s02b00x00p02n01i00892pkg is
+  constant x : integer := 0; -- should not be visible outside
+  function gimme_value return integer is
+  begin
+    return (x);
+  end;
+end c10s02b00x00p02n01i00892pkg;
+
+
+use work.c10s02b00x00p02n01i00892pkg.all;
+ENTITY c10s02b00x00p02n01i00892ent IS
+END c10s02b00x00p02n01i00892ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00892arch OF c10s02b00x00p02n01i00892ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 0 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00892"
+      severity NOTE;
+    assert ( gimme_value = 0 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00892 - A declaration body extends only within the package body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00892arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd
new file mode 100644
index 0000000..b187c55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc893.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n01i00893ent IS
+END c10s02b00x00p02n01i00893ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00893arch OF c10s02b00x00p02n01i00893ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+
+    constant x : integer := 10;    -- should not be visible outside
+    function gimme_value return integer is
+    begin
+      return (x);
+    end;
+
+  BEGIN
+    assert NOT( gimme_value = 10 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00893"
+      severity NOTE;
+    assert ( gimme_value = 10 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00893 - A declaration in a process extends only within the process body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00893arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd
new file mode 100644
index 0000000..4b9d1c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc894.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n02i00894pkg is
+  -- immediate scope area
+  constant local : integer := 10;
+  function gimme_value return integer;
+end c10s02b00x00p02n02i00894pkg;
+
+Package body c10s02b00x00p02n02i00894pkg is
+  -- extended scope area
+  function gimme_value return integer is
+  begin
+    return (local);
+  end gimme_value;
+end c10s02b00x00p02n02i00894pkg;
+
+ENTITY c10s02b00x00p02n02i00894ent IS
+END c10s02b00x00p02n02i00894ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00894arch OF c10s02b00x00p02n02i00894ent IS
+  use work.c10s02b00x00p02n02i00894pkg.all;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 10 )
+      report "***PASSED TEST: c10s02b00x00p02n02i00894"
+      severity NOTE;
+    assert ( gimme_value = 10 )
+      report "***FAILED TEST: c10s02b00x00p02n02i00894 - The scope of the declaration that occurs immediately within a package declaration extends beyond the immediate scope"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00894arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd
new file mode 100644
index 0000000..800054e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc895.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00895ent IS
+  procedure xyz  ( a : integer; b : real );
+  procedure xyz ( a : integer; b : real ) is
+  begin
+    assert NOT( b = 2.0 * real(a) )   
+      report "***PASSED TEST: c10s02b00x00p02n02i00895"
+      severity NOTE;
+    assert ( b = 2.0 * real(a) )   
+      report "***FAILED TEST: c10s02b00x00p02n02i00895 - The scope of the declaration that occurs immediately within a formal parameter declaration extends beyond the immediate scope."
+      severity ERROR;
+  end xyz;
+END c10s02b00x00p02n02i00895ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00895arch OF c10s02b00x00p02n02i00895ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    xyz ( a => 20, b => 40.0 ); -- extended scope for the formals
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00895arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd
new file mode 100644
index 0000000..fae11c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc896.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00896ent IS
+  generic ( x : integer := 2 );
+END c10s02b00x00p02n02i00896ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00896arch OF c10s02b00x00p02n02i00896ent IS
+
+BEGIN
+  -- extended use of declared generic.
+  assert NOT( x = 2 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00896"
+    severity NOTE;
+  assert ( x = 2 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00896 - The scope of the declaration that occurs immediately within a formal generic declaration extends beyond the immediate scope."
+    severity ERROR;
+
+END c10s02b00x00p02n02i00896arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd
new file mode 100644
index 0000000..2dda296
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc897.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00897ent IS
+  port ( x : integer := 2 );
+END c10s02b00x00p02n02i00897ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00897arch OF c10s02b00x00p02n02i00897ent IS
+
+BEGIN
+  -- extended use of declared generic.
+  assert NOT( x = 2 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00897"
+    severity NOTE;
+  assert ( x = 2 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00897 - The scope of the declaration that occurs immediately within a formal port declaration in an entity declaration extends beyond the immediate scope."
+    severity ERROR;
+
+END c10s02b00x00p02n02i00897arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd
new file mode 100644
index 0000000..d95bdd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc898.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s02b00x00p02n02i00898ent_a is
+  generic ( g : integer := 1 );
+end c10s02b00x00p02n02i00898ent_a;
+
+architecture c10s02b00x00p02n02i00898arch_a of c10s02b00x00p02n02i00898ent_a is
+begin
+  assert NOT( g = 6 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00898"
+    severity NOTE;
+  assert ( g = 6 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00898 - Wrong generic value." 
+    severity ERROR;
+end c10s02b00x00p02n02i00898arch_a;
+
+
+ENTITY c10s02b00x00p02n02i00898ent IS
+END c10s02b00x00p02n02i00898ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00898arch OF c10s02b00x00p02n02i00898ent IS
+  component ic_socket
+    generic ( g : integer := 5 ); -- locally declared
+  end component;
+  for instance : ic_socket use entity work.c10s02b00x00p02n02i00898ent_a(c10s02b00x00p02n02i00898arch_a);
+BEGIN
+  instance : ic_socket generic map ( 6 );
+  TESTING: PROCESS
+  BEGIN
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00898arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd
new file mode 100644
index 0000000..bbf9afe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd
@@ -0,0 +1,195 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc90.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p01n01i00090ent IS
+END c04s03b02x00p01n01i00090ent;
+
+ARCHITECTURE c04s03b02x00p01n01i00090arch OF c04s03b02x00p01n01i00090ent IS
+
+  Procedure Variable_params_of_subp (
+    VARIABLE  cp1  : in      Boolean        := FALSE;
+    VARIABLE  cp2  : in      Bit            := '0';
+    VARIABLE  cp3  : in      Character      := '$';
+    VARIABLE  cp4  : in      SEVERITY_LEVEL := FAILURE;
+    VARIABLE  cp5  : in      Integer        := 5 + 6 ;
+    VARIABLE  cp6  : in      Real           := 2.45 ;
+    VARIABLE  cp7  : in      TIME           := 0 fs;
+    VARIABLE  cp8  : in      Natural        := 10;
+    VARIABLE  cp9  : in      Positive       := 99;
+    --
+    VARIABLE  cp12 : out     Boolean        ;
+    VARIABLE  cp13 : out     Bit            ;
+    VARIABLE  cp14 : out     Character      ;
+    VARIABLE  cp15 : out     SEVERITY_LEVEL ;
+    VARIABLE  cp16 : out     Integer        ;
+    VARIABLE  cp17 : out     Real           ;
+    VARIABLE  cp18 : out     TIME           ;
+    VARIABLE  cp19 : out     Natural        ;
+    VARIABLE  cp20 : out     Positive       ;
+    --
+    VARIABLE  cp23 : inout   Boolean        ;
+    VARIABLE  cp24 : inout   Bit            ;
+    VARIABLE  cp25 : inout   Character      ;
+    VARIABLE  cp26 : inout   SEVERITY_LEVEL ;
+    VARIABLE  cp27 : inout   Integer        ;
+    VARIABLE  cp28 : inout   Real           ;
+    VARIABLE  cp29 : inout   TIME           ;
+    VARIABLE  cp30 : inout   Natural        ;
+    VARIABLE  cp31 : inout   Positive
+    ) is
+  begin
+    -- assign ins to outs
+    cp12 := cp1   ;
+    cp13 := cp2   ;
+    cp14 := cp3   ;
+    cp15 := cp4   ;
+    cp16 := cp5   ;
+    cp17 := cp6   ;
+    cp18 := cp7   ;
+    cp19 := cp8   ;
+    cp20 := cp9   ;
+    
+    -- assign ins to inouts
+    cp23 := cp1   ;
+    cp24 := cp2   ;
+    cp25 := cp3   ;
+    cp26 := cp4   ;
+    cp27 := cp5   ;
+    cp28 := cp6   ;
+    cp29 := cp7   ;
+    cp30 := cp8   ;
+    cp31 := cp9   ;
+    
+  end Variable_params_of_subp;
+  
+BEGIN
+  TESTING: PROCESS
+    VARIABLE    v1  :    Boolean        := false;
+    VARIABLE    v2  :    Bit            := '1';
+    VARIABLE    v3  :    Character      := '%';
+    VARIABLE    v4  :    SEVERITY_LEVEL := NOTE;
+    VARIABLE    v5  :    Integer        := 22121;
+    VARIABLE    v6  :    Real           := 2.545;
+    VARIABLE    v7  :    TIME           := 12 ns;
+    VARIABLE    v8  :    Natural        := 90;
+    VARIABLE    v9  :    Positive       := 101;
+    
+    VARIABLE    v12 :  Boolean        ;
+    VARIABLE    v13 :  Bit            ;
+    VARIABLE    v14 :  Character      ;
+    VARIABLE    v15 :  SEVERITY_LEVEL ;
+    VARIABLE    v16 :  Integer        ;
+    VARIABLE    v17 :  Real           ;
+    VARIABLE    v18 :  TIME           ;
+    VARIABLE    v19 :  Natural        ;
+    VARIABLE    v20 :  Positive       ;
+    
+    VARIABLE    v23 :  Boolean        ;
+    VARIABLE    v24 :  Bit            ;
+    VARIABLE    v25 :  Character      ;
+    VARIABLE    v26 :  SEVERITY_LEVEL ;
+    VARIABLE    v27 :  Integer        ;
+    VARIABLE    v28 :  Real           ;
+    VARIABLE    v29 :  TIME           ;
+    VARIABLE    v30 :  Natural        ;
+    VARIABLE    v31 :  Positive       ;
+
+  BEGIN
+
+    Variable_params_of_subp ( v1,v2,v3,v4,v5,v6,v7,v8,v9,
+                              v12,v13,v14,v15,v16,v17,v18,v19,v20,
+                              v23,v24,v25,v26,v27,v28,v29,v30,v31
+                              );
+
+    assert   v12 = v1 report "  v12 /= v1" severity failure;
+    assert   v13 = v2 report "  v13 /= v2" severity failure;
+    assert   v14 = v3 report "  v14 /= v3" severity failure;
+    assert   v15 = v4 report "  v15 /= v4" severity failure;
+    assert   v16 = v5 report "  v16 /= v5" severity failure;
+    assert   v17 = v6 report "  v17 /= v6" severity failure;
+    assert   v18 = v7 report "  v18 /= v7" severity failure;
+    assert   v19 = v8 report "  v19 /= v8" severity failure;
+    assert   v20 = v9 report "  v20 /= v9" severity failure;
+    
+    assert   v23 = v1 report "  v23 /= v1" severity failure;
+    assert   v24 = v2 report "  v24 /= v2" severity failure;
+    assert   v25 = v3 report "  v25 /= v3" severity failure;
+    assert   v26 = v4 report "  v26 /= v4" severity failure;
+    assert   v27 = v5 report "  v27 /= v5" severity failure;
+    assert   v28 = v6 report "  v28 /= v6" severity failure;
+    assert   v29 = v7 report "  v29 /= v7" severity failure;
+    assert   v30 = v8 report "  v30 /= v8" severity failure;
+    assert   v31 = v9 report "  v31 /= v9" severity failure;
+    WAIT for 1 ns;
+
+    assert NOT(       v12 = v1    and
+                      v13 = v2    and
+                      v14 = v3    and
+                      v15 = v4    and
+                      v16 = v5    and
+                      v17 = v6    and
+                      v18 = v7    and
+                      v19 = v8    and
+                      v20 = v9    and
+                      v23 = v1    and
+                      v24 = v2    and
+                      v25 = v3    and
+                      v26 = v4    and
+                      v27 = v5    and
+                      v28 = v6    and
+                      v29 = v7    and
+                      v30 = v8    and
+                      v31 = v9    )   
+      report "***PASSED TEST:c04s03b02x00p01n01i00090"
+      severity NOTE;
+    assert (            v12 = v1    and
+                        v13 = v2    and
+                        v14 = v3    and
+                        v15 = v4    and
+                        v16 = v5    and
+                        v17 = v6    and
+                        v18 = v7    and
+                        v19 = v8    and
+                        v20 = v9    and
+                        v23 = v1    and
+                        v24 = v2    and
+                        v25 = v3    and
+                        v26 = v4    and
+                        v27 = v5    and
+                        v28 = v6    and
+                        v29 = v7    and
+                        v30 = v8    and
+                        v31 = v9    )   
+      report "***FAILED TEST: c04s03b02x00p01n01i00090 - Variables as the interface objects that appear as variable parameters of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p01n01i00090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd
new file mode 100644
index 0000000..5afadc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc900.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p04n01i00900pkg_1 is
+  type MVL1 is (LOW,HIGH,RISING);
+  type MVL2 is (LOW,HIGH,RISING,FALLING,AMBIGUOUS);
+end c10s03b00x00p04n01i00900pkg_1;
+
+use work.c10s03b00x00p04n01i00900pkg_1.all;
+ENTITY c10s03b00x00p04n01i00900ent IS
+END c10s03b00x00p04n01i00900ent;
+
+ARCHITECTURE c10s03b00x00p04n01i00900arch OF c10s03b00x00p04n01i00900ent IS
+  signal S1 : MVL2;
+  signal S2 : MVL2;
+  signal S3 : MVL2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= LOW;           -- No_failure_here
+    S2 <= HIGH;        -- No_failure_here
+    S3 <= RISING;        -- No_failure_here
+    wait for 5 ns;
+    assert NOT(S1 = LOW and S2 = HIGH and S3 = RISING)
+      report "***PASSED TEST: c10s03b00x00p04n01i00900" 
+      severity NOTE;
+    assert (S1 = LOW and S2 = HIGH and S3 = RISING)
+      report "***FAILED TEST: c10s03b00x00p04n01i00900 - The occurence of the identifier is legal if and only if exactly one visible declaration is acceptable for the overloading rules in the given context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p04n01i00900arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd
new file mode 100644
index 0000000..8f44c3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00902ent IS
+  type work is (foo,bar); -- No_Failure_here
+END c10s03b00x00p05n01i00902ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var : work := foo;
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var = foo )
+      report "***PASSED TEST: c10s03b00x00p05n01i00902"
+      severity NOTE;
+    assert ( var = foo )
+      report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00902arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd
new file mode 100644
index 0000000..00b9aae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd
@@ -0,0 +1,300 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c04s03b02x00p01n01i00091pkg IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      --unconstrained array type
+
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          --constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  --unconstrained array subtype
+
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    --constrained array subtype
+
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    --constrained array subtype
+
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+
+END c04s03b02x00p01n01i00091pkg;
+
+
+USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
+ENTITY c04s03b02x00p01n01i00091ent_a IS
+  PORT (
+    SIGNAL     STRING_prt : IN     STRING (1 TO 7);
+    SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
+    SIGNAL   ut_chary_prt : IN   ut_chary (NUL TO ENQ);
+    SIGNAL    ct_word_prt : IN    ct_word;
+    SIGNAL  cst_str10_prt : IN  cst_str10;
+    SIGNAL  cst_digit_prt : IN  cst_digit;
+    SIGNAL    rt_date_prt : IN    rt_date;
+    SIGNAL   rst_date_prt : IN   rst_date
+    );
+END c04s03b02x00p01n01i00091ent_a;
+
+
+
+ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+--
+    FOR I IN 1 TO 7
+    LOOP
+      ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN 0 TO 7
+    LOOP
+      ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN NUL TO ENQ
+    LOOP
+      ASSERT ut_chary_prt(I) = INTEGER'LEFT
+        REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN 0 TO 15
+    LOOP
+      ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    FOR I IN 1 TO 10
+    LOOP
+      ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN '0' TO '9'
+    LOOP
+      ASSERT cst_digit_prt(I) = INTEGER'LEFT
+        REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE;      END LOOP;
+    
+    ASSERT  rt_date_prt.day   = 0    REPORT " rt_date_prt.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_prt.month = Jan  REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_prt.year  = 0    REPORT " rt_date_prt.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_prt.day   = 0    REPORT "rst_date_prt.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_prt.month = Jan  REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_prt.year  = 0    REPORT "rst_date_prt.year  not properly intialized" SEVERITY FAILURE;
+    
+    
+    assert NOT(   STRING_prt(1)      = NUL   and
+                  STRING_prt(2)      = NUL   and   
+                  STRING_prt(3)      = NUL   and   
+                  STRING_prt(4)      = NUL   and   
+                  STRING_prt(5)      = NUL   and   
+                  STRING_prt(6)      = NUL   and   
+                  STRING_prt(7)      = NUL   and   
+                  BIT_VECTOR_prt(1)   = '0'   and
+                  BIT_VECTOR_prt(2)   = '0'   and
+                  BIT_VECTOR_prt(3)   = '0'   and
+                  BIT_VECTOR_prt(4)   = '0'   and
+                  BIT_VECTOR_prt(5)   = '0'   and
+                  BIT_VECTOR_prt(6)   = '0'   and
+                  BIT_VECTOR_prt(7)   = '0'   and
+                  ut_chary_prt(NUL)   = integer'left   and
+                  ut_chary_prt(SOH)   = integer'left   and
+                  ut_chary_prt(STX)   = integer'left   and
+                  ut_chary_prt(ETX)   = integer'left   and
+                  ut_chary_prt(EOT)   = integer'left   and
+                  ut_chary_prt(ENQ)   = integer'left   and
+                  ct_word_prt( 0)      = '0'   and
+                  ct_word_prt( 1)      = '0'   and
+                  ct_word_prt( 2)      = '0'   and
+                  ct_word_prt( 3)      = '0'   and
+                  ct_word_prt( 4)      = '0'   and
+                  ct_word_prt( 5)      = '0'   and
+                  ct_word_prt( 6)      = '0'   and
+                  ct_word_prt( 7)      = '0'   and
+                  ct_word_prt( 8)      = '0'   and
+                  ct_word_prt( 9)      = '0'   and
+                  ct_word_prt(10)      = '0'   and
+                  ct_word_prt(11)      = '0'   and
+                  ct_word_prt(12)      = '0'   and
+                  ct_word_prt(13)      = '0'   and
+                  ct_word_prt(14)      = '0'   and
+                  ct_word_prt(15)      = '0'   and
+                  cst_str10_prt( 1)   = NUL   and
+                  cst_str10_prt( 2)   = NUL   and
+                  cst_str10_prt( 3)   = NUL   and
+                  cst_str10_prt( 4)   = NUL   and
+                  cst_str10_prt( 5)   = NUL   and
+                  cst_str10_prt( 6)   = NUL   and
+                  cst_str10_prt( 7)   = NUL   and
+                  cst_str10_prt( 8)   = NUL   and
+                  cst_str10_prt( 9)   = NUL   and
+                  cst_str10_prt(10)   = NUL   and
+                  cst_digit_prt('0')   = integer'left   and
+                  cst_digit_prt('1')   = integer'left   and
+                  cst_digit_prt('2')   = integer'left   and
+                  cst_digit_prt('3')   = integer'left   and
+                  cst_digit_prt('4')   = integer'left   and
+                  cst_digit_prt('5')   = integer'left   and
+                  cst_digit_prt('6')   = integer'left   and
+                  cst_digit_prt('7')   = integer'left   and
+                  cst_digit_prt('8')   = integer'left   and
+                  cst_digit_prt('9')   = integer'left   and
+                  rt_date_prt.day      = 0   and
+                  rt_date_prt.month   = Jan   and
+                  rt_date_prt.year   = 0   and
+                  rst_date_prt.day   = 0   and
+                  rst_date_prt.month   = Jan   and
+                  rst_date_prt.year   = 0   )
+      report "***PASSED TEST: c04s03b02x00p01n01i00091"
+      severity NOTE;
+    assert (   STRING_prt(1)      = NUL   and
+               STRING_prt(2)      = NUL   and   
+               STRING_prt(3)      = NUL   and   
+               STRING_prt(4)      = NUL   and   
+               STRING_prt(5)      = NUL   and   
+               STRING_prt(6)      = NUL   and   
+               STRING_prt(7)      = NUL   and   
+               BIT_VECTOR_prt(1)   = '0'   and
+               BIT_VECTOR_prt(2)   = '0'   and
+               BIT_VECTOR_prt(3)   = '0'   and
+               BIT_VECTOR_prt(4)   = '0'   and
+               BIT_VECTOR_prt(5)   = '0'   and
+               BIT_VECTOR_prt(6)   = '0'   and
+               BIT_VECTOR_prt(7)   = '0'   and
+               ut_chary_prt(NUL)   = integer'left   and
+               ut_chary_prt(SOH)   = integer'left   and
+               ut_chary_prt(STX)   = integer'left   and
+               ut_chary_prt(ETX)   = integer'left   and
+               ut_chary_prt(EOT)   = integer'left   and
+               ut_chary_prt(ENQ)   = integer'left   and
+               ct_word_prt( 0)      = '0'   and
+               ct_word_prt( 1)      = '0'   and
+               ct_word_prt( 2)      = '0'   and
+               ct_word_prt( 3)      = '0'   and
+               ct_word_prt( 4)      = '0'   and
+               ct_word_prt( 5)      = '0'   and
+               ct_word_prt( 6)      = '0'   and
+               ct_word_prt( 7)      = '0'   and
+               ct_word_prt( 8)      = '0'   and
+               ct_word_prt( 9)      = '0'   and
+               ct_word_prt(10)      = '0'   and
+               ct_word_prt(11)      = '0'   and
+               ct_word_prt(12)      = '0'   and
+               ct_word_prt(13)      = '0'   and
+               ct_word_prt(14)      = '0'   and
+               ct_word_prt(15)      = '0'   and
+               cst_str10_prt( 1)   = NUL   and
+               cst_str10_prt( 2)   = NUL   and
+               cst_str10_prt( 3)   = NUL   and
+               cst_str10_prt( 4)   = NUL   and
+               cst_str10_prt( 5)   = NUL   and
+               cst_str10_prt( 6)   = NUL   and
+               cst_str10_prt( 7)   = NUL   and
+               cst_str10_prt( 8)   = NUL   and
+               cst_str10_prt( 9)   = NUL   and
+               cst_str10_prt(10)   = NUL   and
+               cst_digit_prt('0')   = integer'left   and
+               cst_digit_prt('1')   = integer'left   and
+               cst_digit_prt('2')   = integer'left   and
+               cst_digit_prt('3')   = integer'left   and
+               cst_digit_prt('4')   = integer'left   and
+               cst_digit_prt('5')   = integer'left   and
+               cst_digit_prt('6')   = integer'left   and
+               cst_digit_prt('7')   = integer'left   and
+               cst_digit_prt('8')   = integer'left   and
+               cst_digit_prt('9')   = integer'left   and
+               rt_date_prt.day      = 0   and
+               rt_date_prt.month   = Jan   and
+               rt_date_prt.year   = 0   and
+               rst_date_prt.day   = 0   and
+               rst_date_prt.month   = Jan   and
+               rst_date_prt.year   = 0   )
+      report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c04s03b02x00p01n01i00091arch_a;
+
+
+USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
+ENTITY c04s03b02x00p01n01i00091ent IS
+END c04s03b02x00p01n01i00091ent;
+
+ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
+  COMPONENT c04s03b02x00p01n01i00091ent_a
+    PORT (
+      SIGNAL     STRING_prt : IN     STRING (1 TO 7);
+      SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
+      SIGNAL   ut_chary_prt : IN   ut_chary (NUL TO ENQ);
+      SIGNAL    ct_word_prt : IN    ct_word;
+      SIGNAL  cst_str10_prt : IN  cst_str10;
+      SIGNAL  cst_digit_prt : IN  cst_digit;
+      SIGNAL    rt_date_prt : IN    rt_date;
+      SIGNAL   rst_date_prt : IN   rst_date
+      );
+  END COMPONENT;
+  for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
+  
+  SIGNAL     STRING_prt :     STRING (1 TO 7);
+  SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
+  SIGNAL   ut_chary_prt :   ut_chary (NUL TO ENQ);
+  SIGNAL    ct_word_prt :    ct_word;
+  SIGNAL  cst_str10_prt :  cst_str10;
+  SIGNAL  cst_digit_prt :  cst_digit;
+  SIGNAL    rt_date_prt :    rt_date;
+  SIGNAL   rst_date_prt :   rst_date;
+  
+BEGIN
+  C : c04s03b02x00p01n01i00091ent_a
+    PORT MAP ( STRING_prt,
+               BIT_VECTOR_prt,
+               ut_chary_prt,
+               ct_word_prt,
+               cst_str10_prt,
+               cst_digit_prt,
+               rt_date_prt,
+               rst_date_prt );
+  
+
+END c04s03b02x00p01n01i00091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd
new file mode 100644
index 0000000..0c986d1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc911.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p07n01i00911ent_a is
+end c10s03b00x00p07n01i00911ent_a;
+
+architecture c10s03b00x00p07n01i00911arch_a of c10s03b00x00p07n01i00911ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c10s03b00x00p07n01i00911"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p07n01i00911arch_a;
+
+
+ENTITY c10s03b00x00p07n01i00911ent IS
+END c10s03b00x00p07n01i00911ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00911arch OF c10s03b00x00p07n01i00911ent IS
+  component device
+  end component;
+
+  -- selected use of configuration primary unit
+  for all : device use entity work.c10s03b00x00p07n01i00911ent_a(c10s03b00x00p07n01i00911arch_a);
+BEGIN
+  instance : device;
+END c10s03b00x00p07n01i00911arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd
new file mode 100644
index 0000000..b4cec7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc912.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00912pkg is
+  constant x : integer := 2;
+end c10s03b00x00p07n01i00912pkg;
+
+ENTITY c10s03b00x00p07n01i00912ent IS
+END c10s03b00x00p07n01i00912ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00912arch OF c10s03b00x00p07n01i00912ent IS
+  -- selected use of package element
+  use work.c10s03b00x00p07n01i00912pkg.x;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=2 )
+      report "***PASSED TEST: c10s03b00x00p07n01i00912"
+      severity NOTE;
+    assert ( x=2 )
+      report "***FAILED TEST: c10s03b00x00p07n01i00912 - A primary unit of a library can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p07n01i00912arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd
new file mode 100644
index 0000000..65cde69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc913.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00913pkg is
+  -- It is OK to define a type that overrides the name of a library
+  type work is (foo, bar);   -- No_failure_here
+end c10s03b00x00p07n01i00913pkg;
+
+use work.c10s03b00x00p07n01i00913pkg.all;
+ENTITY c10s03b00x00p07n01i00913ent IS
+END c10s03b00x00p07n01i00913ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00913arch OF c10s03b00x00p07n01i00913ent IS
+
+BEGIN
+  TESTING : PROCESS
+    -- This succeeds in finding type "work" defined in package "c10s03b00x00p07n01i00913pkg"
+    -- in library "work"
+    variable doit : work.c10s03b00x00p07n01i00913pkg.work ;   -- No_failure_here
+  BEGIN
+    doit := foo;
+    wait for 5 ns;
+    assert NOT(doit = foo) 
+      report "***PASSED TEST: c10s03b00x00p07n01i00913"
+      severity NOTE;
+    assert (doit = foo) 
+      report "***FAILED TEST: c10s03b00x00p07n01i00913 - A declaration can be visible by selection for a primary unit contained in a library."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c10s03b00x00p07n01i00913arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd
new file mode 100644
index 0000000..d55d618
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc914.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00914pkg is
+  type c10s03b00x00p07n01i00914pkg is (a,b);
+end c10s03b00x00p07n01i00914pkg;
+
+use work.all;
+ENTITY c10s03b00x00p07n01i00914ent IS
+END c10s03b00x00p07n01i00914ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00914arch OF c10s03b00x00p07n01i00914ent IS
+  signal S : c10s03b00x00p07n01i00914pkg.c10s03b00x00p07n01i00914pkg;
+BEGIN
+  TESTING: PROCESS
+    use work.c10s03b00x00p07n01i00914pkg.all;
+  BEGIN
+    S <= a after 5 ns;
+    wait for 10 ns;
+    assert NOT( S = a )
+      report "***PASSED TEST: c10s03b00x00p07n01i00914"
+      severity NOTE;
+    assert ( S = a )
+      report "***FAILED TEST: c10s03b00x00p07n01i00914 - A primary unit of a library can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p07n01i00914arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd
new file mode 100644
index 0000000..6a3a283
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc915.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p08n01i00915ent IS
+END c10s03b00x00p08n01i00915ent;
+
+ARCHITECTURE c10s03b00x00p08n01i00915arch OF c10s03b00x00p08n01i00915ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c10s03b00x00p08n01i00915"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p08n01i00915arch;
+
+ARCHITECTURE c10s03b00x00p08n01i00915arch_a OF c10s03b00x00p08n01i00915ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c10s03b00x00p08n01i00915 - An architecture body of an entity can be visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p08n01i00915arch_a;
+
+configuration c10s03b00x00p08n01i00915cfg of c10s03b00x00p08n01i00915ent is
+  -- select the architecture you want.
+  for c10s03b00x00p08n01i00915arch
+  end for;
+end c10s03b00x00p08n01i00915cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd
new file mode 100644
index 0000000..c572be2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc916.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p10n01i00916pkg is
+  constant x : integer := 2;
+end c10s03b00x00p10n01i00916pkg;
+
+ENTITY c10s03b00x00p10n01i00916ent IS
+END c10s03b00x00p10n01i00916ent;
+
+ARCHITECTURE c10s03b00x00p10n01i00916arch OF c10s03b00x00p10n01i00916ent IS
+
+  -- selected use of package element
+  use work.c10s03b00x00p10n01i00916pkg.x;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=2 )
+      report "***PASSED TEST: c10s03b00x00p10n01i00916"
+      severity NOTE;
+    assert ( x=2 )
+      report "***FAILED TEST: c10s03b00x00p10n01i00916 - A declaration ina package can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p10n01i00916arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd
new file mode 100644
index 0000000..60e0ce3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc917.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c04s04b00x00p02n01i00917ent_a is
+  generic ( i_generic : integer; r_generic : real );
+end c04s04b00x00p02n01i00917ent_a;
+
+architecture c04s04b00x00p02n01i00917arch_a of c04s04b00x00p02n01i00917ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( i_generic = 0 and r_generic = 15.0 )
+      report "***PASSED TEST: c04s04b00x00p02n01i00917"
+      severity NOTE;
+    assert ( i_generic = 0 and r_generic = 15.0 )
+      report "***FAILED TEST: c04s04b00x00p02n01i00917 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c04s04b00x00p02n01i00917arch_a;
+
+
+ENTITY c04s04b00x00p02n01i00917ent IS
+  subtype    register16    is bit_vector(15 downto 0);
+  constant    reg :    register16 := B"1001_0001_1010_1111";
+END c04s04b00x00p02n01i00917ent;
+
+ARCHITECTURE c04s04b00x00p02n01i00917arch OF c04s04b00x00p02n01i00917ent IS
+  component d
+    generic ( i_generic : integer := 1; r_generic : real := 2.0 );
+  end component;
+  for instance : d use entity work.c04s04b00x00p02n01i00917ent_a(c04s04b00x00p02n01i00917arch_a);
+BEGIN
+  instance : d generic map (reg'low, real(reg'high));
+  assert ( reg'low   = 0 )  report "reg'low   /= 0"  severity FAILURE;
+  assert ( reg'high  = 15 ) report "reg'high  /= 15" severity FAILURE;
+  assert ( reg'right = 0 )  report "reg'right /= 0"  severity FAILURE;
+  assert ( reg'left  = 15 ) report "reg'left  /= 15" severity FAILURE;
+
+END c04s04b00x00p02n01i00917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd
new file mode 100644
index 0000000..51c0cdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc918.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p13n01i00918ent IS
+  procedure subprogram ( a : integer; b : real ) is
+  begin
+    assert ( b = real (a) ) report "not the same" severity FAILURE;
+    assert NOT( b = real(a) )
+      report "***PASSED TEST: c10s03b00x00p13n01i00918"
+      severity NOTE;
+    assert ( b = real(a) )
+      report "***FAILED TEST: c10s03b00x00p13n01i00918 - "
+      severity ERROR;
+  end subprogram;
+END c10s03b00x00p13n01i00918ent;
+
+ARCHITECTURE c10s03b00x00p13n01i00918arch OF c10s03b00x00p13n01i00918ent IS
+
+BEGIN
+  subprogram ( a => 10  , b => 10.0 );
+
+END c10s03b00x00p13n01i00918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd
new file mode 100644
index 0000000..8a35217
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p14n01i00919ent_a is
+  generic ( x : integer; y : real );
+end c10s03b00x00p14n01i00919ent_a;
+
+architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is
+begin
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( real(x) = y )
+      report "***PASSED TEST: c10s03b00x00p14n01i00919"
+      severity NOTE;
+    assert ( real(x) = y )
+      report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p14n01i00919arch_a;
+
+
+ENTITY c10s03b00x00p14n01i00919ent IS
+END c10s03b00x00p14n01i00919ent;
+
+ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS
+  component d
+    generic ( a : integer; b : real );
+  end component;
+BEGIN
+  instance : d generic map (a => 10, b => 10.0);
+
+END c10s03b00x00p14n01i00919arch;
+
+
+configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is
+  for c10s03b00x00p14n01i00919arch
+    for instance : d
+      use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b);
+    end for;
+  end for;
+end c10s03b00x00p14n01i00919cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd
new file mode 100644
index 0000000..f59dfaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc920.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p15n01i00920ent_a is
+  port ( x : integer; y : real );
+end c10s03b00x00p15n01i00920ent_a;
+
+architecture c10s03b00x00p15n01i00920arch_a of c10s03b00x00p15n01i00920ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x) = y )
+      report "***PASSED TEST: c10s03b00x00p15n01i00920"
+      severity NOTE;
+    assert ( real(x) = y )
+      report "***FAILED TEST: c10s03b00x00p15n01i00920 - The named associated local ports can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p15n01i00920arch_a;
+
+ENTITY c10s03b00x00p15n01i00920ent IS
+END c10s03b00x00p15n01i00920ent;
+
+ARCHITECTURE c10s03b00x00p15n01i00920arch OF c10s03b00x00p15n01i00920ent IS
+  component d
+    port ( a : integer; b : real );
+  end component;
+  signal a : integer := 10;
+  signal b : real    := 10.0;
+BEGIN
+
+  instance : d port map ( a => a, b => b );
+
+END c10s03b00x00p15n01i00920arch;
+
+configuration c10s03b00x00p15n01i00920cfg of c10s03b00x00p15n01i00920ent is
+  for c10s03b00x00p15n01i00920arch
+    for instance : d
+      use entity work.c10s03b00x00p15n01i00920ent_a(c10s03b00x00p15n01i00920arch_a) port map ( x => a, y => b );
+    end for;
+  end for;
+end c10s03b00x00p15n01i00920cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd
new file mode 100644
index 0000000..48ff8a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc921.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p16n01i00921ent_a is
+  generic ( x : integer; y : real );
+end c10s03b00x00p16n01i00921ent_a;
+
+architecture c10s03b00x00p16n01i00921arch_a of c10s03b00x00p16n01i00921ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x)=y )
+      report "***PASSED TEST: c10s03b00x00p16n01i00921"
+      severity NOTE;
+    assert ( real(x)=y )
+      report "***FAILED TEST: c10s03b00x00p16n01i00921 - Named associated formal generic can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p16n01i00921arch_a;
+
+ENTITY c10s03b00x00p16n01i00921ent IS
+END c10s03b00x00p16n01i00921ent;
+
+ARCHITECTURE c10s03b00x00p16n01i00921arch OF c10s03b00x00p16n01i00921ent IS
+  component d
+  end component;
+BEGIN
+  instance : d;
+
+END c10s03b00x00p16n01i00921arch;
+
+configuration c10s03b00x00p16n01i00921cfg of c10s03b00x00p16n01i00921ent is
+  for c10s03b00x00p16n01i00921arch
+    for instance : d
+      use entity work.c10s03b00x00p16n01i00921ent_a(c10s03b00x00p16n01i00921arch_a) generic map ( x => 10, y => 10.0 );
+    end for;
+  end for;
+end c10s03b00x00p16n01i00921cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd
new file mode 100644
index 0000000..dc05393
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc922.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p17n01i00922ent_a is
+  port ( x : integer; y : real );
+end c10s03b00x00p17n01i00922ent_a;
+
+architecture c10s03b00x00p17n01i00922arch_a of c10s03b00x00p17n01i00922ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x)=y )
+      report "***PASSED TEST: c10s03b00x00p17n01i00922"
+      severity NOTE;
+    assert ( real(x)=y )
+      report "***FAILED TEST: c10s03b00x00p17n01i00922 - Named formal ports can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p17n01i00922arch_a;
+
+ENTITY c10s03b00x00p17n01i00922ent IS
+END c10s03b00x00p17n01i00922ent;
+
+ARCHITECTURE c10s03b00x00p17n01i00922arch OF c10s03b00x00p17n01i00922ent IS
+  component d
+  end component;
+  signal a : integer := 10;
+  signal b : real    := 10.0;
+BEGIN
+  instance : d;
+
+END c10s03b00x00p17n01i00922arch;
+
+configuration c10s03b00x00p17n01i00922cfg of c10s03b00x00p17n01i00922ent is
+  for c10s03b00x00p17n01i00922arch
+    for instance : d
+      use entity work.c10s03b00x00p17n01i00922ent_a(c10s03b00x00p17n01i00922arch_a) port map ( x => a, y => b );
+    end for;
+  end for;
+end c10s03b00x00p17n01i00922cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd
new file mode 100644
index 0000000..fc61724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc923.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p19n01i00923ent IS
+  type primary is ( red, green, blue );
+END c10s03b00x00p19n01i00923ent;
+
+ARCHITECTURE c10s03b00x00p19n01i00923arch OF c10s03b00x00p19n01i00923ent IS
+
+  procedure xxx is
+    type    primary is ( red, green, blue );
+    constant x : c10s03b00x00p19n01i00923ent.primary := red;
+  begin
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s03b00x00p19n01i00923"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s03b00x00p19n01i00923 - The declarations can be made visible by providing a prefix to the declaration to specify where it had been declared."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+END c10s03b00x00p19n01i00923arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd
new file mode 100644
index 0000000..8b2c363
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc924.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p20n03i00924pkg is
+  type primary is ( red, green, blue );
+end c10s03b00x00p20n03i00924pkg;
+
+
+ENTITY c10s03b00x00p20n03i00924ent IS
+  type primary is ( yellow, pink, orange );
+END c10s03b00x00p20n03i00924ent;
+
+ARCHITECTURE c10s03b00x00p20n03i00924arch OF c10s03b00x00p20n03i00924ent IS
+  procedure xxx is
+    use    work.c10s03b00x00p20n03i00924pkg.all;
+    variable x : work.c10s03b00x00p20n03i00924pkg.primary;
+  begin
+    x := red;
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s03b00x00p20n03i00924"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s03b00x00p20n03i00924 - A use clause can make a declaration visible and hide a local declaration."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s03b00x00p20n03i00924arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd
new file mode 100644
index 0000000..97edf5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p22n01i00925ent IS
+END c10s03b00x00p22n01i00925ent;
+
+ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
+  constant x : integer := 3;
+  procedure xxx is
+    constant x : integer := 5;
+    variable y : bit;
+  begin
+    if x > 3 then 
+      y := '1';
+    else 
+      y := '0';
+    end if;
+    assert NOT( y='1' )
+      report "***PASSED TEST: c10s03b00x00p22n01i00925"
+      severity NOTE;
+    assert ( y='1' )
+      report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s03b00x00p22n01i00925arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd
new file mode 100644
index 0000000..86aa88b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc926.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p23n01i00926ent IS
+END c10s03b00x00p23n01i00926ent;
+
+ARCHITECTURE c10s03b00x00p23n01i00926arch OF c10s03b00x00p23n01i00926ent IS
+  type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' );
+  type std_logic_vector is array ( natural range <> ) of std_logic;
+
+  function "+" ( l,r : bit_vector ) return bit_vector is
+    variable lr : bit_vector ( 1 to l'length ) := l;
+    variable rr : bit_vector ( 1 to r'length ) := r;
+    variable result : bit_vector ( 1 to l'length );
+    variable carry : bit := '0';
+  begin
+    for i in l'length downto 1 loop
+      result(i) := lr(i) xor rr(i) xor carry;
+      carry := (lr(i) and rr(i)) or
+               (rr(i) and carry) or
+               (lr(i) and carry);
+    end loop;
+    return (result);
+  end;
+
+  -- homograph
+  function "+" ( l,r : std_logic_vector ) return std_logic_vector is
+  begin
+  end; 
+
+  signal a : bit_vector ( 15 downto 0 ) := B"0010001010100010";
+  signal b : bit_vector ( 15 downto 0 ) := B"0101111101011101";
+  signal s : bit_vector ( 15 downto 0 );
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s <= (a + b) after 10 ns;
+    wait for 11 ns;
+    assert NOT( s = B"1000000111111111" )
+      report "***PASSED TEST: c10s03b00x00p23n01i00926"
+      severity NOTE;
+    assert ( s = B"1000000111111111" )
+      report "***FAILED TEST: c10s03b00x00p23n01i00926 - If one of the two declarations is the implicit declaration of a predefined operation, the predefined operation is laways hidden by teh other homograph."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p23n01i00926arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd
new file mode 100644
index 0000000..00fb47c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc927.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p01n01i00927pkg is
+  type work is array(0 to 7) of BIT;
+end c10s04b00x00p01n01i00927pkg;
+
+use  work.c10s04b00x00p01n01i00927pkg.all;
+ENTITY c10s04b00x00p01n01i00927ent IS
+  port (P : in  bit);
+END c10s04b00x00p01n01i00927ent;
+
+ARCHITECTURE c10s04b00x00p01n01i00927arch OF c10s04b00x00p01n01i00927ent IS
+  use  work.c10s04b00x00p01n01i00927pkg;
+BEGIN
+  TESTING: PROCESS(P)
+    -- This succeeds because type work is defined in package c10s04b00x00p01n01i00927pkg,
+    -- there is no conflict with library "work"
+    variable doit : c10s04b00x00p01n01i00927pkg.work ;  -- No_failure_here
+  BEGIN
+    assert NOT(doit="00000000") 
+      report "***PASSED TEST: c10s04b00x00p01n01i00927"
+      severity NOTE;
+    assert (doit="00000000") 
+      report "***FAILED TEST: c10s04b00x00p01n01i00927 - Use clause do not make that declaration visible." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c10s04b00x00p01n01i00927arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd
new file mode 100644
index 0000000..16e1548
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc930.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n01i00930pkg is
+  constant x : integer := 2;
+  constant y : real := 5.0;
+  subtype register16 is bit_vector(15 downto 0);
+  function "+" (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p03n01i00930pkg;
+
+package body c10s04b00x00p03n01i00930pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+end c10s04b00x00p03n01i00930pkg;
+
+
+use work.c10s04b00x00p03n01i00930pkg."+";
+use work.c10s04b00x00p03n01i00930pkg.register16;
+ENTITY c10s04b00x00p03n01i00930ent IS
+END c10s04b00x00p03n01i00930ent;
+
+ARCHITECTURE c10s04b00x00p03n01i00930arch OF c10s04b00x00p03n01i00930ent IS
+  signal   i_sig  :  register16 := B"1010_1110_1010_0011";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig + i_sig after 10 ns;
+    wait for 11 ns;
+    assert NOT(i_sig = "1111010100101010")
+      report "***PASSED TEST: c10s04b00x00p03n01i00930"
+      severity NOTE;
+    assert (i_sig = "1111010100101010")
+      report "***FAILED TEST: c10s04b00x00p03n01i00930 - The operator is visible in the declaration region if the suffix of a selected name in a use clause is an operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n01i00930arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd
new file mode 100644
index 0000000..eac447d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc931.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n01i00931pkg is
+  constant x : integer := 2;
+  constant y : real := 5.0;
+  subtype register16 is bit_vector(15 downto 0);
+end c10s04b00x00p03n01i00931pkg;
+
+
+use work.c10s04b00x00p03n01i00931pkg.x;
+ENTITY c10s04b00x00p03n01i00931ent IS
+END c10s04b00x00p03n01i00931ent;
+
+ARCHITECTURE c10s04b00x00p03n01i00931arch OF c10s04b00x00p03n01i00931ent IS
+  signal   i_sig  :  integer := x; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig + x after 10 ns;
+    wait for 11 ns;
+    assert NOT(i_sig = 4)
+      report "***PASSED TEST: c10s04b00x00p03n01i00931"
+      severity NOTE;
+    assert (i_sig = 4)
+      report "***FAILED TEST: c10s04b00x00p03n01i00931 - The identifier is visible in the declarative region if the suffix of a selected name in a use clause is a simple identifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n01i00931arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd
new file mode 100644
index 0000000..11cf9e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc932.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n03i00932pkg is
+  subtype register16 is bit_vector(15 downto 0);
+  function "+" (l,r : bit_vector) return bit_vector;
+  function "-" (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p03n03i00932pkg;
+
+package body c10s04b00x00p03n03i00932pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+  function "-" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+end c10s04b00x00p03n03i00932pkg;
+
+use work.c10s04b00x00p03n03i00932pkg.all;
+ENTITY c10s04b00x00p03n03i00932ent IS
+END c10s04b00x00p03n03i00932ent;
+
+ARCHITECTURE c10s04b00x00p03n03i00932arch OF c10s04b00x00p03n03i00932ent IS
+  signal i_sig : register16 := B"1010_1110_1010_0011";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig - i_sig + B"1111111100000000" after 10 ns;
+    wait for 20 ns;
+    assert NOT( i_sig = (B"1111010100101010") )
+      report "***PASSED TEST: c10s04b00x00p03n03i00932"
+      severity NOTE;
+    assert ( i_sig = (B"1111010100101010") )
+      report "***FAILED TEST: c10s04b00x00p03n03i00932 - All of the declarations of a package are visible within the declarative region if the suffix of a selected name in a use clause is the word 'all'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n03i00932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd
new file mode 100644
index 0000000..5017e86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc933.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p04n01i00933pkg is
+  type    color is ( red, green, blue, yellow, orange, purple );
+  function    "+"    (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p04n01i00933pkg;
+
+package body c10s04b00x00p04n01i00933pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111");
+  end;
+end c10s04b00x00p04n01i00933pkg;
+
+
+entity c10s04b00x00p04n01i00933ent_a is
+  generic ( x : bit_vector(3 downto 0));
+end c10s04b00x00p04n01i00933ent_a;
+
+architecture c10s04b00x00p04n01i00933arch_a of c10s04b00x00p04n01i00933ent_a is
+begin
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=B"1111" )
+      report "***PASSED TEST: c10s04b00x00p04n01i00933"
+      severity NOTE;
+    assert ( x=B"1111" )
+      report "***FAILED TEST: c10s04b00x00p04n01i00933 - Items declared via a use clause are visible in the declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s04b00x00p04n01i00933arch_a;
+
+
+use work.c10s04b00x00p04n01i00933pkg.all;
+ENTITY c10s04b00x00p04n01i00933ent IS
+END c10s04b00x00p04n01i00933ent;
+
+ARCHITECTURE c10s04b00x00p04n01i00933arch OF c10s04b00x00p04n01i00933ent IS
+  constant c : bit_vector(3 downto 0) := B"1011";
+  component d
+  end component;
+BEGIN
+  instance : d;
+
+END c10s04b00x00p04n01i00933arch;
+
+configuration c10s04b00x00p04n01i00933cfg of c10s04b00x00p04n01i00933ent is
+  for c10s04b00x00p04n01i00933arch
+    -- declarations are visible here !
+    for instance : d
+      use entity work.c10s04b00x00p04n01i00933ent_a(c10s04b00x00p04n01i00933arch_a) generic map ( B"0100" + c );
+    end for;
+  end for;
+end c10s04b00x00p04n01i00933cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd
new file mode 100644
index 0000000..ce639ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc934.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p04n01i00934pkg is
+  Type Weekdays is (Monday, Tuesday, Wednesday, Thursday, Friday);
+end c10s04b00x00p04n01i00934pkg;
+
+ENTITY c10s04b00x00p04n01i00934ent IS
+END c10s04b00x00p04n01i00934ent;
+
+use  WORK.c10s04b00x00p04n01i00934pkg.all;
+ARCHITECTURE c10s04b00x00p04n01i00934arch OF c10s04b00x00p04n01i00934ent IS
+  signal done : bit;
+  signal wkday :Weekdays;    -- No_failure_here
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert NOT(wkday = Monday) 
+      report "***PASSED TEST: c10s04b00x00p04n01i00934"
+      severity NOTE;
+    assert (wkday = Monday) 
+      report "***FAILED TEST: c10s04b00x00p04n01i00934 - Items declared via a use clause are visible in the declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p04n01i00934arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd
new file mode 100644
index 0000000..3479c5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc935.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p06n01i00935pkg is
+  constant x : integer := 10;
+end c10s04b00x00p06n01i00935pkg;
+
+ENTITY c10s04b00x00p06n01i00935ent IS
+END c10s04b00x00p06n01i00935ent;
+
+ARCHITECTURE c10s04b00x00p06n01i00935arch OF c10s04b00x00p06n01i00935ent IS
+  procedure xxx is
+    constant x : integer := 5; -- homograph of x
+    -- here we place the declaration after the local homograph !
+    use work.c10s04b00x00p06n01i00935pkg.all;
+  begin
+    assert NOT( x=5 )
+      report "***PASSED TEST: c10s04b00x00p06n01i00935"
+      severity NOTE;
+    assert ( x=5 )
+      report "***FAILED TEST: c10s04b00x00p06n01i00935 - A potentially visible declaration is not visible within the immediate scope of a homograph."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s04b00x00p06n01i00935arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd
new file mode 100644
index 0000000..7f8e9d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc936.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p06n01i00936pkg is
+  constant x : integer := 10;
+end c10s04b00x00p06n01i00936pkg;
+
+ENTITY c10s04b00x00p06n01i00936ent IS
+END c10s04b00x00p06n01i00936ent;
+
+ARCHITECTURE c10s04b00x00p06n01i00936arch OF c10s04b00x00p06n01i00936ent IS
+  use work.c10s04b00x00p06n01i00936pkg.all;
+  procedure xxx is
+    constant x : integer := 5; -- homograph of x
+  begin
+    assert NOT( x=5 )
+      report "***PASSED TEST: c10s04b00x00p06n01i00936"
+      severity NOTE;
+    assert ( x=5 )
+      report "***FAILED TEST: c10s04b00x00p06n01i00936 - A potentially visible declaration is not visible within the immediate scope of a homograph."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s04b00x00p06n01i00936arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd
new file mode 100644
index 0000000..63954d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc938.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p07n01i00938pkg is
+  type color is ( red, white, green, blue );
+  constant x : color := green;
+end c10s04b00x00p07n01i00938pkg;
+
+ENTITY c10s04b00x00p07n01i00938ent IS
+END c10s04b00x00p07n01i00938ent;
+
+ARCHITECTURE c10s04b00x00p07n01i00938arch OF c10s04b00x00p07n01i00938ent IS
+  type    rgb is ( red, green, blue );
+  constant    x : rgb := red; -- homograph of x
+  use work.c10s04b00x00p07n01i00938pkg.all;
+  procedure xxx is
+  begin
+    -- takes the local x
+    assert (x = red) report "x /= red" severity FAILURE;
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s04b00x00p07n01i00938"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s04b00x00p07n01i00938 - A oitentially visible declaration is made visible within the immediate scope of a homograph if the declaration is an enumeration literal."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+END c10s04b00x00p07n01i00938arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd
new file mode 100644
index 0000000..24817e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s05b00x00p03n02i00940pkg1 is
+  function F1(B:in integer) return integer;
+end c10s05b00x00p03n02i00940pkg1;
+
+package body c10s05b00x00p03n02i00940pkg1 is
+  function  F1(B:in integer) return integer is
+  begin
+    return 1;
+  end;
+end c10s05b00x00p03n02i00940pkg1;
+
+
+package c10s05b00x00p03n02i00940pkg2 is
+  function F1(B:in bit) return boolean;
+end c10s05b00x00p03n02i00940pkg2;
+
+package body c10s05b00x00p03n02i00940pkg2 is
+  function  F1(B:in bit) return boolean is
+  begin
+    return false;
+  end;
+end c10s05b00x00p03n02i00940pkg2;
+
+use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all;
+ENTITY c10s05b00x00p03n02i00940ent IS
+END c10s05b00x00p03n02i00940ent;
+
+ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (F1('1') = F1('0')) then  -- No_Failure_here
+      assert FALSE 
+        report "***PASSED TEST: c10s05b00x00p03n02i00940" 
+        severity NOTE;
+    else
+      assert FALSE 
+        report "***FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." 
+        severity ERROR;
+    end if;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p03n02i00940arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd
new file mode 100644
index 0000000..d959db4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc942.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s05b00x00p05n01i00942ent IS
+END c10s05b00x00p05n01i00942ent;
+
+ARCHITECTURE c10s05b00x00p05n01i00942arch OF c10s05b00x00p05n01i00942ent IS
+  type three_state is ( '0','1','X');
+
+  function "and" (l,r : three_state) return three_state is
+  begin
+    if    (l = '0') or  (r = '0') then return('0');
+    elsif (l = '1') and (r = '1') then return('1');
+    else  return ('X');
+    end if;
+  end;
+
+BEGIN
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( ('1' and 'X') = 'X' )
+      report "***PASSED TEST: c10s05b00x00p05n01i00942"
+      severity NOTE;
+    assert ( ('1' and 'X') = 'X' )
+      report "***FAILED TEST: c10s05b00x00p05n01i00942 - A name or expression have a certain type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p05n01i00942arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd
new file mode 100644
index 0000000..a63f5cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc943.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p08n01i00943ent IS
+END c06s01b00x00p08n01i00943ent;
+
+ARCHITECTURE c06s01b00x00p08n01i00943arch OF c06s01b00x00p08n01i00943ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BIT_VECTOR(0 to 5);     -- No_failure_here
+  BEGIN
+    assert NOT( V1="000000" )
+      report "***PASSED TEST: c06s01b00x00p08n01i00943"
+      severity NOTE;
+    assert ( V1="000000" )
+      report "***FAILED TEST: c06s01b00x00p08n01i00943 - The name must be a simple name, an operator symbol, a selected name, an indexed name, a slice name, or an attribute name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p08n01i00943arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd
new file mode 100644
index 0000000..c68ed52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc945.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p09n01i00945ent IS
+END c06s01b00x00p09n01i00945ent;
+
+ARCHITECTURE c06s01b00x00p09n01i00945arch OF c06s01b00x00p09n01i00945ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function "+" (a, b:in integer) return bit is
+      variable c: bit;
+      variable d: integer := 0;
+    begin
+      d := a + b + "+".d; -- function call can be used as a prefix.
+      if (d > 0) then
+        c := '0';
+      end if;
+      if (d < 0) then
+        c := '1';
+      end if;
+      return c; 
+    end;
+    variable k : bit;
+  BEGIN
+    k := "+"(1,2);
+    assert NOT(k='0') 
+      report "***PASSED TEST: c06s01b00x00p09n01i00945" 
+      severity NOTE;
+    assert (k='0') 
+      report "***FAILED TEST: c06s01b00x00p09n01i00945 - Prefix can only be a name or a function_call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p09n01i00945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd
new file mode 100644
index 0000000..500d0ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc951.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00951ent IS
+END c06s01b00x00p10n01i00951ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00951arch OF c06s01b00x00p10n01i00951ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1 is array (TWO) of R1;
+    variable V1: BOOLEAN;
+    variable V2: A1 ;
+  BEGIN
+    V1 := V2(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00951" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00951 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00951arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd
new file mode 100644
index 0000000..d3d1a31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc952.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00952ent IS
+END c06s01b00x00p10n01i00952ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00952arch OF c06s01b00x00p10n01i00952ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1  is array (TWO) of R1;
+    type A2  is array (TWO) of A1;
+    variable V1: BOOLEAN;
+    variable V3: A2 ;
+  BEGIN
+    V1 := V3(2)(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00952" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00952 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00952arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd
new file mode 100644
index 0000000..39749a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc953.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00953ent IS
+END c06s01b00x00p10n01i00953ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00953arch OF c06s01b00x00p10n01i00953ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A11 is array (TWO, TWO) of R1;
+    variable V1: BOOLEAN;
+    variable V4: A11;
+  BEGIN
+    V1 := V4(1,2).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00953" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00953 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00953arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd
new file mode 100644
index 0000000..56823cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc954.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00954ent IS
+END c06s01b00x00p10n01i00954ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00954arch OF c06s01b00x00p10n01i00954ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1  is array (TWO) of R1;
+    type A22 is array (TWO, TWO) of A1;
+    variable V1: BOOLEAN;
+    variable V5: A22;
+  BEGIN
+    V1 := V5(1,2)(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00954" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00954 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00954arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd
new file mode 100644
index 0000000..3e5a060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc955.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n02i00955ent IS
+END c06s01b00x00p10n02i00955ent;
+
+ARCHITECTURE c06s01b00x00p10n02i00955arch OF c06s01b00x00p10n02i00955ent IS
+
+  signal PT : boolean;
+  subtype ONE is integer range 1 to 1;
+  type R1 is record
+               X1: ONE;
+               RE1: BOOLEAN;
+             end record;
+  function rr1(i : integer) return R1 is
+    variable vr : r1;
+  begin
+    return vr;
+  end rr1;
+  attribute AT1       : R1;
+  attribute AT1 of PT : signal is rr1(3);
+  type A1 is array (BOOLEAN) of BOOLEAN;
+BEGIN
+  TESTING: PROCESS
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := PT'AT1.RE1;
+    assert NOT( V1=FALSE )
+      report "***PASSED TEST: c06s01b00x00p10n02i00955"
+      severity NOTE;
+    assert ( V1=FALSE )
+      report "***FAILED TEST: c06s01b00x00p10n02i00955 - The prefix of a name is a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n02i00955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd
new file mode 100644
index 0000000..c38286d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc956.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n02i00956ent IS
+END c06s01b00x00p10n02i00956ent;
+
+ARCHITECTURE c06s01b00x00p10n02i00956arch OF c06s01b00x00p10n02i00956ent IS
+
+  signal PT : boolean;
+  subtype ONE is integer range 1 to 1;
+  type R1 is record
+               X1: ONE;
+               RE1: BOOLEAN;
+             end record;
+  function rr1(i : integer) return R1 is
+    variable vr : r1;
+  begin
+    return vr;
+  end rr1;
+  attribute AT1       : R1;
+  attribute AT1 of PT : signal is rr1(3);
+  type A1 is array (BOOLEAN) of BOOLEAN;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BOOLEAN;
+    variable V2 : A1;
+  BEGIN
+    V1 := V2(PT'AT1.RE1);
+    assert NOT( V1=FALSE )
+      report "***PASSED TEST: c06s01b00x00p10n02i00956"
+      severity NOTE;
+    assert ( V1=FALSE )
+      report "***FAILED TEST: c06s01b00x00p10n02i00956 - The prefix of a name is a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n02i00956arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd
new file mode 100644
index 0000000..9f7e9d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p02n01i00958ent IS
+END c06s03b00x00p02n01i00958ent;
+
+ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ONE is range 1 to 1;
+
+    type R0 is record X: ONE; RE: BOOLEAN; end record;            
+    type R1 is record X: ONE; RE: R0; end record;
+    type R2 is record X: ONE; RE: R1; end record;
+    type R3 is record X: ONE; RE: R2; end record;
+    type R4 is record X: ONE; RE: R3; end record;
+    type R5 is record X: ONE; RE: R4; end record;
+    type R6 is record X: ONE; RE: R5; end record;
+    type R7 is record X: ONE; RE: R6; end record;
+    type R8 is record X: ONE; RE: R7; end record;
+    type R9 is record X: ONE; RE: R8; end record;
+
+    variable V1: R9;
+  BEGIN
+    assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
+      report "***PASSED TEST: c06s03b00x00p02n01i00958"
+      severity NOTE;
+    assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
+      report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p02n01i00958arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd
new file mode 100644
index 0000000..ab758f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc962.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p03n01i00962ent IS
+END c06s03b00x00p03n01i00962ent;
+
+ARCHITECTURE c06s03b00x00p03n01i00962arch OF c06s03b00x00p03n01i00962ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : Bit ;
+                 S2 : Integer;
+               end record;
+    type T2 is record
+                 S11 : BIT ;
+                 S12 : T1 ;
+               end record;
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 10 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT( V1.S12.S2 = 10 )
+      report "***PASSED TEST: c06s03b00x00p03n01i00962"
+      severity NOTE;
+    assert ( V1.S12.S2 = 10 )
+      report "***FAILED TEST: c06s03b00x00p03n01i00962 - The suffix of a selected name can be a simple name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p03n01i00962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd
new file mode 100644
index 0000000..70132d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc964.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p04n02i00964pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p04n02i00964pkg;
+
+use work.c06s03b00x00p04n02i00964pkg.all;
+
+ENTITY c06s03b00x00p04n02i00964ent IS
+END c06s03b00x00p04n02i00964ent;
+
+ARCHITECTURE c06s03b00x00p04n02i00964arch OF c06s03b00x00p04n02i00964ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 20 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V1.S12.S2 = 20)
+      report "***PASSED TEST: c06s03b00x00p04n02i00964"
+      severity NOTE;
+    assert (V1.S12.S2 = 20)
+      report "***FAILED TEST: c06s03b00x00p04n02i00964 - The selected name may be used to denote entities declared within a package."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n02i00964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd
new file mode 100644
index 0000000..a1faa30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p04n01i00965ent IS
+END c06s03b00x00p04n01i00965ent;
+
+ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
+  type Rcd is record
+                RE1: BOOLEAN;
+              end record;
+BEGIN
+  TESTING: PROCESS
+    variable var : Rcd;
+  BEGIN
+    var.RE1 := TRUE;
+    wait for 5 ns;
+    assert NOT(var.RE1 = TRUE) 
+      report "***PASSED TEST: c06s03b00x00p04n01i00965"
+      severity NOTE;
+    assert (var.RE1 = TRUE) 
+      report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n01i00965arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd
new file mode 100644
index 0000000..006b84a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc966.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p04n01i00966pkg is
+  constant   tPLH : TIME := 10 ns;
+  constant   tPHL : TIME := 12 ns;
+end c06s03b00x00p04n01i00966pkg;
+
+ENTITY c06s03b00x00p04n01i00966ent IS
+END c06s03b00x00p04n01i00966ent;
+
+ARCHITECTURE c06s03b00x00p04n01i00966arch OF c06s03b00x00p04n01i00966ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
+      report "***PASSED TEST: c06s03b00x00p04n01i00966" 
+      severity NOTE;
+    assert (work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
+      report "***FAILED TEST: c06s03b00x00p04n01i00966 - Selected name should be able to be used to denote a named entity whose declaration is contained within a package."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n01i00966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd
new file mode 100644
index 0000000..f3be44f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc968.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00968ent IS
+END c06s03b00x00p05n01i00968ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00968arch OF c06s03b00x00p05n01i00968ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        t : time;
+        u : character;
+        v : real;
+        w : severity_level;
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S1, S2 :rec_type;
+  BEGIN
+    S1.t := 10 ns;
+    S1.u := 'A';
+    S1.v := 1.2;
+    S1.w := ERROR;
+    S1.y := 12  ;
+    S1.x := '0' ;   -- legal.
+    S2   := S1  ;
+    assert NOT(S2.t=10 ns and S2.u='A' and S2.v=1.2 and S2.w=ERROR and S2.x='0' and S2.y=12 and S2.z=false) 
+      report "***PASSED TEST: c06s03b00x00p05n01i00968" 
+      severity NOTE;
+    assert (S2.t=10 ns and S2.u='A' and S2.v=1.2 and S2.w=ERROR and S2.x='0' and S2.y=12 and S2.z=false) 
+      report "***FAILED TEST: c06s03b00x00p05n01i00968 - Suffix should denote an element of a record object or value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd
new file mode 100644
index 0000000..795abf4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc969.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00969ent IS
+END c06s03b00x00p05n01i00969ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00969arch OF c06s03b00x00p05n01i00969ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        t : time;
+        u : character;
+        v : real;
+        w : severity_level;
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S1, S2 :rec_type;
+  BEGIN
+    S1.t := 11 ns;
+    S1.u := 'A';
+    S1.v := 2.1;
+    S1.w := NOTE;
+    S1.x := '0' ;   -- legal.
+    S1.y := 12  ;
+    S1.z := true;
+    S2.t := S1.t;
+    S2.u := S1.u;
+    S2.v := S1.v;
+    S2.w := S1.w;
+    S2.x := S1.x;
+    S2.y := S1.y;
+    S2.z := S1.z;
+    assert NOT(   
+      S1.t = 11 ns   and
+      S1.u = 'A'   and
+      S1.v = 2.1   and
+      S1.w = NOTE   and
+      S1.x = '0'    and
+      S1.y = 12     and
+      S1.z = true   and
+      S2.t = 11 ns   and
+      S2.u = 'A'   and
+      S2.v = 2.1   and
+      S2.w = NOTE   and
+      S2.x = '0'    and
+      S2.y = 12     and
+      S2.z = true   )
+      report "***PASSED TEST: c06s03b00x00p05n01i00969" 
+      severity NOTE;
+    assert (   
+      S1.t = 11 ns   and
+      S1.u = 'A'   and
+      S1.v = 2.1   and
+      S1.w = NOTE   and
+      S1.x = '0'    and
+      S1.y = 12     and
+      S1.z = true   and
+      S2.t = 11 ns   and
+      S2.u = 'A'   and
+      S2.v = 2.1   and
+      S2.w = NOTE   and
+      S2.x = '0'    and
+      S2.y = 12     and
+      S2.z = true   )
+      report "***FAILED TEST: c06s03b00x00p05n01i00969 - The prefix is not appropriate for the type of the object or value denoted by the suffix." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd
new file mode 100644
index 0000000..a4348aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00973ent IS
+END c06s03b00x00p05n01i00973ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
+  TYPE simple_record_2_type IS
+    RECORD
+      a2 : integer;
+      b2 : integer;
+    END RECORD;
+
+  TYPE array_of_records_type IS
+    ARRAY (20 TO 30) OF simple_record_2_type;
+
+  SIGNAL sr : array_of_records_type;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE ar,br : array_of_records_type;
+
+    FUNCTION convert (ain : array_of_records_type) RETURN integer IS
+    BEGIN
+      RETURN (ain(25).b2);
+    END;
+  BEGIN
+    wait for 1 ns;
+    br(20).b2 := 8;
+    ar(30).b2 := br(20).b2;
+
+    ar(30).b2 := 8;
+    ar(20).a2 := ar(30).b2;
+
+    sr(30).b2 <= 8;
+    wait for 1 ns;
+    sr(20).a2 <= sr(30).b2;
+    wait for 1 ns;
+
+    ar(25).b2 := 3;
+    sr(25).b2 <= 3;
+    wait for 1 ns;
+    
+    assert NOT((ar(30).b2 = 8)   AND
+               (ar(20).a2 = 8)   AND
+               (sr(20).a2 = 8)   AND
+               (convert(ar) = 3) AND
+               (convert(sr) = 3)) 
+      report "***PASSED TEST: c06s03b00x00p05n01i00973" 
+      severity NOTE;
+    assert    ((ar(30).b2 = 8)   AND
+               (ar(20).a2 = 8)   AND
+               (sr(20).a2 = 8)   AND
+               (convert(ar) = 3) AND
+               (convert(sr) = 3)) 
+      report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd
new file mode 100644
index 0000000..6327a94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc98.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n02i00098ent_a IS
+  GENERIC ( gen_in : IN INTEGER );
+  PORT ( prt_in : IN INTEGER );
+  
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF gen_in : CONSTANT IS 100;
+  ATTRIBUTE attr1 OF prt_in : SIGNAL   IS 200;
+END c04s03b02x00p29n02i00098ent_a;
+
+ARCHITECTURE c04s03b02x00p29n02i00098arch_a OF c04s03b02x00p29n02i00098ent_a IS
+  
+BEGIN
+  PROCESS
+  BEGIN
+    ASSERT gen_in'attr1 = 100 REPORT "ERROR: Bad value for gen_in'attr1" SEVERITY FAILURE;
+    ASSERT prt_in'attr1 = 200 REPORT "ERROR: Bad value for prt_in'attr1" SEVERITY FAILURE;
+    assert NOT(gen_in'attr1 = 100 and prt_in'attr1 = 200) 
+      report "***PASSED TEST: c04s03b02x00p29n02i00098" 
+      severity NOTE;
+    assert (gen_in'attr1 = 100 and prt_in'attr1 = 200) 
+      report "***FAILED TEST: c04s03b02x00p29n02i00098 - Attribute reading fail."
+      severity ERROR;
+    wait;
+  END PROCESS;
+END c04s03b02x00p29n02i00098arch_a;
+
+
+
+ENTITY c04s03b02x00p29n02i00098ent IS
+END c04s03b02x00p29n02i00098ent;
+
+ARCHITECTURE c04s03b02x00p29n02i00098arch OF c04s03b02x00p29n02i00098ent IS
+  COMPONENT c04s03b02x00p29n02i00098ent_a
+    GENERIC ( gen_in : IN INTEGER );
+    PORT ( prt_in : IN INTEGER );
+  END COMPONENT;
+  FOR cmp1 : c04s03b02x00p29n02i00098ent_a USE ENTITY work.c04s03b02x00p29n02i00098ent_a(c04s03b02x00p29n02i00098arch_a); 
+  
+  SIGNAL s : INTEGER;
+BEGIN
+
+  cmp1 : c04s03b02x00p29n02i00098ent_a
+    GENERIC MAP ( 0 )
+    PORT MAP ( s );
+
+END c04s03b02x00p29n02i00098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd
new file mode 100644
index 0000000..000c157
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00983ent IS
+END c06s03b00x00p06n01i00983ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T is
+      record
+        a:integer;
+        b:integer;
+      end record;
+    type A is access T;
+    variable B1, B2: A := new T'(0, 0);
+    variable C     : T;
+    function foo return integer is
+    begin 
+      return 120; 
+    end;
+    function foo return real is
+    begin 
+      return 12.0; 
+    end;
+  BEGIN
+    C      := B1.all;
+    B1.all := B2.all;
+    assert NOT( C.a=0 and C.b=0 )
+      report "***PASSED TEST: c06s03b00x00p06n01i00983"
+      severity NOTE;
+    assert ( C.a=0 and C.b=0 )
+      report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00983arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd
new file mode 100644
index 0000000..d155922
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc986.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00986ent IS
+END c06s03b00x00p06n01i00986ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00986arch OF c06s03b00x00p06n01i00986ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : BIT ;
+                 S2 : Integer;
+               end record;
+    type T2 is access T1;
+    variable V1 : T2 := new T1'('0',0) ;
+    variable V2 : T1;
+  BEGIN
+    V2 := V1.all ; -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V2.S1='0' and V2.S2=0) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00986" 
+      severity NOTE;
+    assert (V2.S1='0' and V2.S2=0) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00986 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00986arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd
new file mode 100644
index 0000000..429fed0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd
@@ -0,0 +1,991 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc987.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p06n01i00987pkg is
+------------------------------------USING ONLY WHITE MATTER---------------------------------
+--------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr is access boolean ;                                  --simple boolean type   
+  type bit_ptr is access bit ;                                          --simple bit type
+  type char_ptr is access character;                                    --simple character type
+  type severity_level_ptr is access severity_level;                     --simple severity type
+  type integer_ptr is access integer;                                   --simple integer type   
+  type real_ptr is access real;                                         --simple real type
+  type time_ptr is access time;                                         --simple time type
+  type natural_ptr is access natural;                                   --simple natural type
+  type positive_ptr is access positive;                                 --simple positive type
+  type string_ptr is access string;                                     --simple string type
+  type bit_vector_ptr is access bit_vector;                             --simple bit_vector type
+
+--------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st is  integer_vector(0 to 15);
+  subtype real_vector_st is  real_vector(0 to 15);
+  subtype time_vector_st is  time_vector(0 to 15);
+  subtype natural_vector_st is  natural_vector(0 to 15);
+  subtype positive_vector_st is  positive_vector(0 to 15);
+  
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  
+---------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  
+---------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector is array (natural range<>,natural range <>) of bit;
+  type s2char_vector is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector is array (natural range <>,natural range <>) of integer;
+  type s2real_vector is array (natural range <>,natural range <>) of real;
+  type s2time_vector is array (natural range <>,natural range <>) of time;
+  type s2natural_vector is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector is array (natural range <>,natural range <>) of positive;
+  
+----------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column is range 1 to 64;
+  type row is range 1 to 1024;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                   --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                    --simple integer type
+                          g:  real_ptr ;                                    --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i: natural_ptr;                                   --simple natural type
+
+                          j:positive_ptr;                                   --simple positive type
+                          k: string_ptr;                                    --simple string type
+                          l: bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+-----------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr is access boolean_vector;
+  type severity_level_vector_ptr is access severity_level_vector;
+  type integer_vector_ptr is access integer_vector;
+  type real_vector_ptr is access real_vector;
+  type time_vector_ptr is access time_vector;
+  type natural_vector_ptr is access natural_vector;
+  type positive_vector_ptr is access positive_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
+  type severity_level_vector_st_ptr is access  severity_level_vector_st;--(0 to 15);
+  type integer_vector_st_ptr is access  integer_vector_st;--(0 to 15);
+  type real_vector_st_ptr is access  real_vector_st;--(0 to 15);
+  type time_vector_st_ptr is access  time_vector_st;--(0 to 15);
+  type natural_vector_st_ptr is access  natural_vector_st;--(0 to 15);
+  type positive_vector_st_ptr is access  positive_vector_st;--(0 to 15);
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr is access severity_level_cons_vector;
+  type integer_cons_vector_ptr is access  integer_cons_vector;
+  type real_cons_vector_ptr is access real_cons_vector;
+  type time_cons_vector_ptr is access time_cons_vector;
+  type natural_cons_vector_ptr is access natural_cons_vector;
+  type positive_cons_vector_ptr is access  positive_cons_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr is access  real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr is access s2boolean_vector;
+  type s2bit_vector_ptr is access  s2bit_vector;
+  type s2char_vector_ptr is access s2char_vector;
+  type s2severity_level_vector_ptr is access s2severity_level_vector;
+  type s2integer_vector_ptr is access s2integer_vector;
+  type s2real_vector_ptr is access s2real_vector;
+  type s2time_vector_ptr is access  s2time_vector;
+  type s2positive_vector_ptr is access s2positive_vector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr is access  s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr is access  s2integer_cons_vector;
+  type s2real_cons_vector_ptr is access  s2real_cons_vector;
+  type s2time_cons_vector_ptr is access  s2time_cons_vector;
+  type s2natural_cons_vector_ptr is access s2natural_cons_vector;
+  type s2positive_cons_vector_ptr is access s2positive_cons_vector;
+----------------------------------------------------------------------------------------------
+  type record_std_package_ptr is access record_std_package;
+  type record_cons_array_ptr is access  record_cons_array;
+  type record_2cons_array_ptr is access  record_2cons_array;
+  type record_cons_arrayofarray_ptr is access  record_cons_arrayofarray;
+  type record_of_ptr_ptr is access record_of_ptr;
+  type record_of_records_ptr is access record_of_records;
+  type record_array_st_ptr is access record_array_st;
+  
+-----------------------------------------------------------------------------------------------
+-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
+  
+  
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;     --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                 --constrained array
+  function resolution(i:in four_value_vector) return four_value;        --bus resolution
+  subtype four_value_state is resolution four_value;                    --function type
+  type state_vector is array (natural range <>) of four_value_state;    --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                      --array of an array
+  type primary_memory_module is                                         --record with field
+    record                                                                --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;       --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr is access four_value;
+  type four_value_map_ptr is access four_value_map;
+  type binary_ptr is access binary;
+  type four_value_vector_ptr is access four_value_vector;               --ennumerated type
+  type byte_ptr is access byte;
+  type word_ptr is access word;
+  type four_value_state_ptr is access four_value_state;
+  type state_vector_ptr is access state_vector;                         --type returned by resolu.
+  type primary_memory_ptr is access primary_memory;
+  type primary_memory_module_ptr is access primary_memory_module;
+  type whole_memory_ptr is access whole_memory;
+  type current_ptr is access current;
+  type resistance_ptr is access resistance;
+  type delay_ptr is access delay;
+-------------------------------------------------------------------------------------------
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  
+  
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+--constant C33 : s2boolean_vector := ((true,true),(false,false));
+--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
+--constant C35 : s2char_vector := (('s','h'),('i','s'));
+--constant C36 : s2severity_level_vector := ((note,error),(error,note));
+--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
+--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
+--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
+--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
+  constant C41 : s2boolean_cons_vector := (others =>(others => C1));
+  constant C42 : s2bit_cons_vector := (others => (others => C2));
+  constant C43 : s2char_cons_vector := (others =>(others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector := (others => (others => C5));
+  constant C46 : s2real_cons_vector := (others =>(others => C6));
+  constant C47 : s2time_cons_vector := (others =>(others => C7));
+  constant C48 : s2natural_cons_vector := (others =>(others => C8));
+  constant C49 : s2positive_cons_vector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
+--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
+  constant C56 : four_value := 'Z';
+  constant C57 : four_value_map := (true,true,true,true);
+  constant C58 : binary := '0';
+  constant C59 : four_value_vector := ('1','0','1','0');
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C62 : four_value_state := 'Z';
+  constant C63 : state_vector := ('Z','Z','Z','Z');
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  
+end c06s03b00x00p06n01i00987pkg;
+
+package body c06s03b00x00p06n01i00987pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c06s03b00x00p06n01i00987pkg;
+
+use work.c06s03b00x00p06n01i00987pkg.all;
+
+ENTITY c06s03b00x00p06n01i00987ent IS
+END c06s03b00x00p06n01i00987ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00987arch OF c06s03b00x00p06n01i00987ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr ;
+    variable var2 : bit_ptr ;
+    variable var3 : char_ptr ;
+    variable var4 : severity_level_ptr ;
+    variable var5 : integer_ptr ;
+    variable var6 : real_ptr ;
+    variable var7 : time_ptr ;
+    variable var8 : natural_ptr ;
+    variable var9 : positive_ptr ;
+    variable var10 : string_ptr ;
+    variable var11 : bit_vector_ptr ;
+    variable var12 : boolean_vector_ptr ;
+    variable var13 : severity_level_vector_ptr ;
+    variable var14 : integer_vector_ptr ;
+    variable var15 : real_vector_ptr ;
+    variable var16 : time_vector_ptr ;
+    variable var17 : natural_vector_ptr ;
+    variable var18 : positive_vector_ptr ;
+    variable var19 : boolean_cons_vector_ptr ;
+    variable var20 : severity_level_cons_vector_ptr ;
+    variable var21 : integer_cons_vector_ptr ;
+    variable var22 : real_cons_vector_ptr ;
+    variable var23 : time_cons_vector_ptr ;
+    variable var24 : natural_cons_vector_ptr ;
+    variable var25 : positive_cons_vector_ptr ;
+    variable var26 : boolean_cons_vectorofvector_ptr ;
+    variable var27 : sev_lvl_cons_vecofvec_ptr ;
+    variable var28 : integer_cons_vectorofvector_ptr ;
+    variable var29 : real_cons_vectorofvector_ptr ;
+    variable var30 : time_cons_vectorofvector_ptr ;
+    variable var31 : natural_cons_vectorofvector_ptr ;
+    variable var32 : posi_cons_vecofvec_ptr ;
+-- variable var33 : s2boolean_vector_ptr ;
+-- variable var34 : s2bit_vector_ptr ;
+-- variable var35 : s2char_vector_ptr ;
+-- variable var36 : s2severity_level_vector_ptr ;
+-- variable var37 : s2integer_vector_ptr ;
+-- variable var38 : s2real_vector_ptr ;
+-- variable var39 : s2time_vector_ptr ;
+-- variable var40 : s2positive_vector_ptr ;
+    variable var41 : s2boolean_cons_vector_ptr ;
+    variable var42 : s2bit_cons_vector_ptr ;
+    variable var43 : s2char_cons_vector_ptr ;
+    variable var44 : s2sev_lvl_cons_vec_ptr ;
+    variable var45 : s2integer_cons_vector_ptr ;
+    variable var46 : s2real_cons_vector_ptr ;
+    variable var47 : s2time_cons_vector_ptr ;
+    variable var48 : s2natural_cons_vector_ptr ;
+    variable var49 : s2positive_cons_vector_ptr ;
+    variable var50 : record_std_package_ptr ;
+    variable var51 : record_cons_array_ptr ;
+    variable var52 : record_2cons_array_ptr ;
+    variable var53 : record_cons_arrayofarray_ptr ;
+    variable var54 : record_of_ptr_ptr ;
+    variable var54a : record_array_st_ptr;
+    variable var55 : record_of_records_ptr ;
+    variable var56 : four_value_ptr ;
+    variable var57 : four_value_map_ptr ;
+    variable var58 : binary_ptr ;
+    variable var59 : four_value_vector_ptr ;
+    variable var60 : byte_ptr ;
+    variable var61 : word_ptr ;
+    variable var62 : four_value_state_ptr ;
+    variable var63 : state_vector_ptr ;
+    variable var64 : primary_memory_ptr ;
+    variable var65 : primary_memory_module_ptr;
+    variable var66 : whole_memory_ptr ;
+    variable var67 : current_ptr ;
+    variable var68 : resistance_ptr ;
+    variable var69 : delay_ptr ;
+    variable var70 : boolean_vector_st_ptr;
+    variable var71 :  severity_level_vector_st_ptr;
+    variable var72 :  integer_vector_st_ptr;
+    variable var73 :  real_vector_st_ptr;
+    variable var74 :  time_vector_st_ptr;
+    variable var75 :  natural_vector_st_ptr;
+    variable var76 : positive_vector_st_ptr;
+    
+    variable vari1 : boolean;
+    variable vari2 : bit;
+    variable vari3 : character;
+    variable vari4 : severity_level;
+    variable vari5 : integer;
+    variable vari6 : real;
+    variable vari7 : time;
+    variable vari8 : natural;
+    variable vari9 : positive;
+    variable vari10 : string(1 to 7);
+    variable vari11 : bit_vector(0 to 3);
+    variable vari12 : boolean_vector(0 to 1);
+    variable vari13 : severity_level_vector(0 to 1);
+    variable vari14 : integer_vector(0 to 3);
+    variable vari15 : real_vector(0 to 3);
+    variable vari16 : time_vector(0 to 3);
+    variable vari17 : natural_vector(0 to 3);
+    variable vari18 : positive_vector(0 to 3);
+    variable vari19 : boolean_cons_vector;
+    variable vari20 : severity_level_cons_vector;
+    variable vari21 : integer_cons_vector;
+    variable vari22 : real_cons_vector;
+    variable vari23 : time_cons_vector;
+    variable vari24 : natural_cons_vector;
+    variable vari25 : positive_cons_vector;
+    variable vari26 : boolean_cons_vectorofvector;
+    variable vari27 : severity_level_cons_vectorofvector;
+    variable vari28 : integer_cons_vectorofvector;
+    variable vari29 : real_cons_vectorofvector;
+    variable vari30 : time_cons_vectorofvector;
+    variable vari31 : natural_cons_vectorofvector;
+    variable vari32 : positive_cons_vectorofvector;
+--variable vari33 : s2boolean_vector;
+--variable vari34 : s2bit_vector;
+--variable vari35 : s2char_vector;
+--variable vari36 : s2severity_level_vector;
+--variable vari37 : s2integer_vector;
+--variable vari38 : s2real_vector;
+--variable vari39 : s2time_vector;
+--variable vari40 : s2positive_vector;
+    variable vari41 : s2boolean_cons_vector;
+    variable vari42 : s2bit_cons_vector;
+    variable vari43 : s2char_cons_vector;
+    variable vari44 : s2severity_level_cons_vector;
+    variable vari45 : s2integer_cons_vector;
+    variable vari46 : s2real_cons_vector;
+    variable vari47 : s2time_cons_vector;
+    variable vari48 : s2natural_cons_vector;
+    variable vari49 : s2positive_cons_vector;
+    variable vari50 : record_std_package;
+    variable vari51 : record_cons_array;
+    variable vari52 : record_2cons_array;
+    variable vari53 : record_cons_arrayofarray;
+    variable vari54 : record_of_ptr;
+    variable vari55 : record_of_records;
+    variable vari56 : four_value;
+    variable vari57 : four_value_map;
+    variable vari58 : binary;
+    variable vari59 : four_value_vector(0 to 3);
+    variable vari60 : byte;
+    variable vari61 : word;
+    variable vari62 : four_value_state;
+    variable vari63 : state_vector(0 to 3);
+    variable vari64 : primary_memory;
+    variable vari65 : primary_memory_module;
+    variable vari66 : whole_memory;
+    variable vari67 : current;
+    variable vari68 : resistance;
+    variable vari69 : delay;
+    variable vari70 : boolean_vector_st;
+    variable vari71 : severity_level_vector_st;
+    variable vari72 : integer_vector_st;
+    variable vari73 : real_vector_st;
+    variable vari74 : time_vector_st;
+    variable vari75 : natural_vector_st;
+    variable vari76 : positive_vector_st;
+    variable vari54a : record_array_st;
+
+  BEGIN
+    var1 := NEW boolean '(C1);
+    var2 := NEW bit '(C2);
+    var3 := NEW character '(C3);
+    var4 := NEW severity_level '(C4);
+    var5 := NEW integer '(C5);
+    var6 := NEW real '(C6);
+    var7 := NEW time '(C7);
+    var8 := NEW natural '(C8);
+    var9 := NEW positive '(C9);
+    var10 := NEW string '(C10);
+    var11 := NEW bit_vector '(C11);
+    var12 := NEW boolean_vector '(C12);
+    var13 := NEW severity_level_vector '(C13);
+    var14 := NEW integer_vector '(C14);
+    var15 := NEW real_vector '(C15);
+    var16 := NEW time_vector '(C16);
+    var17 := NEW natural_vector '(C17);
+    var18 := NEW positive_vector '(C18);
+    var19 := NEW boolean_cons_vector '(C19);
+    var20 := NEW severity_level_cons_vector '(C20);
+    var21 := NEW integer_cons_vector '(C21);
+    var22 := NEW real_cons_vector '(C22);
+    var23 := NEW time_cons_vector '(C23);
+    var24 := NEW natural_cons_vector '(C24);
+    var25 := NEW positive_cons_vector '(C25);
+    var26 := NEW boolean_cons_vectorofvector '(C26);
+    var27 := NEW severity_level_cons_vectorofvector '(C27);
+    var28 := NEW integer_cons_vectorofvector '(C28);
+    var29 := NEW real_cons_vectorofvector '(C29);
+    var30 := NEW time_cons_vectorofvector '(C30);
+    var31 := NEW natural_cons_vectorofvector '(C31);
+    var32 := NEW positive_cons_vectorofvector '(C32);
+--var33 := NEW s2boolean_vector '(C33);
+--var34 := NEW s2bit_vector '(C34);
+--var35 := NEW s2char_vector '(C35);
+--var36 := NEW s2severity_level_vector '(C36);
+--var37 := NEW s2integer_vector '(C37);
+--var38 := NEW s2real_vector '(C38);
+--var39 := NEW s2time_vector '(C39);
+--var40 := NEW s2positive_vector '(C40);
+    var41 := NEW s2boolean_cons_vector '(C41);
+    var42 := NEW s2bit_cons_vector '(C42);
+    var43 := NEW s2char_cons_vector '(C43);
+    var44 := NEW s2severity_level_cons_vector '(C44);
+    var45 := NEW s2integer_cons_vector '(C45);
+    var46 := NEW s2real_cons_vector '(C46);
+    var47 := NEW s2time_cons_vector '(C47);
+    var48 := NEW s2natural_cons_vector '(C48);
+    var49 := NEW s2positive_cons_vector '(C49);
+    var50 := NEW record_std_package '(C50);
+    var51 := NEW record_cons_array '(C51);
+    var52 := NEW record_2cons_array '(C52);
+    var53 := NEW record_cons_arrayofarray '(C53);
+--var54 := NEW record_of_ptr '(C54);
+--var54a := NEW record_array_st '(C54a);
+--var55 := NEW record_of_records '(C55);
+    var56 := NEW four_value '(C56);
+    var57 := NEW four_value_map '(C57);
+    var58 := NEW binary '(C58);
+    var59 := NEW four_value_vector '(C59);
+    var60 := NEW byte '(C60);
+    var61 := NEW word '(C61);
+    var62 := NEW four_value_state '(C62);
+    var63 := NEW state_vector '(C63);
+    var64 := NEW primary_memory '(C64);
+    var65 := NEW primary_memory_module '(C65);
+    var66 := NEW whole_memory '(C66);
+    var67 := NEW current '(C67);
+    var68 := NEW resistance '(C68);
+    var69 := NEW delay '(C69);
+    var70 := NEW boolean_vector_st '(C70);
+    var71 := NEW severity_level_vector_st '(C71);
+    var72 := NEW integer_vector_st '(C72);
+    var73 := NEW real_vector_st '(C73);
+    var74 := NEW time_vector_st '(C74);
+    var75 := NEW natural_vector_st '(C75);
+    var76 := NEW positive_vector_st '(C76);
+    
+    vari1 := var1.all;
+    vari2 := var2.all;
+    vari3 := var3.all;
+    vari4 := var4.all;
+    vari5 := var5.all;
+    vari6 := var6.all;
+    vari7 := var7.all;
+    vari8 := var8.all;
+    vari9 := var9.all;
+    vari10 := var10.all;
+    vari11 := var11.all;
+    vari12 := var12.all;
+    vari13 := var13.all;
+    vari14 := var14.all;
+    vari15 := var15.all;
+    vari16 := var16.all;
+    vari17 := var17.all;
+    vari18 := var18.all;
+    vari19 := var19.all;
+    vari20 := var20.all;
+    vari21 := var21.all;
+    vari22 := var22.all;
+    vari23 := var23.all;
+    vari24 := var24.all;
+    vari25 := var25.all;
+    vari26 := var26.all;
+    vari27 := var27.all;
+    vari28 := var28.all;
+    vari29 := var29.all;
+    vari30 := var30.all;
+    vari31 := var31.all;
+    vari32 := var32.all;
+--vari33 := var33.all;
+--vari34 := var34.all;
+--vari35 := var35.all;
+--vari36 := var36.all;
+--vari37 := var37.all;
+--vari38 := var38.all;
+--vari39 := var39.all;
+--vari40 := var40.all;
+    vari41 := var41.all;
+    vari42 := var42.all;
+    vari43 := var43.all;
+    vari44 := var44.all;
+    vari45 := var45.all;
+    vari46 := var46.all;
+    vari47 := var47.all;
+    vari48 := var48.all;
+    vari49 := var49.all;
+    vari50 := var50.all;
+    vari51 := var51.all;
+    vari52 := var52.all;
+    vari53 := var53.all;
+--vari54 := var54.all;
+--vari55 := var55.all;
+    vari56 := var56.all;
+    vari57 := var57.all;
+    vari58 := var58.all;
+    vari59 := var59.all;
+    vari60 := var60.all;
+    vari61 := var61.all;
+    vari62 := var62.all;
+    vari63 := var63.all;
+    vari64 := var64.all;
+    vari65 := var65.all;
+    vari66 := var66.all;
+    vari67 := var67.all;
+    vari68 := var68.all;
+    vari69 := var69.all;
+    vari70 := var70.all;
+    vari71 := var71.all;
+    vari72 := var72.all;
+    vari73 := var73.all;
+    vari74 := var74.all;
+    vari75 := var75.all;
+    vari76 := var76.all;
+--vari54a := var54a.all;
+
+    ASSERT vari1= C1    report "Improper Assignment of vari1" SEVERITY FAILURE;
+    ASSERT vari2 = C2    report "Improper Assignment of vari2" SEVERITY FAILURE;
+    ASSERT vari3 = C3    report "Improper Assignment of vari3" SEVERITY FAILURE;
+    ASSERT vari4 = C4    report "Improper Assignment of vari4" SEVERITY FAILURE;
+    ASSERT vari5 = C5    report "Improper Assignment of vari5" SEVERITY FAILURE;
+    ASSERT vari6 = C6    report "Improper Assignment of vari6" SEVERITY FAILURE;
+    ASSERT vari7 = C7    report "Improper Assignment of vari7" SEVERITY FAILURE;
+    ASSERT vari8 = C8    report "Improper Assignment of vari8" SEVERITY FAILURE;
+    ASSERT vari9 = C9    report "Improper Assignment of vari9" SEVERITY FAILURE;
+    ASSERT vari10 = C10    report "Improper Assignment of vari10" SEVERITY FAILURE;
+    ASSERT vari11 = C11    report "Improper Assignment of vari11" SEVERITY FAILURE;
+    ASSERT vari12 = C12    report "Improper Assignment of vari12" SEVERITY FAILURE;
+    ASSERT vari13 = C13    report "Improper Assignment of vari13" SEVERITY FAILURE;
+    ASSERT vari14 = C14    report "Improper Assignment of vari14" SEVERITY FAILURE;
+    ASSERT vari15 = C15    report "Improper Assignment of vari15" SEVERITY FAILURE;
+    ASSERT vari16 = C16    report "Improper Assignment of vari16" SEVERITY FAILURE;
+    ASSERT vari17 = C17    report "Improper Assignment of vari17" SEVERITY FAILURE;
+    ASSERT vari18 = C18    report "Improper Assignment of vari18" SEVERITY FAILURE;
+    ASSERT vari19 = C19    report "Improper Assignment of vari19" SEVERITY FAILURE;
+    ASSERT vari20 = C20    report "Improper Assignment of vari20" SEVERITY FAILURE;
+    ASSERT vari21 = C21    report "Improper Assignment of vari21" SEVERITY FAILURE;
+    ASSERT vari22 = C22    report "Improper Assignment of vari22" SEVERITY FAILURE;
+    ASSERT vari23 = C23    report "Improper Assignment of vari23" SEVERITY FAILURE;
+    ASSERT vari24 = C24    report "Improper Assignment of vari24" SEVERITY FAILURE;
+    ASSERT vari25 = C25    report "Improper Assignment of vari25" SEVERITY FAILURE;
+    ASSERT vari26 = C26    report "Improper Assignment of vari26" SEVERITY FAILURE;
+    ASSERT vari27 = C27    report "Improper Assignment of vari27" SEVERITY FAILURE;
+    ASSERT vari28 = C28    report "Improper Assignment of vari28" SEVERITY FAILURE;
+    ASSERT vari29 = C29    report "Improper Assignment of vari29" SEVERITY FAILURE;
+    ASSERT vari30 = C30    report "Improper Assignment of vari30" SEVERITY FAILURE; 
+    ASSERT vari31 = C31    report "Improper Assignment of vari31" SEVERITY FAILURE; 
+    ASSERT vari32 = C32    report "Improper Assignment of vari32" SEVERITY FAILURE; 
+--ASSERT vari33 = C33    report "Improper Assignment of vari33" SEVERITY FAILURE; 
+--ASSERT vari34 = C34    report "Improper Assignment of vari34" SEVERITY FAILURE; 
+--ASSERT vari35 = C35    report "Improper Assignment of vari35" SEVERITY FAILURE; 
+--ASSERT vari36 = C36    report "Improper Assignment of vari36" SEVERITY FAILURE; 
+--ASSERT vari37 = C37    report "Improper Assignment of vari37" SEVERITY FAILURE; 
+--ASSERT vari38 = C38    report "Improper Assignment of vari38" SEVERITY FAILURE; 
+--ASSERT vari39 = C39    report "Improper Assignment of vari39" SEVERITY FAILURE; 
+--ASSERT vari40 = C40    report "Improper Assignment of vari40" SEVERITY FAILURE; 
+    ASSERT vari41 = C41    report "Improper Assignment of vari41" SEVERITY FAILURE; 
+    ASSERT vari42 = C42    report "Improper Assignment of vari42" SEVERITY FAILURE; 
+    ASSERT vari43 = C43    report "Improper Assignment of vari43" SEVERITY FAILURE; 
+    ASSERT vari44 = C44    report "Improper Assignment of vari44" SEVERITY FAILURE; 
+    ASSERT vari45 = C45    report "Improper Assignment of vari45" SEVERITY FAILURE; 
+    ASSERT vari46 = C46    report "Improper Assignment of vari46" SEVERITY FAILURE; 
+    ASSERT vari47 = C47    report "Improper Assignment of vari47" SEVERITY FAILURE; 
+    ASSERT vari48 = C48    report "Improper Assignment of vari48" SEVERITY FAILURE; 
+    ASSERT vari49 = C49    report "Improper Assignment of vari49" SEVERITY FAILURE;
+    ASSERT vari50 = C50    report "Improper Assignment of vari50" SEVERITY FAILURE;
+    ASSERT vari51 = C51    report "Improper Assignment of vari51" SEVERITY FAILURE;
+    ASSERT vari52 = C52    report "Improper Assignment of vari52" SEVERITY FAILURE;
+    ASSERT vari53 = C53    report "Improper Assignment of vari53" SEVERITY FAILURE;
+--ASSERT vari54 = C54    report "Improper Assignment of vari54" SEVERITY FAILURE;
+--ASSERT vari54a = C54a    report "Improper Assignment of vari54a" SEVERITY FAILURE;
+--ASSERT vari55 = C55    report "Improper Assignment of vari55" SEVERITY FAILURE;
+    ASSERT vari56 = C56    report "Improper Assignment of vari56" SEVERITY FAILURE;
+    ASSERT vari57 = C57    report "Improper Assignment of vari57" SEVERITY FAILURE;
+    ASSERT vari58 = C58    report "Improper Assignment of vari58" SEVERITY FAILURE;
+    ASSERT vari59 = C59    report "Improper Assignment of vari59" SEVERITY FAILURE;
+    ASSERT vari60 = C60    report "Improper Assignment of vari60" SEVERITY FAILURE;
+    ASSERT vari61 = C61    report "Improper Assignment of vari61" SEVERITY FAILURE;
+    ASSERT vari62 = C62    report "Improper Assignment of vari62" SEVERITY FAILURE;
+    ASSERT vari63 = C63    report "Improper Assignment of vari63" SEVERITY FAILURE;
+    ASSERT vari64 = C64    report "Improper Assignment of vari64" SEVERITY FAILURE;
+    ASSERT vari65 = C65    report "Improper Assignment of vari65" SEVERITY FAILURE;
+    ASSERT vari66 = C66    report "Improper Assignment of vari66" SEVERITY FAILURE;
+    ASSERT vari67 = C67    report "Improper Assignment of vari67" SEVERITY FAILURE;
+    ASSERT vari68 = C68    report "Improper Assignment of vari68" SEVERITY FAILURE;
+    ASSERT vari69 = C69    report "Improper Assignment of vari69" SEVERITY FAILURE;
+    ASSERT vari70 = C70    report "Improper Assignment of vari70" SEVERITY FAILURE;
+    ASSERT vari71 = C71    report "Improper Assignment of vari71" SEVERITY FAILURE;
+    ASSERT vari72 = C72    report "Improper Assignment of vari72" SEVERITY FAILURE;
+    ASSERT vari73 = C73    report "Improper Assignment of vari73" SEVERITY FAILURE;
+    ASSERT vari74 = C74    report "Improper Assignment of vari74" SEVERITY FAILURE;
+    ASSERT vari74 = C74    report "Improper Assignment of vari74" SEVERITY FAILURE;
+    ASSERT vari75 = C75    report "Improper Assignment of vari75" SEVERITY FAILURE;
+    ASSERT vari76 = C76    report "Improper Assignment of vari76" SEVERITY FAILURE;
+
+    assert NOT(   vari1 = C1    and 
+                  vari2 = C2    and 
+                  vari3 = C3    and 
+                  vari4 = C4    and 
+                  vari5 = C5    and 
+                  vari6 = C6    and 
+                  vari7 = C7    and 
+                  vari8 = C8    and 
+                  vari9 = C9    and 
+                  vari10 = C10    and 
+                  vari11 = C11    and 
+                  vari12 = C12    and 
+                  vari13 = C13    and 
+                  vari14 = C14    and 
+                  vari15 = C15    and 
+                  vari16 = C16    and 
+                  vari17 = C17    and 
+                  vari18 = C18    and 
+                  vari19 = C19    and 
+                  vari20 = C20    and 
+                  vari21 = C21    and 
+                  vari22 = C22    and 
+                  vari23 = C23    and 
+                  vari24 = C24    and 
+                  vari25 = C25    and 
+                  vari26 = C26    and 
+                  vari27 = C27    and 
+                  vari28 = C28    and 
+                  vari29 = C29    and 
+                  vari30 = C30    and 
+                  vari31 = C31    and 
+                  vari32 = C32    and 
+--      vari33 = C33    and 
+--      vari34 = C34    and 
+--      vari35 = C35    and 
+--      vari36 = C36    and 
+--      vari37 = C37    and 
+--      vari38 = C38    and 
+--      vari39 = C39    and 
+--      vari40 = C40    and 
+                  vari41 = C41    and 
+                  vari42 = C42    and 
+                  vari43 = C43    and 
+                  vari44 = C44    and 
+                  vari45 = C45    and 
+                  vari46 = C46    and 
+                  vari47 = C47    and 
+                  vari48 = C48    and 
+                  vari49 = C49    and 
+                  vari50 = C50    and 
+                  vari51 = C51    and 
+                  vari52 = C52    and 
+                  vari53 = C53    and 
+--      vari54 = C54    and 
+--      vari54a = C54a    and 
+--      vari55 = C55    and 
+                  vari56 = C56    and 
+                  vari57 = C57    and 
+                  vari58 = C58    and 
+                  vari59 = C59    and 
+                  vari60 = C60    and 
+                  vari61 = C61    and 
+                  vari62 = C62    and 
+                  vari63 = C63    and 
+                  vari64 = C64    and 
+                  vari65 = C65    and 
+                  vari66 = C66    and 
+                  vari67 = C67    and 
+                  vari68 = C68    and 
+                  vari69 = C69    and 
+                  vari70 = C70    and 
+                  vari71 = C71    and 
+                  vari72 = C72    and 
+                  vari73 = C73    and 
+                  vari74 = C74    and 
+                  vari75 = C75    and 
+                  vari76 = C76    ) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00987" 
+      severity NOTE;
+    assert (   vari1 = C1    and 
+               vari2 = C2    and 
+               vari3 = C3    and 
+               vari4 = C4    and 
+               vari5 = C5    and 
+               vari6 = C6    and 
+               vari7 = C7    and 
+               vari8 = C8    and 
+               vari9 = C9    and 
+               vari10 = C10    and 
+               vari11 = C11    and 
+               vari12 = C12    and 
+               vari13 = C13    and 
+               vari14 = C14    and 
+               vari15 = C15    and 
+               vari16 = C16    and 
+               vari17 = C17    and 
+               vari18 = C18    and 
+               vari19 = C19    and 
+               vari20 = C20    and 
+               vari21 = C21    and 
+               vari22 = C22    and 
+               vari23 = C23    and 
+               vari24 = C24    and 
+               vari25 = C25    and 
+               vari26 = C26    and 
+               vari27 = C27    and 
+               vari28 = C28    and 
+               vari29 = C29    and 
+               vari30 = C30    and 
+               vari31 = C31    and 
+               vari32 = C32    and 
+--      vari33 = C33    and 
+--      vari34 = C34    and 
+--      vari35 = C35    and 
+--      vari36 = C36    and 
+--      vari37 = C37    and 
+--      vari38 = C38    and 
+--      vari39 = C39    and 
+--      vari40 = C40    and 
+               vari41 = C41    and 
+               vari42 = C42    and 
+               vari43 = C43    and 
+               vari44 = C44    and 
+               vari45 = C45    and 
+               vari46 = C46    and 
+               vari47 = C47    and 
+               vari48 = C48    and 
+               vari49 = C49    and 
+               vari50 = C50    and 
+               vari51 = C51    and 
+               vari52 = C52    and 
+               vari53 = C53    and 
+--      vari54 = C54    and 
+--      vari54a = C54a    and 
+--      vari55 = C55    and 
+               vari56 = C56    and 
+               vari57 = C57    and 
+               vari58 = C58    and 
+               vari59 = C59    and 
+               vari60 = C60    and 
+               vari61 = C61    and 
+               vari62 = C62    and 
+               vari63 = C63    and 
+               vari64 = C64    and 
+               vari65 = C65    and 
+               vari66 = C66    and 
+               vari67 = C67    and 
+               vari68 = C68    and 
+               vari69 = C69    and 
+               vari70 = C70    and 
+               vari71 = C71    and 
+               vari72 = C72    and 
+               vari73 = C73    and 
+               vari74 = C74    and 
+               vari75 = C75    and 
+               vari76 = C76    ) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00987 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd
new file mode 100644
index 0000000..bd600d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd
@@ -0,0 +1,916 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc988.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p06n01i00988pkg is
+------------------------------------USING ONLY WHITE MATTER---------------------------------
+--------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr is access boolean ;                                  --simple boolean type   
+  type bit_ptr is access bit ;                                          --simple bit type
+  type char_ptr is access character;                                    --simple character type
+  type severity_level_ptr is access severity_level;                     --simple severity type
+  type integer_ptr is access integer;                                   --simple integer type   
+  type real_ptr is access real;                                         --simple real type
+  type time_ptr is access time;                                         --simple time type
+  type natural_ptr is access natural;                                   --simple natural type
+  type positive_ptr is access positive;                                 --simple positive type
+  type string_ptr is access string;                                     --simple string type
+  type bit_vector_ptr is access bit_vector;                             --simple bit_vector type
+
+--------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st is  integer_vector(0 to 15);
+  subtype real_vector_st is  real_vector(0 to 15);
+  subtype time_vector_st is  time_vector(0 to 15);
+  subtype natural_vector_st is  natural_vector(0 to 15);
+  subtype positive_vector_st is  positive_vector(0 to 15);
+  
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  
+---------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  
+---------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector is array (natural range<>,natural range <>) of bit;
+  type s2char_vector is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector is array (natural range <>,natural range <>) of integer;
+  type s2real_vector is array (natural range <>,natural range <>) of real;
+  type s2time_vector is array (natural range <>,natural range <>) of time;
+  type s2natural_vector is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector is array (natural range <>,natural range <>) of positive;
+  
+----------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column is range 1 to 64;
+  type row is range 1 to 1024;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                   --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                    --simple integer type
+                          g:  real_ptr ;                                    --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i: natural_ptr;                                   --simple natural type
+
+                          j:positive_ptr;                                   --simple positive type
+                          k: string_ptr;                                    --simple string type
+                          l: bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+-----------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr is access boolean_vector;
+  type severity_level_vector_ptr is access severity_level_vector;
+  type integer_vector_ptr is access integer_vector;
+  type real_vector_ptr is access real_vector;
+  type time_vector_ptr is access time_vector;
+  type natural_vector_ptr is access natural_vector;
+  type positive_vector_ptr is access positive_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
+  type severity_level_vector_st_ptr is access  severity_level_vector_st;--(0 to 15);
+  type integer_vector_st_ptr is access  integer_vector_st;--(0 to 15);
+  type real_vector_st_ptr is access  real_vector_st;--(0 to 15);
+  type time_vector_st_ptr is access  time_vector_st;--(0 to 15);
+  type natural_vector_st_ptr is access  natural_vector_st;--(0 to 15);
+  type positive_vector_st_ptr is access  positive_vector_st;--(0 to 15);
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr is access severity_level_cons_vector;
+  type integer_cons_vector_ptr is access  integer_cons_vector;
+  type real_cons_vector_ptr is access real_cons_vector;
+  type time_cons_vector_ptr is access time_cons_vector;
+  type natural_cons_vector_ptr is access natural_cons_vector;
+  type positive_cons_vector_ptr is access  positive_cons_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr is access  real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr is access s2boolean_vector;
+  type s2bit_vector_ptr is access  s2bit_vector;
+  type s2char_vector_ptr is access s2char_vector;
+  type s2severity_level_vector_ptr is access s2severity_level_vector;
+  type s2integer_vector_ptr is access s2integer_vector;
+  type s2real_vector_ptr is access s2real_vector;
+  type s2time_vector_ptr is access  s2time_vector;
+  type s2positive_vector_ptr is access s2positive_vector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr is access  s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr is access  s2integer_cons_vector;
+  type s2real_cons_vector_ptr is access  s2real_cons_vector;
+  type s2time_cons_vector_ptr is access  s2time_cons_vector;
+  type s2natural_cons_vector_ptr is access s2natural_cons_vector;
+  type s2positive_cons_vector_ptr is access s2positive_cons_vector;
+----------------------------------------------------------------------------------------------
+  type record_std_package_ptr is access record_std_package;
+  type record_cons_array_ptr is access  record_cons_array;
+  type record_2cons_array_ptr is access  record_2cons_array;
+  type record_cons_arrayofarray_ptr is access  record_cons_arrayofarray;
+  type record_of_ptr_ptr is access record_of_ptr;
+  type record_of_records_ptr is access record_of_records;
+  type record_array_st_ptr is access record_array_st;
+  
+-----------------------------------------------------------------------------------------------
+-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
+  
+  
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;     --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                 --constrained array
+  function resolution(i:in four_value_vector) return four_value;        --bus resolution
+  subtype four_value_state is resolution four_value;                    --function type
+  type state_vector is array (natural range <>) of four_value_state;    --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                      --array of an array
+  type primary_memory_module is                                         --record with field
+    record                                                                --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;       --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr is access four_value;
+  type four_value_map_ptr is access four_value_map;
+  type binary_ptr is access binary;
+  type four_value_vector_ptr is access four_value_vector;               --ennumerated type
+  type byte_ptr is access byte;
+  type word_ptr is access word;
+  type four_value_state_ptr is access four_value_state;
+  type state_vector_ptr is access state_vector;                         --type returned by resolu.
+  type primary_memory_ptr is access primary_memory;
+  type primary_memory_module_ptr is access primary_memory_module;
+  type whole_memory_ptr is access whole_memory;
+  type current_ptr is access current;
+  type resistance_ptr is access resistance;
+  type delay_ptr is access delay;
+-------------------------------------------------------------------------------------------
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  
+  
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+--constant C33 : s2boolean_vector := ((true,true),(false,false));
+--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
+--constant C35 : s2char_vector := (('s','h'),('i','s'));
+--constant C36 : s2severity_level_vector := ((note,error),(error,note));
+--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
+--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
+--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
+--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
+  constant C41 : s2boolean_cons_vector := (others =>(others => C1));
+  constant C42 : s2bit_cons_vector := (others => (others => C2));
+  constant C43 : s2char_cons_vector := (others =>(others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector := (others => (others => C5));
+  constant C46 : s2real_cons_vector := (others =>(others => C6));
+  constant C47 : s2time_cons_vector := (others =>(others => C7));
+  constant C48 : s2natural_cons_vector := (others =>(others => C8));
+  constant C49 : s2positive_cons_vector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
+--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
+  constant C56 : four_value := 'Z';
+  constant C57 : four_value_map := (true,true,true,true);
+  constant C58 : binary := '0';
+  constant C59 : four_value_vector := ('1','0','1','0');
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C62 : four_value_state := 'Z';
+  constant C63 : state_vector := ('Z','Z','Z','Z');
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  
+end c06s03b00x00p06n01i00988pkg;
+
+package body c06s03b00x00p06n01i00988pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c06s03b00x00p06n01i00988pkg;
+
+use work.c06s03b00x00p06n01i00988pkg.all;
+
+ENTITY c06s03b00x00p06n01i00988ent IS
+END c06s03b00x00p06n01i00988ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00988arch OF c06s03b00x00p06n01i00988ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr := new boolean;
+    variable var2 : bit_ptr := new bit;
+    variable var3 : char_ptr := new character;
+    variable var4 : severity_level_ptr := new severity_level;
+    variable var5 : integer_ptr := new integer;
+    variable var6 : real_ptr := new real;
+    variable var7 : time_ptr := new time;
+    variable var8 : natural_ptr := new natural;
+    variable var9 : positive_ptr := new positive;
+    variable var10 : string_ptr := new string(1 to 7);
+    variable var11 : bit_vector_ptr := new bit_vector(0 to 3);
+    variable var12 : boolean_vector_ptr := new boolean_vector(0 to 1);
+    variable var13 : severity_level_vector_ptr := new severity_level_vector(0 to 1);
+    variable var14 : integer_vector_ptr := new integer_vector(0 to 3);
+    variable var15 : real_vector_ptr := new real_vector(0 to 3);
+    variable var16 : time_vector_ptr := new time_vector(0 to 3);
+    variable var17 : natural_vector_ptr := new natural_vector(0 to 3);
+    variable var18 : positive_vector_ptr := new positive_vector( 0 to 3);
+    variable var19 : boolean_cons_vector_ptr := new boolean_cons_vector;
+    variable var20 : severity_level_cons_vector_ptr := new severity_level_cons_vector;
+    variable var21 : integer_cons_vector_ptr := new integer_cons_vector;
+    variable var22 : real_cons_vector_ptr := new real_cons_vector;
+    variable var23 : time_cons_vector_ptr := new time_cons_vector;
+    variable var24 : natural_cons_vector_ptr := new natural_cons_vector;
+    variable var25 : positive_cons_vector_ptr := new positive_cons_vector;
+    variable var26 : boolean_cons_vectorofvector_ptr := new boolean_cons_vectorofvector;
+    variable var27 : sev_lvl_cons_vecofvec_ptr := new severity_level_cons_vectorofvector;
+    variable var28 : integer_cons_vectorofvector_ptr := new integer_cons_vectorofvector;
+    variable var29 : real_cons_vectorofvector_ptr := new real_cons_vectorofvector;
+    variable var30 : time_cons_vectorofvector_ptr := new time_cons_vectorofvector;
+    variable var31 : natural_cons_vectorofvector_ptr := new natural_cons_vectorofvector;
+    variable var32 : posi_cons_vecofvec_ptr := new positive_cons_vectorofvector;
+--variable var33 : s2boolean_vector_ptr := new s2boolean_vector;
+--variable var34 : s2bit_vector_ptr := new s2bit_vector;
+--variable var35 : s2char_vector_ptr := new s2char_vector;
+--variable var36 : s2severity_level_vector_ptr := new s2severity_level_vector;
+--variable var37 : s2integer_vector_ptr := new s2integer_vector;
+--variable var38 : s2real_vector_ptr := new s2real_vector;
+--variable var39 : s2time_vector_ptr := new s2time_vector;
+--variable var40 : s2positive_vector_ptr := new s2positive_vector;
+    variable var41 : s2boolean_cons_vector_ptr := new s2boolean_cons_vector;
+    variable var42 : s2bit_cons_vector_ptr := new s2bit_cons_vector;
+    variable var43 : s2char_cons_vector_ptr := new s2char_cons_vector;
+    variable var44 : s2sev_lvl_cons_vec_ptr := new s2severity_level_cons_vector;
+    variable var45 : s2integer_cons_vector_ptr := new s2integer_cons_vector;
+    variable var46 : s2real_cons_vector_ptr := new s2real_cons_vector;
+    variable var47 : s2time_cons_vector_ptr := new s2time_cons_vector;
+    variable var48 : s2natural_cons_vector_ptr := new s2natural_cons_vector;
+    variable var49 : s2positive_cons_vector_ptr := new s2positive_cons_vector;
+    variable var50 : record_std_package_ptr := new record_std_package;
+    variable var51 : record_cons_array_ptr := new record_cons_array;
+    variable var52 : record_2cons_array_ptr := new record_2cons_array;
+    variable var53 : record_cons_arrayofarray_ptr := new record_cons_arrayofarray;
+    variable var54 : record_of_ptr_ptr := new record_of_ptr;
+    variable var55 : record_of_records_ptr := new record_of_records;
+    variable var56 : four_value_ptr := new four_value;
+    variable var57 : four_value_map_ptr := new four_value_map;
+    variable var58 : binary_ptr := new binary;
+    variable var59 : four_value_vector_ptr := new four_value_vector(0 to 3);
+    variable var60 : byte_ptr := new byte;
+    variable var61 : word_ptr := new word;
+    variable var62 : four_value_state_ptr := new four_value_state;
+    variable var63 : state_vector_ptr := new state_vector(0 to 3);
+    variable var64 : primary_memory_ptr := new primary_memory;
+    variable var65 : primary_memory_module_ptr := new primary_memory_module;
+    variable var66 : whole_memory_ptr := new whole_memory;
+    variable var67 : current_ptr := new current;
+    variable var68 : resistance_ptr := new resistance;
+    variable var69 : delay_ptr := new delay;
+    variable var70 : boolean_vector_st_ptr := new boolean_vector_st;
+    variable var71 : severity_level_vector_st_ptr := new severity_level_vector_st;
+    variable var72 : integer_vector_st_ptr := new integer_vector_st;
+    variable var73 : real_vector_st_ptr := new real_vector_st;
+    variable var74 : time_vector_st_ptr := new time_vector_st;
+    variable var75 : natural_vector_st_ptr := new natural_vector_st;
+    variable var76 : positive_vector_st_ptr := new positive_vector_st;
+    variable var54a : record_array_st_ptr := new record_array_st;
+    
+    variable vari1 : boolean := C1;
+    variable vari2 : bit := C2;
+    variable vari3 : character := C3;
+    variable vari4 : severity_level := C4;
+    variable vari5 : integer := C5;
+    variable vari6 : real := C6;
+    variable vari7 : time := C7;
+    variable vari8 : natural := C8;
+    variable vari9 : positive := C9;
+    variable vari10 : string(1 to 7) := C10;
+    variable vari11 : bit_vector(0 to 3):= C11;
+    variable vari12 : boolean_vector(0 to 1):= C12;
+    variable vari13 : severity_level_vector(0 to 1) := C13;
+    variable vari14 : integer_vector(0 to 3) := C14;
+    variable vari15 : real_vector(0 to 3):= C15;
+    variable vari16 : time_vector(0 to 3):= C16;
+    variable vari17 : natural_vector(0 to 3):= C17;
+    variable vari18 : positive_vector(0 to 3):= C18;
+    variable vari19 : boolean_cons_vector := C19;
+    variable vari20 : severity_level_cons_vector := C20;
+    variable vari21 : integer_cons_vector := C21;
+    variable vari22 : real_cons_vector := C22;
+    variable vari23 : time_cons_vector := C23;
+    variable vari24 : natural_cons_vector := C24;
+    variable vari25 : positive_cons_vector := C25;
+    variable vari26 : boolean_cons_vectorofvector := C26;
+    variable vari27 : severity_level_cons_vectorofvector := C27;
+    variable vari28 : integer_cons_vectorofvector := C28;
+    variable vari29 : real_cons_vectorofvector := C29;
+    variable vari30 : time_cons_vectorofvector := C30;
+    variable vari31 : natural_cons_vectorofvector := C31;
+    variable vari32 : positive_cons_vectorofvector := C32;
+--variable vari33 : s2boolean_vector := C33;
+--variable vari34 : s2bit_vector := C34;
+--variable vari35 : s2char_vector := C35;
+--variable vari36 : s2severity_level_vector := C36;
+--variable vari37 : s2integer_vector := C37;
+--variable vari38 : s2real_vector := C38;
+--variable vari39 : s2time_vector := C39;
+--variable vari40 : s2positive_vector := C40;
+    variable vari41 : s2boolean_cons_vector := C41;
+    variable vari42 : s2bit_cons_vector := C42;
+    variable vari43 : s2char_cons_vector := C43;
+    variable vari44 : s2severity_level_cons_vector := C44;
+    variable vari45 : s2integer_cons_vector := C45;
+    variable vari46 : s2real_cons_vector := C46;
+    variable vari47 : s2time_cons_vector := C47;
+    variable vari48 : s2natural_cons_vector := C48;
+    variable vari49 : s2positive_cons_vector := C49;
+    variable vari50 : record_std_package := C50;
+    variable vari51 : record_cons_array := C51;
+    variable vari52 : record_2cons_array := C52;
+    variable vari53 : record_cons_arrayofarray := C53;
+--variable vari54 : record_of_ptr := C54;
+--variable vari55 : record_of_records := C55;
+    variable vari56 : four_value := C56;
+    variable vari57 : four_value_map := C57;
+    variable vari58 : binary := C58;
+    variable vari59 : four_value_vector(0 to 3):= C59;
+    variable vari60 : byte := C60;
+    variable vari61 : word := C61;
+    variable vari62 : four_value_state := C62;
+    variable vari63 : state_vector(0 to 3):= C63;
+    variable vari64 : primary_memory := C64;
+    variable vari65 : primary_memory_module := C65;
+    variable vari66 : whole_memory := C66;
+    variable vari67 : current := C67;
+    variable vari68 : resistance := C68;
+    variable vari69 : delay := C69;
+    variable vari70 : boolean_vector_st := C70;
+    variable vari71 : severity_level_vector_st := C71;
+    variable vari72 : integer_vector_st := C72;
+    variable vari73 : real_vector_st := C73;
+    variable vari74 : time_vector_st := C74;
+    variable vari75 : natural_vector_st := C75;
+    variable vari76 : positive_vector_st := C76;
+--variable vari54a : record_array_st := C54a;
+
+  BEGIN
+
+    var1.all := vari1;
+    var2.all := vari2;
+    var3.all := vari3;
+    var4.all := vari4;
+    var5.all := vari5;
+    var6.all := vari6;
+    var7.all := vari7;
+    var8.all := vari8;
+    var9.all := vari9;
+    var10.all := vari10;
+    var11.all := vari11;
+    var12.all := vari12;
+    var13.all := vari13;
+    var14.all := vari14;
+    var15.all := vari15;
+    var16.all := vari16;
+    var17.all := vari17;
+    var18.all := vari18;
+    var19.all := vari19;
+    var20.all := vari20;
+    var21.all := vari21;
+    var22.all := vari22;
+    var23.all := vari23;
+    var24.all := vari24;
+    var25.all := vari25;
+    var26.all := vari26;
+    var27.all := vari27;
+    var28.all := vari28;
+    var29.all := vari29;
+    var30.all := vari30;
+    var31.all := vari31;
+    var32.all := vari32;
+--var33.all := vari33;
+--var34.all := vari34;
+--var35.all := vari35;
+--var36.all := vari36;
+--var37.all := vari37;
+--var38.all := vari38;
+--var39.all := vari39;
+--var40.all := vari40;
+    var41.all := vari41;
+    var42.all := vari42;
+    var43.all := vari43;
+    var44.all := vari44;
+    var45.all := vari45;
+    var46.all := vari46;
+    var47.all := vari47;
+    var48.all := vari48;
+    var49.all := vari49;
+    var50.all := vari50;
+    var51.all := vari51;
+    var52.all := vari52;
+    var53.all := vari53;
+--var54.all := vari54;
+--var55.all := vari55;
+    var56.all := vari56;
+    var57.all := vari57;
+    var58.all := vari58;
+    var59.all := vari59;
+    var60.all := vari60;
+    var61.all := vari61;
+    var62.all := vari62;
+    var63.all := vari63;
+    var64.all := vari64;
+    var65.all := vari65;
+    var66.all := vari66;
+    var67.all := vari67;
+    var68.all := vari68;
+    var69.all := vari69;
+    var70.all := vari70;
+    var71.all := vari71;
+    var72.all := vari72;
+    var73.all := vari73;
+    var74.all := vari74;
+    var75.all := vari75;
+    var76.all := vari76;
+--var54a.all := vari54a;
+    
+    
+    
+    
+    ASSERT var1.all = C1 REPORT "Improper Assignment of var1" SEVERITY FAILURE;
+    ASSERT var2.all = C2 REPORT "Improper Assignment of var2" SEVERITY FAILURE;
+    ASSERT var3.all = C3 REPORT "Improper Assignment of var3" SEVERITY FAILURE;
+    ASSERT var4.all = C4 REPORT "Improper Assignment of var4" SEVERITY FAILURE;
+    ASSERT var5.all = C5 REPORT "Improper Assignment of var5" SEVERITY FAILURE;
+    ASSERT var6.all = C6 REPORT "Improper Assignment of var6" SEVERITY FAILURE;
+    ASSERT var7.all = C7 REPORT "Improper Assignment of var7" SEVERITY FAILURE;
+    ASSERT var8.all = C8 REPORT "Improper Assignment of var8" SEVERITY FAILURE;
+    ASSERT var9.all = C9 REPORT "Improper Assignment of var9" SEVERITY FAILURE;
+    ASSERT var10.all = C10 REPORT "Improper Assignment of var10" SEVERITY FAILURE;
+    ASSERT var11.all = C11 REPORT "Improper Assignment of var11" SEVERITY FAILURE;
+    ASSERT var12.all = C12 REPORT "Improper Assignment of var12" SEVERITY FAILURE;
+    ASSERT var13.all = C13 REPORT "Improper Assignment of var13" SEVERITY FAILURE;
+    ASSERT var14.all = C14 REPORT "Improper Assignment of var14" SEVERITY FAILURE;
+    ASSERT var15.all = C15 REPORT "Improper Assignment of var15" SEVERITY FAILURE;
+    ASSERT var16.all = C16 REPORT "Improper Assignment of var16" SEVERITY FAILURE;
+    ASSERT var17.all = C17 REPORT "Improper Assignment of var17" SEVERITY FAILURE;
+    ASSERT var18.all = C18 REPORT "Improper Assignment of var18" SEVERITY FAILURE;
+    ASSERT var19.all = C19 REPORT "Improper Assignment of var19" SEVERITY FAILURE;
+    ASSERT var20.all = C20 REPORT "Improper Assignment of var20" SEVERITY FAILURE;
+    ASSERT var21.all = C21 REPORT "Improper Assignment of var21" SEVERITY FAILURE;
+    ASSERT var22.all = C22 REPORT "Improper Assignment of var22" SEVERITY FAILURE;
+    ASSERT var23.all = C23 REPORT "Improper Assignment of var23" SEVERITY FAILURE;
+    ASSERT var24.all = C24 REPORT "Improper Assignment of var24" SEVERITY FAILURE;
+    ASSERT var25.all = C25 REPORT "Improper Assignment of var25" SEVERITY FAILURE;
+    ASSERT var26.all = C26 REPORT "Improper Assignment of var26" SEVERITY FAILURE;
+    ASSERT var27.all = C27 REPORT "Improper Assignment of var27" SEVERITY FAILURE;
+    ASSERT var28.all = C28 REPORT "Improper Assignment of var28" SEVERITY FAILURE;
+    ASSERT var29.all = C29 REPORT "Improper Assignment of var29" SEVERITY FAILURE;
+    ASSERT var30.all = C30 REPORT "Improper Assignment of var30" SEVERITY FAILURE;
+    ASSERT var31.all = C31 REPORT "Improper Assignment of var31" SEVERITY FAILURE;
+    ASSERT var32.all = C32 REPORT "Improper Assignment of var32" SEVERITY FAILURE;
+--ASSERT var33.all = C33 REPORT "Improper Assignment of var33" SEVERITY FAILURE;
+--ASSERT var34.all = C34 REPORT "Improper Assignment of var34" SEVERITY FAILURE;
+--ASSERT var35.all = C35 REPORT "Improper Assignment of var35" SEVERITY FAILURE;
+--ASSERT var36.all = C36 REPORT "Improper Assignment of var36" SEVERITY FAILURE;
+--ASSERT var37.all = C37 REPORT "Improper Assignment of var37" SEVERITY FAILURE;
+--ASSERT var38.all = C38 REPORT "Improper Assignment of var38" SEVERITY FAILURE;
+--ASSERT var39.all = C39 REPORT "Improper Assignment of var39" SEVERITY FAILURE;
+--ASSERT var40.all = C40 REPORT "Improper Assignment of var40" SEVERITY FAILURE;
+    ASSERT var41.all = C41 REPORT "Improper Assignment of var41" SEVERITY FAILURE;
+    ASSERT var42.all = C42 REPORT "Improper Assignment of var42" SEVERITY FAILURE;
+    ASSERT var43.all = C43 REPORT "Improper Assignment of var43" SEVERITY FAILURE;
+    ASSERT var44.all = C44 REPORT "Improper Assignment of var44" SEVERITY FAILURE;
+    ASSERT var45.all = C45 REPORT "Improper Assignment of var45" SEVERITY FAILURE;
+    ASSERT var46.all = C46 REPORT "Improper Assignment of var46" SEVERITY FAILURE;
+    ASSERT var47.all = C47 REPORT "Improper Assignment of var47" SEVERITY FAILURE;
+    ASSERT var48.all = C48 REPORT "Improper Assignment of var48" SEVERITY FAILURE;
+    ASSERT var49.all = C49 REPORT "Improper Assignment of var49" SEVERITY FAILURE;
+    ASSERT var50.all = C50 REPORT "Improper Assignment of var50" SEVERITY FAILURE;
+    ASSERT var51.all = C51 REPORT "Improper Assignment of var51" SEVERITY FAILURE;
+    ASSERT var52.all = C52 REPORT "Improper Assignment of var52" SEVERITY FAILURE;
+    ASSERT var53.all = C53 REPORT "Improper Assignment of var53" SEVERITY FAILURE;
+--ASSERT var54.all = C54 REPORT "Improper Assignment of var54" SEVERITY FAILURE;
+--ASSERT var54a.all = C54a REPORT "Improper Assignment of var54a" SEVERITY FAILURE;
+--ASSERT var55.all = C55 REPORT "Improper Assignment of var55" SEVERITY FAILURE;
+    ASSERT var56.all = C56 REPORT "Improper Assignment of var56" SEVERITY FAILURE;
+    ASSERT var57.all = C57 REPORT "Improper Assignment of var57" SEVERITY FAILURE;
+    ASSERT var58.all = C58 REPORT "Improper Assignment of var58" SEVERITY FAILURE;
+    ASSERT var59.all = C59 REPORT "Improper Assignment of var59" SEVERITY FAILURE;
+    ASSERT var60.all = C60 REPORT "Improper Assignment of var60" SEVERITY FAILURE;
+    ASSERT var61.all = C61 REPORT "Improper Assignment of var61" SEVERITY FAILURE;
+    ASSERT var62.all = C62 REPORT "Improper Assignment of var62" SEVERITY FAILURE;
+    ASSERT var63.all = C63 REPORT "Improper Assignment of var63" SEVERITY FAILURE;
+    ASSERT var64.all = C64 REPORT "Improper Assignment of var64" SEVERITY FAILURE;
+    ASSERT var65.all = C65 REPORT "Improper Assignment of var65" SEVERITY FAILURE;
+    ASSERT var66.all = C66 REPORT "Improper Assignment of var66" SEVERITY FAILURE;
+    ASSERT var67.all = C67 REPORT "Improper Assignment of var67" SEVERITY FAILURE;
+    ASSERT var68.all = C68 REPORT "Improper Assignment of var68" SEVERITY FAILURE;
+    ASSERT var69.all = C69 REPORT "Improper Assignment of var69" SEVERITY FAILURE;
+    ASSERT var70.all = C70 REPORT "Improper Assignment of var70" SEVERITY FAILURE;
+    ASSERT var71.all = C71 REPORT "Improper Assignment of var71" SEVERITY FAILURE;
+    ASSERT var72.all = C72 REPORT "Improper Assignment of var72" SEVERITY FAILURE;
+    ASSERT var73.all = C73 REPORT "Improper Assignment of var73" SEVERITY FAILURE;
+    ASSERT var74.all = C74 REPORT "Improper Assignment of var74" SEVERITY FAILURE;
+    ASSERT var75.all = C75 REPORT "Improper Assignment of var75" SEVERITY FAILURE;
+    ASSERT var76.all = C76 REPORT "Improper Assignment of var76" SEVERITY FAILURE;
+
+    assert NOT(   var1.all   = C1    and 
+                  var2.all   = C2    and 
+                  var3.all   = C3    and 
+                  var4.all   = C4    and 
+                  var5.all   = C5    and 
+                  var6.all   = C6    and 
+                  var7.all   = C7    and 
+                  var8.all   = C8    and 
+                  var9.all   = C9    and 
+                  var10.all   = C10    and 
+                  var11.all   = C11    and 
+                  var12.all   = C12    and 
+                  var13.all   = C13    and 
+                  var14.all   = C14    and 
+                  var15.all   = C15    and 
+                  var16.all   = C16    and 
+                  var17.all   = C17    and 
+                  var18.all   = C18    and 
+                  var19.all   = C19    and 
+                  var20.all   = C20    and 
+                  var21.all   = C21    and 
+                  var22.all   = C22    and 
+                  var23.all   = C23    and 
+                  var24.all   = C24    and 
+                  var25.all   = C25    and 
+                  var26.all   = C26    and 
+                  var27.all   = C27    and 
+                  var28.all   = C28    and 
+                  var29.all   = C29    and 
+                  var30.all   = C30    and 
+                  var31.all   = C31    and 
+                  var32.all   = C32    and 
+--      var33.all   = C33    and 
+--      var34.all   = C34    and 
+--      var35.all   = C35    and 
+--      var36.all   = C36    and 
+--      var37.all   = C37    and 
+--      var38.all   = C38    and 
+--      var39.all   = C39    and 
+--      var40.all   = C40    and 
+                  var41.all   = C41    and 
+                  var42.all   = C42    and 
+                  var43.all   = C43    and 
+                  var44.all   = C44    and 
+                  var45.all   = C45    and 
+                  var46.all   = C46    and 
+                  var47.all   = C47    and 
+                  var48.all   = C48    and 
+                  var49.all   = C49    and 
+                  var50.all   = C50    and 
+                  var51.all   = C51    and 
+                  var52.all   = C52    and 
+                  var53.all   = C53    and 
+--      var54.all   = C54    and 
+--      var54a.all   = C54a    and 
+--      var55.all   = C55    and 
+                  var56.all   = C56    and 
+                  var57.all   = C57    and 
+                  var58.all   = C58    and 
+                  var59.all   = C59    and 
+                  var60.all   = C60    and 
+                  var61.all   = C61    and 
+                  var62.all   = C62    and 
+                  var63.all   = C63    and 
+                  var64.all   = C64    and 
+                  var65.all   = C65    and 
+                  var66.all   = C66    and 
+                  var67.all   = C67    and 
+                  var68.all   = C68    and 
+                  var69.all   = C69    and 
+                  var70.all   = C70    and 
+                  var71.all   = C71    and 
+                  var72.all   = C72    and 
+                  var73.all   = C73    and 
+                  var74.all   = C74    and 
+                  var75.all   = C75    and 
+                  var76.all   = C76    ) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00988" 
+      severity NOTE;
+    assert (   var1.all   = C1    and 
+               var2.all   = C2    and 
+               var3.all   = C3    and 
+               var4.all   = C4    and 
+               var5.all   = C5    and 
+               var6.all   = C6    and 
+               var7.all   = C7    and 
+               var8.all   = C8    and 
+               var9.all   = C9    and 
+               var10.all   = C10    and 
+               var11.all   = C11    and 
+               var12.all   = C12    and 
+               var13.all   = C13    and 
+               var14.all   = C14    and 
+               var15.all   = C15    and 
+               var16.all   = C16    and 
+               var17.all   = C17    and 
+               var18.all   = C18    and 
+               var19.all   = C19    and 
+               var20.all   = C20    and 
+               var21.all   = C21    and 
+               var22.all   = C22    and 
+               var23.all   = C23    and 
+               var24.all   = C24    and 
+               var25.all   = C25    and 
+               var26.all   = C26    and 
+               var27.all   = C27    and 
+               var28.all   = C28    and 
+               var29.all   = C29    and 
+               var30.all   = C30    and 
+               var31.all   = C31    and 
+               var32.all   = C32    and 
+--      var33.all   = C33    and 
+--      var34.all   = C34    and 
+--      var35.all   = C35    and 
+--      var36.all   = C36    and 
+--      var37.all   = C37    and 
+--      var38.all   = C38    and 
+--      var39.all   = C39    and 
+--      var40.all   = C40    and 
+               var41.all   = C41    and 
+               var42.all   = C42    and 
+               var43.all   = C43    and 
+               var44.all   = C44    and 
+               var45.all   = C45    and 
+               var46.all   = C46    and 
+               var47.all   = C47    and 
+               var48.all   = C48    and 
+               var49.all   = C49    and 
+               var50.all   = C50    and 
+               var51.all   = C51    and 
+               var52.all   = C52    and 
+               var53.all   = C53    and 
+--      var54.all   = C54    and 
+--      var54a.all   = C54a    and 
+--      var55.all   = C55    and 
+               var56.all   = C56    and 
+               var57.all   = C57    and 
+               var58.all   = C58    and 
+               var59.all   = C59    and 
+               var60.all   = C60    and 
+               var61.all   = C61    and 
+               var62.all   = C62    and 
+               var63.all   = C63    and 
+               var64.all   = C64    and 
+               var65.all   = C65    and 
+               var66.all   = C66    and 
+               var67.all   = C67    and 
+               var68.all   = C68    and 
+               var69.all   = C69    and 
+               var70.all   = C70    and 
+               var71.all   = C71    and 
+               var72.all   = C72    and 
+               var73.all   = C73    and 
+               var74.all   = C74    and 
+               var75.all   = C75    and 
+               var76.all   = C76    ) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00988 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd
new file mode 100644
index 0000000..6a13aa5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc99.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n02i00099ent_a IS
+END c04s03b02x00p29n02i00099ent_a;
+
+ARCHITECTURE c04s03b02x00p29n02i00099arch_a OF c04s03b02x00p29n02i00099ent_a IS
+  
+  PROCEDURE p1 ( prm_in : IN INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_in : constant IS 300;
+  BEGIN
+    ASSERT prm_in'attr1 = 300 REPORT "ERROR: Bad value for prm_in'attr1" SEVERITY FAILURE;
+    assert NOT(prm_in'attr1 = 300)
+      report "***PASSED TEST: c04s03b02x00p29n02i00099"
+      severity NOTE;
+    assert (prm_in'attr1 = 300)
+      report "***FAILED TEST: c04s03b02x00p29n02i00099 - Attribute reading in subprogram fail."
+      severity ERROR;
+  END;
+  
+BEGIN
+  PROCESS
+  BEGIN
+--
+    p1 ( 0 );
+--
+    wait;
+  END PROCESS;
+END c04s03b02x00p29n02i00099arch_a;
+
+
+
+ENTITY c04s03b02x00p29n02i00099ent IS
+END c04s03b02x00p29n02i00099ent;
+
+ARCHITECTURE c04s03b02x00p29n02i00099arch OF c04s03b02x00p29n02i00099ent IS
+  COMPONENT c04s03b02x00p29n02i00099ent_a
+  END COMPONENT;
+  FOR cmp1 : c04s03b02x00p29n02i00099ent_a USE ENTITY work.c04s03b02x00p29n02i00099ent_a(c04s03b02x00p29n02i00099arch_a); 
+  
+  SIGNAL s : INTEGER;
+BEGIN
+
+  cmp1 : c04s03b02x00p29n02i00099ent_a;
+
+END c04s03b02x00p29n02i00099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd
new file mode 100644
index 0000000..6c0fa5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd
@@ -0,0 +1,223 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc992.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p08n01i00992pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+  
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- -----------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- -----------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8;
+-- =========================================================================================
+--
+--          Apply attributes to the package
+--
+  ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      TRUE;
+  ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       '0';
+  ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       'z';
+  ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS         0;
+  ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      10.0;
+  ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS     10 ns;
+  ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS        FX;
+  
+  ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  "packit";
+  ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS    "pack";
+  
+  ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      TRUE;
+  ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       '0';
+  ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       'z';
+  ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS         0;
+  ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      10.0;
+  ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS     10 ns;
+  ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  10000 pf;
+  ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS        FX;
+--
+END;
+
+
+use work.all;
+use c06s03b00x00p08n01i00992pkg.all;
+ENTITY c06s03b00x00p08n01i00992ent IS
+END c06s03b00x00p08n01i00992ent;
+
+ARCHITECTURE c06s03b00x00p08n01i00992arch OF c06s03b00x00p08n01i00992ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+      REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+      REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
+
+    assert NOT( c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+                and c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+                and c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX) 
+      report "***PASSED TEST: c06s03b00x00p08n01i00992"
+      severity NOTE;
+    assert (    c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+                and c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+                and c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX) 
+      report "***FAILED TEST: c06s03b00x00p08n01i00992 - Expanded name denotes a primary unit contained in design library test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n01i00992arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd
new file mode 100644
index 0000000..dac15e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc993.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p08n02i00993pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p08n02i00993pkg;
+
+use work.c06s03b00x00p08n02i00993pkg.all;
+ENTITY c06s03b00x00p08n02i00993ent IS
+END c06s03b00x00p08n02i00993ent;
+
+ARCHITECTURE c06s03b00x00p08n02i00993arch OF c06s03b00x00p08n02i00993ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 10 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V1.S12.S2 = 10)
+      report "***PASSED TEST: c06s03b00x00p08n02i00993"
+      severity NOTE;
+    assert (V1.S12.S2 = 10)
+      report "***FAILED TEST: c06s03b00x00p08n02i00993 - The expanded name denotes all primary units contained in a library if the prefix denotes the library and the suffix is the reserved word all."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n02i00993arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd
new file mode 100644
index 0000000..33cf42a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd
@@ -0,0 +1,216 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc995.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p08n01i00995pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- ------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- ------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8;
+  
+END;
+
+USE WORK.c06s03b00x00p08n01i00995pkg.all;
+ENTITY c06s03b00x00p08n01i00995ent IS
+  ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS      TRUE;
+  ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS       '0';
+  ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS       'z';
+  ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS         0;
+  ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS      10.0;
+  ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS     10 ns;
+  ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS        FX;
+  
+  ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00995ent: ENTITY IS  "entity";
+  ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00995ent: ENTITY IS    "enty";
+  
+  ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS      TRUE;
+  ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS       '0';
+  ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS       'z';
+  ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS         0;
+  ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS      10.0;
+  ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS     10 ns;
+  ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS  10000 pf;
+  ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS        FX;
+END c06s03b00x00p08n01i00995ent;
+
+ARCHITECTURE c06s03b00x00p08n01i00995arch OF c06s03b00x00p08n01i00995ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+      REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+      REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
+
+    assert NOT( c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+                and c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+                and c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'cat_scl8 =        FX   ) 
+      report "***PASSED TEST: c06s03b00x00p08n01i00995"
+      severity NOTE;
+    assert (    c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+                and c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+                and c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'cat_scl8 =        FX   ) 
+      report "***FAILED TEST: c06s03b00x00p08n01i00995 - Expanded name denotes a primary unit contained in design library test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n01i00995arch;