blob: 75d0420829d400d0a9550879ec4a9b8ab6a108de (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc843.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p05n01i00843ent_a is
end c01s03b01x00p05n01i00843ent_a ;
architecture c01s03b01x00p05n01i00843arch_a of c01s03b01x00p05n01i00843ent_a is
begin
AC_BLK : block
signal B : BIT;
begin
B <= '1';
end block;
end c01s03b01x00p05n01i00843arch_a;
ENTITY c01s03b01x00p05n01i00843ent IS
END c01s03b01x00p05n01i00843ent;
ARCHITECTURE c01s03b01x00p05n01i00843arch OF c01s03b01x00p05n01i00843ent IS
BEGIN
A_BLK : block
component C
end component;
begin
L1 : C;
L2 : C;
L3 : C;
L4 : C;
L5 : C;
L6 : C;
L7 : C;
L8 : C;
L9 : C;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p05n01i00843"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p05n01i00843arch;
configuration c01s03b01x00p05n01i00843cfg of c01s03b01x00p05n01i00843ent is
for c01s03b01x00p05n01i00843arch
for A_BLK
for L1 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L2 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L3 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L4 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L5 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L6 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L7 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L8 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
for L9 : C
use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
end for;
end for;
end for ;
end c01s03b01x00p05n01i00843cfg;
|