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author | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
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Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd new file mode 100644 index 0000000..3b2ac9f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd @@ -0,0 +1,121 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +-- code from book + +entity bottom is + port ( terminal Tb : electrical; -- ... ); + -- not in book + terminal Tz : electrical ); + -- end not in book +end entity bottom; + +-- end code from book + + +architecture bottom_arch of bottom is + + -- code from book + + quantity -- ... + i_b1 through Tb to Tz; -- ...; + quantity -- ... + i_b2 through Tb to Tz; -- ...; + quantity -- ... + i_b3 through Tz to Tb; -- ... to Tb; + quantity -- ... + i_b4 through Tz to Tb; -- ... to Tb; + + -- end code from book + +begin + + assert + -- code from book + Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 ) + -- end code from book + ; + +end architecture bottom_arch; + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity other_ent is + port ( terminal Tx, Tz : electrical ); +end entity other_ent; + + +architecture other_arch of other_ent is +begin +end architecture other_arch; + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_03a is + +end entity inline_03a; + + +architecture test of inline_03a is + + terminal Ty, Tb, Tx : electrical; + + -- code from book + + terminal T : electrical; + quantity -- ... + i_t1, i_t2 through T to Ty; -- ...; + quantity -- ... + i_t3 through Ty to T; -- ... to T; + -- ... + + -- end code from book + +begin + + -- code from book + + comp1 : entity work.bottom(bottom_arch) + port map ( Tb => T, -- ... ); + -- not in book + Tz => Ty ); + -- end not in book + + comp2 : entity work.other_ent(other_arch) + port map ( Tx => T, -- ... ); + -- not in book + Tz => Ty ); + -- end not in book + + -- end code from book + + + assert + -- code from book + T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution ) + -- end code from book + ; + +end architecture test; |