Import vests testsuite

11 files changed, 650 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
new file mode 100644
index 0000000..f52bcb8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  port ( terminal node1, node2 : electrical );
+end entity resistor;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+  port ( terminal node1, node2 : electrical );
+end entity capacitor;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity LF353_opamp is
+  port ( terminal plus, minus, output, pos_supply, neg_supply : electrical );
+end entity LF353_opamp;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity active_filter is
+end entity active_filter;
+
+-- end not in book
+
+
+
+library widget_parts, wasp_lib;
+
+architecture component_based of active_filter is
+  
+  -- declaration of signals, terminals, quantities, etc
+  -- ...
+  
+  -- not in book
+
+  terminal input, node2, node3, node4, node7, node15, Vdd, Vss : electrical;
+
+  -- end not in book
+
+begin
+  
+  R1 : entity wasp_lib.resistor
+    port map ( node1 => input, node2 => node2 );
+
+  C1 : entity widget_parts.capacitor
+    port map ( node1 => node3, node2 => ground );
+
+  Amp1 : entity work.LF353_opamp
+    port map ( plus => node4, minus => node7, output => node15,
+               pos_supply => Vdd, neg_supply => Vss );
+
+  -- other component instantiations
+  -- ...
+  
+end architecture component_based;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
new file mode 100644
index 0000000..9532e9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+               
+entity dff is
+  port ( signal d, clk : in std_ulogic;  q : out std_ulogic );
+end entity dff;
+
+----------------------------------------------------------------
+
+architecture behav of dff is
+begin
+  
+  storage : process ( clk ) is
+  begin
+    if clk'event and (clk = '1' or clk = 'H') then
+      q <= d after 5 ns;
+    end if;
+  end process storage;
+        
+end architecture behav;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
new file mode 100644
index 0000000..a01c376
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                          Chapter 7 - Design Processing
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+inverting_integrator.vhd                        entity inverting_integrator             structural                      Figure 7-3
+dff.vhd                                         entity dff                              behav                           Figure 7-4
+volume_sensor.vhd                               entity volume_sensor                    structural                      Figure 7-5
+active_filter.vhd                               entity resistor                         --                              --
+--                                              entity capacitor                        --                              --
+--                                              entity LF353_opamp                      --                              --
+--                                              entity active_filter                    component_based                 Figure 7-7
+inline_01a.vhd                                  entity inline_01a                       test                            Section 7.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 7.1
+inline_03a.vhd                                  entity bottom                           bottom_arch                     Section 7.2
+--                                              entity other_ent                        other_arch                      --
+--                                              entity inline_03a                       test                            Section 7.2
+inline_04a.vhd                                  entity battery                          wrong, correct                  Section 7.2
+--                                              entity inline_04a                       test                            Section 7.2
+inline_05a.vhd                                  entity inline_05a                       test                            Section 7.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_volume_sensor.vhd                            entity tb_volume_sensor                 test_bench                      volume_sensor.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
new file mode 100644
index 0000000..09ff947
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_01a is
+
+end entity inline_01a;
+
+
+----------------------------------------------------------------
+
+
+-- code from book:
+
+library widget_parts, wasp_lib;
+
+use widget_parts.capacitor;
+
+-- end of code from book
+
+
+architecture test of inline_01a is
+
+  terminal node3 : electrical;
+
+begin
+
+  -- code from book:
+
+  C1 : entity capacitor
+    port map ( node1 => node3, node2 => ground );
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
new file mode 100644
index 0000000..f1b8e8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+library wasp_lib;
+
+-- code from book:
+
+use wasp_lib.all;
+
+-- end of code from book
+
+
+architecture test of inline_02a is
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
new file mode 100644
index 0000000..3b2ac9f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+-- code from book
+
+entity bottom is
+  port ( terminal Tb : electrical; -- ... );
+  -- not in book
+         terminal Tz : electrical );
+  -- end not in book
+end entity bottom;
+
+-- end code from book
+
+
+architecture bottom_arch of bottom is
+
+  -- code from book
+
+  quantity -- ...
+           i_b1 through Tb to Tz; -- ...;
+  quantity -- ...
+           i_b2 through Tb to Tz; -- ...;
+  quantity -- ...
+           i_b3 through Tz to Tb; -- ... to Tb;
+  quantity -- ...
+           i_b4 through Tz to Tb; -- ... to Tb;
+
+  -- end code from book
+
+begin
+
+  assert
+  -- code from book
+  Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
+  -- end code from book
+  ;
+
+end architecture bottom_arch;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity other_ent is
+  port ( terminal Tx, Tz : electrical );
+end entity other_ent;
+
+
+architecture other_arch of other_ent is
+begin
+end architecture other_arch;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+  terminal Ty, Tb, Tx : electrical;
+
+  -- code from book
+
+  terminal T : electrical;
+  quantity -- ...
+           i_t1, i_t2 through T to Ty; -- ...;
+  quantity -- ...
+           i_t3 through Ty to T; -- ... to T;
+  -- ...
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  comp1 : entity work.bottom(bottom_arch)
+    port map ( Tb => T, -- ... );
+    -- not in book
+               Tz => Ty );
+    -- end not in book
+  
+  comp2 : entity work.other_ent(other_arch)
+    port map ( Tx => T, -- ... );
+    -- not in book
+               Tz => Ty );
+    -- end not in book
+ 
+  -- end code from book
+
+
+  assert
+  -- code from book
+    T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
+  -- end code from book
+  ;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
new file mode 100644
index 0000000..a3e8cf0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+-- code from book
+
+entity battery is
+  port ( terminal plus, minus : electrical );
+end entity battery;
+
+architecture wrong of battery is
+  constant v_nominal : real := 9.0;
+  quantity v across plus to minus;
+begin
+  v == v_nominal;
+end architecture wrong;
+
+--
+
+architecture correct of battery is
+  constant v_nominal : real := 9.0;
+  quantity v across i through plus to minus;
+begin
+  v == v_nominal;
+end architecture correct;
+
+-- end code from book
+
+                        
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+  signal clamp : bit;
+  quantity v1, v2 : real;
+
+begin
+
+  -- code from book
+
+  if clamp = '1' use
+    v1 == 5.0;
+    v2 == 0.0;
+  else
+    v1 == v2;
+  end use;
+
+  -- end code from book
+
+end architecture test;
+                        
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
new file mode 100644
index 0000000..7cfd1fc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+  -- code from book
+
+  type domain_type is (quiescent_domain, time_domain, frequency_domain);
+  
+  signal domain : domain_type := quiescent_domain;
+
+  -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
new file mode 100644
index 0000000..82e86c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inverting_integrator is 
+  port ( terminal input, output : electrical;
+         signal rst : in std_ulogic );
+end entity inverting_integrator;
+
+----------------------------------------------------------------
+
+architecture structural of inverting_integrator is
+  terminal internal : electrical;
+begin
+  
+  r1 : entity work.resistor(ideal)
+    port map ( node1 => input, node2 => internal);
+  
+  c1 : entity work.capacitor(leakage)
+    port map ( node1 => internal, node2 => output );
+  
+  amp : entity work.opamp(slew_limited)
+    port map ( plus_in => electrical_ref, minus_in => internal,
+               output => output);
+  
+  switch : entity work.analog_switch(ideal)
+    port map ( n1 => internal, n2 => output, control => rst );
+  
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
new file mode 100644
index 0000000..82307fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- created by: Veribest WaveBench Version 16.00.00.02
+library work; use work.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.std_logic_1164.all;
+
+entity  tb_volume_sensor is
+end  tb_volume_sensor;
+
+architecture test_bench of tb_volume_sensor is
+    -- Component declarations
+    -- Signal declarations
+  signal	clk, full, rst : std_logic;
+  terminal	flow, minus_ref : electrical;
+
+begin
+    -- Signal assignments
+    -- Component instances
+
+    vol1 : entity work.volume_sensor(structural)
+        port map(
+            clk => clk,
+            full => full,
+			rst => rst,
+			flow => flow,
+			minus_ref => minus_ref
+        );
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 16.0
+        )
+        port map(
+            pos => flow,
+            neg => ELECTRICAL_REF
+        );
+    vm_ref : entity work.v_constant(ideal)
+        generic map(
+            level => -10.0
+        )
+        port map(
+            pos => minus_ref,
+            neg => ELECTRICAL_REF
+        );
+-- Test code generation processes  
+  -- clk
+    P_clk :
+    process
+    begin
+        clk <= '1';
+        wait for 500000.000 ns;
+        clk <= '0';
+        wait for 500000.000 ns;
+    end process P_clk;
+
+  -- rst
+    P_rst :
+    process
+    begin
+    	wait for 0.0 ms;	rst <=  '0';
+  		wait for 2.0 ms;	rst <=  '1';
+		wait for 2.0 ms;	rst <=  '0';
+		wait;
+    end process;
+
+  end test_bench;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
new file mode 100644
index 0000000..6791450
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity volume_sensor is
+  port ( terminal flow, minus_ref : electrical;
+         signal clk, rst : in std_ulogic;
+         signal full : out std_ulogic );
+end entity volume_sensor;
+
+----------------------------------------------------------------
+
+architecture structural of volume_sensor is
+  
+  terminal minus_volume : electrical;
+  signal async_full, sync1_full : std_ulogic;
+  
+begin
+  
+  int : entity work.inverting_integrator(structural)
+    port map ( input => flow, output => minus_volume, rst => rst );
+        
+  comp : entity work.comparator(hysteresis)
+    port map ( plus_in => minus_volume, minus_in => minus_ref,
+               output => async_full );
+        
+  sync1 : entity work.dff(behav)
+    port map ( d => async_full, clk => clk, q => sync1_full );
+        
+  sync2 : entity work.dff(behav)
+    port map ( d => sync1_full, clk => clk, q => full );
+        
+end architecture structural;