Import vests testsuite

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+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: res_component.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity resistor is
+	port (terminal P, N : electrical );
+end resistor;
+
+architecture behav of resistor is 
+   quantity VPTON across IPTON through P to N;
+begin
+	res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture structure of resistor_ckt is
+
+	component resistor is 
+           port (terminal P, N : electrical );
+	end component;
+        for all : resistor use entity work.resistor(behav);  
+	terminal X,Y,Z,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across X to electrical'reference;
+
+begin
+	R1 : resistor port map (P => X, N => Y);
+	R2 : resistor port map (P => Y, N => Z);
+ 	--R3 : vout == iout * 200.0;
+	R3 : resistor port map (P => t2, N => ground);
+	R4 : resistor port map (P => Z, N => t1);
+	R5 : resistor port map (P => t1, N => t2);
+      vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+end structure;