Import vests testsuite

14 files changed, 1287 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
new file mode 100644
index 0000000..c3bf7ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: above_attr.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+   -- NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  constant R1: real :=10.0;
+  constant R2: real :=5.0;
+  terminal T1,T2:electrical;
+  quantity V1 across I1 through T1 to T2;
+  quantity V2 across I2 through T2;
+  quantity VS across T1;
+  quantity rt:real;
+  signal ABSIG,o:boolean;
+  --signal y:bit;
+
+begin
+
+
+ABSIG<=V1'above(V2+1.0);
+            
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 33) :=
+            "time ABSIG";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        VARIABLE tmp:bit;
+        FILE outfile: text OPEN WRITE_MODE IS "above_attr.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            IF (ABSIG = true) THEN
+            tmp:='1';
+            ELSE
+            tmp:='0';
+            WRITE(outline,tmp);
+            END IF;
+            WRITE(outline,seperator);
+            writeline(outfile,outline);
+        END IF;
+        WAIT ON ABSIG;
+    END PROCESS;
+
+e1:      V1 == I1*R1;
+e2:      V2 == I2*R2;
+esource: VS == 5.0 * sin(2.0 * 3.141592 *100.0 * real(time'pos(now))*1.0e-15);
+
+END ARCHITECTURE atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams
new file mode 100644
index 0000000..cd49b93
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams
@@ -0,0 +1,135 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: am_modulation.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--Package defining eleectrical nature and some functions...
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.ALL;
+----------------------------------------------------------------------  
+-- The sinusoidal voltage source definition begins.....  
+----------------------------------------------------------------------  
+-- Schematic of the sinusoidal voltage source:  
+-- -------------------------------------------  
+--  
+--        p o----(~)----o m a sinusoidal voltage of amplitude ampl  
+--                  Vs          and frequency 'freq'.  
+----------------------------------------------------------------------  
+ 
+--entity declaration.  
+ENTITY sineSource IS    
+    generic (ampl,freq : REAL);  
+    PORT(TERMINAL p,m: ELECTRICAL); --Interface ports.  
+END;  
+ 
+--architecture declaration.  
+ARCHITECTURE behav OF sineSource IS  
+    --quantity declarations.  
+    quantity v_in across i_out through p to m;  
+BEGIN  
+     -- The sinusoidal voltage source equation.        
+     v_in==ampl * sin (2.0*3.14* freq *  real(time'pos(now)) * 1.0e-15); --input sinusoidal source  
+END;  
+   
+USE work.electricalSystem.ALL; 
+----------------------------------------------------------------------  
+-- The resistor definition begins.....  
+----------------------------------------------------------------------  
+-- Schematic of the resistor component:  
+--  
+--        p o----/\/\/\----o m  
+--          
+----------------------------------------------------------------------  
+ 
+ENTITY resistor IS  
+    GENERIC  (resistance    : REAL);        --resistance value given as a generic parameter.
+ 
+    PORT     (TERMINAL p,m  : ELECTRICAL);    --Interface ports.  
+END resistor;  
+ 
+ARCHITECTURE behav OF resistor IS  
+    quantity r_e across r_i through p to m;  
+BEGIN  
+    r_i == r_e/resistance;  -- The ohmic resistance equation.  
+END behav;  
+----------------------------------------------------------------  
+ 
+ 
+USE work.electricalSystem.ALL;
+-----------------------------------------------------------------     
+--testbench  
+-- ==============================================================  
+--  n1                    R2 1k                     n2  
+--  o __________________/\/\/\__________________o                    
+--  |             |               |        |                    
+--  | T1          |               |        |  
+--  |             <               <        |  
+-- (~)modulation  < R1            <    R3 (~) basiswave  
+--  | 100(sinwt)  < 1k            <    1k    |  320(sinwt)   
+--  |              |               |        |  
+--  |             |               |        |  
+--  o___________________________________________o  
+--                        | gnd          
+--                      -----      
+ 
+ENTITY network IS  
+END;  
+                                                 
+ARCHITECTURE behav OF network IS 
+component sineSource IS
+    generic (ampl,freq : REAL);
+    PORT(TERMINAL p,m: ELECTRICAL); --Interface ports.
+END component;
+
+component resistor IS
+    GENERIC  (resistance    : REAL);        --resistance value given as a generic parameter.
+    
+    PORT     (TERMINAL p,m  : ELECTRICAL);    --Interface ports.
+END component;
+     
+    terminal n1,n2: ELECTRICAL;  
+BEGIN  
+    Modulation  : sineSource  generic MAP(100.0,5000.0) PORT MAP(n1,ground);
+ 
+    R1   : Resistor    generic MAP(1000.0)       PORT MAP(n1,ground);
+ 
+    Groundwave  : sineSource  generic MAP(320.0,500.0)  PORT MAP(n2,ground);
+ 
+    R3   : Resistor    generic MAP(1000.0)       PORT MAP (n2,ground);
+ 
+    R2   : Resistor    generic MAP(1000.0)       PORT MAP (n1, n2);
+ 
+END;              
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
new file mode 100644
index 0000000..eb636b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: generic_model.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- trying to check both ports and generics.
+-- resistor component below has both port and generic.
+-- same example as in mixed_mode_1 with ports
+-- simulate for 2e10
+-- end comments by shishir.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use std.textio.all ;
+
+entity NOT_GATE is
+  generic ( delay : TIME := 100 ns ) ; 
+  port (
+    C : in bit;
+    Cbar : out bit);
+ 
+end NOT_GATE;
+ 
+architecture dataflow  of NOT_GATE is
+ --signal my : bit := '0'; 
+begin  -- dataflow
+ 
+  Cbar <= not C after delay ;
+ 
+end dataflow ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+entity resistor is
+        generic ( resvalue : real := 100.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * resvalue ;
+end behav;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component NOT_GATE is
+  generic ( delay : TIME := 100 ns) ; 
+  port (
+    C : in bit;
+    Cbar : out bit);
+        end component ;
+   for all : NOT_GATE use entity work.NOT_GATE(dataflow) ;
+
+   component resistor is
+           generic ( resvalue : real := 100.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+  --QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2;
+  --QUANTITY vr2 ACROSS ir2 THROUGH n2 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+-- digital component instantiation.
+   D2 : NOT_GATE generic map ( delay => 1000 ns) port map(C=>y, Cbar=>y);       
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y ";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "generic_model.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+
+-- analog  component instantiation.
+-- for some strange reason if i put it above the process, it does not work.
+
+  R1 : resistor generic map ( resvalue => 500.0) port map (P => n1, N => n2); 
+  --R1 : resistor port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+--    R1 : vr1 == ir1 * 100.0 ;
+ --   R2 : vr2 == ir2 * 100.0 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out
new file mode 100644
index 0000000..34d04f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out
@@ -0,0 +1,21 @@
+time ABSIGtestbenchwork_Dte
+1098543.277411 NS  
+4034001.034625 NS 0 
+11029402.988035 NS  
+14000633.820645 NS 0 
+21180065.574642 NS  
+24074961.958137 NS 0 
+31051068.654154 NS  
+34010938.898262 NS 0 
+41184808.429215 NS  
+44077392.700384 NS 0 
+51052348.254524 NS  
+54011554.141123 NS 0 
+61185092.495303 NS  
+64077540.337822 NS 0 
+71052427.799030 NS  
+74011594.434932 NS 0 
+81185113.202536 NS  
+84077552.980693 NS 0 
+91052436.416308 NS  
+94011600.731912 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out
new file mode 100644
index 0000000..5e1e142
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out
@@ -0,0 +1,21 @@
+time y 
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out
new file mode 100644
index 0000000..5530249
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out
@@ -0,0 +1,21 @@
+time y
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out
new file mode 100644
index 0000000..5530249
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out
@@ -0,0 +1,21 @@
+time y
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams
new file mode 100644
index 0000000..f0e4f12
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 1998-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mesh.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- /**************************************************************************/
+-- /* File: mesh.ams                                                         */
+-- /**************************************************************************/
+-- /* Author:           Venkateswaran Krishna                                */
+-- /* Date of creation: Dec 1 1998                                           */
+-- /* Last changed by:  Venkateswaran Krishna                                */
+-- /**************************************************************************/
+-- Roadmap
+----------
+--While it might look like a trivial circuit this model actually
+--managed to find a breach in seams!! Specifically with the code
+--generation of generics... so it is important to have it as part
+--of the test suite. The model is a small mesh ckt with 3 resistors
+--and 2 voltage sources.. simple nodal soln of the mesh is all that
+--seams has to do
+--
+--
+--    t1    1      t2    3      t3
+--    o---/\/\/\---o---/\/\/\---o
+--    |            |            |
+--    |            <            |
+--   ( )5v         <2          ( )10v
+--    |            <            |
+--    |            |            |
+--    o------------o------------o
+--                 |
+--                _|
+--                \/
+
+--package definition
+PACKAGE electricalSystem IS
+    
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+    
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+   generic(r: real := 10000.0 );  --- resistance
+   port( terminal tr1,tr2 : electrical); --- interface ports
+end resistor;
+
+architecture rbehavior of resistor is
+   quantity Vr across Ir through tr1 to tr2;
+begin
+   Vr == Ir*r;
+end architecture rbehavior; --- of resisitor
+
+
+use work.electricalSystem.all;
+ENTITY constVSource IS
+    GENERIC (voltage : real := 10.0);
+    PORT (TERMINAL ta4, tb4 : electrical );
+END constVSource;
+
+ARCHITECTURE behavioral OF constVSource IS
+    quantity vsource across isource through ta4 TO tb4;
+BEGIN  -- behavior
+    constSource_equation: vsource == voltage;
+END behavioral;
+
+
+use work.electricalSystem.all;
+
+entity mesh is
+end mesh;
+
+architecture struc of mesh is
+
+  terminal t1, t2, t3  : electrical;
+
+  component resComp
+    generic(r: real := 10000.0 );  --- resistance
+    port( terminal tr1,tr2 : electrical); --- interface ports
+  end component;
+
+  for all : rescomp use entity work.resistor(rbehavior);
+
+  component source
+    GENERIC (voltage : real := 10.0);
+    PORT (TERMINAL ta4, tb4 : electrical );
+  END component;
+
+  for all : source use entity work.constVSource(behavioral);
+
+begin
+
+  voltage_source1: source
+    generic map(5.0)
+    port map(t1, ground);
+
+  voltage_source2: source
+    port map(t3, ground);
+
+  r1: resComp
+    generic map(1.0)
+    port map(t1, t2);
+
+  r2: resComp
+    generic map(2.0)
+    port map(t2, ground);
+
+  r3: resComp
+    generic map(3.0)
+    port map(t2, t3);
+
+end;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
new file mode 100644
index 0000000..10fd3bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_model_1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- an example of a model having both a signal assignment statement
+-- as well as a simple simultaneous statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+    CONSTANT resistance1 : real := 100.0;        -- value of R1
+    terminal n1 : electrical;
+  QUANTITY vIn ACROSS n1;
+  QUANTITY vR ACROSS iR THROUGH n1 ;
+  signal y:bit:='0';
+BEGIN
+
+process(y)
+begin
+  y <= not(y) after 1000 ns;
+ 
+end process;
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "mixed_model_1.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+  res_stmt1: vR == iR * resistance1 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
new file mode 100644
index 0000000..dd80c23
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_model_2.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This is a model that has both a signal assignment statement as well as a
+-- simple simultaneous statement.  So supposedly uses both digital and
+-- analog kernel but does not have any interaction between digital and
+-- analog portion.  Also there is a port declaration to check whether
+-- addition of code for terminals in ports has not affected the digital
+-- part.  same example as in mixed_mode_1 with ports simulate for 2e10 end
+-- comments by shishir.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use std.textio.all ;
+
+entity NOT_GATE is
+ 
+  port (
+    C : in bit;
+    Cbar : out bit);
+ 
+end NOT_GATE;
+ 
+architecture dataflow  of NOT_GATE is
+ 
+begin  -- dataflow
+ 
+  Cbar <= not C after 1000 ns;
+ 
+end dataflow ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+entity resistor is
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component NOT_GATE is
+  port (
+    C : in bit;
+    Cbar : out bit);
+        end component ;
+   for all : NOT_GATE use entity work.NOT_GATE(dataflow) ;
+
+   component resistor is
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+  QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2;
+  QUANTITY vr2 ACROSS ir2 THROUGH n2 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+-- digital component instantiation.
+   D2 : NOT_GATE port map(C=>y, Cbar=>y);       
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "mixed_model_2.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+
+-- analog  component instantiation.
+-- for some strange reason if i put it above the process, it does not work.
+
+  R1 : resistor port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+--    R1 : vr1 == ir1 * 100.0 ;
+ --   R2 : vr2 == ir2 * 100.0 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams
new file mode 100644
index 0000000..c09cd0f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: multiple_res_comp.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity bad_resistor is
+	port (terminal P, N : electrical );
+end bad_resistor;
+
+architecture behav of bad_resistor is 
+   quantity VPTON across IPTON through P to N;
+begin
+	res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+use work.electricalsystem.all;
+entity good_resistor is
+	port (terminal P, N : electrical );
+end good_resistor;
+
+architecture behav of good_resistor is 
+   quantity VP across IP through P to N;
+begin
+	res1 : VP == IP * 1000.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture structure of resistor_ckt is
+
+	component bad_resistor is 
+           port (terminal P, N : electrical );
+	end component;
+
+	component good_resistor is 
+           port (terminal P, N : electrical );
+	end component;
+
+        for all : good_resistor use entity work.good_resistor(behav);  
+        for all : bad_resistor use entity work.bad_resistor(behav);  
+
+	terminal X,Y,Z,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across X to electrical'reference;
+
+begin
+	R1 : bad_resistor port map (P => X, N => Y);
+	R2 : bad_resistor port map (P => Y, N => Z);
+ 	R3 : vout == iout * 1200.0;
+	R4 : good_resistor port map (P => Z, N => t1);
+	R5 : good_resistor port map (P => t1, N => t2);
+      vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+end structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams
new file mode 100644
index 0000000..5ceeaf0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: parallel-plate.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This model was tested and compared with SPICE.
+-- The results match with SPICE
+-- The model implements a simple parallel place cap with just 
+-- one top and one bottom  plate.
+-- simulation time 2e11.
+-- Initially proposed by Dr. Carter.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity plate is 
+	generic (
+		cell_resistance : real := 1000.0 
+		);
+
+	port ( 
+		terminal up, down, left, right, top : electrical 
+	    );
+end entity plate;
+
+architecture behav of plate is 
+
+quantity Vup across Iup through up to top ;
+quantity Vdown across Idown through down to top ;
+quantity Vleft across Ileft through left to top ;
+quantity Vright across Iright through right to top ;
+
+begin
+
+	Rup : Vup == Iup * cell_resistance ; 
+	Rdown : Vdown == Idown * cell_resistance ; 
+	Rleft : Vleft == Ileft * cell_resistance ; 
+	Rright : Vright == Iright * cell_resistance ; 
+end behav ;
+
+
+use work.electricalSystem.all;
+
+entity parallel_plate_cap is
+end entity;
+
+architecture struc of parallel_plate_cap is
+	component plate is 
+        generic (
+                cell_resistance : real := 1000.0
+                );
+	    port (
+		   terminal up, down, left, right, top : electrical
+                 );
+	end component ;
+        for all : plate use entity work.plate(behav);    
+
+	terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2 : electrical ;
+
+	quantity vcap across icap through top1 to top2 ;
+	quantity vrgnd across irgnd through top2 ;
+	quantity vs1 across left1 to left2;
+	quantity vs2 across right1 to right2;
+	quantity vs3 across up1 to up2;
+	quantity vs4 across down1 to down2;
+
+	constant cell_cap : real := 1.0e-6;
+	
+begin
+	plate1 : plate port map ( up1, down1, left1, right1, top1) ;
+        plate2 : plate port map ( up2, down2, left2, right2, top2) ;
+	--plate2 : plate port map ( up2, down2, left2, right2, ground) ;
+	
+	capeqn : icap == cell_cap * vcap'dot;
+	-- there should be some ground
+	resgnd : vrgnd == irgnd * 1000.0 ;
+        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc2 : vs2  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc3 : vs3  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc4 : vs4  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+
+end struc ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams
new file mode 100644
index 0000000..a4ebbe2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams
@@ -0,0 +1,161 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: parallel-plates4.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This model was tested and compared with SPICE.
+-- The results match with SPICE
+-- The model implements a simple parallel plate cap with just 
+-- one top and one bottom  plate.
+-- The top and bottom plates have been divided into 4 sub plates.
+-- Actually its like 4 parallel-plate subsections have been connected
+-- to form the capacitor.
+-- simulation time 2e11.
+-- Initially proposed by Dr. Carter.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity plate is 
+	generic (
+		cell_resistance : real := 1000.0 
+		);
+
+	port ( 
+		terminal up, down, left, right, top : electrical 
+	    );
+end entity plate;
+
+architecture behav of plate is 
+
+quantity Vup across Iup through up to top ;
+quantity Vdown across Idown through down to top ;
+quantity Vleft across Ileft through left to top ;
+quantity Vright across Iright through right to top ;
+
+begin
+
+	Rup : Vup == Iup * cell_resistance ; 
+	Rdown : Vdown == Idown * cell_resistance ; 
+	Rleft : Vleft == Ileft * cell_resistance ; 
+	Rright : Vright == Iright * cell_resistance ; 
+end behav ;
+
+
+use work.electricalSystem.all;
+
+entity parallel_plate_cap is
+	port ( 
+	     terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical 
+	    );
+end entity;
+
+architecture struc of parallel_plate_cap is
+	component plate is 
+        generic (
+                cell_resistance : real := 1000.0
+                );
+	    port (
+		   terminal up, down, left, right, top : electrical
+                 );
+	end component ;
+        for all : plate use entity work.plate(behav);    
+
+	-- this need not be in the port list but i am adding it
+	-- to observe vcap uniquely.
+	--terminal top1, top2 : electrical ;
+	quantity vcap across icap through top1 to top2 ;
+	quantity vrgnd across irgnd through top2 ;
+--	quantity vs1 across left1 to left2;
+--	quantity vs2 across right1 to right2;
+--	quantity vs3 across up1 to up2;
+--	quantity vs4 across down1 to down2;
+
+	constant cell_cap : real := 1.0e-8;
+	
+begin
+	plate1 : plate port map ( up1, down1, left1, right1, top1) ;
+        plate2 : plate port map ( up2, down2, left2, right2, top2) ;
+	--plate2 : plate port map ( up2, down2, left2, right2, ground) ;
+	
+	capeqn : icap == cell_cap * vcap'dot;
+	-- there should be some ground
+	resgnd : vrgnd == irgnd * 1000.0 ;
+--        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                   --            * real(time'pos(now)) * 1.0e-15);
+ --       vsrc2 : vs2  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+ --                              * real(time'pos(now)) * 1.0e-15);
+  --      vsrc3 : vs3  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+   --                            * real(time'pos(now)) * 1.0e-15);
+    --    vsrc4 : vs4  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+     --                          * real(time'pos(now)) * 1.0e-15);
+
+end struc ;
+
+use work.electricalSystem.all;
+
+entity real_cap is 
+end entity ;
+
+architecture struct of real_cap is 
+	component parallel_plate_cap is
+	port ( 
+	     terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical 
+	    );
+	end component ;
+
+	for all : parallel_plate_cap use entity work.parallel_plate_cap(struc);
+
+	terminal u1, u2, u3 , u4, d1, d2, d3, d4, l1, l2 , r1, r2, r3, r4 , t1, t2, t3, t4: electrical ;
+	terminal d11, d21, d31, d41, l11, l21 , r11, r21, r31, r41 , t11, t21, t31, t41: electrical ;
+	-- not needed.
+	--terminal l3 , l4 : electrical ;
+
+	quantity vs across l1 to l2 ;
+	quantity vs1 across l11 to l21 ;
+
+
+begin
+
+	p1 : parallel_plate_cap port map (u1, u2, d1, d2, l1, l2, r1, r2, t1, t2);
+	p2 : parallel_plate_cap port map (u3, u4, d3, d4, r1, r2, r3, r4, t3, t4);
+	p3 : parallel_plate_cap port map (d1, d2, d11, d21, l11, l21, r11, r21, t11, t21);
+	p4 : parallel_plate_cap port map (d3, d4, d31, d41, r11, r21, r31, r41, t31, t41);
+
+        vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                              * real(time'pos(now)) * 1.0e-15);
+        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                              * real(time'pos(now)) * 1.0e-15);
+
+end ;	
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams
new file mode 100644
index 0000000..32f8762
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: res_component.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity resistor is
+	port (terminal P, N : electrical );
+end resistor;
+
+architecture behav of resistor is 
+   quantity VPTON across IPTON through P to N;
+begin
+	res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture structure of resistor_ckt is
+
+	component resistor is 
+           port (terminal P, N : electrical );
+	end component;
+        for all : resistor use entity work.resistor(behav);  
+	terminal X,Y,Z,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across X to electrical'reference;
+
+begin
+	R1 : resistor port map (P => X, N => Y);
+	R2 : resistor port map (P => Y, N => Z);
+ 	--R3 : vout == iout * 200.0;
+	R3 : resistor port map (P => t2, N => ground);
+	R4 : resistor port map (P => Z, N => t1);
+	R5 : resistor port map (P => t1, N => t2);
+      vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+end structure;