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author | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd')
-rw-r--r-- | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd new file mode 100644 index 0000000..2e9a327 --- /dev/null +++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +architecture behavioral of accumulator_reg is +begin + + behavior : process (clk) is + + constant Tpd_clk_out : time := 3 ns; + + begin + if rising_edge(clk) then + if To_X01(clr) = '1' then + q <= (others => '0') after Tpd_clk_out; + else + q <= d after Tpd_clk_out; + end if; + end if; + end process behavior; + +end architecture behavioral; |