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authorTristan Gingold2015-03-14 07:27:00 +0100
committerTristan Gingold2015-03-14 07:27:00 +0100
commitcf2ab2cf781a5c689739d57097d6da7ea6e710a0 (patch)
tree250447e93cb38e3bca1f766bf255c2cbfa1393f6 /testsuite/gna/ticket40/generic_when_test2.vhdl
parentfb10c3db8616f63ed33ba3d2d0f62bc0514ac536 (diff)
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Add reproducer for ticket40.
Diffstat (limited to 'testsuite/gna/ticket40/generic_when_test2.vhdl')
-rw-r--r--testsuite/gna/ticket40/generic_when_test2.vhdl37
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/gna/ticket40/generic_when_test2.vhdl b/testsuite/gna/ticket40/generic_when_test2.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+--use work.GENERIC_WHEN.all;
+
+entity TEST2 is
+begin
+end entity TEST2;
+
+architecture BEHAVIOUR of TEST2 is
+ component GENERIC_WHEN is
+ generic( FOO : std_logic_vector(1 downto 0) );
+ port( IN1 : in std_logic_vector(1 downto 0);
+ OUT1 : out std_logic_vector(1 downto 0) );
+ end component GENERIC_WHEN;
+
+ signal S1 : std_logic_vector(1 downto 0);
+ signal S2 : std_logic_vector(1 downto 0);
+begin
+
+ GENERIC_WHEN_INST : GENERIC_WHEN
+ generic map ( FOO => "0" & "0")
+ port map ( IN1 => S1,
+ OUT1 => S2 );
+ process
+ variable l : line;
+ begin
+ S1 <= "01";
+ writeline(output, l);
+ wait;
+ end process;
+
+end architecture BEHAVIOUR;
+