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| author | Tristan Gingold | 2016-01-16 13:37:17 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2016-01-16 13:37:17 +0100 |
| commit | c3c11edfccd3fca36417ad2ad60531272c3766aa (patch) | |
| tree | 06b9cd453477b7e361b350abba856b54726097c1 /testsuite/gna/issue17/cond_assign_sig.vhdl | |
| parent | 929fc2f9cfd2df23876ee289fe2faba20489d715 (diff) | |
| download | ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.tar.gz ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.tar.bz2 ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.zip | |
Add testcase for issue17.
Diffstat (limited to 'testsuite/gna/issue17/cond_assign_sig.vhdl')
| -rw-r--r-- | testsuite/gna/issue17/cond_assign_sig.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/gna/issue17/cond_assign_sig.vhdl b/testsuite/gna/issue17/cond_assign_sig.vhdl new file mode 100644 index 0000000..ad8a0a4 --- /dev/null +++ b/testsuite/gna/issue17/cond_assign_sig.vhdl @@ -0,0 +1,28 @@ +library ieee ;
+use ieee.std_logic_1164.all ;
+use std.textio.all ;
+
+entity cond_assign_sig is
+end entity cond_assign_sig ;
+
+architecture doit of cond_assign_sig is
+ signal Clk : std_logic := '0' ;
+ signal Y : std_logic ;
+begin
+ Clk <= not Clk after 10 ns ;
+
+ process (Clk)
+ begin
+ Y <= 'H' when Clk = '1' else 'L' ;
+ end process ;
+
+-- Y <= 'H' when Clk = '1' else 'L' ;
+
+ process
+ begin
+ wait for 500 ns ;
+ std.env.stop ;
+ end process ;
+end architecture doit ;
+
+
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