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| author | Tristan Gingold | 2016-01-16 13:37:17 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2016-01-16 13:37:17 +0100 |
| commit | c3c11edfccd3fca36417ad2ad60531272c3766aa (patch) | |
| tree | 06b9cd453477b7e361b350abba856b54726097c1 | |
| parent | 929fc2f9cfd2df23876ee289fe2faba20489d715 (diff) | |
| download | ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.tar.gz ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.tar.bz2 ghdl-c3c11edfccd3fca36417ad2ad60531272c3766aa.zip | |
Add testcase for issue17.
| -rw-r--r-- | testsuite/gna/issue17/cond_assign_proc.vhdl | 30 | ||||
| -rw-r--r-- | testsuite/gna/issue17/cond_assign_sig.vhdl | 28 | ||||
| -rw-r--r-- | testsuite/gna/issue17/cond_assign_var.vhdl | 31 | ||||
| -rwxr-xr-x | testsuite/gna/issue17/testsuite.sh | 17 |
4 files changed, 106 insertions, 0 deletions
diff --git a/testsuite/gna/issue17/cond_assign_proc.vhdl b/testsuite/gna/issue17/cond_assign_proc.vhdl new file mode 100644 index 0000000..8a2660d --- /dev/null +++ b/testsuite/gna/issue17/cond_assign_proc.vhdl @@ -0,0 +1,30 @@ +library ieee ;
+use ieee.std_logic_1164.all ;
+use std.textio.all ;
+
+entity cond_assign_proc is
+end entity cond_assign_proc ;
+architecture doit of cond_assign_proc is
+ signal Clk : std_logic := '0' ;
+ signal Y : std_logic ;
+begin
+ Clk <= not Clk after 10 ns ;
+
+ process (Clk)
+ variable A : std_logic ;
+ begin
+ A := 'H' when Clk = '1' else 'L' ;
+ Y <= A ;
+-- Y <= 'H' when Clk = '1' else 'L' ;
+ end process ;
+
+-- Y <= 'H' when Clk = '1' else 'L' ;
+
+ process
+ begin
+ wait for 500 ns ;
+ std.env.stop ;
+ end process ;
+end architecture doit ;
+
+
diff --git a/testsuite/gna/issue17/cond_assign_sig.vhdl b/testsuite/gna/issue17/cond_assign_sig.vhdl new file mode 100644 index 0000000..ad8a0a4 --- /dev/null +++ b/testsuite/gna/issue17/cond_assign_sig.vhdl @@ -0,0 +1,28 @@ +library ieee ;
+use ieee.std_logic_1164.all ;
+use std.textio.all ;
+
+entity cond_assign_sig is
+end entity cond_assign_sig ;
+
+architecture doit of cond_assign_sig is
+ signal Clk : std_logic := '0' ;
+ signal Y : std_logic ;
+begin
+ Clk <= not Clk after 10 ns ;
+
+ process (Clk)
+ begin
+ Y <= 'H' when Clk = '1' else 'L' ;
+ end process ;
+
+-- Y <= 'H' when Clk = '1' else 'L' ;
+
+ process
+ begin
+ wait for 500 ns ;
+ std.env.stop ;
+ end process ;
+end architecture doit ;
+
+
diff --git a/testsuite/gna/issue17/cond_assign_var.vhdl b/testsuite/gna/issue17/cond_assign_var.vhdl new file mode 100644 index 0000000..c6e4af8 --- /dev/null +++ b/testsuite/gna/issue17/cond_assign_var.vhdl @@ -0,0 +1,31 @@ +library ieee ;
+use ieee.std_logic_1164.all ;
+use std.textio.all ;
+
+entity cond_assign_var is
+end entity cond_assign_var ;
+
+architecture doit of cond_assign_var is
+ signal Clk : std_logic := '0' ;
+ signal Y : std_logic ;
+begin
+ Clk <= not Clk after 10 ns ;
+
+ process (Clk)
+ variable A : std_logic ;
+ begin
+ A := 'H' when Clk = '1' else 'L' ;
+ Y <= A ;
+-- Y <= 'H' when Clk = '1' else 'L' ;
+ end process ;
+
+-- Y <= 'H' when Clk = '1' else 'L' ;
+
+ process
+ begin
+ wait for 500 ns ;
+ std.env.stop ;
+ end process ;
+end architecture doit ;
+
+
diff --git a/testsuite/gna/issue17/testsuite.sh b/testsuite/gna/issue17/testsuite.sh new file mode 100755 index 0000000..d5b08e9 --- /dev/null +++ b/testsuite/gna/issue17/testsuite.sh @@ -0,0 +1,17 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +analyze cond_assign_var.vhdl +elab_simulate cond_assign_var + +analyze cond_assign_sig.vhdl +elab_simulate cond_assign_sig + +analyze cond_assign_proc.vhdl +elab_simulate cond_assign_proc + +clean + +echo "Test successful" |