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author | Tristan Gingold | 2014-11-29 10:12:20 +0100 |
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committer | Tristan Gingold | 2014-11-29 10:12:20 +0100 |
commit | 3046834bd44cde0c05ff49eecbd76d3b98401119 (patch) | |
tree | a6bf8c0fa0ed1cc35afe257d8ceaa237663c2405 /src/vhdl | |
parent | c79a6fbdf9f0ca556d9f2409f99d59856db79a3d (diff) | |
download | ghdl-3046834bd44cde0c05ff49eecbd76d3b98401119.tar.gz ghdl-3046834bd44cde0c05ff49eecbd76d3b98401119.tar.bz2 ghdl-3046834bd44cde0c05ff49eecbd76d3b98401119.zip |
Allow -frelaxed-rules for v87 designs
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/sem_expr.adb | 2 | ||||
-rw-r--r-- | src/vhdl/sem_names.adb | 6 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap7.adb | 2 |
3 files changed, 6 insertions, 4 deletions
diff --git a/src/vhdl/sem_expr.adb b/src/vhdl/sem_expr.adb index f7af76c..1fa2a87 100644 --- a/src/vhdl/sem_expr.adb +++ b/src/vhdl/sem_expr.adb @@ -809,7 +809,7 @@ package body Sem_Expr is -- predefined type INTEGER is assumed if the type of both bounds -- (prior the implicit conversion) is the type universal_integer. null; - elsif Vhdl_Std = Vhdl_93c then + elsif Vhdl_Std = Vhdl_93c or else Flag_Relaxed_Rules then -- GHDL: this is not allowed, however often used: -- eg: for i in 0 to v'length + 1 loop -- eg: for i in -1 to 1 loop diff --git a/src/vhdl/sem_names.adb b/src/vhdl/sem_names.adb index 151e817..fb75627 100644 --- a/src/vhdl/sem_names.adb +++ b/src/vhdl/sem_names.adb @@ -3055,7 +3055,7 @@ package body Sem_Names is -- since the prefix (a signal) is not a static expression. Set_Expr_Staticness (Res, None); - -- LRM 6.1 + -- LRM02 6.1 / LRM08 8.1 -- A name is said to be a static name if and only if at least one of -- the following conditions holds: -- [...] @@ -3063,7 +3063,9 @@ package body Sem_Names is -- and whose suffix is one of the predefined attributes 'DELAYED, -- 'STABLE, 'QUIET or 'TRANSACTION. -- According to LRM 6.1, attributes are not static names. - if Flags.Vhdl_Std = Vhdl_93c or Flags.Vhdl_Std >= Vhdl_02 then + if Flags.Vhdl_Std = Vhdl_93c or Flag_Relaxed_Rules + or Flags.Vhdl_Std >= Vhdl_02 + then case Get_Kind (Res) is when Iir_Kind_Stable_Attribute | Iir_Kind_Quiet_Attribute diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 6c0ec50..db6eafc 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -1564,7 +1564,7 @@ package body Trans.Chap7 is end if; -- For a non-null bounds result. - if Flags.Vhdl_Std > Vhdl_87 then + if Flags.Vhdl_Std > Vhdl_87 or Flag_Relaxed_Rules then -- Vhdl 93 case: lean and simple. Chap3.Create_Range_From_Length (Index_Type, Var_Length, Get_Res_Range, Left); |