diff options
Diffstat (limited to 'library/SubcircuitLibrary')
79 files changed, 11623 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib b/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib new file mode 100644 index 00000000..58420ef7 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.cir b/library/SubcircuitLibrary/CY74FCT480T/74480.cir new file mode 100644 index 00000000..41b94a89 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.cir @@ -0,0 +1,32 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74480\74480.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/20/25 19:44:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad1_ d_xor +U5 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U10-Pad2_ d_xor +U6 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U11-Pad1_ d_xor +U7 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U11-Pad2_ d_xor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_xor +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_xor +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U14-Pad3_ d_xor +U8 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U12-Pad1_ d_xor +U9 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U12-Pad2_ d_xor +U2 Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U13-Pad1_ d_xor +U3 Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U13-Pad2_ d_xor +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_xor +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_xor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U15-Pad3_ d_xor +U20 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U1-Pad20_ d_xor +U21 Net-_U15-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad22_ d_xor +U22 Net-_U1-Pad20_ Net-_U1-Pad22_ Net-_U1-Pad21_ d_nor +U18 Net-_U16-Pad3_ Net-_U18-Pad2_ d_inverter +U16 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U16-Pad3_ d_and +U17 Net-_U1-Pad10_ Net-_U1-Pad19_ Net-_U17-Pad3_ d_and +U19 Net-_U17-Pad3_ Net-_U19-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT + +.end diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out b/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out new file mode 100644 index 00000000..59fd5704 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out @@ -0,0 +1,96 @@ +* c:\fossee\esim\library\subcircuitlibrary\74480\74480.cir + +* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad1_ d_xor +* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_xor +* u6 net-_u1-pad5_ net-_u1-pad6_ net-_u11-pad1_ d_xor +* u7 net-_u1-pad7_ net-_u1-pad8_ net-_u11-pad2_ d_xor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_xor +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_xor +* u8 net-_u1-pad11_ net-_u1-pad12_ net-_u12-pad1_ d_xor +* u9 net-_u1-pad13_ net-_u1-pad14_ net-_u12-pad2_ d_xor +* u2 net-_u1-pad15_ net-_u1-pad16_ net-_u13-pad1_ d_xor +* u3 net-_u1-pad17_ net-_u1-pad18_ net-_u13-pad2_ d_xor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_xor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_xor +* u20 net-_u14-pad3_ net-_u18-pad2_ net-_u1-pad20_ d_xor +* u21 net-_u15-pad3_ net-_u19-pad2_ net-_u1-pad22_ d_xor +* u22 net-_u1-pad20_ net-_u1-pad22_ net-_u1-pad21_ d_nor +* u18 net-_u16-pad3_ net-_u18-pad2_ d_inverter +* u16 net-_u1-pad9_ net-_u1-pad10_ net-_u16-pad3_ d_and +* u17 net-_u1-pad10_ net-_u1-pad19_ net-_u17-pad3_ d_and +* u19 net-_u17-pad3_ net-_u19-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad1_ u4 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u5 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u11-pad1_ u6 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u11-pad2_ u7 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14 +a8 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u12-pad1_ u8 +a9 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u12-pad2_ u9 +a10 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u13-pad1_ u2 +a11 [net-_u1-pad17_ net-_u1-pad18_ ] net-_u13-pad2_ u3 +a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15 +a15 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u1-pad20_ u20 +a16 [net-_u15-pad3_ net-_u19-pad2_ ] net-_u1-pad22_ u21 +a17 [net-_u1-pad20_ net-_u1-pad22_ ] net-_u1-pad21_ u22 +a18 net-_u16-pad3_ net-_u18-pad2_ u18 +a19 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u16-pad3_ u16 +a20 [net-_u1-pad10_ net-_u1-pad19_ ] net-_u17-pad3_ u17 +a21 net-_u17-pad3_ net-_u19-pad2_ u19 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u15 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.pro b/library/SubcircuitLibrary/CY74FCT480T/74480.pro new file mode 100644 index 00000000..52048d93 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.pro @@ -0,0 +1,83 @@ +update=05/06/25 21:00:50 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.sch b/library/SubcircuitLibrary/CY74FCT480T/74480.sch new file mode 100644 index 00000000..12144421 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.sch @@ -0,0 +1,698 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U4 +U 1 1 6804FCB9 +P 2950 1100 +F 0 "U4" H 2950 1100 60 0000 C CNN +F 1 "d_xor" H 3000 1200 47 0000 C CNN +F 2 "" H 2950 1100 60 0000 C CNN +F 3 "" H 2950 1100 60 0000 C CNN + 1 2950 1100 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U5 +U 1 1 6804FCEE +P 2950 1550 +F 0 "U5" H 2950 1550 60 0000 C CNN +F 1 "d_xor" H 3000 1650 47 0000 C CNN +F 2 "" H 2950 1550 60 0000 C CNN +F 3 "" H 2950 1550 60 0000 C CNN + 1 2950 1550 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 6804FD11 +P 2950 2050 +F 0 "U6" H 2950 2050 60 0000 C CNN +F 1 "d_xor" H 3000 2150 47 0000 C CNN +F 2 "" H 2950 2050 60 0000 C CNN +F 3 "" H 2950 2050 60 0000 C CNN + 1 2950 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 6804FD38 +P 2950 2550 +F 0 "U7" H 2950 2550 60 0000 C CNN +F 1 "d_xor" H 3000 2650 47 0000 C CNN +F 2 "" H 2950 2550 60 0000 C CNN +F 3 "" H 2950 2550 60 0000 C CNN + 1 2950 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U10 +U 1 1 6804FD5D +P 4250 1300 +F 0 "U10" H 4250 1300 60 0000 C CNN +F 1 "d_xor" H 4300 1400 47 0000 C CNN +F 2 "" H 4250 1300 60 0000 C CNN +F 3 "" H 4250 1300 60 0000 C CNN + 1 4250 1300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U11 +U 1 1 6804FD84 +P 4250 2300 +F 0 "U11" H 4250 2300 60 0000 C CNN +F 1 "d_xor" H 4300 2400 47 0000 C CNN +F 2 "" H 4250 2300 60 0000 C CNN +F 3 "" H 4250 2300 60 0000 C CNN + 1 4250 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U14 +U 1 1 6804FDB9 +P 5350 1750 +F 0 "U14" H 5350 1750 60 0000 C CNN +F 1 "d_xor" H 5400 1850 47 0000 C CNN +F 2 "" H 5350 1750 60 0000 C CNN +F 3 "" H 5350 1750 60 0000 C CNN + 1 5350 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U8 +U 1 1 6804FDE2 +P 2950 3650 +F 0 "U8" H 2950 3650 60 0000 C CNN +F 1 "d_xor" H 3000 3750 47 0000 C CNN +F 2 "" H 2950 3650 60 0000 C CNN +F 3 "" H 2950 3650 60 0000 C CNN + 1 2950 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U9 +U 1 1 6804FE11 +P 2950 4150 +F 0 "U9" H 2950 4150 60 0000 C CNN +F 1 "d_xor" H 3000 4250 47 0000 C CNN +F 2 "" H 2950 4150 60 0000 C CNN +F 3 "" H 2950 4150 60 0000 C CNN + 1 2950 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U2 +U 1 1 6804FE42 +P 2900 4650 +F 0 "U2" H 2900 4650 60 0000 C CNN +F 1 "d_xor" H 2950 4750 47 0000 C CNN +F 2 "" H 2900 4650 60 0000 C CNN +F 3 "" H 2900 4650 60 0000 C CNN + 1 2900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U3 +U 1 1 6804FE73 +P 2900 5100 +F 0 "U3" H 2900 5100 60 0000 C CNN +F 1 "d_xor" H 2950 5200 47 0000 C CNN +F 2 "" H 2900 5100 60 0000 C CNN +F 3 "" H 2900 5100 60 0000 C CNN + 1 2900 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U12 +U 1 1 6804FEA4 +P 4300 3850 +F 0 "U12" H 4300 3850 60 0000 C CNN +F 1 "d_xor" H 4350 3950 47 0000 C CNN +F 2 "" H 4300 3850 60 0000 C CNN +F 3 "" H 4300 3850 60 0000 C CNN + 1 4300 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U13 +U 1 1 6804FED3 +P 4350 4850 +F 0 "U13" H 4350 4850 60 0000 C CNN +F 1 "d_xor" H 4400 4950 47 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U15 +U 1 1 6804FF0C +P 5600 4350 +F 0 "U15" H 5600 4350 60 0000 C CNN +F 1 "d_xor" H 5650 4450 47 0000 C CNN +F 2 "" H 5600 4350 60 0000 C CNN +F 3 "" H 5600 4350 60 0000 C CNN + 1 5600 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U20 +U 1 1 6804FF43 +P 7800 1700 +F 0 "U20" H 7800 1700 60 0000 C CNN +F 1 "d_xor" H 7850 1800 47 0000 C CNN +F 2 "" H 7800 1700 60 0000 C CNN +F 3 "" H 7800 1700 60 0000 C CNN + 1 7800 1700 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U21 +U 1 1 6804FF8C +P 7850 4400 +F 0 "U21" H 7850 4400 60 0000 C CNN +F 1 "d_xor" H 7900 4500 47 0000 C CNN +F 2 "" H 7850 4400 60 0000 C CNN +F 3 "" H 7850 4400 60 0000 C CNN + 1 7850 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U22 +U 1 1 6804FFCD +P 9550 3050 +F 0 "U22" H 9550 3050 60 0000 C CNN +F 1 "d_nor" H 9600 3150 60 0000 C CNN +F 2 "" H 9550 3050 60 0000 C CNN +F 3 "" H 9550 3050 60 0000 C CNN + 1 9550 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 68050016 +P 7200 2300 +F 0 "U18" H 7200 2200 60 0000 C CNN +F 1 "d_inverter" H 7200 2450 60 0000 C CNN +F 2 "" H 7250 2250 60 0000 C CNN +F 3 "" H 7250 2250 60 0000 C CNN + 1 7200 2300 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U16 +U 1 1 6805005D +P 6700 2950 +F 0 "U16" H 6700 2950 60 0000 C CNN +F 1 "d_and" H 6750 3050 60 0000 C CNN +F 2 "" H 6700 2950 60 0000 C CNN +F 3 "" H 6700 2950 60 0000 C CNN + 1 6700 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 680500A4 +P 6800 5450 +F 0 "U17" H 6800 5450 60 0000 C CNN +F 1 "d_and" H 6850 5550 60 0000 C CNN +F 2 "" H 6800 5450 60 0000 C CNN +F 3 "" H 6800 5450 60 0000 C CNN + 1 6800 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 680500E7 +P 7350 4900 +F 0 "U19" H 7350 4800 60 0000 C CNN +F 1 "d_inverter" H 7350 5050 60 0000 C CNN +F 2 "" H 7400 4850 60 0000 C CNN +F 3 "" H 7400 4850 60 0000 C CNN + 1 7350 4900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 6805012C +P 1550 900 +F 0 "U1" H 1600 1000 30 0000 C CNN +F 1 "PORT" H 1550 900 30 0000 C CNN +F 2 "" H 1550 900 60 0000 C CNN +F 3 "" H 1550 900 60 0000 C CNN + 1 1550 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6805029B +P 1550 1100 +F 0 "U1" H 1600 1200 30 0000 C CNN +F 1 "PORT" H 1550 1100 30 0000 C CNN +F 2 "" H 1550 1100 60 0000 C CNN +F 3 "" H 1550 1100 60 0000 C CNN + 2 1550 1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 680502E2 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 3 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6805032D +P 1550 1550 +F 0 "U1" H 1600 1650 30 0000 C CNN +F 1 "PORT" H 1550 1550 30 0000 C CNN +F 2 "" H 1550 1550 60 0000 C CNN +F 3 "" H 1550 1550 60 0000 C CNN + 4 1550 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 680503C1 +P 1550 1800 +F 0 "U1" H 1600 1900 30 0000 C CNN +F 1 "PORT" H 1550 1800 30 0000 C CNN +F 2 "" H 1550 1800 60 0000 C CNN +F 3 "" H 1550 1800 60 0000 C CNN + 5 1550 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68050412 +P 1550 2000 +F 0 "U1" H 1600 2100 30 0000 C CNN +F 1 "PORT" H 1550 2000 30 0000 C CNN +F 2 "" H 1550 2000 60 0000 C CNN +F 3 "" H 1550 2000 60 0000 C CNN + 6 1550 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68050465 +P 1550 2300 +F 0 "U1" H 1600 2400 30 0000 C CNN +F 1 "PORT" H 1550 2300 30 0000 C CNN +F 2 "" H 1550 2300 60 0000 C CNN +F 3 "" H 1550 2300 60 0000 C CNN + 7 1550 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 680504B8 +P 1550 2500 +F 0 "U1" H 1600 2600 30 0000 C CNN +F 1 "PORT" H 1550 2500 30 0000 C CNN +F 2 "" H 1550 2500 60 0000 C CNN +F 3 "" H 1550 2500 60 0000 C CNN + 8 1550 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68050543 +P 1550 2750 +F 0 "U1" H 1600 2850 30 0000 C CNN +F 1 "PORT" H 1550 2750 30 0000 C CNN +F 2 "" H 1550 2750 60 0000 C CNN +F 3 "" H 1550 2750 60 0000 C CNN + 9 1550 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6805059A +P 1550 3050 +F 0 "U1" H 1600 3150 30 0000 C CNN +F 1 "PORT" H 1550 3050 30 0000 C CNN +F 2 "" H 1550 3050 60 0000 C CNN +F 3 "" H 1550 3050 60 0000 C CNN + 10 1550 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 680505EF +P 1550 3450 +F 0 "U1" H 1600 3550 30 0000 C CNN +F 1 "PORT" H 1550 3450 30 0000 C CNN +F 2 "" H 1550 3450 60 0000 C CNN +F 3 "" H 1550 3450 60 0000 C CNN + 11 1550 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6805064C +P 1550 3700 +F 0 "U1" H 1600 3800 30 0000 C CNN +F 1 "PORT" H 1550 3700 30 0000 C CNN +F 2 "" H 1550 3700 60 0000 C CNN +F 3 "" H 1550 3700 60 0000 C CNN + 12 1550 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 680506A9 +P 1550 4000 +F 0 "U1" H 1600 4100 30 0000 C CNN +F 1 "PORT" H 1550 4000 30 0000 C CNN +F 2 "" H 1550 4000 60 0000 C CNN +F 3 "" H 1550 4000 60 0000 C CNN + 13 1550 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68050702 +P 1550 4200 +F 0 "U1" H 1600 4300 30 0000 C CNN +F 1 "PORT" H 1550 4200 30 0000 C CNN +F 2 "" H 1550 4200 60 0000 C CNN +F 3 "" H 1550 4200 60 0000 C CNN + 14 1550 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6805075F +P 1550 4450 +F 0 "U1" H 1600 4550 30 0000 C CNN +F 1 "PORT" H 1550 4450 30 0000 C CNN +F 2 "" H 1550 4450 60 0000 C CNN +F 3 "" H 1550 4450 60 0000 C CNN + 15 1550 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 680507CC +P 1550 4650 +F 0 "U1" H 1600 4750 30 0000 C CNN +F 1 "PORT" H 1550 4650 30 0000 C CNN +F 2 "" H 1550 4650 60 0000 C CNN +F 3 "" H 1550 4650 60 0000 C CNN + 16 1550 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 68050831 +P 1550 4900 +F 0 "U1" H 1600 5000 30 0000 C CNN +F 1 "PORT" H 1550 4900 30 0000 C CNN +F 2 "" H 1550 4900 60 0000 C CNN +F 3 "" H 1550 4900 60 0000 C CNN + 17 1550 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 68050896 +P 1550 5100 +F 0 "U1" H 1600 5200 30 0000 C CNN +F 1 "PORT" H 1550 5100 30 0000 C CNN +F 2 "" H 1550 5100 60 0000 C CNN +F 3 "" H 1550 5100 60 0000 C CNN + 18 1550 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 680509C6 +P 1550 5350 +F 0 "U1" H 1600 5450 30 0000 C CNN +F 1 "PORT" H 1550 5350 30 0000 C CNN +F 2 "" H 1550 5350 60 0000 C CNN +F 3 "" H 1550 5350 60 0000 C CNN + 19 1550 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 68050B25 +P 10750 3000 +F 0 "U1" H 10800 3100 30 0000 C CNN +F 1 "PORT" H 10750 3000 30 0000 C CNN +F 2 "" H 10750 3000 60 0000 C CNN +F 3 "" H 10750 3000 60 0000 C CNN + 21 10750 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 20 1 68050B96 +P 10700 1300 +F 0 "U1" H 10750 1400 30 0000 C CNN +F 1 "PORT" H 10700 1300 30 0000 C CNN +F 2 "" H 10700 1300 60 0000 C CNN +F 3 "" H 10700 1300 60 0000 C CNN + 20 10700 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 22 1 68050C07 +P 10700 4300 +F 0 "U1" H 10750 4400 30 0000 C CNN +F 1 "PORT" H 10700 4300 30 0000 C CNN +F 2 "" H 10700 4300 60 0000 C CNN +F 3 "" H 10700 4300 60 0000 C CNN + 22 10700 4300 + -1 0 0 1 +$EndComp +Wire Wire Line + 1800 900 2500 900 +Wire Wire Line + 2500 900 2500 1000 +Wire Wire Line + 1800 1100 2500 1100 +Wire Wire Line + 1800 1350 2500 1350 +Wire Wire Line + 2500 1350 2500 1450 +Wire Wire Line + 1800 1550 2500 1550 +Wire Wire Line + 3400 1050 3800 1050 +Wire Wire Line + 3800 1050 3800 1200 +Wire Wire Line + 3400 1500 3800 1500 +Wire Wire Line + 3800 1500 3800 1300 +Wire Wire Line + 1800 1800 2500 1800 +Wire Wire Line + 2500 1800 2500 1950 +Wire Wire Line + 1800 2000 1800 2050 +Wire Wire Line + 1800 2050 2500 2050 +Wire Wire Line + 3400 2000 3800 2000 +Wire Wire Line + 3800 2000 3800 2200 +Wire Wire Line + 1800 2300 2500 2300 +Wire Wire Line + 2500 2300 2500 2450 +Wire Wire Line + 1800 2500 2500 2500 +Wire Wire Line + 2500 2500 2500 2550 +Wire Wire Line + 3400 2500 3800 2500 +Wire Wire Line + 3800 2500 3800 2300 +Wire Wire Line + 1800 2750 6250 2750 +Wire Wire Line + 6250 2750 6250 2850 +Wire Wire Line + 4700 1250 4900 1250 +Wire Wire Line + 4900 1250 4900 1650 +Wire Wire Line + 4700 2250 4900 2250 +Wire Wire Line + 4900 2250 4900 1750 +Wire Wire Line + 7150 2900 7200 2900 +Wire Wire Line + 7200 2900 7200 2600 +Wire Wire Line + 5800 1700 6650 1700 +Wire Wire Line + 6650 1700 6650 1600 +Wire Wire Line + 6650 1600 7350 1600 +Wire Wire Line + 7200 2000 7200 1700 +Wire Wire Line + 7200 1700 7350 1700 +Wire Wire Line + 1800 3050 6150 3050 +Wire Wire Line + 6350 5350 6150 5350 +Wire Wire Line + 6150 5350 6150 2950 +Wire Wire Line + 6150 2950 6250 2950 +Connection ~ 6150 3050 +Wire Wire Line + 6050 4300 7400 4300 +Wire Wire Line + 7400 4400 7350 4400 +Wire Wire Line + 7350 4400 7350 4600 +Wire Wire Line + 7250 5400 7350 5400 +Wire Wire Line + 7350 5400 7350 5200 +Wire Wire Line + 1800 5350 5700 5350 +Wire Wire Line + 5700 5350 5700 5450 +Wire Wire Line + 5700 5450 6350 5450 +Wire Wire Line + 1800 3450 2500 3450 +Wire Wire Line + 2500 3450 2500 3550 +Wire Wire Line + 1800 3700 2500 3700 +Wire Wire Line + 2500 3700 2500 3650 +Wire Wire Line + 1800 4000 2500 4000 +Wire Wire Line + 2500 4000 2500 4050 +Wire Wire Line + 1800 4200 2500 4200 +Wire Wire Line + 2500 4200 2500 4150 +Wire Wire Line + 1800 4450 2400 4450 +Wire Wire Line + 2400 4450 2400 4550 +Wire Wire Line + 2400 4550 2450 4550 +Wire Wire Line + 1800 4650 2450 4650 +Wire Wire Line + 1800 4900 2450 4900 +Wire Wire Line + 2450 4900 2450 5000 +Wire Wire Line + 1800 5100 2450 5100 +Wire Wire Line + 3400 3600 3850 3600 +Wire Wire Line + 3850 3600 3850 3750 +Wire Wire Line + 3400 4100 3850 4100 +Wire Wire Line + 3850 4100 3850 3850 +Wire Wire Line + 3350 4600 3900 4600 +Wire Wire Line + 3900 4600 3900 4750 +Wire Wire Line + 3350 5050 3900 5050 +Wire Wire Line + 3900 5050 3900 4850 +Wire Wire Line + 4750 3800 5150 3800 +Wire Wire Line + 5150 3800 5150 4250 +Wire Wire Line + 4800 4800 5150 4800 +Wire Wire Line + 5150 4800 5150 4350 +Wire Wire Line + 8250 1650 10450 1650 +Wire Wire Line + 10450 1650 10450 1300 +Wire Wire Line + 8500 1650 8500 2950 +Wire Wire Line + 8500 2950 9100 2950 +Connection ~ 8500 1650 +Wire Wire Line + 8300 4350 10450 4350 +Wire Wire Line + 10450 4350 10450 4300 +Wire Wire Line + 9100 3050 8700 3050 +Wire Wire Line + 8700 3050 8700 4350 +Connection ~ 8700 4350 +Wire Wire Line + 10000 3000 10500 3000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.sub b/library/SubcircuitLibrary/CY74FCT480T/74480.sub new file mode 100644 index 00000000..d91baa60 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480.sub @@ -0,0 +1,90 @@ +* Subcircuit 74480 +.subckt 74480 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ +* c:\fossee\esim\library\subcircuitlibrary\74480\74480.cir +* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad1_ d_xor +* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_xor +* u6 net-_u1-pad5_ net-_u1-pad6_ net-_u11-pad1_ d_xor +* u7 net-_u1-pad7_ net-_u1-pad8_ net-_u11-pad2_ d_xor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_xor +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_xor +* u8 net-_u1-pad11_ net-_u1-pad12_ net-_u12-pad1_ d_xor +* u9 net-_u1-pad13_ net-_u1-pad14_ net-_u12-pad2_ d_xor +* u2 net-_u1-pad15_ net-_u1-pad16_ net-_u13-pad1_ d_xor +* u3 net-_u1-pad17_ net-_u1-pad18_ net-_u13-pad2_ d_xor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_xor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_xor +* u20 net-_u14-pad3_ net-_u18-pad2_ net-_u1-pad20_ d_xor +* u21 net-_u15-pad3_ net-_u19-pad2_ net-_u1-pad22_ d_xor +* u22 net-_u1-pad20_ net-_u1-pad22_ net-_u1-pad21_ d_nor +* u18 net-_u16-pad3_ net-_u18-pad2_ d_inverter +* u16 net-_u1-pad9_ net-_u1-pad10_ net-_u16-pad3_ d_and +* u17 net-_u1-pad10_ net-_u1-pad19_ net-_u17-pad3_ d_and +* u19 net-_u17-pad3_ net-_u19-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad1_ u4 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u5 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u11-pad1_ u6 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u11-pad2_ u7 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14 +a8 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u12-pad1_ u8 +a9 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u12-pad2_ u9 +a10 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u13-pad1_ u2 +a11 [net-_u1-pad17_ net-_u1-pad18_ ] net-_u13-pad2_ u3 +a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15 +a15 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u1-pad20_ u20 +a16 [net-_u15-pad3_ net-_u19-pad2_ ] net-_u1-pad22_ u21 +a17 [net-_u1-pad20_ net-_u1-pad22_ ] net-_u1-pad21_ u22 +a18 net-_u16-pad3_ net-_u18-pad2_ u18 +a19 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u16-pad3_ u16 +a20 [net-_u1-pad10_ net-_u1-pad19_ ] net-_u17-pad3_ u17 +a21 net-_u17-pad3_ net-_u19-pad2_ u19 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u15 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74480
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml b/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml new file mode 100644 index 00000000..cca77fc4 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_xor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_xor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_xor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u11><u14 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_xor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_xor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u2 name="type">d_xor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xor<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_xor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_xor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_xor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u20 name="type">d_xor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u22><u18 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u19></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CY74FCT480T/analysis b/library/SubcircuitLibrary/CY74FCT480T/analysis new file mode 100644 index 00000000..5c9b0b46 --- /dev/null +++ b/library/SubcircuitLibrary/CY74FCT480T/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DM7447A/7447-cache.lib b/library/SubcircuitLibrary/DM7447A/7447-cache.lib new file mode 100644 index 00000000..a8a60642 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447-cache.lib @@ -0,0 +1,162 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DM7447A/7447.cir b/library/SubcircuitLibrary/DM7447A/7447.cir new file mode 100644 index 00000000..2def1963 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447.cir @@ -0,0 +1,63 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\7447\7447.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/03/25 19:04:33 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad6_ Net-_U10-Pad1_ d_nand +U4 Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U11-Pad1_ d_nand +U5 Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U12-Pad1_ d_nand +U2 Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad7_ Net-_U6-Pad2_ d_inverter +X1 Net-_U1-Pad6_ Net-_U6-Pad2_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U33-Pad1_ 4_and +U9 Net-_U13-Pad1_ Net-_U10-Pad1_ Net-_U33-Pad2_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U10-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U1-Pad5_ Net-_U11-Pad3_ d_nand +U12 Net-_U12-Pad1_ Net-_U1-Pad5_ Net-_U12-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U1-Pad5_ Net-_U13-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U14 Net-_U11-Pad3_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_and +U15 Net-_U10-Pad1_ Net-_U12-Pad3_ Net-_U15-Pad3_ d_and +X10 Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ ? 4_and +U16 Net-_U11-Pad3_ Net-_U13-Pad3_ Net-_U16-Pad3_ d_and +X2 Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U23-Pad2_ 3_and +X3 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U36-Pad2_ 3_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_and +X4 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U12-Pad1_ Net-_U27-Pad2_ 3_and +X5 Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U24-Pad1_ 3_and +X6 Net-_U10-Pad1_ Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U24-Pad2_ 3_and +X7 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U37-Pad2_ 3_and +U21 Net-_U10-Pad3_ Net-_U21-Pad2_ d_buffer +U18 Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_and +U19 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U19-Pad3_ d_and +U20 Net-_U11-Pad3_ Net-_U12-Pad1_ Net-_U20-Pad3_ d_and +X8 Net-_U10-Pad3_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U38-Pad2_ 3_and +X9 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U28-Pad1_ 3_and +X11 Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U1-Pad6_ Net-_U28-Pad2_ 4_and +U27 Net-_U17-Pad3_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nor +U26 Net-_U21-Pad2_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_nor +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nor +U22 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U22-Pad3_ d_nor +U29 Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U29-Pad3_ d_nor +U35 Net-_U29-Pad3_ ? Net-_U35-Pad3_ d_nor +U23 Net-_U16-Pad3_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nor +U30 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U30-Pad3_ d_nor +U36 Net-_U30-Pad3_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_nor +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor +U31 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U31-Pad3_ d_nor +U37 Net-_U31-Pad3_ Net-_U37-Pad2_ Net-_U37-Pad3_ d_nor +U25 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad3_ d_nor +U32 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_nor +U38 Net-_U32-Pad3_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_nor +U33 Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U1-Pad5_ d_nand +U39 Net-_U35-Pad3_ Net-_U1-Pad8_ d_inverter +U40 Net-_U36-Pad3_ Net-_U1-Pad9_ d_inverter +U34 Net-_U27-Pad3_ Net-_U1-Pad10_ d_inverter +U41 Net-_U37-Pad3_ Net-_U1-Pad11_ d_inverter +U8 Net-_U26-Pad3_ Net-_U1-Pad12_ d_inverter +U42 Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter +U7 Net-_U28-Pad3_ Net-_U1-Pad14_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/DM7447A/7447.cir.out b/library/SubcircuitLibrary/DM7447A/7447.cir.out new file mode 100644 index 00000000..2090985a --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447.cir.out @@ -0,0 +1,189 @@ +* c:\fossee\esim\library\subcircuitlibrary\7447\7447.cir + +.include 4_and.sub +.include 3_and.sub +* u3 net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand +* u4 net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand +* u5 net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand +* u2 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter +x1 net-_u1-pad6_ net-_u6-pad2_ net-_u11-pad1_ net-_u12-pad1_ net-_u33-pad1_ 4_and +* u9 net-_u13-pad1_ net-_u10-pad1_ net-_u33-pad2_ d_and +* u10 net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u14 net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and +* u15 net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and +x10 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ ? 4_and +* u16 net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and +x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad2_ 3_and +x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad2_ 3_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and +x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u27-pad2_ 3_and +x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u24-pad1_ 3_and +x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u24-pad2_ 3_and +x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u37-pad2_ 3_and +* u21 net-_u10-pad3_ net-_u21-pad2_ d_buffer +* u18 net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and +* u19 net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and +* u20 net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and +x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad2_ 3_and +x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u28-pad1_ 3_and +x11 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad2_ 4_and +* u27 net-_u17-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u26 net-_u21-pad2_ net-_u18-pad3_ net-_u26-pad3_ d_nor +* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor +* u22 net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor +* u29 net-_u22-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u35 net-_u29-pad3_ ? net-_u35-pad3_ d_nor +* u23 net-_u16-pad3_ net-_u23-pad2_ net-_u23-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_nor +* u36 net-_u30-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_nor +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor +* u31 net-_u24-pad3_ net-_u24-pad3_ net-_u31-pad3_ d_nor +* u37 net-_u31-pad3_ net-_u37-pad2_ net-_u37-pad3_ d_nor +* u25 net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor +* u32 net-_u25-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_nor +* u38 net-_u32-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nor +* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u1-pad5_ d_nand +* u39 net-_u35-pad3_ net-_u1-pad8_ d_inverter +* u40 net-_u36-pad3_ net-_u1-pad9_ d_inverter +* u34 net-_u27-pad3_ net-_u1-pad10_ d_inverter +* u41 net-_u37-pad3_ net-_u1-pad11_ d_inverter +* u8 net-_u26-pad3_ net-_u1-pad12_ d_inverter +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u7 net-_u28-pad3_ net-_u1-pad14_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u3 +a2 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u4 +a3 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u5 +a4 net-_u1-pad4_ net-_u13-pad1_ u2 +a5 net-_u1-pad7_ net-_u6-pad2_ u6 +a6 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u33-pad2_ u9 +a7 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10 +a8 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11 +a9 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12 +a10 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13 +a11 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a12 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15 +a13 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 net-_u10-pad3_ net-_u21-pad2_ u21 +a16 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a17 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19 +a18 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20 +a19 [net-_u17-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a20 [net-_u21-pad2_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a22 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 +a23 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u29-pad3_ ? ] net-_u35-pad3_ u35 +a25 [net-_u16-pad3_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30 +a27 [net-_u30-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36 +a28 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a29 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a31 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25 +a32 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a34 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u1-pad5_ u33 +a35 net-_u35-pad3_ net-_u1-pad8_ u39 +a36 net-_u36-pad3_ net-_u1-pad9_ u40 +a37 net-_u27-pad3_ net-_u1-pad10_ u34 +a38 net-_u37-pad3_ net-_u1-pad11_ u41 +a39 net-_u26-pad3_ net-_u1-pad12_ u8 +a40 net-_u38-pad3_ net-_u1-pad13_ u42 +a41 net-_u28-pad3_ net-_u1-pad14_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DM7447A/7447.pro b/library/SubcircuitLibrary/DM7447A/7447.pro new file mode 100644 index 00000000..51d5ef29 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447.pro @@ -0,0 +1,83 @@ +update=05/06/25 21:02:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/DM7447A/7447.sch b/library/SubcircuitLibrary/DM7447A/7447.sch new file mode 100644 index 00000000..010bba39 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447.sch @@ -0,0 +1,1224 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:7447-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 680723FC +P 1550 1450 +F 0 "U3" H 1550 1450 60 0000 C CNN +F 1 "d_nand" H 1600 1550 60 0000 C CNN +F 2 "" H 1550 1450 60 0000 C CNN +F 3 "" H 1550 1450 60 0000 C CNN + 1 1550 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6807242F +P 1550 2450 +F 0 "U4" H 1550 2450 60 0000 C CNN +F 1 "d_nand" H 1600 2550 60 0000 C CNN +F 2 "" H 1550 2450 60 0000 C CNN +F 3 "" H 1550 2450 60 0000 C CNN + 1 1550 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68072448 +P 1650 3350 +F 0 "U5" H 1650 3350 60 0000 C CNN +F 1 "d_nand" H 1700 3450 60 0000 C CNN +F 2 "" H 1650 3350 60 0000 C CNN +F 3 "" H 1650 3350 60 0000 C CNN + 1 1650 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68072469 +P 1500 4200 +F 0 "U2" H 1500 4100 60 0000 C CNN +F 1 "d_inverter" H 1500 4350 60 0000 C CNN +F 2 "" H 1550 4150 60 0000 C CNN +F 3 "" H 1550 4150 60 0000 C CNN + 1 1500 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6807248E +P 1850 7600 +F 0 "U6" H 1850 7500 60 0000 C CNN +F 1 "d_inverter" H 1850 7750 60 0000 C CNN +F 2 "" H 1900 7550 60 0000 C CNN +F 3 "" H 1900 7550 60 0000 C CNN + 1 1850 7600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X1 +U 1 1 68072548 +P 2200 6900 +F 0 "X1" H 2250 6850 60 0000 C CNN +F 1 "4_and" H 2300 7000 60 0000 C CNN +F 2 "" H 2200 6900 60 0000 C CNN +F 3 "" H 2200 6900 60 0000 C CNN + 1 2200 6900 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 680725A5 +P 2650 6850 +F 0 "U9" H 2650 6850 60 0000 C CNN +F 1 "d_and" H 2700 6950 60 0000 C CNN +F 2 "" H 2650 6850 60 0000 C CNN +F 3 "" H 2650 6850 60 0000 C CNN + 1 2650 6850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U10 +U 1 1 68072846 +P 3100 1900 +F 0 "U10" H 3100 1900 60 0000 C CNN +F 1 "d_nand" H 3150 2000 60 0000 C CNN +F 2 "" H 3100 1900 60 0000 C CNN +F 3 "" H 3100 1900 60 0000 C CNN + 1 3100 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U11 +U 1 1 6807288D +P 3100 2950 +F 0 "U11" H 3100 2950 60 0000 C CNN +F 1 "d_nand" H 3150 3050 60 0000 C CNN +F 2 "" H 3100 2950 60 0000 C CNN +F 3 "" H 3100 2950 60 0000 C CNN + 1 3100 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 680728CC +P 3100 3900 +F 0 "U12" H 3100 3900 60 0000 C CNN +F 1 "d_nand" H 3150 4000 60 0000 C CNN +F 2 "" H 3100 3900 60 0000 C CNN +F 3 "" H 3100 3900 60 0000 C CNN + 1 3100 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 680729B3 +P 3100 4400 +F 0 "U13" H 3100 4400 60 0000 C CNN +F 1 "d_nand" H 3150 4500 60 0000 C CNN +F 2 "" H 3100 4400 60 0000 C CNN +F 3 "" H 3100 4400 60 0000 C CNN + 1 3100 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68072AB2 +P 700 1300 +F 0 "U1" H 750 1400 30 0000 C CNN +F 1 "PORT" H 700 1300 30 0000 C CNN +F 2 "" H 700 1300 60 0000 C CNN +F 3 "" H 700 1300 60 0000 C CNN + 1 700 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68072AEF +P 700 2300 +F 0 "U1" H 750 2400 30 0000 C CNN +F 1 "PORT" H 700 2300 30 0000 C CNN +F 2 "" H 700 2300 60 0000 C CNN +F 3 "" H 700 2300 60 0000 C CNN + 2 700 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68072B26 +P 700 3200 +F 0 "U1" H 750 3300 30 0000 C CNN +F 1 "PORT" H 700 3200 30 0000 C CNN +F 2 "" H 700 3200 60 0000 C CNN +F 3 "" H 700 3200 60 0000 C CNN + 3 700 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68072B65 +P 750 4200 +F 0 "U1" H 800 4300 30 0000 C CNN +F 1 "PORT" H 750 4200 30 0000 C CNN +F 2 "" H 750 4200 60 0000 C CNN +F 3 "" H 750 4200 60 0000 C CNN + 4 750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68072B9E +P 750 4750 +F 0 "U1" H 800 4850 30 0000 C CNN +F 1 "PORT" H 750 4750 30 0000 C CNN +F 2 "" H 750 4750 60 0000 C CNN +F 3 "" H 750 4750 60 0000 C CNN + 5 750 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68072C7D +P 750 7000 +F 0 "U1" H 800 7100 30 0000 C CNN +F 1 "PORT" H 750 7000 30 0000 C CNN +F 2 "" H 750 7000 60 0000 C CNN +F 3 "" H 750 7000 60 0000 C CNN + 6 750 7000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68072D0E +P 750 7550 +F 0 "U1" H 800 7650 30 0000 C CNN +F 1 "PORT" H 750 7550 30 0000 C CNN +F 2 "" H 750 7550 60 0000 C CNN +F 3 "" H 750 7550 60 0000 C CNN + 7 750 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 68072ECF +P 6000 850 +F 0 "U14" H 6000 850 60 0000 C CNN +F 1 "d_and" H 6050 950 60 0000 C CNN +F 2 "" H 6000 850 60 0000 C CNN +F 3 "" H 6000 850 60 0000 C CNN + 1 6000 850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 68072F20 +P 6000 1200 +F 0 "U15" H 6000 1200 60 0000 C CNN +F 1 "d_and" H 6050 1300 60 0000 C CNN +F 2 "" H 6000 1200 60 0000 C CNN +F 3 "" H 6000 1200 60 0000 C CNN + 1 6000 1200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 68072F61 +P 5950 1550 +F 0 "X10" H 6000 1500 60 0000 C CNN +F 1 "4_and" H 6050 1650 60 0000 C CNN +F 2 "" H 5950 1550 60 0000 C CNN +F 3 "" H 5950 1550 60 0000 C CNN + 1 5950 1550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 68072FE7 +P 6000 2000 +F 0 "U16" H 6000 2000 60 0000 C CNN +F 1 "d_and" H 6050 2100 60 0000 C CNN +F 2 "" H 6000 2000 60 0000 C CNN +F 3 "" H 6000 2000 60 0000 C CNN + 1 6000 2000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68073046 +P 5900 2350 +F 0 "X2" H 6000 2300 60 0000 C CNN +F 1 "3_and" H 6050 2500 60 0000 C CNN +F 2 "" H 5900 2350 60 0000 C CNN +F 3 "" H 5900 2350 60 0000 C CNN + 1 5900 2350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 68073109 +P 5900 2700 +F 0 "X3" H 6000 2650 60 0000 C CNN +F 1 "3_and" H 6050 2850 60 0000 C CNN +F 2 "" H 5900 2700 60 0000 C CNN +F 3 "" H 5900 2700 60 0000 C CNN + 1 5900 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 68073276 +P 6000 3050 +F 0 "U17" H 6000 3050 60 0000 C CNN +F 1 "d_and" H 6050 3150 60 0000 C CNN +F 2 "" H 6000 3050 60 0000 C CNN +F 3 "" H 6000 3050 60 0000 C CNN + 1 6000 3050 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 680732D1 +P 5900 3350 +F 0 "X4" H 6000 3300 60 0000 C CNN +F 1 "3_and" H 6050 3500 60 0000 C CNN +F 2 "" H 5900 3350 60 0000 C CNN +F 3 "" H 5900 3350 60 0000 C CNN + 1 5900 3350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 68073324 +P 5900 3700 +F 0 "X5" H 6000 3650 60 0000 C CNN +F 1 "3_and" H 6050 3850 60 0000 C CNN +F 2 "" H 5900 3700 60 0000 C CNN +F 3 "" H 5900 3700 60 0000 C CNN + 1 5900 3700 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6807337B +P 5900 4050 +F 0 "X6" H 6000 4000 60 0000 C CNN +F 1 "3_and" H 6050 4200 60 0000 C CNN +F 2 "" H 5900 4050 60 0000 C CNN +F 3 "" H 5900 4050 60 0000 C CNN + 1 5900 4050 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 680733D8 +P 5900 4400 +F 0 "X7" H 6000 4350 60 0000 C CNN +F 1 "3_and" H 6050 4550 60 0000 C CNN +F 2 "" H 5900 4400 60 0000 C CNN +F 3 "" H 5900 4400 60 0000 C CNN + 1 5900 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U21 +U 1 1 68073437 +P 6050 4800 +F 0 "U21" H 6050 4750 60 0000 C CNN +F 1 "d_buffer" H 6050 4850 60 0000 C CNN +F 2 "" H 6050 4800 60 0000 C CNN +F 3 "" H 6050 4800 60 0000 C CNN + 1 6050 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 68073568 +P 6000 5250 +F 0 "U18" H 6000 5250 60 0000 C CNN +F 1 "d_and" H 6050 5350 60 0000 C CNN +F 2 "" H 6000 5250 60 0000 C CNN +F 3 "" H 6000 5250 60 0000 C CNN + 1 6000 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 680735CF +P 6000 5500 +F 0 "U19" H 6000 5500 60 0000 C CNN +F 1 "d_and" H 6050 5600 60 0000 C CNN +F 2 "" H 6000 5500 60 0000 C CNN +F 3 "" H 6000 5500 60 0000 C CNN + 1 6000 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 68073632 +P 6000 5750 +F 0 "U20" H 6000 5750 60 0000 C CNN +F 1 "d_and" H 6050 5850 60 0000 C CNN +F 2 "" H 6000 5750 60 0000 C CNN +F 3 "" H 6000 5750 60 0000 C CNN + 1 6000 5750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 6807370E +P 5900 6100 +F 0 "X8" H 6000 6050 60 0000 C CNN +F 1 "3_and" H 6050 6250 60 0000 C CNN +F 2 "" H 5900 6100 60 0000 C CNN +F 3 "" H 5900 6100 60 0000 C CNN + 1 5900 6100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X9 +U 1 1 68073773 +P 5900 6450 +F 0 "X9" H 6000 6400 60 0000 C CNN +F 1 "3_and" H 6050 6600 60 0000 C CNN +F 2 "" H 5900 6450 60 0000 C CNN +F 3 "" H 5900 6450 60 0000 C CNN + 1 5900 6450 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X11 +U 1 1 680737DA +P 5950 6850 +F 0 "X11" H 6000 6800 60 0000 C CNN +F 1 "4_and" H 6050 6950 60 0000 C CNN +F 2 "" H 5950 6850 60 0000 C CNN +F 3 "" H 5950 6850 60 0000 C CNN + 1 5950 6850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 1300 1100 1300 +Wire Wire Line + 1100 1300 1100 1350 +Wire Wire Line + 950 2300 1100 2300 +Wire Wire Line + 1100 2300 1100 2350 +Wire Wire Line + 1100 1450 1100 7800 +Wire Wire Line + 1100 7800 5550 7800 +Wire Wire Line + 5550 7800 5550 7000 +Wire Wire Line + 950 3200 1200 3200 +Wire Wire Line + 1200 3200 1200 3250 +Wire Wire Line + 1000 4200 1200 4200 +Connection ~ 1100 2450 +Connection ~ 1100 3350 +Wire Wire Line + 1200 3350 1100 3350 +Wire Wire Line + 2000 1400 3700 1400 +Wire Wire Line + 2650 1400 2650 1800 +Wire Wire Line + 2650 1900 2400 1900 +Wire Wire Line + 2000 2400 5350 2400 +Wire Wire Line + 2650 2400 2650 2850 +Wire Wire Line + 2650 2950 2400 2950 +Connection ~ 2400 2950 +Wire Wire Line + 2100 3300 3150 3300 +Wire Wire Line + 2600 3300 2600 3800 +Wire Wire Line + 2600 3800 2650 3800 +Wire Wire Line + 2650 3900 2400 3900 +Connection ~ 2400 3900 +Wire Wire Line + 1800 4200 5050 4200 +Wire Wire Line + 2650 4200 2650 4300 +Wire Wire Line + 2400 4400 2650 4400 +Connection ~ 2400 4400 +Wire Wire Line + 2350 6250 2200 6250 +Wire Wire Line + 2200 6250 2200 6400 +Wire Wire Line + 2450 6250 2600 6250 +Wire Wire Line + 2600 6250 2600 6400 +Wire Wire Line + 1000 4750 1850 4750 +Wire Wire Line + 1000 7550 1550 7550 +Wire Wire Line + 1550 7550 1550 7600 +Wire Wire Line + 2150 7600 2150 7300 +$Comp +L d_nor U27 +U 1 1 68075D1B +P 7850 3200 +F 0 "U27" H 7850 3200 60 0000 C CNN +F 1 "d_nor" H 7900 3300 60 0000 C CNN +F 2 "" H 7850 3200 60 0000 C CNN +F 3 "" H 7850 3200 60 0000 C CNN + 1 7850 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U26 +U 1 1 68075ED6 +P 7800 5100 +F 0 "U26" H 7800 5100 60 0000 C CNN +F 1 "d_nor" H 7850 5200 60 0000 C CNN +F 2 "" H 7800 5100 60 0000 C CNN +F 3 "" H 7800 5100 60 0000 C CNN + 1 7800 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U28 +U 1 1 68076083 +P 7900 6750 +F 0 "U28" H 7900 6750 60 0000 C CNN +F 1 "d_nor" H 7950 6850 60 0000 C CNN +F 2 "" H 7900 6750 60 0000 C CNN +F 3 "" H 7900 6750 60 0000 C CNN + 1 7900 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 1100 3700 7300 +Wire Wire Line + 3700 1100 5550 1100 +Connection ~ 2650 1400 +Wire Wire Line + 3550 1850 3850 1850 +Wire Wire Line + 3850 1400 3850 6300 +Wire Wire Line + 3850 1400 5550 1400 +Wire Wire Line + 5350 2400 5350 2300 +Wire Wire Line + 5350 2300 5550 2300 +Connection ~ 2650 2400 +Wire Wire Line + 4700 2900 3550 2900 +Wire Wire Line + 4700 750 4700 6400 +Wire Wire Line + 4700 2650 5550 2650 +Wire Wire Line + 3150 3400 5550 3400 +Wire Wire Line + 3150 3300 3150 3400 +Connection ~ 2600 3300 +Wire Wire Line + 4000 4450 5550 4450 +Wire Wire Line + 4000 4450 4000 3850 +Wire Wire Line + 4000 3850 3550 3850 +Wire Wire Line + 5050 6900 5550 6900 +Wire Wire Line + 5050 1700 5050 7450 +Connection ~ 2650 4200 +Wire Wire Line + 3550 4350 3550 3050 +Wire Wire Line + 3550 3050 5550 3050 +Wire Wire Line + 3700 2550 5550 2550 +Connection ~ 3700 1400 +Wire Wire Line + 3700 3200 5550 3200 +Connection ~ 3700 2550 +Wire Wire Line + 3700 3900 5550 3900 +Connection ~ 3700 3200 +Wire Wire Line + 3700 7300 2650 7300 +Connection ~ 3700 3900 +Wire Wire Line + 3850 2200 5550 2200 +Connection ~ 3850 1850 +Wire Wire Line + 3850 3550 5550 3550 +Connection ~ 3850 2200 +Wire Wire Line + 3850 4250 5550 4250 +Connection ~ 3850 3550 +Wire Wire Line + 3850 4800 5550 4800 +Connection ~ 3850 4250 +Wire Wire Line + 3850 5400 5550 5400 +Connection ~ 3850 4800 +Wire Wire Line + 3850 5950 5550 5950 +Connection ~ 3850 5400 +Wire Wire Line + 3850 6300 5550 6300 +Connection ~ 3850 5950 +Wire Wire Line + 4000 1500 4000 3800 +Wire Wire Line + 4000 1500 5550 1500 +Connection ~ 4000 2400 +Wire Wire Line + 4000 3650 5550 3650 +Wire Wire Line + 4000 3800 4150 3800 +Wire Wire Line + 4150 3800 4150 7650 +Wire Wire Line + 4150 4000 5550 4000 +Connection ~ 4000 3650 +Wire Wire Line + 4150 5150 5550 5150 +Connection ~ 4150 4000 +Wire Wire Line + 4150 6700 5550 6700 +Connection ~ 4150 5150 +Wire Wire Line + 5050 7450 2550 7450 +Wire Wire Line + 2550 7450 2550 7300 +Connection ~ 5050 6900 +Wire Wire Line + 4700 750 5550 750 +Connection ~ 4700 2650 +Wire Wire Line + 5550 1900 4700 1900 +Connection ~ 4700 1900 +Wire Wire Line + 4700 3300 5550 3300 +Connection ~ 4700 2900 +Wire Wire Line + 4700 4350 5550 4350 +Connection ~ 4700 3300 +Wire Wire Line + 4700 5500 5550 5500 +Connection ~ 4700 4350 +Wire Wire Line + 4700 5650 5550 5650 +Connection ~ 4700 5500 +Wire Wire Line + 4700 6400 5550 6400 +Connection ~ 4700 5650 +Wire Wire Line + 4350 1600 4350 7550 +Wire Wire Line + 4350 1600 5550 1600 +Connection ~ 4350 3400 +Wire Wire Line + 4350 3750 5550 3750 +Wire Wire Line + 4350 5750 5550 5750 +Connection ~ 4350 3750 +Wire Wire Line + 4350 6050 5550 6050 +Connection ~ 4350 5750 +Wire Wire Line + 4350 6800 5550 6800 +Connection ~ 4350 6050 +Wire Wire Line + 4350 7550 2350 7550 +Wire Wire Line + 2350 7550 2350 7300 +Connection ~ 4350 6800 +Wire Wire Line + 4500 1200 4500 6500 +Wire Wire Line + 4500 1200 5550 1200 +Connection ~ 4500 4450 +Wire Wire Line + 5550 2400 5400 2400 +Wire Wire Line + 5400 2400 5400 3000 +Wire Wire Line + 5400 3000 4500 3000 +Connection ~ 4500 3000 +Wire Wire Line + 5550 2750 5400 2750 +Connection ~ 5400 2750 +Wire Wire Line + 5550 2950 5400 2950 +Connection ~ 5400 2950 +Wire Wire Line + 5550 4100 4500 4100 +Connection ~ 4500 4100 +Wire Wire Line + 4500 5250 5550 5250 +Wire Wire Line + 4500 6500 5550 6500 +Connection ~ 4500 5250 +Wire Wire Line + 4200 850 4200 3050 +Wire Wire Line + 4200 850 5550 850 +Connection ~ 4200 3050 +Wire Wire Line + 5550 2000 4200 2000 +Wire Wire Line + 4200 2000 4200 1950 +Connection ~ 4200 1950 +Wire Wire Line + 4150 7650 2250 7650 +Wire Wire Line + 2250 7650 2250 7300 +Connection ~ 4150 6700 +Wire Wire Line + 5050 6150 5550 6150 +Connection ~ 5050 6150 +Wire Wire Line + 5550 1700 5050 1700 +Connection ~ 5050 4200 +$Comp +L d_nor U22 +U 1 1 6807B01F +P 7400 950 +F 0 "U22" H 7400 950 60 0000 C CNN +F 1 "d_nor" H 7450 1050 60 0000 C CNN +F 2 "" H 7400 950 60 0000 C CNN +F 3 "" H 7400 950 60 0000 C CNN + 1 7400 950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U29 +U 1 1 6807B09C +P 8550 900 +F 0 "U29" H 8550 900 60 0000 C CNN +F 1 "d_nor" H 8600 1000 60 0000 C CNN +F 2 "" H 8550 900 60 0000 C CNN +F 3 "" H 8550 900 60 0000 C CNN + 1 8550 900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U35 +U 1 1 6807B127 +P 9000 1450 +F 0 "U35" H 9000 1450 60 0000 C CNN +F 1 "d_nor" H 9050 1550 60 0000 C CNN +F 2 "" H 9000 1450 60 0000 C CNN +F 3 "" H 9000 1450 60 0000 C CNN + 1 9000 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U23 +U 1 1 6807B65C +P 7400 2100 +F 0 "U23" H 7400 2100 60 0000 C CNN +F 1 "d_nor" H 7450 2200 60 0000 C CNN +F 2 "" H 7400 2100 60 0000 C CNN +F 3 "" H 7400 2100 60 0000 C CNN + 1 7400 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U30 +U 1 1 6807B662 +P 8550 2050 +F 0 "U30" H 8550 2050 60 0000 C CNN +F 1 "d_nor" H 8600 2150 60 0000 C CNN +F 2 "" H 8550 2050 60 0000 C CNN +F 3 "" H 8550 2050 60 0000 C CNN + 1 8550 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U36 +U 1 1 6807B668 +P 9000 2600 +F 0 "U36" H 9000 2600 60 0000 C CNN +F 1 "d_nor" H 9050 2700 60 0000 C CNN +F 2 "" H 9000 2600 60 0000 C CNN +F 3 "" H 9000 2600 60 0000 C CNN + 1 9000 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U24 +U 1 1 6807B7A0 +P 7400 3800 +F 0 "U24" H 7400 3800 60 0000 C CNN +F 1 "d_nor" H 7450 3900 60 0000 C CNN +F 2 "" H 7400 3800 60 0000 C CNN +F 3 "" H 7400 3800 60 0000 C CNN + 1 7400 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U31 +U 1 1 6807B7A6 +P 8550 3750 +F 0 "U31" H 8550 3750 60 0000 C CNN +F 1 "d_nor" H 8600 3850 60 0000 C CNN +F 2 "" H 8550 3750 60 0000 C CNN +F 3 "" H 8550 3750 60 0000 C CNN + 1 8550 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U37 +U 1 1 6807B7AC +P 9000 4300 +F 0 "U37" H 9000 4300 60 0000 C CNN +F 1 "d_nor" H 9050 4400 60 0000 C CNN +F 2 "" H 9000 4300 60 0000 C CNN +F 3 "" H 9000 4300 60 0000 C CNN + 1 9000 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U25 +U 1 1 6807BABC +P 7400 5650 +F 0 "U25" H 7400 5650 60 0000 C CNN +F 1 "d_nor" H 7450 5750 60 0000 C CNN +F 2 "" H 7400 5650 60 0000 C CNN +F 3 "" H 7400 5650 60 0000 C CNN + 1 7400 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U32 +U 1 1 6807BAC2 +P 8550 5600 +F 0 "U32" H 8550 5600 60 0000 C CNN +F 1 "d_nor" H 8600 5700 60 0000 C CNN +F 2 "" H 8550 5600 60 0000 C CNN +F 3 "" H 8550 5600 60 0000 C CNN + 1 8550 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U38 +U 1 1 6807BAC8 +P 9000 6150 +F 0 "U38" H 9000 6150 60 0000 C CNN +F 1 "d_nor" H 9050 6250 60 0000 C CNN +F 2 "" H 9000 6150 60 0000 C CNN +F 3 "" H 9000 6150 60 0000 C CNN + 1 9000 6150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6807C68E +P 10900 1400 +F 0 "U1" H 10950 1500 30 0000 C CNN +F 1 "PORT" H 10900 1400 30 0000 C CNN +F 2 "" H 10900 1400 60 0000 C CNN +F 3 "" H 10900 1400 60 0000 C CNN + 8 10900 1400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6807D315 +P 10900 2550 +F 0 "U1" H 10950 2650 30 0000 C CNN +F 1 "PORT" H 10900 2550 30 0000 C CNN +F 2 "" H 10900 2550 60 0000 C CNN +F 3 "" H 10900 2550 60 0000 C CNN + 9 10900 2550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6807D3B8 +P 10900 3150 +F 0 "U1" H 10950 3250 30 0000 C CNN +F 1 "PORT" H 10900 3150 30 0000 C CNN +F 2 "" H 10900 3150 60 0000 C CNN +F 3 "" H 10900 3150 60 0000 C CNN + 10 10900 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6807D457 +P 10900 4250 +F 0 "U1" H 10950 4350 30 0000 C CNN +F 1 "PORT" H 10900 4250 30 0000 C CNN +F 2 "" H 10900 4250 60 0000 C CNN +F 3 "" H 10900 4250 60 0000 C CNN + 11 10900 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6807D4F4 +P 10900 5050 +F 0 "U1" H 10950 5150 30 0000 C CNN +F 1 "PORT" H 10900 5050 30 0000 C CNN +F 2 "" H 10900 5050 60 0000 C CNN +F 3 "" H 10900 5050 60 0000 C CNN + 12 10900 5050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6807D719 +P 10900 6100 +F 0 "U1" H 10950 6200 30 0000 C CNN +F 1 "PORT" H 10900 6100 30 0000 C CNN +F 2 "" H 10900 6100 60 0000 C CNN +F 3 "" H 10900 6100 60 0000 C CNN + 13 10900 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6807D7BA +P 10900 6700 +F 0 "U1" H 10950 6800 30 0000 C CNN +F 1 "PORT" H 10900 6700 30 0000 C CNN +F 2 "" H 10900 6700 60 0000 C CNN +F 3 "" H 10900 6700 60 0000 C CNN + 14 10900 6700 + -1 0 0 1 +$EndComp +Wire Wire Line + 6450 800 6950 800 +Wire Wire Line + 6950 800 6950 850 +Wire Wire Line + 6450 1150 6950 1150 +Wire Wire Line + 6950 1150 6950 950 +Wire Wire Line + 6450 1950 6950 1950 +Wire Wire Line + 7950 2050 7850 2050 +Wire Wire Line + 7950 1950 7950 2050 +Wire Wire Line + 7950 1950 8100 1950 +Wire Wire Line + 7950 2000 8100 2000 +Wire Wire Line + 8100 2000 8100 2050 +Connection ~ 7950 2000 +Wire Wire Line + 9000 2000 9000 2400 +Wire Wire Line + 9000 2400 8550 2400 +Wire Wire Line + 8550 2400 8550 2500 +Wire Wire Line + 6400 1550 8550 1550 +Wire Wire Line + 8550 1550 8550 1450 +Wire Wire Line + 7850 900 7850 800 +Wire Wire Line + 7850 800 8100 800 +Wire Wire Line + 7900 800 7900 900 +Wire Wire Line + 7900 900 8100 900 +Connection ~ 7900 800 +Wire Wire Line + 9000 850 9000 1150 +Wire Wire Line + 9000 1150 8550 1150 +Wire Wire Line + 8550 1150 8550 1350 +Wire Wire Line + 6400 2300 6950 2300 +Wire Wire Line + 6950 2300 6950 2100 +Wire Wire Line + 6950 1950 6950 2000 +Wire Wire Line + 6400 2650 8550 2650 +Wire Wire Line + 8550 2650 8550 2600 +Wire Wire Line + 6450 3000 7400 3000 +Wire Wire Line + 7400 3000 7400 3100 +Wire Wire Line + 6400 3300 7400 3300 +Wire Wire Line + 7400 3300 7400 3200 +Wire Wire Line + 6400 3650 6950 3650 +Wire Wire Line + 6950 3650 6950 3700 +Wire Wire Line + 6400 4000 6400 3800 +Wire Wire Line + 6400 3800 6950 3800 +Wire Wire Line + 6400 4350 8550 4350 +Wire Wire Line + 8550 4350 8550 4300 +Wire Wire Line + 7850 3750 7850 3650 +Wire Wire Line + 7850 3650 8100 3650 +Wire Wire Line + 7950 3650 7950 3750 +Wire Wire Line + 7950 3750 8100 3750 +Connection ~ 7950 3650 +Wire Wire Line + 9000 3700 9000 4100 +Wire Wire Line + 9000 4100 8550 4100 +Wire Wire Line + 8550 4100 8550 4200 +Wire Wire Line + 6700 4800 7350 4800 +Wire Wire Line + 7350 4800 7350 5000 +Wire Wire Line + 6450 5200 7350 5200 +Wire Wire Line + 7350 5200 7350 5100 +Wire Wire Line + 6400 6400 7450 6400 +Wire Wire Line + 7450 6400 7450 6650 +Wire Wire Line + 6450 6850 7450 6850 +Wire Wire Line + 7450 6850 7450 6750 +Wire Wire Line + 6450 5450 6950 5450 +Wire Wire Line + 6950 5450 6950 5550 +Wire Wire Line + 6450 5700 6950 5700 +Wire Wire Line + 6950 5700 6950 5650 +Wire Wire Line + 6400 6050 8300 6050 +Wire Wire Line + 8300 6050 8300 6150 +Wire Wire Line + 8300 6150 8550 6150 +Wire Wire Line + 9000 5550 9000 5850 +Wire Wire Line + 9000 5850 8550 5850 +Wire Wire Line + 8550 5850 8550 6050 +Wire Wire Line + 8100 5500 8000 5500 +Wire Wire Line + 8000 5500 8000 5600 +Wire Wire Line + 8000 5600 8100 5600 +Wire Wire Line + 7850 5600 7850 5550 +Wire Wire Line + 7850 5550 8000 5550 +Connection ~ 8000 5550 +Wire Wire Line + 2400 5300 1850 5300 +Connection ~ 2400 5300 +Wire Wire Line + 1850 5300 1850 4750 +Wire Wire Line + 2400 1900 2400 5350 +Wire Wire Line + 1000 7000 1750 7000 +$Comp +L d_nand U33 +U 1 1 6808DDE8 +P 2450 5800 +F 0 "U33" H 2450 5800 60 0000 C CNN +F 1 "d_nand" H 2500 5900 60 0000 C CNN +F 2 "" H 2450 5800 60 0000 C CNN +F 3 "" H 2450 5800 60 0000 C CNN + 1 2450 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 1750 6400 1750 7300 +Wire Wire Line + 1750 7300 2050 7300 +Wire Wire Line + 1750 6400 1100 6400 +Connection ~ 1100 6400 +Connection ~ 1750 7000 +$Comp +L d_inverter U39 +U 1 1 68161C40 +P 10050 1400 +F 0 "U39" H 10050 1300 60 0000 C CNN +F 1 "d_inverter" H 10050 1550 60 0000 C CNN +F 2 "" H 10100 1350 60 0000 C CNN +F 3 "" H 10100 1350 60 0000 C CNN + 1 10050 1400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 1400 9750 1400 +Wire Wire Line + 10350 1400 10650 1400 +$Comp +L d_inverter U40 +U 1 1 6816223F +P 10050 2550 +F 0 "U40" H 10050 2450 60 0000 C CNN +F 1 "d_inverter" H 10050 2700 60 0000 C CNN +F 2 "" H 10100 2500 60 0000 C CNN +F 3 "" H 10100 2500 60 0000 C CNN + 1 10050 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 2550 9750 2550 +Wire Wire Line + 10350 2550 10650 2550 +$Comp +L d_inverter U34 +U 1 1 6816284C +P 9800 3150 +F 0 "U34" H 9800 3050 60 0000 C CNN +F 1 "d_inverter" H 9800 3300 60 0000 C CNN +F 2 "" H 9850 3100 60 0000 C CNN +F 3 "" H 9850 3100 60 0000 C CNN + 1 9800 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 3150 9500 3150 +Wire Wire Line + 10100 3150 10650 3150 +$Comp +L d_inverter U41 +U 1 1 68162B94 +P 10050 4250 +F 0 "U41" H 10050 4150 60 0000 C CNN +F 1 "d_inverter" H 10050 4400 60 0000 C CNN +F 2 "" H 10100 4200 60 0000 C CNN +F 3 "" H 10100 4200 60 0000 C CNN + 1 10050 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 4250 9750 4250 +Wire Wire Line + 10350 4250 10650 4250 +$Comp +L d_inverter U8 +U 1 1 6816304F +P 9700 5050 +F 0 "U8" H 9700 4950 60 0000 C CNN +F 1 "d_inverter" H 9700 5200 60 0000 C CNN +F 2 "" H 9750 5000 60 0000 C CNN +F 3 "" H 9750 5000 60 0000 C CNN + 1 9700 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8250 5050 9400 5050 +Wire Wire Line + 10000 5050 10650 5050 +$Comp +L d_inverter U42 +U 1 1 68163399 +P 10100 6100 +F 0 "U42" H 10100 6000 60 0000 C CNN +F 1 "d_inverter" H 10100 6250 60 0000 C CNN +F 2 "" H 10150 6050 60 0000 C CNN +F 3 "" H 10150 6050 60 0000 C CNN + 1 10100 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 6100 9800 6100 +Wire Wire Line + 10400 6100 10650 6100 +$Comp +L d_inverter U7 +U 1 1 681636FC +P 9650 6700 +F 0 "U7" H 9650 6600 60 0000 C CNN +F 1 "d_inverter" H 9650 6850 60 0000 C CNN +F 2 "" H 9700 6650 60 0000 C CNN +F 3 "" H 9700 6650 60 0000 C CNN + 1 9650 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8350 6700 9350 6700 +Wire Wire Line + 9950 6700 10650 6700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DM7447A/7447.sub b/library/SubcircuitLibrary/DM7447A/7447.sub new file mode 100644 index 00000000..8ca0b8b1 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447.sub @@ -0,0 +1,183 @@ +* Subcircuit 7447 +.subckt 7447 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\7447\7447.cir +.include 4_and.sub +.include 3_and.sub +* u3 net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand +* u4 net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand +* u5 net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand +* u2 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter +x1 net-_u1-pad6_ net-_u6-pad2_ net-_u11-pad1_ net-_u12-pad1_ net-_u33-pad1_ 4_and +* u9 net-_u13-pad1_ net-_u10-pad1_ net-_u33-pad2_ d_and +* u10 net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand +* u14 net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and +* u15 net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and +x10 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ ? 4_and +* u16 net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and +x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad2_ 3_and +x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad2_ 3_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and +x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u27-pad2_ 3_and +x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u24-pad1_ 3_and +x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u24-pad2_ 3_and +x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u37-pad2_ 3_and +* u21 net-_u10-pad3_ net-_u21-pad2_ d_buffer +* u18 net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and +* u19 net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and +* u20 net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and +x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad2_ 3_and +x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u28-pad1_ 3_and +x11 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad2_ 4_and +* u27 net-_u17-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u26 net-_u21-pad2_ net-_u18-pad3_ net-_u26-pad3_ d_nor +* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor +* u22 net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor +* u29 net-_u22-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u35 net-_u29-pad3_ ? net-_u35-pad3_ d_nor +* u23 net-_u16-pad3_ net-_u23-pad2_ net-_u23-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_nor +* u36 net-_u30-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_nor +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor +* u31 net-_u24-pad3_ net-_u24-pad3_ net-_u31-pad3_ d_nor +* u37 net-_u31-pad3_ net-_u37-pad2_ net-_u37-pad3_ d_nor +* u25 net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor +* u32 net-_u25-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_nor +* u38 net-_u32-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nor +* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u1-pad5_ d_nand +* u39 net-_u35-pad3_ net-_u1-pad8_ d_inverter +* u40 net-_u36-pad3_ net-_u1-pad9_ d_inverter +* u34 net-_u27-pad3_ net-_u1-pad10_ d_inverter +* u41 net-_u37-pad3_ net-_u1-pad11_ d_inverter +* u8 net-_u26-pad3_ net-_u1-pad12_ d_inverter +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u7 net-_u28-pad3_ net-_u1-pad14_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u3 +a2 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u4 +a3 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u5 +a4 net-_u1-pad4_ net-_u13-pad1_ u2 +a5 net-_u1-pad7_ net-_u6-pad2_ u6 +a6 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u33-pad2_ u9 +a7 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10 +a8 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11 +a9 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12 +a10 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13 +a11 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a12 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15 +a13 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 net-_u10-pad3_ net-_u21-pad2_ u21 +a16 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18 +a17 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19 +a18 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20 +a19 [net-_u17-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a20 [net-_u21-pad2_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a22 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 +a23 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u29-pad3_ ? ] net-_u35-pad3_ u35 +a25 [net-_u16-pad3_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30 +a27 [net-_u30-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36 +a28 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a29 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a31 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25 +a32 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a34 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u1-pad5_ u33 +a35 net-_u35-pad3_ net-_u1-pad8_ u39 +a36 net-_u36-pad3_ net-_u1-pad9_ u40 +a37 net-_u27-pad3_ net-_u1-pad10_ u34 +a38 net-_u37-pad3_ net-_u1-pad11_ u41 +a39 net-_u26-pad3_ net-_u1-pad12_ u8 +a40 net-_u38-pad3_ net-_u1-pad13_ u42 +a41 net-_u28-pad3_ net-_u1-pad14_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 7447
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml b/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml new file mode 100644 index 00000000..6a315fdb --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_buffer<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u20><u27 name="type">d_nor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_nor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_nor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u28><u39 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u39><u34 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u33><u22 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u22><u29 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u29><u35 name="type">d_nor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u35><u40 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u40><u23 name="type">d_nor<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23><u30 name="type">d_nor<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u30><u36 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u36><u41 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u41><u24 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u24><u31 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u31><u37 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u37><u42 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u42><u25 name="type">d_nor<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u25><u32 name="type">d_nor<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u32><u38 name="type">d_nor<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u38><u43 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u43><u8 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u8><u39 name="type">d_buffer<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u39><u33 name="type">d_buffer<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u33><u33 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u33><u8 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x10><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x11></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DM7447A/analysis b/library/SubcircuitLibrary/DM7447A/analysis new file mode 100644 index 00000000..9b724012 --- /dev/null +++ b/library/SubcircuitLibrary/DM7447A/analysis @@ -0,0 +1 @@ +.tran 1e-03 20e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC149/74149.cir b/library/SubcircuitLibrary/HD74HC149/74149.cir new file mode 100644 index 00000000..c1bd662d --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.cir @@ -0,0 +1,52 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74149\74149.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/12/25 14:03:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad9_ Net-_U14-Pad1_ d_inverter +U3 Net-_U1-Pad8_ Net-_U11-Pad1_ d_inverter +U4 Net-_U1-Pad7_ Net-_U12-Pad1_ d_inverter +U5 Net-_U1-Pad6_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U15-Pad1_ d_inverter +U7 Net-_U1-Pad4_ Net-_U16-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U19-Pad1_ d_inverter +U9 Net-_U1-Pad2_ Net-_U17-Pad1_ d_inverter +U10 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U18 Net-_U10-Pad2_ Net-_U18-Pad2_ d_inverter +U20 Net-_U18-Pad2_ Net-_U20-Pad2_ d_inverter +U21 Net-_U11-Pad1_ Net-_U14-Pad2_ Net-_U21-Pad3_ d_and +U24 Net-_U14-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad18_ d_nand +U25 Net-_U21-Pad3_ Net-_U20-Pad2_ Net-_U1-Pad17_ d_nand +X1 Net-_U12-Pad1_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U26-Pad1_ 3_and +X2 Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U27-Pad1_ 4_and +X3 Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U23-Pad1_ 4_and +U26 Net-_U26-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad16_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad15_ d_nand +X7 Net-_U15-Pad1_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U29-Pad1_ 3_and +U29 Net-_U29-Pad1_ Net-_U1-Pad14_ d_inverter +U22 Net-_U16-Pad1_ Net-_U15-Pad2_ Net-_U22-Pad3_ d_and +X4 Net-_U19-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_X4-Pad4_ 3_and +X5 Net-_U17-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_X10-Pad1_ 4_and +X6 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_U17-Pad2_ Net-_U23-Pad2_ 4_and +X8 Net-_U22-Pad3_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U30-Pad1_ 3_and +X9 Net-_X4-Pad4_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U31-Pad1_ 3_and +X10 Net-_X10-Pad1_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U32-Pad1_ 3_and +U28 Net-_U23-Pad3_ Net-_U20-Pad2_ Net-_U1-Pad10_ d_nand +U30 Net-_U30-Pad1_ Net-_U1-Pad13_ d_inverter +U31 Net-_U31-Pad1_ Net-_U1-Pad12_ d_inverter +U32 Net-_U32-Pad1_ Net-_U1-Pad11_ d_inverter +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/HD74HC149/74149.cir.out b/library/SubcircuitLibrary/HD74HC149/74149.cir.out new file mode 100644 index 00000000..6b56ec63 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.cir.out @@ -0,0 +1,148 @@ +* c:\fossee\esim\library\subcircuitlibrary\74149\74149.cir + +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad9_ net-_u14-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u4 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u5 net-_u1-pad6_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad4_ net-_u16-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u19-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u17-pad1_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u18-pad2_ d_inverter +* u20 net-_u18-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u24 net-_u14-pad1_ net-_u20-pad2_ net-_u1-pad18_ d_nand +* u25 net-_u21-pad3_ net-_u20-pad2_ net-_u1-pad17_ d_nand +x1 net-_u12-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u26-pad1_ 3_and +x2 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u27-pad1_ 4_and +x3 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u23-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u20-pad2_ net-_u1-pad16_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u20-pad2_ net-_u1-pad15_ d_nand +x7 net-_u15-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u29-pad1_ 3_and +* u29 net-_u29-pad1_ net-_u1-pad14_ d_inverter +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +x4 net-_u19-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_x4-pad4_ 3_and +x5 net-_u17-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_x10-pad1_ 4_and +x6 net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u17-pad2_ net-_u23-pad2_ 4_and +x8 net-_u22-pad3_ net-_u23-pad1_ net-_u20-pad2_ net-_u30-pad1_ 3_and +x9 net-_x4-pad4_ net-_u23-pad1_ net-_u20-pad2_ net-_u31-pad1_ 3_and +x10 net-_x10-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u32-pad1_ 3_and +* u28 net-_u23-pad3_ net-_u20-pad2_ net-_u1-pad10_ d_nand +* u30 net-_u30-pad1_ net-_u1-pad13_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad12_ d_inverter +* u32 net-_u32-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 net-_u1-pad9_ net-_u14-pad1_ u2 +a2 net-_u1-pad8_ net-_u11-pad1_ u3 +a3 net-_u1-pad7_ net-_u12-pad1_ u4 +a4 net-_u1-pad6_ net-_u13-pad1_ u5 +a5 net-_u1-pad5_ net-_u15-pad1_ u6 +a6 net-_u1-pad4_ net-_u16-pad1_ u7 +a7 net-_u1-pad3_ net-_u19-pad1_ u8 +a8 net-_u1-pad2_ net-_u17-pad1_ u9 +a9 net-_u1-pad1_ net-_u10-pad2_ u10 +a10 net-_u14-pad1_ net-_u14-pad2_ u14 +a11 net-_u11-pad1_ net-_u11-pad2_ u11 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u19-pad1_ net-_u19-pad2_ u19 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u10-pad2_ net-_u18-pad2_ u18 +a18 net-_u18-pad2_ net-_u20-pad2_ u20 +a19 [net-_u11-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a20 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u1-pad18_ u24 +a21 [net-_u21-pad3_ net-_u20-pad2_ ] net-_u1-pad17_ u25 +a22 [net-_u26-pad1_ net-_u20-pad2_ ] net-_u1-pad16_ u26 +a23 net-_u12-pad1_ net-_u12-pad2_ u12 +a24 [net-_u27-pad1_ net-_u20-pad2_ ] net-_u1-pad15_ u27 +a25 net-_u29-pad1_ net-_u1-pad14_ u29 +a26 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a27 [net-_u23-pad3_ net-_u20-pad2_ ] net-_u1-pad10_ u28 +a28 net-_u30-pad1_ net-_u1-pad13_ u30 +a29 net-_u31-pad1_ net-_u1-pad12_ u31 +a30 net-_u32-pad1_ net-_u1-pad11_ u32 +a31 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74HC149/74149.pro b/library/SubcircuitLibrary/HD74HC149/74149.pro new file mode 100644 index 00000000..1ae53d0a --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.pro @@ -0,0 +1,83 @@ +update=05/12/25 17:39:01 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/HD74HC149/74149.sch b/library/SubcircuitLibrary/HD74HC149/74149.sch new file mode 100644 index 00000000..762be4ab --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.sch @@ -0,0 +1,1012 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74149-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68219668 +P 2100 1000 +F 0 "U2" H 2100 900 60 0000 C CNN +F 1 "d_inverter" H 2100 1150 60 0000 C CNN +F 2 "" H 2150 950 60 0000 C CNN +F 3 "" H 2150 950 60 0000 C CNN + 1 2100 1000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6821967F +P 2100 1800 +F 0 "U3" H 2100 1700 60 0000 C CNN +F 1 "d_inverter" H 2100 1950 60 0000 C CNN +F 2 "" H 2150 1750 60 0000 C CNN +F 3 "" H 2150 1750 60 0000 C CNN + 1 2100 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68219698 +P 2100 2200 +F 0 "U4" H 2100 2100 60 0000 C CNN +F 1 "d_inverter" H 2100 2350 60 0000 C CNN +F 2 "" H 2150 2150 60 0000 C CNN +F 3 "" H 2150 2150 60 0000 C CNN + 1 2100 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 682196BF +P 2100 2600 +F 0 "U5" H 2100 2500 60 0000 C CNN +F 1 "d_inverter" H 2100 2750 60 0000 C CNN +F 2 "" H 2150 2550 60 0000 C CNN +F 3 "" H 2150 2550 60 0000 C CNN + 1 2100 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 682196E6 +P 2200 3750 +F 0 "U6" H 2200 3650 60 0000 C CNN +F 1 "d_inverter" H 2200 3900 60 0000 C CNN +F 2 "" H 2250 3700 60 0000 C CNN +F 3 "" H 2250 3700 60 0000 C CNN + 1 2200 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68219705 +P 2200 4300 +F 0 "U7" H 2200 4200 60 0000 C CNN +F 1 "d_inverter" H 2200 4450 60 0000 C CNN +F 2 "" H 2250 4250 60 0000 C CNN +F 3 "" H 2250 4250 60 0000 C CNN + 1 2200 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68219726 +P 2200 4700 +F 0 "U8" H 2200 4600 60 0000 C CNN +F 1 "d_inverter" H 2200 4850 60 0000 C CNN +F 2 "" H 2250 4650 60 0000 C CNN +F 3 "" H 2250 4650 60 0000 C CNN + 1 2200 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6821974F +P 2200 5100 +F 0 "U9" H 2200 5000 60 0000 C CNN +F 1 "d_inverter" H 2200 5250 60 0000 C CNN +F 2 "" H 2250 5050 60 0000 C CNN +F 3 "" H 2250 5050 60 0000 C CNN + 1 2200 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68219778 +P 2200 5650 +F 0 "U10" H 2200 5550 60 0000 C CNN +F 1 "d_inverter" H 2200 5800 60 0000 C CNN +F 2 "" H 2250 5600 60 0000 C CNN +F 3 "" H 2250 5600 60 0000 C CNN + 1 2200 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 682197A3 +P 3700 1300 +F 0 "U14" H 3700 1200 60 0000 C CNN +F 1 "d_inverter" H 3700 1450 60 0000 C CNN +F 2 "" H 3750 1250 60 0000 C CNN +F 3 "" H 3750 1250 60 0000 C CNN + 1 3700 1300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 682197CC +P 3650 2000 +F 0 "U11" H 3650 1900 60 0000 C CNN +F 1 "d_inverter" H 3650 2150 60 0000 C CNN +F 2 "" H 3700 1950 60 0000 C CNN +F 3 "" H 3700 1950 60 0000 C CNN + 1 3650 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 682197FB +P 3650 2850 +F 0 "U13" H 3650 2750 60 0000 C CNN +F 1 "d_inverter" H 3650 3000 60 0000 C CNN +F 2 "" H 3700 2800 60 0000 C CNN +F 3 "" H 3700 2800 60 0000 C CNN + 1 3650 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 68219828 +P 3700 4150 +F 0 "U15" H 3700 4050 60 0000 C CNN +F 1 "d_inverter" H 3700 4300 60 0000 C CNN +F 2 "" H 3750 4100 60 0000 C CNN +F 3 "" H 3750 4100 60 0000 C CNN + 1 3700 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6821985D +P 3700 4700 +F 0 "U16" H 3700 4600 60 0000 C CNN +F 1 "d_inverter" H 3700 4850 60 0000 C CNN +F 2 "" H 3750 4650 60 0000 C CNN +F 3 "" H 3750 4650 60 0000 C CNN + 1 3700 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6821988E +P 3750 5150 +F 0 "U19" H 3750 5050 60 0000 C CNN +F 1 "d_inverter" H 3750 5300 60 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 1 3750 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 682198C1 +P 3700 5600 +F 0 "U17" H 3700 5500 60 0000 C CNN +F 1 "d_inverter" H 3700 5750 60 0000 C CNN +F 2 "" H 3750 5550 60 0000 C CNN +F 3 "" H 3750 5550 60 0000 C CNN + 1 3700 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 68219937 +P 3700 6450 +F 0 "U18" H 3700 6350 60 0000 C CNN +F 1 "d_inverter" H 3700 6600 60 0000 C CNN +F 2 "" H 3750 6400 60 0000 C CNN +F 3 "" H 3750 6400 60 0000 C CNN + 1 3700 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 68219986 +P 4650 6450 +F 0 "U20" H 4650 6350 60 0000 C CNN +F 1 "d_inverter" H 4650 6600 60 0000 C CNN +F 2 "" H 4700 6400 60 0000 C CNN +F 3 "" H 4700 6400 60 0000 C CNN + 1 4650 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 682199C3 +P 5150 1450 +F 0 "U21" H 5150 1450 60 0000 C CNN +F 1 "d_and" H 5200 1550 60 0000 C CNN +F 2 "" H 5150 1450 60 0000 C CNN +F 3 "" H 5150 1450 60 0000 C CNN + 1 5150 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 68219A3E +P 7250 1000 +F 0 "U24" H 7250 1000 60 0000 C CNN +F 1 "d_nand" H 7300 1100 60 0000 C CNN +F 2 "" H 7250 1000 60 0000 C CNN +F 3 "" H 7250 1000 60 0000 C CNN + 1 7250 1000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U25 +U 1 1 6821A1E3 +P 7250 1400 +F 0 "U25" H 7250 1400 60 0000 C CNN +F 1 "d_nand" H 7300 1500 60 0000 C CNN +F 2 "" H 7250 1400 60 0000 C CNN +F 3 "" H 7250 1400 60 0000 C CNN + 1 7250 1400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6821A3F2 +P 5050 2150 +F 0 "X1" H 5150 2100 60 0000 C CNN +F 1 "3_and" H 5200 2300 60 0000 C CNN +F 2 "" H 5050 2150 60 0000 C CNN +F 3 "" H 5050 2150 60 0000 C CNN + 1 5050 2150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 6821A445 +P 5100 2700 +F 0 "X2" H 5150 2650 60 0000 C CNN +F 1 "4_and" H 5200 2800 60 0000 C CNN +F 2 "" H 5100 2700 60 0000 C CNN +F 3 "" H 5100 2700 60 0000 C CNN + 1 5100 2700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 6821A496 +P 5100 3400 +F 0 "X3" H 5150 3350 60 0000 C CNN +F 1 "4_and" H 5200 3500 60 0000 C CNN +F 2 "" H 5100 3400 60 0000 C CNN +F 3 "" H 5100 3400 60 0000 C CNN + 1 5100 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U26 +U 1 1 6821A6C0 +P 7250 2100 +F 0 "U26" H 7250 2100 60 0000 C CNN +F 1 "d_nand" H 7300 2200 60 0000 C CNN +F 2 "" H 7250 2100 60 0000 C CNN +F 3 "" H 7250 2100 60 0000 C CNN + 1 7250 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6821ADED +P 3650 2400 +F 0 "U12" H 3650 2300 60 0000 C CNN +F 1 "d_inverter" H 3650 2550 60 0000 C CNN +F 2 "" H 3700 2350 60 0000 C CNN +F 3 "" H 3700 2350 60 0000 C CNN + 1 3650 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U27 +U 1 1 6821B1F9 +P 7250 2750 +F 0 "U27" H 7250 2750 60 0000 C CNN +F 1 "d_nand" H 7300 2850 60 0000 C CNN +F 2 "" H 7250 2750 60 0000 C CNN +F 3 "" H 7250 2750 60 0000 C CNN + 1 7250 2750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 6821B792 +P 7150 3900 +F 0 "X7" H 7250 3850 60 0000 C CNN +F 1 "3_and" H 7300 4050 60 0000 C CNN +F 2 "" H 7150 3900 60 0000 C CNN +F 3 "" H 7150 3900 60 0000 C CNN + 1 7150 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6821B7EF +P 8150 3850 +F 0 "U29" H 8150 3750 60 0000 C CNN +F 1 "d_inverter" H 8150 4000 60 0000 C CNN +F 2 "" H 8200 3800 60 0000 C CNN +F 3 "" H 8200 3800 60 0000 C CNN + 1 8150 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 6821BAF1 +P 5200 4100 +F 0 "U22" H 5200 4100 60 0000 C CNN +F 1 "d_and" H 5250 4200 60 0000 C CNN +F 2 "" H 5200 4100 60 0000 C CNN +F 3 "" H 5200 4100 60 0000 C CNN + 1 5200 4100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 6821BB50 +P 5100 4700 +F 0 "X4" H 5200 4650 60 0000 C CNN +F 1 "3_and" H 5250 4850 60 0000 C CNN +F 2 "" H 5100 4700 60 0000 C CNN +F 3 "" H 5100 4700 60 0000 C CNN + 1 5100 4700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 6821BBAF +P 5150 5250 +F 0 "X5" H 5200 5200 60 0000 C CNN +F 1 "4_and" H 5250 5350 60 0000 C CNN +F 2 "" H 5150 5250 60 0000 C CNN +F 3 "" H 5150 5250 60 0000 C CNN + 1 5150 5250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 6821BC0A +P 5150 5800 +F 0 "X6" H 5200 5750 60 0000 C CNN +F 1 "4_and" H 5250 5900 60 0000 C CNN +F 2 "" H 5150 5800 60 0000 C CNN +F 3 "" H 5150 5800 60 0000 C CNN + 1 5150 5800 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 6821BC65 +P 7150 4350 +F 0 "X8" H 7250 4300 60 0000 C CNN +F 1 "3_and" H 7300 4500 60 0000 C CNN +F 2 "" H 7150 4350 60 0000 C CNN +F 3 "" H 7150 4350 60 0000 C CNN + 1 7150 4350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X9 +U 1 1 6821BCC4 +P 7150 4750 +F 0 "X9" H 7250 4700 60 0000 C CNN +F 1 "3_and" H 7300 4900 60 0000 C CNN +F 2 "" H 7150 4750 60 0000 C CNN +F 3 "" H 7150 4750 60 0000 C CNN + 1 7150 4750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X10 +U 1 1 6821BD29 +P 7150 5150 +F 0 "X10" H 7250 5100 60 0000 C CNN +F 1 "3_and" H 7300 5300 60 0000 C CNN +F 2 "" H 7150 5150 60 0000 C CNN +F 3 "" H 7150 5150 60 0000 C CNN + 1 7150 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U28 +U 1 1 6821BD8E +P 7250 5550 +F 0 "U28" H 7250 5550 60 0000 C CNN +F 1 "d_nand" H 7300 5650 60 0000 C CNN +F 2 "" H 7250 5550 60 0000 C CNN +F 3 "" H 7250 5550 60 0000 C CNN + 1 7250 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 6821BDF3 +P 8200 4300 +F 0 "U30" H 8200 4200 60 0000 C CNN +F 1 "d_inverter" H 8200 4450 60 0000 C CNN +F 2 "" H 8250 4250 60 0000 C CNN +F 3 "" H 8250 4250 60 0000 C CNN + 1 8200 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 6821BE5C +P 8200 4700 +F 0 "U31" H 8200 4600 60 0000 C CNN +F 1 "d_inverter" H 8200 4850 60 0000 C CNN +F 2 "" H 8250 4650 60 0000 C CNN +F 3 "" H 8250 4650 60 0000 C CNN + 1 8200 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U32 +U 1 1 6821BEC7 +P 8200 5100 +F 0 "U32" H 8200 5000 60 0000 C CNN +F 1 "d_inverter" H 8200 5250 60 0000 C CNN +F 2 "" H 8250 5050 60 0000 C CNN +F 3 "" H 8250 5050 60 0000 C CNN + 1 8200 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7650 3850 7850 3850 +Wire Wire Line + 7650 4300 7900 4300 +Wire Wire Line + 7650 4700 7900 4700 +Wire Wire Line + 7650 5100 7900 5100 +Wire Wire Line + 6600 6450 4950 6450 +Wire Wire Line + 2500 5650 2500 6450 +Wire Wire Line + 2500 6450 3400 6450 +Wire Wire Line + 4000 6450 4350 6450 +Wire Wire Line + 6600 1000 6600 6450 +Wire Wire Line + 6600 5550 6800 5550 +Wire Wire Line + 6800 5200 6600 5200 +Connection ~ 6600 5550 +Connection ~ 6600 5200 +Wire Wire Line + 6800 3950 6600 3950 +Connection ~ 6600 3950 +Wire Wire Line + 6800 4400 6600 4400 +Connection ~ 6600 4400 +Wire Wire Line + 6800 4800 6600 4800 +Connection ~ 6600 4800 +Wire Wire Line + 6600 2750 6800 2750 +Wire Wire Line + 6600 2100 6800 2100 +Connection ~ 6600 2750 +Wire Wire Line + 6600 1400 6800 1400 +Connection ~ 6600 2100 +Wire Wire Line + 6600 1000 6800 1000 +Connection ~ 6600 1400 +Wire Wire Line + 2400 1000 6000 1000 +Wire Wire Line + 6000 1000 6000 900 +Wire Wire Line + 6000 900 6800 900 +Wire Wire Line + 3200 1000 3200 1300 +Wire Wire Line + 3200 1300 3400 1300 +Connection ~ 3200 1000 +Wire Wire Line + 2400 1800 4300 1800 +Wire Wire Line + 3100 1800 3100 2000 +Wire Wire Line + 3100 2000 3350 2000 +Wire Wire Line + 4300 1800 4300 1350 +Wire Wire Line + 4300 1350 4700 1350 +Connection ~ 3100 1800 +Wire Wire Line + 4000 1300 4450 1300 +Wire Wire Line + 4450 1300 4450 3250 +Wire Wire Line + 4450 2100 4700 2100 +Wire Wire Line + 4450 1450 4700 1450 +Connection ~ 4450 1450 +Wire Wire Line + 4450 2650 4700 2650 +Connection ~ 4450 2100 +Wire Wire Line + 4450 3250 4700 3250 +Connection ~ 4450 2650 +Wire Wire Line + 3950 2000 4300 2000 +Wire Wire Line + 4300 2000 4300 3350 +Wire Wire Line + 4300 2200 4700 2200 +Wire Wire Line + 4300 2750 4700 2750 +Connection ~ 4300 2200 +Wire Wire Line + 4300 3350 4700 3350 +Connection ~ 4300 2750 +Wire Wire Line + 2400 2200 4100 2200 +Wire Wire Line + 4100 2200 4100 1900 +Wire Wire Line + 4100 1900 4700 1900 +Wire Wire Line + 4700 1900 4700 2000 +Wire Wire Line + 3100 2200 3100 2400 +Wire Wire Line + 3100 2400 3350 2400 +Connection ~ 3100 2200 +Wire Wire Line + 3950 2400 4100 2400 +Wire Wire Line + 4100 2400 4100 3450 +Wire Wire Line + 4100 2850 4700 2850 +Wire Wire Line + 4100 3450 4700 3450 +Connection ~ 4100 2850 +Wire Wire Line + 2400 2600 4550 2600 +Wire Wire Line + 4550 2600 4550 2450 +Wire Wire Line + 4550 2450 4700 2450 +Wire Wire Line + 4700 2450 4700 2550 +Wire Wire Line + 3100 2600 3100 2850 +Wire Wire Line + 3100 2850 3350 2850 +Connection ~ 3100 2600 +Wire Wire Line + 3950 2850 3950 3550 +Wire Wire Line + 3950 3550 4700 3550 +Wire Wire Line + 5600 1400 5600 1300 +Wire Wire Line + 5600 1300 6800 1300 +Wire Wire Line + 5550 2100 5550 2000 +Wire Wire Line + 5550 2000 6800 2000 +Wire Wire Line + 5600 2700 5600 2650 +Wire Wire Line + 5600 2650 6800 2650 +$Comp +L d_nand U23 +U 1 1 6821F335 +P 6250 6200 +F 0 "U23" H 6250 6200 60 0000 C CNN +F 1 "d_nand" H 6300 6300 60 0000 C CNN +F 2 "" H 6250 6200 60 0000 C CNN +F 3 "" H 6250 6200 60 0000 C CNN + 1 6250 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5650 5800 5650 6200 +Wire Wire Line + 5650 6200 5800 6200 +Wire Wire Line + 5600 3400 5800 3400 +Wire Wire Line + 5800 3400 5800 6100 +Wire Wire Line + 2500 3750 6800 3750 +Wire Wire Line + 5800 3850 6800 3850 +Connection ~ 5800 3850 +Wire Wire Line + 6800 4300 5800 4300 +Connection ~ 5800 4300 +Wire Wire Line + 6800 4700 5800 4700 +Connection ~ 5800 4700 +Wire Wire Line + 6800 5100 5800 5100 +Connection ~ 5800 5100 +Wire Wire Line + 6700 6150 6700 5450 +Wire Wire Line + 6700 5450 6800 5450 +Wire Wire Line + 3150 3750 3150 4150 +Wire Wire Line + 3150 4150 3400 4150 +Connection ~ 3150 3750 +Wire Wire Line + 4000 4150 4750 4150 +Wire Wire Line + 4750 4150 4750 4100 +Wire Wire Line + 2500 4300 4400 4300 +Wire Wire Line + 4400 4300 4400 4000 +Wire Wire Line + 4400 4000 4750 4000 +Wire Wire Line + 4600 4150 4600 5650 +Wire Wire Line + 4600 4650 4750 4650 +Connection ~ 4600 4150 +Wire Wire Line + 4600 5200 4750 5200 +Connection ~ 4600 4650 +Wire Wire Line + 4600 5650 4750 5650 +Connection ~ 4600 5200 +Wire Wire Line + 3200 4300 3200 4700 +Wire Wire Line + 3200 4700 3400 4700 +Connection ~ 3200 4300 +Wire Wire Line + 4000 4700 4350 4700 +Wire Wire Line + 4350 4700 4350 5750 +Wire Wire Line + 4350 4750 4750 4750 +Wire Wire Line + 4350 5300 4750 5300 +Connection ~ 4350 4750 +Wire Wire Line + 4350 5750 4750 5750 +Connection ~ 4350 5300 +Wire Wire Line + 2500 4700 3050 4700 +Wire Wire Line + 3050 4700 3050 5150 +Wire Wire Line + 3050 5150 3450 5150 +Wire Wire Line + 3050 4900 4150 4900 +Wire Wire Line + 4150 4900 4150 4550 +Wire Wire Line + 4150 4550 4750 4550 +Connection ~ 3050 4900 +Wire Wire Line + 4050 5150 4450 5150 +Wire Wire Line + 4450 5150 4450 5850 +Wire Wire Line + 4450 5400 4750 5400 +Wire Wire Line + 4450 5850 4750 5850 +Connection ~ 4450 5400 +Wire Wire Line + 2500 5100 2500 5450 +Wire Wire Line + 2500 5450 3400 5450 +Wire Wire Line + 3400 5450 3400 5600 +Wire Wire Line + 3250 5450 3250 5250 +Wire Wire Line + 3250 5250 4200 5250 +Wire Wire Line + 4200 5250 4200 5100 +Wire Wire Line + 4200 5100 4750 5100 +Connection ~ 3250 5450 +Wire Wire Line + 4000 5600 4250 5600 +Wire Wire Line + 4250 5600 4250 5950 +Wire Wire Line + 4250 5950 4750 5950 +$Comp +L PORT U1 +U 1 1 68220E85 +P 1500 5650 +F 0 "U1" H 1550 5750 30 0000 C CNN +F 1 "PORT" H 1500 5650 30 0000 C CNN +F 2 "" H 1500 5650 60 0000 C CNN +F 3 "" H 1500 5650 60 0000 C CNN + 1 1500 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 682210FC +P 1500 5100 +F 0 "U1" H 1550 5200 30 0000 C CNN +F 1 "PORT" H 1500 5100 30 0000 C CNN +F 2 "" H 1500 5100 60 0000 C CNN +F 3 "" H 1500 5100 60 0000 C CNN + 2 1500 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 682211F6 +P 1500 4700 +F 0 "U1" H 1550 4800 30 0000 C CNN +F 1 "PORT" H 1500 4700 30 0000 C CNN +F 2 "" H 1500 4700 60 0000 C CNN +F 3 "" H 1500 4700 60 0000 C CNN + 3 1500 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68221265 +P 1500 4300 +F 0 "U1" H 1550 4400 30 0000 C CNN +F 1 "PORT" H 1500 4300 30 0000 C CNN +F 2 "" H 1500 4300 60 0000 C CNN +F 3 "" H 1500 4300 60 0000 C CNN + 4 1500 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 682213E6 +P 1500 3750 +F 0 "U1" H 1550 3850 30 0000 C CNN +F 1 "PORT" H 1500 3750 30 0000 C CNN +F 2 "" H 1500 3750 60 0000 C CNN +F 3 "" H 1500 3750 60 0000 C CNN + 5 1500 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6822145F +P 1500 2600 +F 0 "U1" H 1550 2700 30 0000 C CNN +F 1 "PORT" H 1500 2600 30 0000 C CNN +F 2 "" H 1500 2600 60 0000 C CNN +F 3 "" H 1500 2600 60 0000 C CNN + 6 1500 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68222182 +P 1500 2200 +F 0 "U1" H 1550 2300 30 0000 C CNN +F 1 "PORT" H 1500 2200 30 0000 C CNN +F 2 "" H 1500 2200 60 0000 C CNN +F 3 "" H 1500 2200 60 0000 C CNN + 7 1500 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68222411 +P 1500 1800 +F 0 "U1" H 1550 1900 30 0000 C CNN +F 1 "PORT" H 1500 1800 30 0000 C CNN +F 2 "" H 1500 1800 60 0000 C CNN +F 3 "" H 1500 1800 60 0000 C CNN + 8 1500 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68222581 +P 1500 1000 +F 0 "U1" H 1550 1100 30 0000 C CNN +F 1 "PORT" H 1500 1000 30 0000 C CNN +F 2 "" H 1500 1000 60 0000 C CNN +F 3 "" H 1500 1000 60 0000 C CNN + 9 1500 1000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1800 1000 1750 1000 +Wire Wire Line + 1800 1800 1750 1800 +Wire Wire Line + 1800 2200 1750 2200 +Wire Wire Line + 1800 2600 1750 2600 +Wire Wire Line + 1750 3750 1900 3750 +Wire Wire Line + 1750 4300 1900 4300 +Wire Wire Line + 1750 4700 1900 4700 +Wire Wire Line + 1750 5100 1900 5100 +$Comp +L PORT U1 +U 10 1 68224C0D +P 9300 5500 +F 0 "U1" H 9350 5600 30 0000 C CNN +F 1 "PORT" H 9300 5500 30 0000 C CNN +F 2 "" H 9300 5500 60 0000 C CNN +F 3 "" H 9300 5500 60 0000 C CNN + 10 9300 5500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68224D06 +P 9300 5100 +F 0 "U1" H 9350 5200 30 0000 C CNN +F 1 "PORT" H 9300 5100 30 0000 C CNN +F 2 "" H 9300 5100 60 0000 C CNN +F 3 "" H 9300 5100 60 0000 C CNN + 11 9300 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 68224F0B +P 9300 4700 +F 0 "U1" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 12 9300 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6822500E +P 9300 4300 +F 0 "U1" H 9350 4400 30 0000 C CNN +F 1 "PORT" H 9300 4300 30 0000 C CNN +F 2 "" H 9300 4300 60 0000 C CNN +F 3 "" H 9300 4300 60 0000 C CNN + 13 9300 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 682250D6 +P 9300 3850 +F 0 "U1" H 9350 3950 30 0000 C CNN +F 1 "PORT" H 9300 3850 30 0000 C CNN +F 2 "" H 9300 3850 60 0000 C CNN +F 3 "" H 9300 3850 60 0000 C CNN + 14 9300 3850 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5500 9050 5500 +Wire Wire Line + 8500 5100 9050 5100 +Wire Wire Line + 8500 4700 9050 4700 +Wire Wire Line + 8500 4300 9050 4300 +Wire Wire Line + 8450 3850 9050 3850 +$Comp +L PORT U1 +U 15 1 68225CA3 +P 9300 2700 +F 0 "U1" H 9350 2800 30 0000 C CNN +F 1 "PORT" H 9300 2700 30 0000 C CNN +F 2 "" H 9300 2700 60 0000 C CNN +F 3 "" H 9300 2700 60 0000 C CNN + 15 9300 2700 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 2700 9050 2700 +$Comp +L PORT U1 +U 16 1 68225FD7 +P 9300 2050 +F 0 "U1" H 9350 2150 30 0000 C CNN +F 1 "PORT" H 9300 2050 30 0000 C CNN +F 2 "" H 9300 2050 60 0000 C CNN +F 3 "" H 9300 2050 60 0000 C CNN + 16 9300 2050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 2050 9050 2050 +$Comp +L PORT U1 +U 17 1 68226BC9 +P 9300 1350 +F 0 "U1" H 9350 1450 30 0000 C CNN +F 1 "PORT" H 9300 1350 30 0000 C CNN +F 2 "" H 9300 1350 60 0000 C CNN +F 3 "" H 9300 1350 60 0000 C CNN + 17 9300 1350 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 1350 9050 1350 +$Comp +L PORT U1 +U 18 1 68226F4F +P 9300 900 +F 0 "U1" H 9350 1000 30 0000 C CNN +F 1 "PORT" H 9300 900 30 0000 C CNN +F 2 "" H 9300 900 60 0000 C CNN +F 3 "" H 9300 900 60 0000 C CNN + 18 9300 900 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 950 9050 950 +Wire Wire Line + 9050 950 9050 900 +Wire Wire Line + 1750 5650 1900 5650 +Wire Wire Line + 5650 4050 6800 4050 +Wire Wire Line + 6800 4050 6800 4200 +Wire Wire Line + 5600 4650 6800 4650 +Wire Wire Line + 6800 4650 6800 4600 +Wire Wire Line + 5650 5250 5650 5000 +Wire Wire Line + 5650 5000 6800 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74HC149/74149.sub b/library/SubcircuitLibrary/HD74HC149/74149.sub new file mode 100644 index 00000000..8de8694c --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.sub @@ -0,0 +1,142 @@ +* Subcircuit 74149 +.subckt 74149 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\fossee\esim\library\subcircuitlibrary\74149\74149.cir +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad9_ net-_u14-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u4 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u5 net-_u1-pad6_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad4_ net-_u16-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u19-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u17-pad1_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u18-pad2_ d_inverter +* u20 net-_u18-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u24 net-_u14-pad1_ net-_u20-pad2_ net-_u1-pad18_ d_nand +* u25 net-_u21-pad3_ net-_u20-pad2_ net-_u1-pad17_ d_nand +x1 net-_u12-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u26-pad1_ 3_and +x2 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u27-pad1_ 4_and +x3 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u23-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u20-pad2_ net-_u1-pad16_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u20-pad2_ net-_u1-pad15_ d_nand +x7 net-_u15-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u29-pad1_ 3_and +* u29 net-_u29-pad1_ net-_u1-pad14_ d_inverter +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +x4 net-_u19-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_x4-pad4_ 3_and +x5 net-_u17-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_x10-pad1_ 4_and +x6 net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u17-pad2_ net-_u23-pad2_ 4_and +x8 net-_u22-pad3_ net-_u23-pad1_ net-_u20-pad2_ net-_u30-pad1_ 3_and +x9 net-_x4-pad4_ net-_u23-pad1_ net-_u20-pad2_ net-_u31-pad1_ 3_and +x10 net-_x10-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u32-pad1_ 3_and +* u28 net-_u23-pad3_ net-_u20-pad2_ net-_u1-pad10_ d_nand +* u30 net-_u30-pad1_ net-_u1-pad13_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad12_ d_inverter +* u32 net-_u32-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nand +a1 net-_u1-pad9_ net-_u14-pad1_ u2 +a2 net-_u1-pad8_ net-_u11-pad1_ u3 +a3 net-_u1-pad7_ net-_u12-pad1_ u4 +a4 net-_u1-pad6_ net-_u13-pad1_ u5 +a5 net-_u1-pad5_ net-_u15-pad1_ u6 +a6 net-_u1-pad4_ net-_u16-pad1_ u7 +a7 net-_u1-pad3_ net-_u19-pad1_ u8 +a8 net-_u1-pad2_ net-_u17-pad1_ u9 +a9 net-_u1-pad1_ net-_u10-pad2_ u10 +a10 net-_u14-pad1_ net-_u14-pad2_ u14 +a11 net-_u11-pad1_ net-_u11-pad2_ u11 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u19-pad1_ net-_u19-pad2_ u19 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u10-pad2_ net-_u18-pad2_ u18 +a18 net-_u18-pad2_ net-_u20-pad2_ u20 +a19 [net-_u11-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a20 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u1-pad18_ u24 +a21 [net-_u21-pad3_ net-_u20-pad2_ ] net-_u1-pad17_ u25 +a22 [net-_u26-pad1_ net-_u20-pad2_ ] net-_u1-pad16_ u26 +a23 net-_u12-pad1_ net-_u12-pad2_ u12 +a24 [net-_u27-pad1_ net-_u20-pad2_ ] net-_u1-pad15_ u27 +a25 net-_u29-pad1_ net-_u1-pad14_ u29 +a26 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a27 [net-_u23-pad3_ net-_u20-pad2_ ] net-_u1-pad10_ u28 +a28 net-_u30-pad1_ net-_u1-pad13_ u30 +a29 net-_u31-pad1_ net-_u1-pad12_ u31 +a30 net-_u32-pad1_ net-_u1-pad11_ u32 +a31 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74149
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml b/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml new file mode 100644 index 00000000..1279b07e --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u16><u19 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u19><u17 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u12 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u12><u27 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u27><u29 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u22 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u22><u28 name="type">d_nand<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u30 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u32><u23 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC149/analysis b/library/SubcircuitLibrary/HD74HC149/analysis new file mode 100644 index 00000000..5c9b0b46 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS139/74139-cache.lib b/library/SubcircuitLibrary/HD74LS139/74139-cache.lib new file mode 100644 index 00000000..ca3dbb87 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74LS139/74139.cir b/library/SubcircuitLibrary/HD74LS139/74139.cir new file mode 100644 index 00000000..4df10d23 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139.cir @@ -0,0 +1,37 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74139\74139.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/21/25 11:14:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U13-Pad1_ 3_and +U13 Net-_U13-Pad1_ Net-_U1-Pad7_ d_inverter +X6 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U14-Pad1_ 3_and +U14 Net-_U14-Pad1_ Net-_U1-Pad8_ d_inverter +X7 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U18-Pad1_ 3_and +U18 Net-_U18-Pad1_ Net-_U1-Pad9_ d_inverter +X8 Net-_U2-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U15-Pad1_ 3_and +U15 Net-_U15-Pad1_ Net-_U1-Pad10_ d_inverter +X1 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U7-Pad2_ Net-_U19-Pad1_ 3_and +U19 Net-_U19-Pad1_ Net-_U1-Pad11_ d_inverter +X2 Net-_U7-Pad2_ Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad1_ 3_and +U16 Net-_U16-Pad1_ Net-_U1-Pad12_ d_inverter +X3 Net-_U7-Pad2_ Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad1_ 3_and +U17 Net-_U17-Pad1_ Net-_U1-Pad13_ d_inverter +X4 Net-_U7-Pad2_ Net-_U11-Pad2_ Net-_U10-Pad2_ Net-_U12-Pad1_ 3_and +U12 Net-_U12-Pad1_ Net-_U1-Pad14_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U6 Net-_U4-Pad2_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad4_ Net-_U7-Pad2_ d_inverter +U9 Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U8 Net-_U1-Pad6_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/HD74LS139/74139.cir.out b/library/SubcircuitLibrary/HD74LS139/74139.cir.out new file mode 100644 index 00000000..21304303 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139.cir.out @@ -0,0 +1,93 @@ +* c:\fossee\esim\library\subcircuitlibrary\74139\74139.cir + +.include 3_and.sub +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +* u13 net-_u13-pad1_ net-_u1-pad7_ d_inverter +x6 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u14-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u1-pad8_ d_inverter +x7 net-_u2-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u18-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u1-pad9_ d_inverter +x8 net-_u2-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u15-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u1-pad10_ d_inverter +x1 net-_u11-pad1_ net-_u10-pad1_ net-_u7-pad2_ net-_u19-pad1_ 3_and +* u19 net-_u19-pad1_ net-_u1-pad11_ d_inverter +x2 net-_u7-pad2_ net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u1-pad12_ d_inverter +x3 net-_u7-pad2_ net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad1_ 3_and +* u17 net-_u17-pad1_ net-_u1-pad13_ d_inverter +x4 net-_u7-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u1-pad14_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad4_ net-_u7-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u1-pad6_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +a1 net-_u13-pad1_ net-_u1-pad7_ u13 +a2 net-_u14-pad1_ net-_u1-pad8_ u14 +a3 net-_u18-pad1_ net-_u1-pad9_ u18 +a4 net-_u15-pad1_ net-_u1-pad10_ u15 +a5 net-_u19-pad1_ net-_u1-pad11_ u19 +a6 net-_u16-pad1_ net-_u1-pad12_ u16 +a7 net-_u17-pad1_ net-_u1-pad13_ u17 +a8 net-_u12-pad1_ net-_u1-pad14_ u12 +a9 net-_u1-pad1_ net-_u2-pad2_ u2 +a10 net-_u1-pad2_ net-_u3-pad2_ u3 +a11 net-_u3-pad2_ net-_u5-pad2_ u5 +a12 net-_u1-pad3_ net-_u4-pad2_ u4 +a13 net-_u4-pad2_ net-_u6-pad2_ u6 +a14 net-_u1-pad4_ net-_u7-pad2_ u7 +a15 net-_u1-pad5_ net-_u11-pad1_ u9 +a16 net-_u11-pad1_ net-_u11-pad2_ u11 +a17 net-_u1-pad6_ net-_u10-pad1_ u8 +a18 net-_u10-pad1_ net-_u10-pad2_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74LS139/74139.pro b/library/SubcircuitLibrary/HD74LS139/74139.pro new file mode 100644 index 00000000..82579415 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139.pro @@ -0,0 +1,83 @@ +update=05/06/25 21:01:46 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/HD74LS139/74139.sch b/library/SubcircuitLibrary/HD74LS139/74139.sch new file mode 100644 index 00000000..ac975979 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139.sch @@ -0,0 +1,675 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74139-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X5 +U 1 1 6805C3A6 +P 8650 1300 +F 0 "X5" H 8750 1250 60 0000 C CNN +F 1 "3_and" H 8800 1450 60 0000 C CNN +F 2 "" H 8650 1300 60 0000 C CNN +F 3 "" H 8650 1300 60 0000 C CNN + 1 8650 1300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 6805C41F +P 9600 1250 +F 0 "U13" H 9600 1150 60 0000 C CNN +F 1 "d_inverter" H 9600 1400 60 0000 C CNN +F 2 "" H 9650 1200 60 0000 C CNN +F 3 "" H 9650 1200 60 0000 C CNN + 1 9600 1250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6805C440 +P 8650 1900 +F 0 "X6" H 8750 1850 60 0000 C CNN +F 1 "3_and" H 8800 2050 60 0000 C CNN +F 2 "" H 8650 1900 60 0000 C CNN +F 3 "" H 8650 1900 60 0000 C CNN + 1 8650 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6805C46B +P 9600 1850 +F 0 "U14" H 9600 1750 60 0000 C CNN +F 1 "d_inverter" H 9600 2000 60 0000 C CNN +F 2 "" H 9650 1800 60 0000 C CNN +F 3 "" H 9650 1800 60 0000 C CNN + 1 9600 1850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 6805C48A +P 8650 2500 +F 0 "X7" H 8750 2450 60 0000 C CNN +F 1 "3_and" H 8800 2650 60 0000 C CNN +F 2 "" H 8650 2500 60 0000 C CNN +F 3 "" H 8650 2500 60 0000 C CNN + 1 8650 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6805C4B7 +P 9650 2450 +F 0 "U18" H 9650 2350 60 0000 C CNN +F 1 "d_inverter" H 9650 2600 60 0000 C CNN +F 2 "" H 9700 2400 60 0000 C CNN +F 3 "" H 9700 2400 60 0000 C CNN + 1 9650 2450 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 6805C4DC +P 8650 3050 +F 0 "X8" H 8750 3000 60 0000 C CNN +F 1 "3_and" H 8800 3200 60 0000 C CNN +F 2 "" H 8650 3050 60 0000 C CNN +F 3 "" H 8650 3050 60 0000 C CNN + 1 8650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6805C513 +P 9600 3000 +F 0 "U15" H 9600 2900 60 0000 C CNN +F 1 "d_inverter" H 9600 3150 60 0000 C CNN +F 2 "" H 9650 2950 60 0000 C CNN +F 3 "" H 9650 2950 60 0000 C CNN + 1 9600 3000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6805C538 +P 8600 3950 +F 0 "X1" H 8700 3900 60 0000 C CNN +F 1 "3_and" H 8750 4100 60 0000 C CNN +F 2 "" H 8600 3950 60 0000 C CNN +F 3 "" H 8600 3950 60 0000 C CNN + 1 8600 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6805C573 +P 9650 3900 +F 0 "U19" H 9650 3800 60 0000 C CNN +F 1 "d_inverter" H 9650 4050 60 0000 C CNN +F 2 "" H 9700 3850 60 0000 C CNN +F 3 "" H 9700 3850 60 0000 C CNN + 1 9650 3900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6805C5A4 +P 8600 4450 +F 0 "X2" H 8700 4400 60 0000 C CNN +F 1 "3_and" H 8750 4600 60 0000 C CNN +F 2 "" H 8600 4450 60 0000 C CNN +F 3 "" H 8600 4450 60 0000 C CNN + 1 8600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6805C5D3 +P 9600 4400 +F 0 "U16" H 9600 4300 60 0000 C CNN +F 1 "d_inverter" H 9600 4550 60 0000 C CNN +F 2 "" H 9650 4350 60 0000 C CNN +F 3 "" H 9650 4350 60 0000 C CNN + 1 9600 4400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 6805C604 +P 8600 5000 +F 0 "X3" H 8700 4950 60 0000 C CNN +F 1 "3_and" H 8750 5150 60 0000 C CNN +F 2 "" H 8600 5000 60 0000 C CNN +F 3 "" H 8600 5000 60 0000 C CNN + 1 8600 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6805C63F +P 9600 4950 +F 0 "U17" H 9600 4850 60 0000 C CNN +F 1 "d_inverter" H 9600 5100 60 0000 C CNN +F 2 "" H 9650 4900 60 0000 C CNN +F 3 "" H 9650 4900 60 0000 C CNN + 1 9600 4950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 6805C876 +P 8600 5450 +F 0 "X4" H 8700 5400 60 0000 C CNN +F 1 "3_and" H 8750 5600 60 0000 C CNN +F 2 "" H 8600 5450 60 0000 C CNN +F 3 "" H 8600 5450 60 0000 C CNN + 1 8600 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6805C8AB +P 9550 5400 +F 0 "U12" H 9550 5300 60 0000 C CNN +F 1 "d_inverter" H 9550 5550 60 0000 C CNN +F 2 "" H 9600 5350 60 0000 C CNN +F 3 "" H 9600 5350 60 0000 C CNN + 1 9550 5400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 2050 3000 2050 +Wire Wire Line + 3000 2050 3000 2100 +Wire Wire Line + 7000 1150 7000 1750 +Wire Wire Line + 7000 1750 8300 1750 +Wire Wire Line + 3800 750 3800 2100 +Wire Wire Line + 3800 750 8250 750 +Wire Wire Line + 8250 750 8250 1150 +Wire Wire Line + 8250 1150 8300 1150 +Connection ~ 3800 2100 +Wire Wire Line + 4100 900 4100 2550 +Wire Wire Line + 4100 900 8150 900 +Wire Wire Line + 8150 900 8150 1250 +Wire Wire Line + 8150 1250 8300 1250 +Connection ~ 4100 2550 +Wire Wire Line + 6550 1950 6550 3000 +Wire Wire Line + 6550 3000 8300 3000 +Wire Wire Line + 6550 1950 8300 1950 +Connection ~ 6550 2100 +Wire Wire Line + 6400 2550 6400 3100 +Wire Wire Line + 6400 3100 8300 3100 +Wire Wire Line + 6750 3100 6750 2550 +Wire Wire Line + 6750 2550 8300 2550 +Connection ~ 6750 3100 +Wire Wire Line + 7650 2900 8300 2900 +Wire Wire Line + 7650 1350 7650 2900 +Wire Wire Line + 7650 1350 8300 1350 +Wire Wire Line + 8300 2350 7650 2350 +Connection ~ 7650 2350 +Wire Wire Line + 4100 1350 6200 1350 +Wire Wire Line + 6200 1350 6200 1850 +Wire Wire Line + 6200 1850 8300 1850 +Connection ~ 4100 1350 +Wire Wire Line + 3800 1900 6150 1900 +Wire Wire Line + 6150 1900 6150 2450 +Wire Wire Line + 6150 2450 8300 2450 +Connection ~ 3800 1900 +Wire Wire Line + 9150 1250 9300 1250 +Wire Wire Line + 9900 1250 10300 1250 +Wire Wire Line + 9150 1850 9300 1850 +Wire Wire Line + 9900 1850 10300 1850 +Wire Wire Line + 9150 2450 9350 2450 +Wire Wire Line + 9950 2450 10300 2450 +Wire Wire Line + 9150 3000 9300 3000 +Wire Wire Line + 9900 3000 10300 3000 +Wire Wire Line + 9100 3900 9350 3900 +Wire Wire Line + 9950 3900 10300 3900 +Wire Wire Line + 9100 4400 9300 4400 +Wire Wire Line + 9900 4400 10300 4400 +Wire Wire Line + 10300 4400 10300 4350 +Wire Wire Line + 9100 4950 9300 4950 +Wire Wire Line + 9900 4950 10300 4950 +Wire Wire Line + 9100 5400 9250 5400 +Wire Wire Line + 9850 5400 10300 5400 +Wire Wire Line + 8250 4200 8250 4300 +Wire Wire Line + 3800 3800 3800 5000 +Wire Wire Line + 3800 3800 8250 3800 +Connection ~ 3800 5000 +Wire Wire Line + 4300 3900 4300 5450 +Wire Wire Line + 4300 3900 8250 3900 +Connection ~ 4300 5450 +Wire Wire Line + 4300 4400 8250 4400 +Connection ~ 4300 4400 +Wire Wire Line + 3800 4800 7800 4800 +Wire Wire Line + 7800 4800 7800 4950 +Wire Wire Line + 7800 4950 8250 4950 +Connection ~ 3800 4800 +Wire Wire Line + 7800 5050 7800 5500 +Wire Wire Line + 7800 5500 8250 5500 +Wire Wire Line + 7800 5050 8250 5050 +Connection ~ 7800 5450 +Wire Wire Line + 7050 4500 8250 4500 +Wire Wire Line + 7050 5400 8250 5400 +Connection ~ 7050 5000 +Wire Wire Line + 8250 4000 7550 4000 +Wire Wire Line + 7550 4000 7550 5300 +Wire Wire Line + 7550 5300 8250 5300 +Wire Wire Line + 8250 4850 8250 4650 +Wire Wire Line + 8250 4650 7550 4650 +Connection ~ 7550 4650 +$Comp +L PORT U1 +U 1 1 6805D472 +P 1350 1150 +F 0 "U1" H 1400 1250 30 0000 C CNN +F 1 "PORT" H 1350 1150 30 0000 C CNN +F 2 "" H 1350 1150 60 0000 C CNN +F 3 "" H 1350 1150 60 0000 C CNN + 1 1350 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6805D4C5 +P 2250 2050 +F 0 "U1" H 2300 2150 30 0000 C CNN +F 1 "PORT" H 2250 2050 30 0000 C CNN +F 2 "" H 2250 2050 60 0000 C CNN +F 3 "" H 2250 2050 60 0000 C CNN + 2 2250 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6805D51C +P 2250 2550 +F 0 "U1" H 2300 2650 30 0000 C CNN +F 1 "PORT" H 2250 2550 30 0000 C CNN +F 2 "" H 2250 2550 60 0000 C CNN +F 3 "" H 2250 2550 60 0000 C CNN + 3 2250 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6805D640 +P 1450 4200 +F 0 "U1" H 1500 4300 30 0000 C CNN +F 1 "PORT" H 1450 4200 30 0000 C CNN +F 2 "" H 1450 4200 60 0000 C CNN +F 3 "" H 1450 4200 60 0000 C CNN + 4 1450 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6805D69B +P 2350 5000 +F 0 "U1" H 2400 5100 30 0000 C CNN +F 1 "PORT" H 2350 5000 30 0000 C CNN +F 2 "" H 2350 5000 60 0000 C CNN +F 3 "" H 2350 5000 60 0000 C CNN + 5 2350 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6805D7CD +P 2350 5450 +F 0 "U1" H 2400 5550 30 0000 C CNN +F 1 "PORT" H 2350 5450 30 0000 C CNN +F 2 "" H 2350 5450 60 0000 C CNN +F 3 "" H 2350 5450 60 0000 C CNN + 6 2350 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6805D9F0 +P 10550 1250 +F 0 "U1" H 10600 1350 30 0000 C CNN +F 1 "PORT" H 10550 1250 30 0000 C CNN +F 2 "" H 10550 1250 60 0000 C CNN +F 3 "" H 10550 1250 60 0000 C CNN + 7 10550 1250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6805DA57 +P 10550 1850 +F 0 "U1" H 10600 1950 30 0000 C CNN +F 1 "PORT" H 10550 1850 30 0000 C CNN +F 2 "" H 10550 1850 60 0000 C CNN +F 3 "" H 10550 1850 60 0000 C CNN + 8 10550 1850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6805DABE +P 10550 2450 +F 0 "U1" H 10600 2550 30 0000 C CNN +F 1 "PORT" H 10550 2450 30 0000 C CNN +F 2 "" H 10550 2450 60 0000 C CNN +F 3 "" H 10550 2450 60 0000 C CNN + 9 10550 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6805DC41 +P 10550 3000 +F 0 "U1" H 10600 3100 30 0000 C CNN +F 1 "PORT" H 10550 3000 30 0000 C CNN +F 2 "" H 10550 3000 60 0000 C CNN +F 3 "" H 10550 3000 60 0000 C CNN + 10 10550 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6805DCB2 +P 10550 3900 +F 0 "U1" H 10600 4000 30 0000 C CNN +F 1 "PORT" H 10550 3900 30 0000 C CNN +F 2 "" H 10550 3900 60 0000 C CNN +F 3 "" H 10550 3900 60 0000 C CNN + 11 10550 3900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6805DD1D +P 10550 4350 +F 0 "U1" H 10600 4450 30 0000 C CNN +F 1 "PORT" H 10550 4350 30 0000 C CNN +F 2 "" H 10550 4350 60 0000 C CNN +F 3 "" H 10550 4350 60 0000 C CNN + 12 10550 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6805DD94 +P 10550 4950 +F 0 "U1" H 10600 5050 30 0000 C CNN +F 1 "PORT" H 10550 4950 30 0000 C CNN +F 2 "" H 10550 4950 60 0000 C CNN +F 3 "" H 10550 4950 60 0000 C CNN + 13 10550 4950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6805DF1C +P 10550 5400 +F 0 "U1" H 10600 5500 30 0000 C CNN +F 1 "PORT" H 10550 5400 30 0000 C CNN +F 2 "" H 10550 5400 60 0000 C CNN +F 3 "" H 10550 5400 60 0000 C CNN + 14 10550 5400 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6805F0D7 +P 2600 1150 +F 0 "U2" H 2600 1050 60 0000 C CNN +F 1 "d_inverter" H 2600 1300 60 0000 C CNN +F 2 "" H 2650 1100 60 0000 C CNN +F 3 "" H 2650 1100 60 0000 C CNN + 1 2600 1150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 1150 2300 1150 +Wire Wire Line + 2900 1150 7000 1150 +$Comp +L d_inverter U3 +U 1 1 6805F313 +P 3300 2100 +F 0 "U3" H 3300 2000 60 0000 C CNN +F 1 "d_inverter" H 3300 2250 60 0000 C CNN +F 2 "" H 3350 2050 60 0000 C CNN +F 3 "" H 3350 2050 60 0000 C CNN + 1 3300 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6805F378 +P 4750 2100 +F 0 "U5" H 4750 2000 60 0000 C CNN +F 1 "d_inverter" H 4750 2250 60 0000 C CNN +F 2 "" H 4800 2050 60 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4750 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2100 4450 2100 +Wire Wire Line + 5050 2100 6550 2100 +$Comp +L d_inverter U4 +U 1 1 6805F4EB +P 3350 2550 +F 0 "U4" H 3350 2450 60 0000 C CNN +F 1 "d_inverter" H 3350 2700 60 0000 C CNN +F 2 "" H 3400 2500 60 0000 C CNN +F 3 "" H 3400 2500 60 0000 C CNN + 1 3350 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6805F546 +P 4750 2550 +F 0 "U6" H 4750 2450 60 0000 C CNN +F 1 "d_inverter" H 4750 2700 60 0000 C CNN +F 2 "" H 4800 2500 60 0000 C CNN +F 3 "" H 4800 2500 60 0000 C CNN + 1 4750 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 2550 3050 2550 +Wire Wire Line + 3650 2550 4450 2550 +Wire Wire Line + 5050 2550 6400 2550 +$Comp +L d_inverter U7 +U 1 1 6805F904 +P 2450 4200 +F 0 "U7" H 2450 4100 60 0000 C CNN +F 1 "d_inverter" H 2450 4350 60 0000 C CNN +F 2 "" H 2500 4150 60 0000 C CNN +F 3 "" H 2500 4150 60 0000 C CNN + 1 2450 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 4200 2150 4200 +Wire Wire Line + 2750 4200 8250 4200 +$Comp +L d_inverter U9 +U 1 1 6805FB1C +P 3250 5000 +F 0 "U9" H 3250 4900 60 0000 C CNN +F 1 "d_inverter" H 3250 5150 60 0000 C CNN +F 2 "" H 3300 4950 60 0000 C CNN +F 3 "" H 3300 4950 60 0000 C CNN + 1 3250 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6805FB7B +P 4900 5000 +F 0 "U11" H 4900 4900 60 0000 C CNN +F 1 "d_inverter" H 4900 5150 60 0000 C CNN +F 2 "" H 4950 4950 60 0000 C CNN +F 3 "" H 4950 4950 60 0000 C CNN + 1 4900 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6805FC04 +P 3200 5450 +F 0 "U8" H 3200 5350 60 0000 C CNN +F 1 "d_inverter" H 3200 5600 60 0000 C CNN +F 2 "" H 3250 5400 60 0000 C CNN +F 3 "" H 3250 5400 60 0000 C CNN + 1 3200 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6805FC67 +P 4850 5450 +F 0 "U10" H 4850 5350 60 0000 C CNN +F 1 "d_inverter" H 4850 5600 60 0000 C CNN +F 2 "" H 4900 5400 60 0000 C CNN +F 3 "" H 4900 5400 60 0000 C CNN + 1 4850 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 5000 2950 5000 +Wire Wire Line + 2600 5450 2900 5450 +Wire Wire Line + 3550 5000 4600 5000 +Wire Wire Line + 3500 5450 4550 5450 +Wire Wire Line + 7050 5000 5200 5000 +Wire Wire Line + 7050 4500 7050 5400 +Wire Wire Line + 5150 5450 7800 5450 +Connection ~ 7550 4200 +Connection ~ 7650 1750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74LS139/74139.sub b/library/SubcircuitLibrary/HD74LS139/74139.sub new file mode 100644 index 00000000..f044a755 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139.sub @@ -0,0 +1,87 @@ +* Subcircuit 74139 +.subckt 74139 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74139\74139.cir +.include 3_and.sub +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +* u13 net-_u13-pad1_ net-_u1-pad7_ d_inverter +x6 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u14-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u1-pad8_ d_inverter +x7 net-_u2-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u18-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u1-pad9_ d_inverter +x8 net-_u2-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u15-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u1-pad10_ d_inverter +x1 net-_u11-pad1_ net-_u10-pad1_ net-_u7-pad2_ net-_u19-pad1_ 3_and +* u19 net-_u19-pad1_ net-_u1-pad11_ d_inverter +x2 net-_u7-pad2_ net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u1-pad12_ d_inverter +x3 net-_u7-pad2_ net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad1_ 3_and +* u17 net-_u17-pad1_ net-_u1-pad13_ d_inverter +x4 net-_u7-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad4_ net-_u7-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u1-pad6_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +a1 net-_u13-pad1_ net-_u1-pad7_ u13 +a2 net-_u14-pad1_ net-_u1-pad8_ u14 +a3 net-_u18-pad1_ net-_u1-pad9_ u18 +a4 net-_u15-pad1_ net-_u1-pad10_ u15 +a5 net-_u19-pad1_ net-_u1-pad11_ u19 +a6 net-_u16-pad1_ net-_u1-pad12_ u16 +a7 net-_u17-pad1_ net-_u1-pad13_ u17 +a8 net-_u12-pad1_ net-_u1-pad14_ u12 +a9 net-_u1-pad1_ net-_u2-pad2_ u2 +a10 net-_u1-pad2_ net-_u3-pad2_ u3 +a11 net-_u3-pad2_ net-_u5-pad2_ u5 +a12 net-_u1-pad3_ net-_u4-pad2_ u4 +a13 net-_u4-pad2_ net-_u6-pad2_ u6 +a14 net-_u1-pad4_ net-_u7-pad2_ u7 +a15 net-_u1-pad5_ net-_u11-pad1_ u9 +a16 net-_u11-pad1_ net-_u11-pad2_ u11 +a17 net-_u1-pad6_ net-_u10-pad1_ u8 +a18 net-_u10-pad1_ net-_u10-pad2_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74139
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml new file mode 100644 index 00000000..7328b6f2 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u13 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u18><u15 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u19 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u19><u16 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u12 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u12><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u11><u2 name="type">d_buffer<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_buffer<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS139/analysis b/library/SubcircuitLibrary/HD74LS139/analysis new file mode 100644 index 00000000..2e3711be --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS139/analysis @@ -0,0 +1 @@ +.tran 10e-03 13e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib b/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib new file mode 100644 index 00000000..f840f078 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 7421 +# +DEF 7421 X 0 40 Y Y 1 F N +F0 "X" 0 250 60 H V C CNN +F1 "7421" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 150 400 -650 0 1 0 N +X IN1 1 -750 50 200 R 50 50 1 1 I +X IN2 2 -750 -100 200 R 50 50 1 1 I +X IN3 3 -750 -250 200 R 50 50 1 1 I +X IN4 4 -750 -400 200 R 50 50 1 1 I +X OUT1 5 -750 -550 200 R 50 50 1 1 O +X IN1 6 600 50 200 L 50 50 1 1 I +X IN2 7 600 -100 200 L 50 50 1 1 I +X IN3 8 600 -250 200 L 50 50 1 1 I +X IN4 9 600 -400 200 L 50 50 1 1 I +X OUT2 10 600 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CD4077 +# +DEF CD4077 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "CD4077" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 -150 450 -1050 0 1 0 N +X IN1 1 -550 -250 200 R 50 50 1 1 I +X IN2 2 -550 -350 200 R 50 50 1 1 I +X IN1 3 -550 -450 200 R 50 50 1 1 I +X IN2 4 -550 -550 200 R 50 50 1 1 I +X IN1 5 -550 -650 200 R 50 50 1 1 I +X IN2 6 -550 -750 200 R 50 50 1 1 I +X IN1 7 -550 -850 200 R 50 50 1 1 I +X IN2 8 -550 -950 200 R 50 50 1 1 I +X OUT1 9 650 -250 200 L 50 50 1 1 O +X OUT2 10 650 -500 200 L 50 50 1 1 O +X OUT3 11 650 -700 200 L 50 50 1 1 O +X OUT4 12 650 -900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.cir b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir new file mode 100644 index 00000000..1f23492e --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir @@ -0,0 +1,31 @@ +* C:\Users\pt710\eSim-Workspace\74520N\74520N.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/25 12:10:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X1-Pad9_ Net-_X1-Pad10_ Net-_X1-Pad11_ Net-_X1-Pad12_ CD4077 +X2 Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_X2-Pad9_ Net-_X2-Pad10_ Net-_X2-Pad11_ Net-_X2-Pad12_ CD4077 +X3 Net-_X1-Pad9_ Net-_X1-Pad10_ Net-_X1-Pad11_ Net-_X1-Pad12_ Net-_U3-Pad1_ Net-_X2-Pad12_ Net-_X2-Pad11_ Net-_X2-Pad10_ Net-_X2-Pad9_ Net-_U3-Pad2_ 7421 +U1 Net-_U1-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad5_ Net-_U1-Pad5_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ adc_bridge_8 +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +R1 out GND 10k +U5 out plot_v1 +v1 Net-_U1-Pad1_ GND DC +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_and +v2 Net-_U1-Pad3_ GND DC +v3 Net-_U1-Pad5_ GND DC +v4 Net-_U1-Pad8_ GND DC +v5 Net-_U2-Pad1_ GND DC +v6 Net-_U2-Pad2_ GND DC +v7 Net-_U2-Pad3_ GND DC +v8 Net-_U2-Pad4_ GND DC +v9 Net-_U2-Pad5_ GND DC +v10 Net-_U2-Pad6_ GND DC +v11 Net-_U2-Pad7_ GND DC +v12 Net-_U2-Pad8_ GND DC +U4 Net-_U3-Pad3_ out dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out new file mode 100644 index 00000000..00c8acc3 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out @@ -0,0 +1,47 @@ +* c:\users\pt710\esim-workspace\74520n\74520n.cir + +.include 7421.sub +.include CD4077.sub +x1 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ CD4077 +x2 net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_x2-pad9_ net-_x2-pad10_ net-_x2-pad11_ net-_x2-pad12_ CD4077 +x3 net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ net-_u3-pad1_ net-_x2-pad12_ net-_x2-pad11_ net-_x2-pad10_ net-_x2-pad9_ net-_u3-pad2_ 7421 +* u1 net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ adc_bridge_8 +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +r1 out gnd 10k +* u5 out plot_v1 +v1 net-_u1-pad1_ gnd dc 5 +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and +v2 net-_u1-pad3_ gnd dc 5 +v3 net-_u1-pad5_ gnd dc 5 +v4 net-_u1-pad8_ gnd dc 5 +v5 net-_u2-pad1_ gnd dc 5 +v6 net-_u2-pad2_ gnd dc 5 +v7 net-_u2-pad3_ gnd dc 5 +v8 net-_u2-pad4_ gnd dc 5 +v9 net-_u2-pad5_ gnd dc 5 +v10 net-_u2-pad6_ gnd dc 5 +v11 net-_u2-pad7_ gnd dc 5 +v12 net-_u2-pad8_ gnd dc 5 +* u4 net-_u3-pad3_ out dac_bridge_1 +a1 [net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ ] [out ] u4 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-06 10e-03 1e-06 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out) +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.pro b/library/SubcircuitLibrary/SN74ALS520N/74520N.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.proj b/library/SubcircuitLibrary/SN74ALS520N/74520N.proj new file mode 100644 index 00000000..8a55fd63 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.proj @@ -0,0 +1 @@ +schematicFile 74520N.sch diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.sch b/library/SubcircuitLibrary/SN74ALS520N/74520N.sch new file mode 100644 index 00000000..2dff2365 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.sch @@ -0,0 +1,629 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CD4077 X1 +U 1 1 67DCFD03 +P 4900 1350 +F 0 "X1" H 4900 1350 60 0000 C CNN +F 1 "CD4077" H 4900 1450 60 0000 C CNN +F 2 "" H 4900 1350 60 0001 C CNN +F 3 "" H 4900 1350 60 0001 C CNN + 1 4900 1350 + 1 0 0 -1 +$EndComp +$Comp +L CD4077 X2 +U 1 1 67DCFE03 +P 4900 2550 +F 0 "X2" H 4900 2550 60 0000 C CNN +F 1 "CD4077" H 4900 2650 60 0000 C CNN +F 2 "" H 4900 2550 60 0001 C CNN +F 3 "" H 4900 2550 60 0001 C CNN + 1 4900 2550 + 1 0 0 -1 +$EndComp +$Comp +L 7421 X3 +U 1 1 67DCFE8E +P 7150 1700 +F 0 "X3" H 7150 1950 60 0000 C CNN +F 1 "7421" H 7150 2050 60 0000 C CNN +F 2 "" H 7150 1700 60 0001 C CNN +F 3 "" H 7150 1700 60 0001 C CNN + 1 7150 1700 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U1 +U 1 1 67DCFF30 +P 3250 1650 +F 0 "U1" H 3250 1650 60 0000 C CNN +F 1 "adc_bridge_8" H 3250 1800 60 0000 C CNN +F 2 "" H 3250 1650 60 0000 C CNN +F 3 "" H 3250 1650 60 0000 C CNN + 1 3250 1650 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U2 +U 1 1 67DCFF9B +P 3250 2850 +F 0 "U2" H 3250 2850 60 0000 C CNN +F 1 "adc_bridge_8" H 3250 3000 60 0000 C CNN +F 2 "" H 3250 2850 60 0000 C CNN +F 3 "" H 3250 2850 60 0000 C CNN + 1 3250 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 1600 4350 1600 +Wire Wire Line + 3800 1700 4350 1700 +Wire Wire Line + 3800 1800 4350 1800 +Wire Wire Line + 3800 1900 4350 1900 +Wire Wire Line + 3800 2000 4350 2000 +Wire Wire Line + 3800 2100 4350 2100 +Wire Wire Line + 3800 2200 4350 2200 +Wire Wire Line + 3800 2300 4350 2300 +Wire Wire Line + 5550 1600 6400 1600 +Wire Wire Line + 6400 1600 6400 1650 +Wire Wire Line + 5550 1850 6400 1850 +Wire Wire Line + 6400 1850 6400 1800 +Wire Wire Line + 5550 2050 6400 2050 +Wire Wire Line + 6400 2050 6400 1950 +Wire Wire Line + 5550 2250 6200 2250 +Wire Wire Line + 6200 2250 6200 2100 +Wire Wire Line + 6200 2100 6400 2100 +Wire Wire Line + 3800 2800 4350 2800 +Wire Wire Line + 3800 2900 4350 2900 +Wire Wire Line + 3800 3000 4350 3000 +Wire Wire Line + 3800 3100 4350 3100 +Wire Wire Line + 3800 3200 4350 3200 +Wire Wire Line + 3800 3300 4350 3300 +Wire Wire Line + 3800 3400 4350 3400 +Wire Wire Line + 3800 3500 4350 3500 +Wire Wire Line + 5550 2800 8200 2800 +Wire Wire Line + 8200 2800 8200 2100 +Wire Wire Line + 8200 2100 7750 2100 +Wire Wire Line + 5550 3050 8400 3050 +Wire Wire Line + 8400 3050 8400 1950 +Wire Wire Line + 8400 1950 7750 1950 +Wire Wire Line + 5550 3250 8650 3250 +Wire Wire Line + 8650 3250 8650 1800 +Wire Wire Line + 8650 1800 7750 1800 +Wire Wire Line + 5550 3450 8900 3450 +Wire Wire Line + 8900 3450 8900 1650 +Wire Wire Line + 8900 1650 7750 1650 +Wire Wire Line + 6400 2250 6400 4350 +Wire Wire Line + 6400 4350 6650 4350 +Wire Wire Line + 7750 2250 7750 4050 +Wire Wire Line + 7750 4050 5750 4050 +Wire Wire Line + 5750 4050 5750 4450 +Wire Wire Line + 5750 4450 6650 4450 +$Comp +L GND #PWR01 +U 1 1 67DD0482 +P 10250 4350 +F 0 "#PWR01" H 10250 4100 50 0001 C CNN +F 1 "GND" H 10250 4200 50 0000 C CNN +F 2 "" H 10250 4350 50 0001 C CNN +F 3 "" H 10250 4350 50 0001 C CNN + 1 10250 4350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67DD04C2 +P 9450 4400 +F 0 "R1" H 9500 4530 50 0000 C CNN +F 1 "10k" H 9500 4350 50 0000 C CNN +F 2 "" H 9500 4380 30 0000 C CNN +F 3 "" V 9500 4450 30 0000 C CNN + 1 9450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8650 4400 9350 4400 +Wire Wire Line + 9350 4400 9350 4350 +Wire Wire Line + 9650 4350 10250 4350 +$Comp +L plot_v1 U5 +U 1 1 67DD05F6 +P 8950 4600 +F 0 "U5" H 8950 5100 60 0000 C CNN +F 1 "plot_v1" H 9150 4950 60 0000 C CNN +F 2 "" H 8950 4600 60 0000 C CNN +F 3 "" H 8950 4600 60 0000 C CNN + 1 8950 4600 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 67DD074A +P 1850 1600 +F 0 "v1" H 1650 1700 60 0000 C CNN +F 1 "DC" H 1700 1450 60 0000 C CNN +F 2 "R1" H 1850 1600 60 0000 C CNN +F 3 "" H 1850 1600 60 0000 C CNN + 1 1850 1600 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 67DD07A8 +P 7100 4450 +F 0 "U3" H 7100 4450 60 0000 C CNN +F 1 "d_and" H 7150 4550 60 0000 C CNN +F 2 "" H 7100 4450 60 0000 C CNN +F 3 "" H 7100 4450 60 0000 C CNN + 1 7100 4450 + 1 0 0 -1 +$EndComp +Text GLabel 8950 4400 0 60 Input ~ 0 +out +$Comp +L DC v2 +U 1 1 67DD0928 +P 1850 1900 +F 0 "v2" H 1700 2050 60 0000 C CNN +F 1 "DC" H 1700 1750 60 0000 C CNN +F 2 "R1" H 1850 1900 60 0000 C CNN +F 3 "" H 1850 1900 60 0000 C CNN + 1 1850 1900 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 67DD0975 +P 1850 2200 +F 0 "v3" H 1700 2350 60 0000 C CNN +F 1 "DC" H 1750 2050 60 0000 C CNN +F 2 "R1" H 1850 2200 60 0000 C CNN +F 3 "" H 1850 2200 60 0000 C CNN + 1 1850 2200 + 0 1 1 0 +$EndComp +$Comp +L DC v4 +U 1 1 67DD0B88 +P 1850 2500 +F 0 "v4" H 1750 2700 60 0000 C CNN +F 1 "DC" H 1700 2350 60 0000 C CNN +F 2 "R1" H 1550 2500 60 0000 C CNN +F 3 "" H 1850 2500 60 0000 C CNN + 1 1850 2500 + 0 1 1 0 +$EndComp +$Comp +L DC v5 +U 1 1 67DD0C23 +P 1850 2800 +F 0 "v5" H 1700 2950 60 0000 C CNN +F 1 "DC" H 1700 2650 60 0000 C CNN +F 2 "R1" H 1550 2800 60 0000 C CNN +F 3 "" H 1850 2800 60 0000 C CNN + 1 1850 2800 + 0 1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 67DD0E6E +P 1850 3100 +F 0 "v6" H 1700 3250 60 0000 C CNN +F 1 "DC" H 1700 2950 60 0000 C CNN +F 2 "R1" H 1550 3100 60 0000 C CNN +F 3 "" H 1850 3100 60 0000 C CNN + 1 1850 3100 + 0 1 1 0 +$EndComp +$Comp +L DC v7 +U 1 1 67DD1147 +P 1850 3400 +F 0 "v7" H 1700 3550 60 0000 C CNN +F 1 "DC" H 1700 3250 60 0000 C CNN +F 2 "R1" H 1550 3400 60 0000 C CNN +F 3 "" H 1850 3400 60 0000 C CNN + 1 1850 3400 + 0 1 1 0 +$EndComp +$Comp +L DC v8 +U 1 1 67DD142C +P 1850 3700 +F 0 "v8" H 1700 3850 60 0000 C CNN +F 1 "DC" H 1700 3550 60 0000 C CNN +F 2 "R1" H 1550 3700 60 0000 C CNN +F 3 "" H 1850 3700 60 0000 C CNN + 1 1850 3700 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 67DD16E5 +P 1000 1600 +F 0 "#PWR02" H 1000 1350 50 0001 C CNN +F 1 "GND" H 1000 1450 50 0000 C CNN +F 2 "" H 1000 1600 50 0001 C CNN +F 3 "" H 1000 1600 50 0001 C CNN + 1 1000 1600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 67DD1719 +P 1000 1900 +F 0 "#PWR03" H 1000 1650 50 0001 C CNN +F 1 "GND" H 1000 1750 50 0000 C CNN +F 2 "" H 1000 1900 50 0001 C CNN +F 3 "" H 1000 1900 50 0001 C CNN + 1 1000 1900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 67DD174D +P 1000 2200 +F 0 "#PWR04" H 1000 1950 50 0001 C CNN +F 1 "GND" H 1000 2050 50 0000 C CNN +F 2 "" H 1000 2200 50 0001 C CNN +F 3 "" H 1000 2200 50 0001 C CNN + 1 1000 2200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 67DD1781 +P 1000 2500 +F 0 "#PWR05" H 1000 2250 50 0001 C CNN +F 1 "GND" H 1000 2350 50 0000 C CNN +F 2 "" H 1000 2500 50 0001 C CNN +F 3 "" H 1000 2500 50 0001 C CNN + 1 1000 2500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 67DD17B5 +P 1000 2800 +F 0 "#PWR06" H 1000 2550 50 0001 C CNN +F 1 "GND" H 1000 2650 50 0000 C CNN +F 2 "" H 1000 2800 50 0001 C CNN +F 3 "" H 1000 2800 50 0001 C CNN + 1 1000 2800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 67DD17E9 +P 1000 3100 +F 0 "#PWR07" H 1000 2850 50 0001 C CNN +F 1 "GND" H 1000 2950 50 0000 C CNN +F 2 "" H 1000 3100 50 0001 C CNN +F 3 "" H 1000 3100 50 0001 C CNN + 1 1000 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 67DD190D +P 1000 3400 +F 0 "#PWR08" H 1000 3150 50 0001 C CNN +F 1 "GND" H 1000 3250 50 0000 C CNN +F 2 "" H 1000 3400 50 0001 C CNN +F 3 "" H 1000 3400 50 0001 C CNN + 1 1000 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 67DD1941 +P 1000 3700 +F 0 "#PWR09" H 1000 3450 50 0001 C CNN +F 1 "GND" H 1000 3550 50 0000 C CNN +F 2 "" H 1000 3700 50 0001 C CNN +F 3 "" H 1000 3700 50 0001 C CNN + 1 1000 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1000 1600 1400 1600 +Wire Wire Line + 2300 1600 2650 1600 +Wire Wire Line + 2300 1700 2650 1700 +Wire Wire Line + 2250 1900 2500 1900 +Wire Wire Line + 2500 1900 2500 1800 +Wire Wire Line + 2500 1800 2650 1800 +Wire Wire Line + 2300 2200 2650 2200 +Wire Wire Line + 2300 2500 2300 2300 +Wire Wire Line + 2300 2300 2650 2300 +Wire Wire Line + 1000 1900 1400 1900 +Wire Wire Line + 1000 2200 1400 2200 +Wire Wire Line + 1000 2500 1400 2500 +Wire Wire Line + 2250 1950 2650 1950 +Wire Wire Line + 2650 2000 2400 2000 +Wire Wire Line + 2650 1950 2650 1900 +Wire Wire Line + 2550 2050 2650 2050 +Wire Wire Line + 2650 2050 2650 2100 +Wire Wire Line + 1000 2800 1400 2800 +Wire Wire Line + 1000 3100 1400 3100 +Wire Wire Line + 1000 3400 1400 3400 +Wire Wire Line + 1400 3700 1000 3700 +Wire Wire Line + 2300 2800 2650 2800 +Wire Wire Line + 2300 3100 2300 2900 +Wire Wire Line + 2300 2900 2650 2900 +Wire Wire Line + 2300 3400 2350 3400 +Wire Wire Line + 2350 3400 2350 3000 +Wire Wire Line + 2350 3000 2650 3000 +Wire Wire Line + 2300 3700 2400 3700 +Wire Wire Line + 2400 3700 2400 3100 +Wire Wire Line + 2400 3100 2650 3100 +$Comp +L DC v9 +U 1 1 67DD2460 +P 1850 4000 +F 0 "v9" H 1700 4150 60 0000 C CNN +F 1 "DC" H 1700 3850 60 0000 C CNN +F 2 "R1" H 1550 4000 60 0000 C CNN +F 3 "" H 1850 4000 60 0000 C CNN + 1 1850 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v10 +U 1 1 67DD24B5 +P 1850 4300 +F 0 "v10" H 1700 4450 60 0000 C CNN +F 1 "DC" H 1700 4150 60 0000 C CNN +F 2 "R1" H 1550 4300 60 0000 C CNN +F 3 "" H 1850 4300 60 0000 C CNN + 1 1850 4300 + 0 1 1 0 +$EndComp +$Comp +L DC v11 +U 1 1 67DD258A +P 1850 4600 +F 0 "v11" H 1700 4750 60 0000 C CNN +F 1 "DC" H 1700 4450 60 0000 C CNN +F 2 "R1" H 1550 4600 60 0000 C CNN +F 3 "" H 1850 4600 60 0000 C CNN + 1 1850 4600 + 0 1 1 0 +$EndComp +$Comp +L DC v12 +U 1 1 67DD25CD +P 1850 4900 +F 0 "v12" H 1700 5050 60 0000 C CNN +F 1 "DC" H 1700 4750 60 0000 C CNN +F 2 "R1" H 1550 4900 60 0000 C CNN +F 3 "" H 1850 4900 60 0000 C CNN + 1 1850 4900 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR013 +U 1 1 67DD261A +P 1000 4000 +F 0 "#PWR013" H 1000 3750 50 0001 C CNN +F 1 "GND" H 1000 3850 50 0000 C CNN +F 2 "" H 1000 4000 50 0001 C CNN +F 3 "" H 1000 4000 50 0001 C CNN + 1 1000 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR014 +U 1 1 67DD2656 +P 1000 4300 +F 0 "#PWR014" H 1000 4050 50 0001 C CNN +F 1 "GND" H 1000 4150 50 0000 C CNN +F 2 "" H 1000 4300 50 0001 C CNN +F 3 "" H 1000 4300 50 0001 C CNN + 1 1000 4300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR015 +U 1 1 67DD2692 +P 1000 4600 +F 0 "#PWR015" H 1000 4350 50 0001 C CNN +F 1 "GND" H 1000 4450 50 0000 C CNN +F 2 "" H 1000 4600 50 0001 C CNN +F 3 "" H 1000 4600 50 0001 C CNN + 1 1000 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR016 +U 1 1 67DD26CE +P 1000 4900 +F 0 "#PWR016" H 1000 4650 50 0001 C CNN +F 1 "GND" H 1000 4750 50 0000 C CNN +F 2 "" H 1000 4900 50 0001 C CNN +F 3 "" H 1000 4900 50 0001 C CNN + 1 1000 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1000 4000 1400 4000 +Wire Wire Line + 1000 4300 1400 4300 +Wire Wire Line + 1000 4600 1400 4600 +Wire Wire Line + 1000 4900 1400 4900 +Wire Wire Line + 2300 4000 2450 4000 +Wire Wire Line + 2450 4000 2450 3200 +Wire Wire Line + 2450 3200 2650 3200 +Wire Wire Line + 2300 4300 2500 4300 +Wire Wire Line + 2500 4300 2500 3300 +Wire Wire Line + 2500 3300 2650 3300 +Wire Wire Line + 2300 4600 2550 4600 +Wire Wire Line + 2550 4600 2550 3400 +Wire Wire Line + 2550 3400 2650 3400 +Wire Wire Line + 2300 4900 2650 4900 +Wire Wire Line + 2650 4900 2650 3500 +$Comp +L dac_bridge_1 U4 +U 1 1 67DD3EDA +P 8100 4450 +F 0 "U4" H 8100 4450 60 0000 C CNN +F 1 "dac_bridge_1" H 8100 4600 60 0000 C CNN +F 2 "" H 8100 4450 60 0000 C CNN +F 3 "" H 8100 4450 60 0000 C CNN + 1 8100 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 4400 7550 4400 +Wire Wire Line + 2550 2050 2550 2200 +Connection ~ 2550 2200 +Wire Wire Line + 2300 1700 2300 1600 +Wire Wire Line + 2250 1950 2250 1900 +Connection ~ 2300 1900 +Wire Wire Line + 2400 2000 2400 2200 +Wire Wire Line + 2400 2200 2350 2200 +Connection ~ 2350 2200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml new file mode 100644 index 00000000..052d2364 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">5</field1></v8><v9 name="Source type">dc<field1 name="Value">5</field1></v9><v10 name="Source type">dc<field1 name="Value">5</field1></v10><v11 name="Source type">dc<field1 name="Value">5</field1></v11><v12 name="Source type">dc<field1 name="Value">5</field1></v12></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u2 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">dac_bridge<field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter value for out_undef (default=0.5)" /><field15 name="Enter value for input load (default=1.0e-12)" /><field16 name="Enter the Rise Time (default=1.0e-9)" /><field17 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4077</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4077</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\7421</field></x3></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">us</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS520N/analysis b/library/SubcircuitLibrary/SN74ALS520N/analysis new file mode 100644 index 00000000..79194fd6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/analysis @@ -0,0 +1 @@ +.tran 1e-06 10e-03 1e-06
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74HC688/74688-cache.lib b/library/SubcircuitLibrary/SN74HC688/74688-cache.lib new file mode 100644 index 00000000..a488b30b --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688-cache.lib @@ -0,0 +1,132 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74HC688/74688.cir b/library/SubcircuitLibrary/SN74HC688/74688.cir new file mode 100644 index 00000000..6e028afb --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74688\74688.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/21/25 17:00:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_xnor +U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U4-Pad3_ d_xnor +U5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U5-Pad3_ d_xnor +U6 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U6-Pad3_ d_xnor +U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U7-Pad3_ d_xnor +U8 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U8-Pad3_ d_xnor +U9 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U11-Pad1_ d_xnor +U10 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U10-Pad3_ d_xnor +X1 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_X1-Pad4_ 3_and +X2 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_X2-Pad4_ 3_and +U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U11-Pad3_ d_and +X3 Net-_U2-Pad2_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U11-Pad3_ Net-_U12-Pad1_ 4_and +U12 Net-_U12-Pad1_ Net-_U1-Pad18_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74HC688/74688.cir.out b/library/SubcircuitLibrary/SN74HC688/74688.cir.out new file mode 100644 index 00000000..c4cde047 --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688.cir.out @@ -0,0 +1,61 @@ +* c:\fossee\esim\library\subcircuitlibrary\74688\74688.cir + +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u5-pad3_ d_xnor +* u6 net-_u1-pad8_ net-_u1-pad9_ net-_u6-pad3_ d_xnor +* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u7-pad3_ d_xnor +* u8 net-_u1-pad12_ net-_u1-pad13_ net-_u8-pad3_ d_xnor +* u9 net-_u1-pad14_ net-_u1-pad15_ net-_u11-pad1_ d_xnor +* u10 net-_u1-pad16_ net-_u1-pad17_ net-_u10-pad3_ d_xnor +x1 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ net-_x1-pad4_ 3_and +x2 net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_x2-pad4_ 3_and +* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_and +x3 net-_u2-pad2_ net-_x1-pad4_ net-_x2-pad4_ net-_u11-pad3_ net-_u12-pad1_ 4_and +* u12 net-_u12-pad1_ net-_u1-pad18_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u5-pad3_ u5 +a5 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u6-pad3_ u6 +a6 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u7-pad3_ u7 +a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u8-pad3_ u8 +a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u11-pad1_ u9 +a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11 +a11 net-_u12-pad1_ net-_u1-pad18_ u12 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74HC688/74688.pro b/library/SubcircuitLibrary/SN74HC688/74688.pro new file mode 100644 index 00000000..b72f7f2d --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688.pro @@ -0,0 +1,83 @@ +update=05/06/25 21:03:17 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74HC688/74688.sch b/library/SubcircuitLibrary/SN74HC688/74688.sch new file mode 100644 index 00000000..380c98cf --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688.sch @@ -0,0 +1,514 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 680629D0 +P 3700 1200 +F 0 "U2" H 3700 1100 60 0000 C CNN +F 1 "d_inverter" H 3700 1350 60 0000 C CNN +F 2 "" H 3750 1150 60 0000 C CNN +F 3 "" H 3750 1150 60 0000 C CNN + 1 3700 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U3 +U 1 1 680629FD +P 3850 1800 +F 0 "U3" H 3850 1800 60 0000 C CNN +F 1 "d_xnor" H 3900 1900 47 0000 C CNN +F 2 "" H 3850 1800 60 0000 C CNN +F 3 "" H 3850 1800 60 0000 C CNN + 1 3850 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U4 +U 1 1 68062A24 +P 3850 2250 +F 0 "U4" H 3850 2250 60 0000 C CNN +F 1 "d_xnor" H 3900 2350 47 0000 C CNN +F 2 "" H 3850 2250 60 0000 C CNN +F 3 "" H 3850 2250 60 0000 C CNN + 1 3850 2250 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U5 +U 1 1 68062A49 +P 3850 2700 +F 0 "U5" H 3850 2700 60 0000 C CNN +F 1 "d_xnor" H 3900 2800 47 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U6 +U 1 1 68062A80 +P 3850 3150 +F 0 "U6" H 3850 3150 60 0000 C CNN +F 1 "d_xnor" H 3900 3250 47 0000 C CNN +F 2 "" H 3850 3150 60 0000 C CNN +F 3 "" H 3850 3150 60 0000 C CNN + 1 3850 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U7 +U 1 1 68062AAF +P 3850 3600 +F 0 "U7" H 3850 3600 60 0000 C CNN +F 1 "d_xnor" H 3900 3700 47 0000 C CNN +F 2 "" H 3850 3600 60 0000 C CNN +F 3 "" H 3850 3600 60 0000 C CNN + 1 3850 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U8 +U 1 1 68062AD4 +P 3850 4050 +F 0 "U8" H 3850 4050 60 0000 C CNN +F 1 "d_xnor" H 3900 4150 47 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U9 +U 1 1 68062AFF +P 3850 4500 +F 0 "U9" H 3850 4500 60 0000 C CNN +F 1 "d_xnor" H 3900 4600 47 0000 C CNN +F 2 "" H 3850 4500 60 0000 C CNN +F 3 "" H 3850 4500 60 0000 C CNN + 1 3850 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U10 +U 1 1 68062B2E +P 3850 4950 +F 0 "U10" H 3850 4950 60 0000 C CNN +F 1 "d_xnor" H 3900 5050 47 0000 C CNN +F 2 "" H 3850 4950 60 0000 C CNN +F 3 "" H 3850 4950 60 0000 C CNN + 1 3850 4950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 68062B5D +P 5850 2300 +F 0 "X1" H 5950 2250 60 0000 C CNN +F 1 "3_and" H 6000 2450 60 0000 C CNN +F 2 "" H 5850 2300 60 0000 C CNN +F 3 "" H 5850 2300 60 0000 C CNN + 1 5850 2300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68062B8E +P 5850 3450 +F 0 "X2" H 5950 3400 60 0000 C CNN +F 1 "3_and" H 6000 3600 60 0000 C CNN +F 2 "" H 5850 3450 60 0000 C CNN +F 3 "" H 5850 3450 60 0000 C CNN + 1 5850 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 68062BC5 +P 6000 4750 +F 0 "U11" H 6000 4750 60 0000 C CNN +F 1 "d_and" H 6050 4850 60 0000 C CNN +F 2 "" H 6000 4750 60 0000 C CNN +F 3 "" H 6000 4750 60 0000 C CNN + 1 6000 4750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 68062C02 +P 7750 3400 +F 0 "X3" H 7800 3350 60 0000 C CNN +F 1 "4_and" H 7850 3500 60 0000 C CNN +F 2 "" H 7750 3400 60 0000 C CNN +F 3 "" H 7750 3400 60 0000 C CNN + 1 7750 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68062C3D +P 8700 3400 +F 0 "U12" H 8700 3300 60 0000 C CNN +F 1 "d_inverter" H 8700 3550 60 0000 C CNN +F 2 "" H 8750 3350 60 0000 C CNN +F 3 "" H 8750 3350 60 0000 C CNN + 1 8700 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68062C78 +P 2800 1200 +F 0 "U1" H 2850 1300 30 0000 C CNN +F 1 "PORT" H 2800 1200 30 0000 C CNN +F 2 "" H 2800 1200 60 0000 C CNN +F 3 "" H 2800 1200 60 0000 C CNN + 1 2800 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68062CEB +P 2800 1700 +F 0 "U1" H 2850 1800 30 0000 C CNN +F 1 "PORT" H 2800 1700 30 0000 C CNN +F 2 "" H 2800 1700 60 0000 C CNN +F 3 "" H 2800 1700 60 0000 C CNN + 2 2800 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68062D2E +P 2800 1900 +F 0 "U1" H 2850 2000 30 0000 C CNN +F 1 "PORT" H 2800 1900 30 0000 C CNN +F 2 "" H 2800 1900 60 0000 C CNN +F 3 "" H 2800 1900 60 0000 C CNN + 3 2800 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68062D69 +P 2800 2150 +F 0 "U1" H 2850 2250 30 0000 C CNN +F 1 "PORT" H 2800 2150 30 0000 C CNN +F 2 "" H 2800 2150 60 0000 C CNN +F 3 "" H 2800 2150 60 0000 C CNN + 4 2800 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68062DAA +P 2800 2350 +F 0 "U1" H 2850 2450 30 0000 C CNN +F 1 "PORT" H 2800 2350 30 0000 C CNN +F 2 "" H 2800 2350 60 0000 C CNN +F 3 "" H 2800 2350 60 0000 C CNN + 5 2800 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68062EAD +P 2800 2600 +F 0 "U1" H 2850 2700 30 0000 C CNN +F 1 "PORT" H 2800 2600 30 0000 C CNN +F 2 "" H 2800 2600 60 0000 C CNN +F 3 "" H 2800 2600 60 0000 C CNN + 6 2800 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68062EEE +P 2800 2800 +F 0 "U1" H 2850 2900 30 0000 C CNN +F 1 "PORT" H 2800 2800 30 0000 C CNN +F 2 "" H 2800 2800 60 0000 C CNN +F 3 "" H 2800 2800 60 0000 C CNN + 7 2800 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68062F35 +P 2800 3050 +F 0 "U1" H 2850 3150 30 0000 C CNN +F 1 "PORT" H 2800 3050 30 0000 C CNN +F 2 "" H 2800 3050 60 0000 C CNN +F 3 "" H 2800 3050 60 0000 C CNN + 8 2800 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68062F84 +P 2800 3250 +F 0 "U1" H 2850 3350 30 0000 C CNN +F 1 "PORT" H 2800 3250 30 0000 C CNN +F 2 "" H 2800 3250 60 0000 C CNN +F 3 "" H 2800 3250 60 0000 C CNN + 9 2800 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68062FD3 +P 2800 3500 +F 0 "U1" H 2850 3600 30 0000 C CNN +F 1 "PORT" H 2800 3500 30 0000 C CNN +F 2 "" H 2800 3500 60 0000 C CNN +F 3 "" H 2800 3500 60 0000 C CNN + 10 2800 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6806301E +P 2800 3700 +F 0 "U1" H 2850 3800 30 0000 C CNN +F 1 "PORT" H 2800 3700 30 0000 C CNN +F 2 "" H 2800 3700 60 0000 C CNN +F 3 "" H 2800 3700 60 0000 C CNN + 11 2800 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6806306D +P 2800 3950 +F 0 "U1" H 2850 4050 30 0000 C CNN +F 1 "PORT" H 2800 3950 30 0000 C CNN +F 2 "" H 2800 3950 60 0000 C CNN +F 3 "" H 2800 3950 60 0000 C CNN + 12 2800 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 680630BA +P 2800 4150 +F 0 "U1" H 2850 4250 30 0000 C CNN +F 1 "PORT" H 2800 4150 30 0000 C CNN +F 2 "" H 2800 4150 60 0000 C CNN +F 3 "" H 2800 4150 60 0000 C CNN + 13 2800 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68063113 +P 2800 4400 +F 0 "U1" H 2850 4500 30 0000 C CNN +F 1 "PORT" H 2800 4400 30 0000 C CNN +F 2 "" H 2800 4400 60 0000 C CNN +F 3 "" H 2800 4400 60 0000 C CNN + 14 2800 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6806316E +P 2800 4600 +F 0 "U1" H 2850 4700 30 0000 C CNN +F 1 "PORT" H 2800 4600 30 0000 C CNN +F 2 "" H 2800 4600 60 0000 C CNN +F 3 "" H 2800 4600 60 0000 C CNN + 15 2800 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 680631C1 +P 2800 4850 +F 0 "U1" H 2850 4950 30 0000 C CNN +F 1 "PORT" H 2800 4850 30 0000 C CNN +F 2 "" H 2800 4850 60 0000 C CNN +F 3 "" H 2800 4850 60 0000 C CNN + 16 2800 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 68063218 +P 2800 5050 +F 0 "U1" H 2850 5150 30 0000 C CNN +F 1 "PORT" H 2800 5050 30 0000 C CNN +F 2 "" H 2800 5050 60 0000 C CNN +F 3 "" H 2800 5050 60 0000 C CNN + 17 2800 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 6806334C +P 9550 3400 +F 0 "U1" H 9600 3500 30 0000 C CNN +F 1 "PORT" H 9550 3400 30 0000 C CNN +F 2 "" H 9550 3400 60 0000 C CNN +F 3 "" H 9550 3400 60 0000 C CNN + 18 9550 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 3050 1200 3400 1200 +Wire Wire Line + 3050 1700 3400 1700 +Wire Wire Line + 3050 1900 3400 1900 +Wire Wire Line + 3400 1900 3400 1800 +Wire Wire Line + 3050 2150 3400 2150 +Wire Wire Line + 3050 2350 3400 2350 +Wire Wire Line + 3400 2350 3400 2250 +Wire Wire Line + 3050 2600 3400 2600 +Wire Wire Line + 3050 2800 3400 2800 +Wire Wire Line + 3400 2800 3400 2700 +Wire Wire Line + 3050 3050 3400 3050 +Wire Wire Line + 3050 3250 3400 3250 +Wire Wire Line + 3400 3250 3400 3150 +Wire Wire Line + 3050 3500 3400 3500 +Wire Wire Line + 3050 3700 3400 3700 +Wire Wire Line + 3400 3700 3400 3600 +Wire Wire Line + 3050 3950 3400 3950 +Wire Wire Line + 3050 4150 3400 4150 +Wire Wire Line + 3400 4150 3400 4050 +Wire Wire Line + 3050 4400 3400 4400 +Wire Wire Line + 3050 4600 3400 4600 +Wire Wire Line + 3400 4600 3400 4500 +Wire Wire Line + 3050 4850 3400 4850 +Wire Wire Line + 3050 5050 3400 5050 +Wire Wire Line + 3400 5050 3400 4950 +Wire Wire Line + 4300 4450 5550 4450 +Wire Wire Line + 5550 4450 5550 4650 +Wire Wire Line + 4300 4900 5550 4900 +Wire Wire Line + 5550 4900 5550 4750 +Wire Wire Line + 6450 4700 7350 4700 +Wire Wire Line + 7350 4700 7350 3550 +Wire Wire Line + 4300 3100 5500 3100 +Wire Wire Line + 5500 3100 5500 3300 +Wire Wire Line + 4300 3550 5050 3550 +Wire Wire Line + 5050 3550 5050 3400 +Wire Wire Line + 5050 3400 5500 3400 +Wire Wire Line + 4300 4000 5500 4000 +Wire Wire Line + 5500 4000 5500 3500 +Wire Wire Line + 6350 3400 7350 3400 +Wire Wire Line + 7350 3400 7350 3450 +Wire Wire Line + 4000 1200 7350 1200 +Wire Wire Line + 7350 1200 7350 3250 +Wire Wire Line + 4300 1750 5500 1750 +Wire Wire Line + 5500 1750 5500 2150 +Wire Wire Line + 4300 2200 5500 2200 +Wire Wire Line + 5500 2200 5500 2250 +Wire Wire Line + 4300 2650 5500 2650 +Wire Wire Line + 5500 2650 5500 2350 +Wire Wire Line + 6350 2250 7150 2250 +Wire Wire Line + 7150 2250 7150 3350 +Wire Wire Line + 7150 3350 7350 3350 +Wire Wire Line + 8250 3400 8400 3400 +Wire Wire Line + 9000 3400 9300 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74HC688/74688.sub b/library/SubcircuitLibrary/SN74HC688/74688.sub new file mode 100644 index 00000000..d68463db --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688.sub @@ -0,0 +1,55 @@ +* Subcircuit 74688 +.subckt 74688 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\fossee\esim\library\subcircuitlibrary\74688\74688.cir +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u5-pad3_ d_xnor +* u6 net-_u1-pad8_ net-_u1-pad9_ net-_u6-pad3_ d_xnor +* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u7-pad3_ d_xnor +* u8 net-_u1-pad12_ net-_u1-pad13_ net-_u8-pad3_ d_xnor +* u9 net-_u1-pad14_ net-_u1-pad15_ net-_u11-pad1_ d_xnor +* u10 net-_u1-pad16_ net-_u1-pad17_ net-_u10-pad3_ d_xnor +x1 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ net-_x1-pad4_ 3_and +x2 net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_x2-pad4_ 3_and +* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_and +x3 net-_u2-pad2_ net-_x1-pad4_ net-_x2-pad4_ net-_u11-pad3_ net-_u12-pad1_ 4_and +* u12 net-_u12-pad1_ net-_u1-pad18_ d_inverter +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u5-pad3_ u5 +a5 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u6-pad3_ u6 +a6 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u7-pad3_ u7 +a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u8-pad3_ u8 +a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u11-pad1_ u9 +a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11 +a11 net-_u12-pad1_ net-_u1-pad18_ u12 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74688
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml new file mode 100644 index 00000000..b87a5652 --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_xnor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_xnor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_xnor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74HC688/analysis b/library/SubcircuitLibrary/SN74HC688/analysis new file mode 100644 index 00000000..b7cf1aee --- /dev/null +++ b/library/SubcircuitLibrary/SN74HC688/analysis @@ -0,0 +1 @@ +.tran 10e-03 4e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148/74148-cache.lib b/library/SubcircuitLibrary/SN74LS148/74148-cache.lib new file mode 100644 index 00000000..3f72f50a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148-cache.lib @@ -0,0 +1,168 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148/74148.cir b/library/SubcircuitLibrary/SN74LS148/74148.cir new file mode 100644 index 00000000..85cd484a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.cir @@ -0,0 +1,55 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74148\74148.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/19/25 14:31:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U17 Net-_U10-Pad3_ Net-_U10-Pad3_ Net-_U17-Pad3_ d_nor +U18 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U18-Pad3_ d_nor +U25 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U1-Pad12_ d_nor +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor +U19 Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_nor +U20 Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U20-Pad3_ d_nor +U26 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U1-Pad13_ d_nor +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U21 Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U21-Pad3_ d_nor +U22 Net-_U15-Pad3_ Net-_U15-Pad3_ Net-_U22-Pad3_ d_nor +U27 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U1-Pad14_ d_nor +U24 Net-_U1-Pad10_ Net-_U24-Pad2_ Net-_U1-Pad11_ d_nand +X7 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U16-Pad1_ 5_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U23 Net-_U16-Pad3_ Net-_U1-Pad10_ d_inverter +X5 Net-_U37-Pad2_ Net-_U2-Pad2_ Net-_U30-Pad2_ Net-_U29-Pad2_ Net-_U24-Pad2_ Net-_U10-Pad1_ 5_and +X2 Net-_U32-Pad2_ Net-_U30-Pad2_ Net-_U29-Pad2_ Net-_U24-Pad2_ Net-_U10-Pad2_ 4_and +X1 Net-_U28-Pad1_ Net-_U29-Pad2_ Net-_U24-Pad2_ Net-_U11-Pad1_ 3_and +U3 Net-_U3-Pad1_ Net-_U24-Pad2_ Net-_U11-Pad2_ d_and +X3 Net-_U2-Pad1_ Net-_U30-Pad2_ Net-_U28-Pad2_ Net-_U24-Pad2_ Net-_U12-Pad1_ 4_and +X4 Net-_U32-Pad2_ Net-_U30-Pad2_ Net-_U28-Pad2_ Net-_U24-Pad2_ Net-_U12-Pad2_ 4_and +U4 Net-_U29-Pad1_ Net-_U24-Pad2_ Net-_U13-Pad1_ d_and +U5 Net-_U3-Pad1_ Net-_U24-Pad2_ Net-_U13-Pad2_ d_and +U6 Net-_U30-Pad1_ Net-_U24-Pad2_ Net-_U14-Pad1_ d_and +U7 Net-_U28-Pad1_ Net-_U24-Pad2_ Net-_U14-Pad2_ d_and +U8 Net-_U29-Pad1_ Net-_U24-Pad2_ Net-_U15-Pad1_ d_and +U9 Net-_U3-Pad1_ Net-_U24-Pad2_ Net-_U15-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ d_inverter +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +X6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U24-Pad2_ Net-_U16-Pad2_ 4_and +U37 Net-_U1-Pad2_ Net-_U37-Pad2_ d_inverter +U35 Net-_U1-Pad3_ Net-_U2-Pad1_ d_inverter +U32 Net-_U1-Pad4_ Net-_U32-Pad2_ d_inverter +U31 Net-_U1-Pad5_ Net-_U30-Pad1_ d_inverter +U34 Net-_U1-Pad6_ Net-_U28-Pad1_ d_inverter +U36 Net-_U1-Pad7_ Net-_U29-Pad1_ d_inverter +U33 Net-_U1-Pad8_ Net-_U3-Pad1_ d_inverter +U38 Net-_U1-Pad9_ Net-_U24-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74LS148/74148.cir.out b/library/SubcircuitLibrary/SN74LS148/74148.cir.out new file mode 100644 index 00000000..c72b8440 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.cir.out @@ -0,0 +1,170 @@ +* c:\fossee\esim\library\subcircuitlibrary\74148\74148.cir + +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u17 net-_u10-pad3_ net-_u10-pad3_ net-_u17-pad3_ d_nor +* u18 net-_u11-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor +* u25 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad12_ d_nor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor +* u19 net-_u12-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_nor +* u20 net-_u13-pad3_ net-_u13-pad3_ net-_u20-pad3_ d_nor +* u26 net-_u19-pad3_ net-_u20-pad3_ net-_u1-pad13_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u21 net-_u14-pad3_ net-_u14-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u15-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor +* u27 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad14_ d_nor +* u24 net-_u1-pad10_ net-_u24-pad2_ net-_u1-pad11_ d_nand +x7 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u16-pad1_ 5_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u23 net-_u16-pad3_ net-_u1-pad10_ d_inverter +x5 net-_u37-pad2_ net-_u2-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad1_ 5_and +x2 net-_u32-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad2_ 4_and +x1 net-_u28-pad1_ net-_u29-pad2_ net-_u24-pad2_ net-_u11-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u24-pad2_ net-_u11-pad2_ d_and +x3 net-_u2-pad1_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad1_ 4_and +x4 net-_u32-pad2_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad2_ 4_and +* u4 net-_u29-pad1_ net-_u24-pad2_ net-_u13-pad1_ d_and +* u5 net-_u3-pad1_ net-_u24-pad2_ net-_u13-pad2_ d_and +* u6 net-_u30-pad1_ net-_u24-pad2_ net-_u14-pad1_ d_and +* u7 net-_u28-pad1_ net-_u24-pad2_ net-_u14-pad2_ d_and +* u8 net-_u29-pad1_ net-_u24-pad2_ net-_u15-pad1_ d_and +* u9 net-_u3-pad1_ net-_u24-pad2_ net-_u15-pad2_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +x6 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u24-pad2_ net-_u16-pad2_ 4_and +* u37 net-_u1-pad2_ net-_u37-pad2_ d_inverter +* u35 net-_u1-pad3_ net-_u2-pad1_ d_inverter +* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter +* u31 net-_u1-pad5_ net-_u30-pad1_ d_inverter +* u34 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u36 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u33 net-_u1-pad8_ net-_u3-pad1_ d_inverter +* u38 net-_u1-pad9_ net-_u24-pad2_ d_inverter +a1 net-_u2-pad1_ net-_u2-pad2_ u2 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a5 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18 +a6 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad12_ u25 +a7 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a9 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u20-pad3_ u20 +a11 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u1-pad13_ u26 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u21-pad3_ u21 +a15 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 +a16 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad14_ u27 +a17 [net-_u1-pad10_ net-_u24-pad2_ ] net-_u1-pad11_ u24 +a18 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a19 net-_u16-pad3_ net-_u1-pad10_ u23 +a20 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u11-pad2_ u3 +a21 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u13-pad1_ u4 +a22 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u13-pad2_ u5 +a23 [net-_u30-pad1_ net-_u24-pad2_ ] net-_u14-pad1_ u6 +a24 [net-_u28-pad1_ net-_u24-pad2_ ] net-_u14-pad2_ u7 +a25 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u15-pad1_ u8 +a26 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u15-pad2_ u9 +a27 net-_u30-pad1_ net-_u30-pad2_ u30 +a28 net-_u28-pad1_ net-_u28-pad2_ u28 +a29 net-_u29-pad1_ net-_u29-pad2_ u29 +a30 net-_u1-pad2_ net-_u37-pad2_ u37 +a31 net-_u1-pad3_ net-_u2-pad1_ u35 +a32 net-_u1-pad4_ net-_u32-pad2_ u32 +a33 net-_u1-pad5_ net-_u30-pad1_ u31 +a34 net-_u1-pad6_ net-_u28-pad1_ u34 +a35 net-_u1-pad7_ net-_u29-pad1_ u36 +a36 net-_u1-pad8_ net-_u3-pad1_ u33 +a37 net-_u1-pad9_ net-_u24-pad2_ u38 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148/74148.pro b/library/SubcircuitLibrary/SN74LS148/74148.pro new file mode 100644 index 00000000..f2514212 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.pro @@ -0,0 +1,83 @@ +update=05/06/25 20:59:52 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74LS148/74148.sch b/library/SubcircuitLibrary/SN74LS148/74148.sch new file mode 100644 index 00000000..30059d36 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.sch @@ -0,0 +1,1070 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74148-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68034E56 +P 3900 2100 +F 0 "U2" H 3900 2000 60 0000 C CNN +F 1 "d_inverter" H 3900 2250 60 0000 C CNN +F 2 "" H 3950 2050 60 0000 C CNN +F 3 "" H 3950 2050 60 0000 C CNN + 1 3900 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 68034F56 +P 8100 2650 +F 0 "U11" H 8100 2650 60 0000 C CNN +F 1 "d_nor" H 8150 2750 60 0000 C CNN +F 2 "" H 8100 2650 60 0000 C CNN +F 3 "" H 8100 2650 60 0000 C CNN + 1 8100 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 68034FBB +P 8100 2150 +F 0 "U10" H 8100 2150 60 0000 C CNN +F 1 "d_nor" H 8150 2250 60 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 68034FE6 +P 9250 2150 +F 0 "U17" H 9250 2150 60 0000 C CNN +F 1 "d_nor" H 9300 2250 60 0000 C CNN +F 2 "" H 9250 2150 60 0000 C CNN +F 3 "" H 9250 2150 60 0000 C CNN + 1 9250 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U18 +U 1 1 6803501F +P 9250 2650 +F 0 "U18" H 9250 2650 60 0000 C CNN +F 1 "d_nor" H 9300 2750 60 0000 C CNN +F 2 "" H 9250 2650 60 0000 C CNN +F 3 "" H 9250 2650 60 0000 C CNN + 1 9250 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U25 +U 1 1 68035044 +P 10150 2350 +F 0 "U25" H 10150 2350 60 0000 C CNN +F 1 "d_nor" H 10200 2450 60 0000 C CNN +F 2 "" H 10150 2350 60 0000 C CNN +F 3 "" H 10150 2350 60 0000 C CNN + 1 10150 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U13 +U 1 1 68035274 +P 8100 4100 +F 0 "U13" H 8100 4100 60 0000 C CNN +F 1 "d_nor" H 8150 4200 60 0000 C CNN +F 2 "" H 8100 4100 60 0000 C CNN +F 3 "" H 8100 4100 60 0000 C CNN + 1 8100 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 6803527A +P 8100 3600 +F 0 "U12" H 8100 3600 60 0000 C CNN +F 1 "d_nor" H 8150 3700 60 0000 C CNN +F 2 "" H 8100 3600 60 0000 C CNN +F 3 "" H 8100 3600 60 0000 C CNN + 1 8100 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U19 +U 1 1 68035280 +P 9250 3600 +F 0 "U19" H 9250 3600 60 0000 C CNN +F 1 "d_nor" H 9300 3700 60 0000 C CNN +F 2 "" H 9250 3600 60 0000 C CNN +F 3 "" H 9250 3600 60 0000 C CNN + 1 9250 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U20 +U 1 1 68035286 +P 9250 4100 +F 0 "U20" H 9250 4100 60 0000 C CNN +F 1 "d_nor" H 9300 4200 60 0000 C CNN +F 2 "" H 9250 4100 60 0000 C CNN +F 3 "" H 9250 4100 60 0000 C CNN + 1 9250 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U26 +U 1 1 6803528C +P 10150 3800 +F 0 "U26" H 10150 3800 60 0000 C CNN +F 1 "d_nor" H 10200 3900 60 0000 C CNN +F 2 "" H 10150 3800 60 0000 C CNN +F 3 "" H 10150 3800 60 0000 C CNN + 1 10150 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 68035357 +P 8150 5700 +F 0 "U15" H 8150 5700 60 0000 C CNN +F 1 "d_nor" H 8200 5800 60 0000 C CNN +F 2 "" H 8150 5700 60 0000 C CNN +F 3 "" H 8150 5700 60 0000 C CNN + 1 8150 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 6803535D +P 8150 5200 +F 0 "U14" H 8150 5200 60 0000 C CNN +F 1 "d_nor" H 8200 5300 60 0000 C CNN +F 2 "" H 8150 5200 60 0000 C CNN +F 3 "" H 8150 5200 60 0000 C CNN + 1 8150 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U21 +U 1 1 68035363 +P 9300 5200 +F 0 "U21" H 9300 5200 60 0000 C CNN +F 1 "d_nor" H 9350 5300 60 0000 C CNN +F 2 "" H 9300 5200 60 0000 C CNN +F 3 "" H 9300 5200 60 0000 C CNN + 1 9300 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U22 +U 1 1 68035369 +P 9300 5700 +F 0 "U22" H 9300 5700 60 0000 C CNN +F 1 "d_nor" H 9350 5800 60 0000 C CNN +F 2 "" H 9300 5700 60 0000 C CNN +F 3 "" H 9300 5700 60 0000 C CNN + 1 9300 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U27 +U 1 1 6803536F +P 10200 5400 +F 0 "U27" H 10200 5400 60 0000 C CNN +F 1 "d_nor" H 10250 5500 60 0000 C CNN +F 2 "" H 10200 5400 60 0000 C CNN +F 3 "" H 10200 5400 60 0000 C CNN + 1 10200 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 68035387 +P 10100 1450 +F 0 "U24" H 10100 1450 60 0000 C CNN +F 1 "d_nand" H 10150 1550 60 0000 C CNN +F 2 "" H 10100 1450 60 0000 C CNN +F 3 "" H 10100 1450 60 0000 C CNN + 1 10100 1450 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 680353EA +P 7700 800 +F 0 "X7" H 7750 700 60 0000 C CNN +F 1 "5_and" H 7800 950 60 0000 C CNN +F 2 "" H 7700 800 60 0000 C CNN +F 3 "" H 7700 800 60 0000 C CNN + 1 7700 800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 68035472 +P 8850 1050 +F 0 "U16" H 8850 1050 60 0000 C CNN +F 1 "d_and" H 8900 1150 60 0000 C CNN +F 2 "" H 8850 1050 60 0000 C CNN +F 3 "" H 8850 1050 60 0000 C CNN + 1 8850 1050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 68035581 +P 9850 1000 +F 0 "U23" H 9850 900 60 0000 C CNN +F 1 "d_inverter" H 9850 1150 60 0000 C CNN +F 2 "" H 9900 950 60 0000 C CNN +F 3 "" H 9900 950 60 0000 C CNN + 1 9850 1000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 680355C4 +P 6650 1850 +F 0 "X5" H 6700 1750 60 0000 C CNN +F 1 "5_and" H 6750 2000 60 0000 C CNN +F 2 "" H 6650 1850 60 0000 C CNN +F 3 "" H 6650 1850 60 0000 C CNN + 1 6650 1850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 68035621 +P 6600 2400 +F 0 "X2" H 6650 2350 60 0000 C CNN +F 1 "4_and" H 6700 2500 60 0000 C CNN +F 2 "" H 6600 2400 60 0000 C CNN +F 3 "" H 6600 2400 60 0000 C CNN + 1 6600 2400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 68035670 +P 6550 2900 +F 0 "X1" H 6650 2850 60 0000 C CNN +F 1 "3_and" H 6700 3050 60 0000 C CNN +F 2 "" H 6550 2900 60 0000 C CNN +F 3 "" H 6550 2900 60 0000 C CNN + 1 6550 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 680356BF +P 6650 3250 +F 0 "U3" H 6650 3250 60 0000 C CNN +F 1 "d_and" H 6700 3350 60 0000 C CNN +F 2 "" H 6650 3250 60 0000 C CNN +F 3 "" H 6650 3250 60 0000 C CNN + 1 6650 3250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 68035718 +P 6600 3600 +F 0 "X3" H 6650 3550 60 0000 C CNN +F 1 "4_and" H 6700 3700 60 0000 C CNN +F 2 "" H 6600 3600 60 0000 C CNN +F 3 "" H 6600 3600 60 0000 C CNN + 1 6600 3600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 6803576F +P 6600 4150 +F 0 "X4" H 6650 4100 60 0000 C CNN +F 1 "4_and" H 6700 4250 60 0000 C CNN +F 2 "" H 6600 4150 60 0000 C CNN +F 3 "" H 6600 4150 60 0000 C CNN + 1 6600 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 680357C6 +P 6650 4600 +F 0 "U4" H 6650 4600 60 0000 C CNN +F 1 "d_and" H 6700 4700 60 0000 C CNN +F 2 "" H 6650 4600 60 0000 C CNN +F 3 "" H 6650 4600 60 0000 C CNN + 1 6650 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68035819 +P 6650 4900 +F 0 "U5" H 6650 4900 60 0000 C CNN +F 1 "d_and" H 6700 5000 60 0000 C CNN +F 2 "" H 6650 4900 60 0000 C CNN +F 3 "" H 6650 4900 60 0000 C CNN + 1 6650 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 68035870 +P 6650 5200 +F 0 "U6" H 6650 5200 60 0000 C CNN +F 1 "d_and" H 6700 5300 60 0000 C CNN +F 2 "" H 6650 5200 60 0000 C CNN +F 3 "" H 6650 5200 60 0000 C CNN + 1 6650 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 680358C7 +P 6650 5500 +F 0 "U7" H 6650 5500 60 0000 C CNN +F 1 "d_and" H 6700 5600 60 0000 C CNN +F 2 "" H 6650 5500 60 0000 C CNN +F 3 "" H 6650 5500 60 0000 C CNN + 1 6650 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 68035922 +P 6650 5800 +F 0 "U8" H 6650 5800 60 0000 C CNN +F 1 "d_and" H 6700 5900 60 0000 C CNN +F 2 "" H 6650 5800 60 0000 C CNN +F 3 "" H 6650 5800 60 0000 C CNN + 1 6650 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 6803598F +P 6650 6100 +F 0 "U9" H 6650 6100 60 0000 C CNN +F 1 "d_and" H 6700 6200 60 0000 C CNN +F 2 "" H 6650 6100 60 0000 C CNN +F 3 "" H 6650 6100 60 0000 C CNN + 1 6650 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8250 800 8400 800 +Wire Wire Line + 8400 800 8400 950 +Wire Wire Line + 8200 1300 8400 1250 +Wire Wire Line + 8400 1250 8400 1050 +Wire Wire Line + 9300 1000 9550 1000 +Wire Wire Line + 9450 1350 9650 1350 +Wire Wire Line + 10150 1000 10150 1250 +Wire Wire Line + 10150 1250 9450 1250 +Wire Wire Line + 9450 1250 9450 1350 +Wire Wire Line + 5800 1450 5800 6100 +Wire Wire Line + 4250 6100 6200 6100 +Wire Wire Line + 5800 1500 9650 1500 +Wire Wire Line + 9650 1500 9650 1450 +Connection ~ 5800 1500 +Wire Wire Line + 6200 2050 5800 2050 +Connection ~ 5800 2050 +Wire Wire Line + 6200 2550 5800 2550 +Connection ~ 5800 2550 +Wire Wire Line + 6200 2950 5800 2950 +Connection ~ 5800 2950 +Wire Wire Line + 6200 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 6200 3750 5800 3750 +Connection ~ 5800 3750 +Wire Wire Line + 6200 4300 5800 4300 +Connection ~ 5800 4300 +Wire Wire Line + 6200 4600 5800 4600 +Connection ~ 5800 4600 +Wire Wire Line + 6200 4900 5800 4900 +Connection ~ 5800 4900 +Wire Wire Line + 6200 5200 5800 5200 +Connection ~ 5800 5200 +Wire Wire Line + 6200 5500 5800 5500 +Connection ~ 5800 5500 +Wire Wire Line + 6200 5800 5800 5800 +Connection ~ 5800 5800 +Wire Wire Line + 7100 5150 7350 5150 +Wire Wire Line + 7350 5150 7350 5050 +Wire Wire Line + 7350 5050 7700 5050 +Wire Wire Line + 7700 5050 7700 5100 +Wire Wire Line + 7100 5450 7100 5200 +Wire Wire Line + 7100 5200 7700 5200 +Wire Wire Line + 7100 5750 7100 5600 +Wire Wire Line + 7100 5600 7700 5600 +Wire Wire Line + 7100 6050 7700 6050 +Wire Wire Line + 7700 6050 7700 5700 +Wire Wire Line + 8600 5150 8750 5150 +Wire Wire Line + 8750 5100 8750 5200 +Wire Wire Line + 8750 5100 8850 5100 +Wire Wire Line + 8750 5200 8850 5200 +Connection ~ 8750 5150 +Wire Wire Line + 8600 5650 8750 5650 +Wire Wire Line + 8750 5600 8750 5700 +Wire Wire Line + 8750 5600 8850 5600 +Wire Wire Line + 8750 5700 8850 5700 +Connection ~ 8750 5650 +Wire Wire Line + 9750 5150 9750 5300 +Wire Wire Line + 9750 5400 9750 5650 +Wire Wire Line + 7100 3600 7100 3500 +Wire Wire Line + 7100 3500 7650 3500 +Wire Wire Line + 7100 4150 7100 3800 +Wire Wire Line + 7100 3800 7650 3800 +Wire Wire Line + 7650 3800 7650 3600 +Wire Wire Line + 7100 4550 7100 4350 +Wire Wire Line + 7100 4350 7350 4350 +Wire Wire Line + 7350 4350 7350 4000 +Wire Wire Line + 7350 4000 7650 4000 +Wire Wire Line + 7100 4850 7650 4850 +Wire Wire Line + 7650 4850 7650 4100 +Wire Wire Line + 8550 3550 8700 3550 +Wire Wire Line + 8700 3500 8700 3600 +Wire Wire Line + 8700 3500 8800 3500 +Wire Wire Line + 8700 3600 8800 3600 +Connection ~ 8700 3550 +Wire Wire Line + 8550 4050 8700 4050 +Wire Wire Line + 8700 4000 8700 4100 +Wire Wire Line + 8700 4000 8800 4000 +Wire Wire Line + 8700 4100 8800 4100 +Connection ~ 8700 4050 +Wire Wire Line + 9700 3550 9700 3700 +Wire Wire Line + 9700 4050 9700 3800 +Wire Wire Line + 7200 1850 7650 1850 +Wire Wire Line + 7650 1850 7650 2050 +Wire Wire Line + 7100 2400 7650 2400 +Wire Wire Line + 7650 2400 7650 2150 +Wire Wire Line + 7050 2850 7100 2850 +Wire Wire Line + 7100 2850 7100 2550 +Wire Wire Line + 7100 2550 7650 2550 +Wire Wire Line + 7100 3200 7650 3200 +Wire Wire Line + 7650 3200 7650 2650 +Wire Wire Line + 8550 2100 8750 2100 +Wire Wire Line + 8750 2050 8750 2150 +Wire Wire Line + 8750 2050 8800 2050 +Wire Wire Line + 8750 2150 8800 2150 +Connection ~ 8750 2100 +Wire Wire Line + 8550 2600 8700 2600 +Wire Wire Line + 8700 2550 8700 2650 +Wire Wire Line + 8700 2550 8800 2550 +Wire Wire Line + 8700 2650 8800 2650 +Connection ~ 8700 2600 +Wire Wire Line + 9700 2100 9700 2250 +Wire Wire Line + 9700 2350 9700 2600 +$Comp +L PORT U1 +U 1 1 680376C3 +P 650 600 +F 0 "U1" H 700 700 30 0000 C CNN +F 1 "PORT" H 650 600 30 0000 C CNN +F 2 "" H 650 600 60 0000 C CNN +F 3 "" H 650 600 60 0000 C CNN + 1 650 600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 680377EE +P 800 1450 +F 0 "U1" H 850 1550 30 0000 C CNN +F 1 "PORT" H 800 1450 30 0000 C CNN +F 2 "" H 800 1450 60 0000 C CNN +F 3 "" H 800 1450 60 0000 C CNN + 2 800 1450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68037920 +P 900 2100 +F 0 "U1" H 950 2200 30 0000 C CNN +F 1 "PORT" H 900 2100 30 0000 C CNN +F 2 "" H 900 2100 60 0000 C CNN +F 3 "" H 900 2100 60 0000 C CNN + 3 900 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68037989 +P 1000 2750 +F 0 "U1" H 1050 2850 30 0000 C CNN +F 1 "PORT" H 1000 2750 30 0000 C CNN +F 2 "" H 1000 2750 60 0000 C CNN +F 3 "" H 1000 2750 60 0000 C CNN + 4 1000 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 680379F4 +P 1100 3400 +F 0 "U1" H 1150 3500 30 0000 C CNN +F 1 "PORT" H 1100 3400 30 0000 C CNN +F 2 "" H 1100 3400 60 0000 C CNN +F 3 "" H 1100 3400 60 0000 C CNN + 5 1100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68037A5B +P 1200 3950 +F 0 "U1" H 1250 4050 30 0000 C CNN +F 1 "PORT" H 1200 3950 30 0000 C CNN +F 2 "" H 1200 3950 60 0000 C CNN +F 3 "" H 1200 3950 60 0000 C CNN + 6 1200 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68037BF6 +P 1350 4600 +F 0 "U1" H 1400 4700 30 0000 C CNN +F 1 "PORT" H 1350 4600 30 0000 C CNN +F 2 "" H 1350 4600 60 0000 C CNN +F 3 "" H 1350 4600 60 0000 C CNN + 7 1350 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68037C5D +P 1450 5200 +F 0 "U1" H 1500 5300 30 0000 C CNN +F 1 "PORT" H 1450 5200 30 0000 C CNN +F 2 "" H 1450 5200 60 0000 C CNN +F 3 "" H 1450 5200 60 0000 C CNN + 8 1450 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68037CCA +P 1600 5900 +F 0 "U1" H 1650 6000 30 0000 C CNN +F 1 "PORT" H 1600 5900 30 0000 C CNN +F 2 "" H 1600 5900 60 0000 C CNN +F 3 "" H 1600 5900 60 0000 C CNN + 9 1600 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68038497 +P 10950 1000 +F 0 "U1" H 11000 1100 30 0000 C CNN +F 1 "PORT" H 10950 1000 30 0000 C CNN +F 2 "" H 10950 1000 60 0000 C CNN +F 3 "" H 10950 1000 60 0000 C CNN + 10 10950 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6803850C +P 10950 1400 +F 0 "U1" H 11000 1500 30 0000 C CNN +F 1 "PORT" H 10950 1400 30 0000 C CNN +F 2 "" H 10950 1400 60 0000 C CNN +F 3 "" H 10950 1400 60 0000 C CNN + 11 10950 1400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6803857F +P 11000 2300 +F 0 "U1" H 11050 2400 30 0000 C CNN +F 1 "PORT" H 11000 2300 30 0000 C CNN +F 2 "" H 11000 2300 60 0000 C CNN +F 3 "" H 11000 2300 60 0000 C CNN + 12 11000 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 680385FD +P 11000 3750 +F 0 "U1" H 11050 3850 30 0000 C CNN +F 1 "PORT" H 11000 3750 30 0000 C CNN +F 2 "" H 11000 3750 60 0000 C CNN +F 3 "" H 11000 3750 60 0000 C CNN + 13 11000 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 680387EC +P 11050 5350 +F 0 "U1" H 11100 5450 30 0000 C CNN +F 1 "PORT" H 11050 5350 30 0000 C CNN +F 2 "" H 11050 5350 60 0000 C CNN +F 3 "" H 11050 5350 60 0000 C CNN + 14 11050 5350 + -1 0 0 1 +$EndComp +Wire Wire Line + 10650 5350 10800 5350 +Wire Wire Line + 10600 3750 10750 3750 +Wire Wire Line + 10600 2300 10750 2300 +Wire Wire Line + 10550 1400 10700 1400 +Wire Wire Line + 10150 1000 10700 1000 +Wire Wire Line + 900 600 7250 600 +Wire Wire Line + 5250 1450 5250 1650 +Wire Wire Line + 5250 1650 6200 1650 +Wire Wire Line + 1200 1450 1200 700 +Wire Wire Line + 1200 700 7250 700 +Connection ~ 1200 1450 +Wire Wire Line + 1150 2100 2550 2100 +Wire Wire Line + 4200 2100 5250 2100 +Wire Wire Line + 5250 2100 5250 1750 +Wire Wire Line + 5250 1750 6200 1750 +Wire Wire Line + 1400 2100 1400 800 +Wire Wire Line + 1400 800 7250 800 +Connection ~ 1400 2100 +Wire Wire Line + 3150 2100 3150 3450 +Wire Wire Line + 3150 3450 6200 3450 +Connection ~ 3150 2100 +Wire Wire Line + 4900 2250 4900 4000 +Wire Wire Line + 4900 2250 6200 2250 +Wire Wire Line + 4900 4000 6200 4000 +Connection ~ 4900 2750 +$Comp +L d_inverter U30 +U 1 1 6803A0F5 +P 3850 3300 +F 0 "U30" H 3850 3200 60 0000 C CNN +F 1 "d_inverter" H 3850 3450 60 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 1 3850 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1550 2750 1550 900 +Wire Wire Line + 1550 900 7250 900 +Connection ~ 1550 2750 +Wire Wire Line + 1350 3400 2400 3400 +Wire Wire Line + 3000 3400 3550 3400 +Wire Wire Line + 3550 3400 3550 3300 +Wire Wire Line + 1650 3400 1650 1000 +Wire Wire Line + 1650 1000 7250 1000 +Connection ~ 1650 3400 +Wire Wire Line + 5400 3300 4150 3300 +Wire Wire Line + 5400 1850 5400 4100 +Wire Wire Line + 5400 1850 6200 1850 +Wire Wire Line + 5400 2350 6200 2350 +Connection ~ 5400 2350 +Wire Wire Line + 5400 3550 6200 3550 +Connection ~ 5400 3300 +Wire Wire Line + 5400 4100 6200 4100 +Connection ~ 5400 3550 +Wire Wire Line + 3000 3400 3000 5100 +Wire Wire Line + 3000 5100 6200 5100 +Connection ~ 3000 3400 +$Comp +L d_inverter U28 +U 1 1 6803A9D1 +P 3700 3950 +F 0 "U28" H 3700 3850 60 0000 C CNN +F 1 "d_inverter" H 3700 4100 60 0000 C CNN +F 2 "" H 3750 3900 60 0000 C CNN +F 3 "" H 3750 3900 60 0000 C CNN + 1 3700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6803AA4C +P 3750 4550 +F 0 "U29" H 3750 4450 60 0000 C CNN +F 1 "d_inverter" H 3750 4700 60 0000 C CNN +F 2 "" H 3800 4500 60 0000 C CNN +F 3 "" H 3800 4500 60 0000 C CNN + 1 3750 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 3950 5650 3950 +Wire Wire Line + 5650 3650 5650 4200 +Wire Wire Line + 5650 3650 6200 3650 +Wire Wire Line + 5650 4200 6200 4200 +Connection ~ 5650 3950 +Wire Wire Line + 3100 3950 3100 4400 +Wire Wire Line + 3100 4400 5550 4400 +Wire Wire Line + 5550 2750 5550 5400 +Wire Wire Line + 5550 2750 6200 2750 +Connection ~ 3100 3950 +Wire Wire Line + 5550 5400 6200 5400 +Connection ~ 5550 4400 +Wire Wire Line + 1950 3950 1950 1150 +Wire Wire Line + 1950 1150 7250 1150 +Connection ~ 1950 3950 +$Comp +L 4_and X6 +U 1 1 6803B5B1 +P 7650 1300 +F 0 "X6" H 7700 1250 60 0000 C CNN +F 1 "4_and" H 7750 1400 60 0000 C CNN +F 2 "" H 7650 1300 60 0000 C CNN +F 3 "" H 7650 1300 60 0000 C CNN + 1 7650 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 1450 7250 1450 +Wire Wire Line + 8200 1300 8150 1300 +Wire Wire Line + 4250 5900 4250 6100 +Connection ~ 5800 6100 +Wire Wire Line + 1700 5200 1900 5200 +Wire Wire Line + 1900 5200 1900 5750 +Wire Wire Line + 5600 3150 5600 6000 +Wire Wire Line + 5600 6000 6200 6000 +Wire Wire Line + 5600 4800 6200 4800 +Connection ~ 5600 5750 +Wire Wire Line + 5600 3150 6200 3150 +Connection ~ 5600 4800 +Wire Wire Line + 2000 1350 2000 5750 +Wire Wire Line + 2000 1350 7250 1350 +Connection ~ 2000 5750 +Wire Wire Line + 3450 4600 3450 4550 +Wire Wire Line + 2350 4600 2350 1250 +Wire Wire Line + 2350 1250 7250 1250 +Connection ~ 2350 4600 +Wire Wire Line + 3150 4600 3150 5700 +Wire Wire Line + 3150 5700 6200 5700 +Connection ~ 3150 4600 +Wire Wire Line + 6000 5700 6000 4500 +Wire Wire Line + 6000 4500 6200 4500 +Connection ~ 6000 5700 +Wire Wire Line + 5750 4550 4050 4550 +Wire Wire Line + 5750 1950 5750 4550 +Wire Wire Line + 5750 1950 6200 1950 +Wire Wire Line + 5750 2450 6200 2450 +Connection ~ 5750 2450 +Wire Wire Line + 5750 2850 6200 2850 +Connection ~ 5750 2850 +$Comp +L d_inverter U37 +U 1 1 68036AB6 +P 3000 1450 +F 0 "U37" H 3000 1350 60 0000 C CNN +F 1 "d_inverter" H 3000 1600 60 0000 C CNN +F 2 "" H 3050 1400 60 0000 C CNN +F 3 "" H 3050 1400 60 0000 C CNN + 1 3000 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 1450 2700 1450 +Wire Wire Line + 3300 1450 5250 1450 +$Comp +L d_inverter U35 +U 1 1 6803703F +P 2850 2100 +F 0 "U35" H 2850 2000 60 0000 C CNN +F 1 "d_inverter" H 2850 2250 60 0000 C CNN +F 2 "" H 2900 2050 60 0000 C CNN +F 3 "" H 2900 2050 60 0000 C CNN + 1 2850 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 2100 3600 2100 +$Comp +L d_inverter U32 +U 1 1 68037359 +P 2750 2750 +F 0 "U32" H 2750 2650 60 0000 C CNN +F 1 "d_inverter" H 2750 2900 60 0000 C CNN +F 2 "" H 2800 2700 60 0000 C CNN +F 3 "" H 2800 2700 60 0000 C CNN + 1 2750 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 2750 2450 2750 +Wire Wire Line + 3050 2750 4900 2750 +$Comp +L d_inverter U31 +U 1 1 680376A2 +P 2700 3400 +F 0 "U31" H 2700 3300 60 0000 C CNN +F 1 "d_inverter" H 2700 3550 60 0000 C CNN +F 2 "" H 2750 3350 60 0000 C CNN +F 3 "" H 2750 3350 60 0000 C CNN + 1 2700 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 6803789B +P 2800 3950 +F 0 "U34" H 2800 3850 60 0000 C CNN +F 1 "d_inverter" H 2800 4100 60 0000 C CNN +F 2 "" H 2850 3900 60 0000 C CNN +F 3 "" H 2850 3900 60 0000 C CNN + 1 2800 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1450 3950 2500 3950 +Wire Wire Line + 3100 3950 3400 3950 +$Comp +L d_inverter U36 +U 1 1 68037CD4 +P 2850 4600 +F 0 "U36" H 2850 4500 60 0000 C CNN +F 1 "d_inverter" H 2850 4750 60 0000 C CNN +F 2 "" H 2900 4550 60 0000 C CNN +F 3 "" H 2900 4550 60 0000 C CNN + 1 2850 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 4600 2550 4600 +Wire Wire Line + 3150 4600 3450 4600 +$Comp +L d_inverter U33 +U 1 1 68037FCC +P 2750 5750 +F 0 "U33" H 2750 5650 60 0000 C CNN +F 1 "d_inverter" H 2750 5900 60 0000 C CNN +F 2 "" H 2800 5700 60 0000 C CNN +F 3 "" H 2800 5700 60 0000 C CNN + 1 2750 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 5750 2450 5750 +Wire Wire Line + 3050 5750 5600 5750 +$Comp +L d_inverter U38 +U 1 1 680382A1 +P 3450 5900 +F 0 "U38" H 3450 5800 60 0000 C CNN +F 1 "d_inverter" H 3450 6050 60 0000 C CNN +F 2 "" H 3500 5850 60 0000 C CNN +F 3 "" H 3500 5850 60 0000 C CNN + 1 3450 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1850 5900 3150 5900 +Wire Wire Line + 3750 5900 4250 5900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148/74148.sub b/library/SubcircuitLibrary/SN74LS148/74148.sub new file mode 100644 index 00000000..a4dc5a51 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.sub @@ -0,0 +1,164 @@ +* Subcircuit 74148 +.subckt 74148 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74148\74148.cir +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u17 net-_u10-pad3_ net-_u10-pad3_ net-_u17-pad3_ d_nor +* u18 net-_u11-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor +* u25 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad12_ d_nor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor +* u19 net-_u12-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_nor +* u20 net-_u13-pad3_ net-_u13-pad3_ net-_u20-pad3_ d_nor +* u26 net-_u19-pad3_ net-_u20-pad3_ net-_u1-pad13_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u21 net-_u14-pad3_ net-_u14-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u15-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor +* u27 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad14_ d_nor +* u24 net-_u1-pad10_ net-_u24-pad2_ net-_u1-pad11_ d_nand +x7 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u16-pad1_ 5_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u23 net-_u16-pad3_ net-_u1-pad10_ d_inverter +x5 net-_u37-pad2_ net-_u2-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad1_ 5_and +x2 net-_u32-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad2_ 4_and +x1 net-_u28-pad1_ net-_u29-pad2_ net-_u24-pad2_ net-_u11-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u24-pad2_ net-_u11-pad2_ d_and +x3 net-_u2-pad1_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad1_ 4_and +x4 net-_u32-pad2_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad2_ 4_and +* u4 net-_u29-pad1_ net-_u24-pad2_ net-_u13-pad1_ d_and +* u5 net-_u3-pad1_ net-_u24-pad2_ net-_u13-pad2_ d_and +* u6 net-_u30-pad1_ net-_u24-pad2_ net-_u14-pad1_ d_and +* u7 net-_u28-pad1_ net-_u24-pad2_ net-_u14-pad2_ d_and +* u8 net-_u29-pad1_ net-_u24-pad2_ net-_u15-pad1_ d_and +* u9 net-_u3-pad1_ net-_u24-pad2_ net-_u15-pad2_ d_and +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +x6 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u24-pad2_ net-_u16-pad2_ 4_and +* u37 net-_u1-pad2_ net-_u37-pad2_ d_inverter +* u35 net-_u1-pad3_ net-_u2-pad1_ d_inverter +* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter +* u31 net-_u1-pad5_ net-_u30-pad1_ d_inverter +* u34 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u36 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u33 net-_u1-pad8_ net-_u3-pad1_ d_inverter +* u38 net-_u1-pad9_ net-_u24-pad2_ d_inverter +a1 net-_u2-pad1_ net-_u2-pad2_ u2 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a5 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18 +a6 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad12_ u25 +a7 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a9 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u20-pad3_ u20 +a11 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u1-pad13_ u26 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u21-pad3_ u21 +a15 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 +a16 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad14_ u27 +a17 [net-_u1-pad10_ net-_u24-pad2_ ] net-_u1-pad11_ u24 +a18 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a19 net-_u16-pad3_ net-_u1-pad10_ u23 +a20 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u11-pad2_ u3 +a21 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u13-pad1_ u4 +a22 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u13-pad2_ u5 +a23 [net-_u30-pad1_ net-_u24-pad2_ ] net-_u14-pad1_ u6 +a24 [net-_u28-pad1_ net-_u24-pad2_ ] net-_u14-pad2_ u7 +a25 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u15-pad1_ u8 +a26 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u15-pad2_ u9 +a27 net-_u30-pad1_ net-_u30-pad2_ u30 +a28 net-_u28-pad1_ net-_u28-pad2_ u28 +a29 net-_u29-pad1_ net-_u29-pad2_ u29 +a30 net-_u1-pad2_ net-_u37-pad2_ u37 +a31 net-_u1-pad3_ net-_u2-pad1_ u35 +a32 net-_u1-pad4_ net-_u32-pad2_ u32 +a33 net-_u1-pad5_ net-_u30-pad1_ u31 +a34 net-_u1-pad6_ net-_u28-pad1_ u34 +a35 net-_u1-pad7_ net-_u29-pad1_ u36 +a36 net-_u1-pad8_ net-_u3-pad1_ u33 +a37 net-_u1-pad9_ net-_u24-pad2_ u38 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74148
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148/74148_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148/74148_Previous_Values.xml new file mode 100644 index 00000000..590eac2d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u11 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u10><u17 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u18><u25 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u25><u13 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_nor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u12><u19 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_nor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u20><u26 name="type">d_nor<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u26><u15 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u21 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u22><u27 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u27><u24 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u24><u16 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u16><u23 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u23><u3 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u9><u30 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u30><u28 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u29><u37 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u37><u35 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u35><u32 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u32><u31 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u31><u34 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u34><u36 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u36><u33 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u33><u38 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u38></model><devicemodel /><subcircuit><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148/analysis b/library/SubcircuitLibrary/SN74LS148/analysis new file mode 100644 index 00000000..7dec7ebc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/analysis @@ -0,0 +1 @@ +.tran 10e-03 50e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS151/74151-cache.lib b/library/SubcircuitLibrary/SN74LS151/74151-cache.lib new file mode 100644 index 00000000..63457e0b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS151/74151.cir b/library/SubcircuitLibrary/SN74LS151/74151.cir new file mode 100644 index 00000000..b01b335b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74151\74151.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/18/25 20:22:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad4_ Net-_U16-Pad1_ d_inverter +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad5_ Net-_U11-Pad1_ 4_and +X2 Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad6_ Net-_U11-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad7_ Net-_U13-Pad2_ 4_and +X4 Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad8_ Net-_U14-Pad2_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad9_ Net-_U12-Pad1_ 4_and +X6 Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad10_ Net-_U12-Pad2_ 4_and +X7 Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad11_ Net-_U9-Pad2_ 4_and +X8 Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U1-Pad12_ Net-_U10-Pad2_ 4_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U14 Net-_U13-Pad3_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or +U9 Net-_U12-Pad3_ Net-_U9-Pad2_ Net-_U10-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U15 Net-_U14-Pad3_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U15-Pad3_ Net-_U1-Pad13_ d_and +U17 Net-_U1-Pad13_ Net-_U1-Pad14_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U7 Net-_U3-Pad2_ Net-_U7-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U8 Net-_U4-Pad2_ Net-_U8-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS151/74151.cir.out b/library/SubcircuitLibrary/SN74LS151/74151.cir.out new file mode 100644 index 00000000..141a4401 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.cir.out @@ -0,0 +1,85 @@ +* c:\fossee\esim\library\subcircuitlibrary\74151\74151.cir + +.include 4_and.sub +* u5 net-_u1-pad4_ net-_u16-pad1_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad5_ net-_u11-pad1_ 4_and +x2 net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u11-pad2_ 4_and +x3 net-_u2-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad7_ net-_u13-pad2_ 4_and +x4 net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad8_ net-_u14-pad2_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad9_ net-_u12-pad1_ 4_and +x6 net-_u6-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad10_ net-_u12-pad2_ 4_and +x7 net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad11_ net-_u9-pad2_ 4_and +x8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad12_ net-_u10-pad2_ 4_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u14 net-_u13-pad3_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u15 net-_u14-pad3_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u16 net-_u16-pad1_ net-_u15-pad3_ net-_u1-pad13_ d_and +* u17 net-_u1-pad13_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u1-pad4_ net-_u16-pad1_ u5 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a4 [net-_u13-pad3_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u10-pad1_ u9 +a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a8 [net-_u14-pad3_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a9 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u1-pad13_ u16 +a10 net-_u1-pad13_ net-_u1-pad14_ u17 +a11 net-_u1-pad1_ net-_u2-pad2_ u2 +a12 net-_u2-pad2_ net-_u6-pad2_ u6 +a13 net-_u1-pad2_ net-_u3-pad2_ u3 +a14 net-_u3-pad2_ net-_u7-pad2_ u7 +a15 net-_u1-pad3_ net-_u4-pad2_ u4 +a16 net-_u4-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS151/74151.pro b/library/SubcircuitLibrary/SN74LS151/74151.pro new file mode 100644 index 00000000..ad9ee7a2 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.pro @@ -0,0 +1,83 @@ +update=05/06/25 20:58:57 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74LS151/74151.sch b/library/SubcircuitLibrary/SN74LS151/74151.sch new file mode 100644 index 00000000..373289ec --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.sch @@ -0,0 +1,736 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U5 +U 1 1 680256E1 +P 2300 1200 +F 0 "U5" H 2300 1100 60 0000 C CNN +F 1 "d_inverter" H 2300 1350 60 0000 C CNN +F 2 "" H 2350 1150 60 0000 C CNN +F 3 "" H 2350 1150 60 0000 C CNN + 1 2300 1200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X1 +U 1 1 68025716 +P 4050 1800 +F 0 "X1" H 4100 1750 60 0000 C CNN +F 1 "4_and" H 4150 1900 60 0000 C CNN +F 2 "" H 4050 1800 60 0000 C CNN +F 3 "" H 4050 1800 60 0000 C CNN + 1 4050 1800 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 68025737 +P 4050 2300 +F 0 "X2" H 4100 2250 60 0000 C CNN +F 1 "4_and" H 4150 2400 60 0000 C CNN +F 2 "" H 4050 2300 60 0000 C CNN +F 3 "" H 4050 2300 60 0000 C CNN + 1 4050 2300 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 68025752 +P 4050 2800 +F 0 "X3" H 4100 2750 60 0000 C CNN +F 1 "4_and" H 4150 2900 60 0000 C CNN +F 2 "" H 4050 2800 60 0000 C CNN +F 3 "" H 4050 2800 60 0000 C CNN + 1 4050 2800 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 68025775 +P 4050 3250 +F 0 "X4" H 4100 3200 60 0000 C CNN +F 1 "4_and" H 4150 3350 60 0000 C CNN +F 2 "" H 4050 3250 60 0000 C CNN +F 3 "" H 4050 3250 60 0000 C CNN + 1 4050 3250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 68025794 +P 4050 3750 +F 0 "X5" H 4100 3700 60 0000 C CNN +F 1 "4_and" H 4150 3850 60 0000 C CNN +F 2 "" H 4050 3750 60 0000 C CNN +F 3 "" H 4050 3750 60 0000 C CNN + 1 4050 3750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 680257C7 +P 4050 4250 +F 0 "X6" H 4100 4200 60 0000 C CNN +F 1 "4_and" H 4150 4350 60 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 1 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 680257F2 +P 4050 4750 +F 0 "X7" H 4100 4700 60 0000 C CNN +F 1 "4_and" H 4150 4850 60 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 1 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 6802581B +P 4050 5250 +F 0 "X8" H 4100 5200 60 0000 C CNN +F 1 "4_and" H 4150 5350 60 0000 C CNN +F 2 "" H 4050 5250 60 0000 C CNN +F 3 "" H 4050 5250 60 0000 C CNN + 1 4050 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U11 +U 1 1 6802584A +P 6350 2550 +F 0 "U11" H 6350 2550 60 0000 C CNN +F 1 "d_or" H 6350 2650 60 0000 C CNN +F 2 "" H 6350 2550 60 0000 C CNN +F 3 "" H 6350 2550 60 0000 C CNN + 1 6350 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U13 +U 1 1 68025893 +P 6400 3050 +F 0 "U13" H 6400 3050 60 0000 C CNN +F 1 "d_or" H 6400 3150 60 0000 C CNN +F 2 "" H 6400 3050 60 0000 C CNN +F 3 "" H 6400 3050 60 0000 C CNN + 1 6400 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U14 +U 1 1 68025938 +P 6400 3450 +F 0 "U14" H 6400 3450 60 0000 C CNN +F 1 "d_or" H 6400 3550 60 0000 C CNN +F 2 "" H 6400 3450 60 0000 C CNN +F 3 "" H 6400 3450 60 0000 C CNN + 1 6400 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U12 +U 1 1 68025975 +P 6350 4100 +F 0 "U12" H 6350 4100 60 0000 C CNN +F 1 "d_or" H 6350 4200 60 0000 C CNN +F 2 "" H 6350 4100 60 0000 C CNN +F 3 "" H 6350 4100 60 0000 C CNN + 1 6350 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 680259B2 +P 6300 4450 +F 0 "U9" H 6300 4450 60 0000 C CNN +F 1 "d_or" H 6300 4550 60 0000 C CNN +F 2 "" H 6300 4450 60 0000 C CNN +F 3 "" H 6300 4450 60 0000 C CNN + 1 6300 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 680259F1 +P 6300 4800 +F 0 "U10" H 6300 4800 60 0000 C CNN +F 1 "d_or" H 6300 4900 60 0000 C CNN +F 2 "" H 6300 4800 60 0000 C CNN +F 3 "" H 6300 4800 60 0000 C CNN + 1 6300 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 68025A26 +P 8350 3750 +F 0 "U15" H 8350 3750 60 0000 C CNN +F 1 "d_or" H 8350 3850 60 0000 C CNN +F 2 "" H 8350 3750 60 0000 C CNN +F 3 "" H 8350 3750 60 0000 C CNN + 1 8350 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 68025A81 +P 9500 3350 +F 0 "U16" H 9500 3350 60 0000 C CNN +F 1 "d_and" H 9550 3450 60 0000 C CNN +F 2 "" H 9500 3350 60 0000 C CNN +F 3 "" H 9500 3350 60 0000 C CNN + 1 9500 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 68025AF6 +P 10450 3600 +F 0 "U17" H 10450 3500 60 0000 C CNN +F 1 "d_inverter" H 10450 3750 60 0000 C CNN +F 2 "" H 10500 3550 60 0000 C CNN +F 3 "" H 10500 3550 60 0000 C CNN + 1 10450 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68025B39 +P 1700 5650 +F 0 "U2" H 1700 5550 60 0000 C CNN +F 1 "d_inverter" H 1700 5800 60 0000 C CNN +F 2 "" H 1750 5600 60 0000 C CNN +F 3 "" H 1750 5600 60 0000 C CNN + 1 1700 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68025BA0 +P 2450 5650 +F 0 "U6" H 2450 5550 60 0000 C CNN +F 1 "d_inverter" H 2450 5800 60 0000 C CNN +F 2 "" H 2500 5600 60 0000 C CNN +F 3 "" H 2500 5600 60 0000 C CNN + 1 2450 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68025BDD +P 1700 6100 +F 0 "U3" H 1700 6000 60 0000 C CNN +F 1 "d_inverter" H 1700 6250 60 0000 C CNN +F 2 "" H 1750 6050 60 0000 C CNN +F 3 "" H 1750 6050 60 0000 C CNN + 1 1700 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68025C1C +P 2450 6150 +F 0 "U7" H 2450 6050 60 0000 C CNN +F 1 "d_inverter" H 2450 6300 60 0000 C CNN +F 2 "" H 2500 6100 60 0000 C CNN +F 3 "" H 2500 6100 60 0000 C CNN + 1 2450 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68025C63 +P 1700 6600 +F 0 "U4" H 1700 6500 60 0000 C CNN +F 1 "d_inverter" H 1700 6750 60 0000 C CNN +F 2 "" H 1750 6550 60 0000 C CNN +F 3 "" H 1750 6550 60 0000 C CNN + 1 1700 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68025CB4 +P 2500 6600 +F 0 "U8" H 2500 6500 60 0000 C CNN +F 1 "d_inverter" H 2500 6750 60 0000 C CNN +F 2 "" H 2550 6550 60 0000 C CNN +F 3 "" H 2550 6550 60 0000 C CNN + 1 2500 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68025CFD +P 1050 1200 +F 0 "U1" H 1100 1300 30 0000 C CNN +F 1 "PORT" H 1050 1200 30 0000 C CNN +F 2 "" H 1050 1200 60 0000 C CNN +F 3 "" H 1050 1200 60 0000 C CNN + 4 1050 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68025D54 +P 1050 1950 +F 0 "U1" H 1100 2050 30 0000 C CNN +F 1 "PORT" H 1050 1950 30 0000 C CNN +F 2 "" H 1050 1950 60 0000 C CNN +F 3 "" H 1050 1950 60 0000 C CNN + 5 1050 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68025DA7 +P 1050 2400 +F 0 "U1" H 1100 2500 30 0000 C CNN +F 1 "PORT" H 1050 2400 30 0000 C CNN +F 2 "" H 1050 2400 60 0000 C CNN +F 3 "" H 1050 2400 60 0000 C CNN + 6 1050 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68025DF8 +P 1050 2900 +F 0 "U1" H 1100 3000 30 0000 C CNN +F 1 "PORT" H 1050 2900 30 0000 C CNN +F 2 "" H 1050 2900 60 0000 C CNN +F 3 "" H 1050 2900 60 0000 C CNN + 7 1050 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68025E53 +P 1050 3350 +F 0 "U1" H 1100 3450 30 0000 C CNN +F 1 "PORT" H 1050 3350 30 0000 C CNN +F 2 "" H 1050 3350 60 0000 C CNN +F 3 "" H 1050 3350 60 0000 C CNN + 8 1050 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68025EA4 +P 1050 3800 +F 0 "U1" H 1100 3900 30 0000 C CNN +F 1 "PORT" H 1050 3800 30 0000 C CNN +F 2 "" H 1050 3800 60 0000 C CNN +F 3 "" H 1050 3800 60 0000 C CNN + 9 1050 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68025F03 +P 1050 4250 +F 0 "U1" H 1100 4350 30 0000 C CNN +F 1 "PORT" H 1050 4250 30 0000 C CNN +F 2 "" H 1050 4250 60 0000 C CNN +F 3 "" H 1050 4250 60 0000 C CNN + 10 1050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68025F64 +P 1050 4700 +F 0 "U1" H 1100 4800 30 0000 C CNN +F 1 "PORT" H 1050 4700 30 0000 C CNN +F 2 "" H 1050 4700 60 0000 C CNN +F 3 "" H 1050 4700 60 0000 C CNN + 11 1050 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68025FBB +P 1050 5250 +F 0 "U1" H 1100 5350 30 0000 C CNN +F 1 "PORT" H 1050 5250 30 0000 C CNN +F 2 "" H 1050 5250 60 0000 C CNN +F 3 "" H 1050 5250 60 0000 C CNN + 12 1050 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68026020 +P 950 5650 +F 0 "U1" H 1000 5750 30 0000 C CNN +F 1 "PORT" H 950 5650 30 0000 C CNN +F 2 "" H 950 5650 60 0000 C CNN +F 3 "" H 950 5650 60 0000 C CNN + 1 950 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6802607F +P 950 6100 +F 0 "U1" H 1000 6200 30 0000 C CNN +F 1 "PORT" H 950 6100 30 0000 C CNN +F 2 "" H 950 6100 60 0000 C CNN +F 3 "" H 950 6100 60 0000 C CNN + 2 950 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 680260DC +P 950 6600 +F 0 "U1" H 1000 6700 30 0000 C CNN +F 1 "PORT" H 950 6600 30 0000 C CNN +F 2 "" H 950 6600 60 0000 C CNN +F 3 "" H 950 6600 60 0000 C CNN + 3 950 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68026141 +P 11000 3300 +F 0 "U1" H 11050 3400 30 0000 C CNN +F 1 "PORT" H 11000 3300 30 0000 C CNN +F 2 "" H 11000 3300 60 0000 C CNN +F 3 "" H 11000 3300 60 0000 C CNN + 13 11000 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 680261B0 +P 11150 3600 +F 0 "U1" H 11200 3700 30 0000 C CNN +F 1 "PORT" H 11150 3600 30 0000 C CNN +F 2 "" H 11150 3600 60 0000 C CNN +F 3 "" H 11150 3600 60 0000 C CNN + 14 11150 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 1300 1200 2000 1200 +Wire Wire Line + 1300 1950 3650 1950 +Wire Wire Line + 1300 2400 3650 2400 +Wire Wire Line + 3650 2400 3650 2450 +Wire Wire Line + 1300 2900 3650 2900 +Wire Wire Line + 3650 2900 3650 2950 +Wire Wire Line + 1300 3350 3650 3350 +Wire Wire Line + 3650 3350 3650 3400 +Wire Wire Line + 1300 3800 3450 3800 +Wire Wire Line + 3450 3800 3450 3900 +Wire Wire Line + 3450 3900 3650 3900 +Wire Wire Line + 1300 4250 3100 4250 +Wire Wire Line + 3100 4250 3100 4400 +Wire Wire Line + 3100 4400 3650 4400 +Wire Wire Line + 1300 4700 2900 4700 +Wire Wire Line + 2900 4700 2900 4900 +Wire Wire Line + 2900 4900 3650 4900 +Wire Wire Line + 1300 5250 2750 5250 +Wire Wire Line + 2750 5250 2750 5350 +Wire Wire Line + 2750 5350 3650 5350 +Wire Wire Line + 3650 5350 3650 5400 +Wire Wire Line + 1200 5650 1400 5650 +Wire Wire Line + 1200 6100 1400 6100 +Wire Wire Line + 1200 6600 1400 6600 +Wire Wire Line + 2000 5650 2150 5650 +Wire Wire Line + 2000 6100 2150 6100 +Wire Wire Line + 2150 6100 2150 6150 +Wire Wire Line + 2000 6600 2200 6600 +Wire Wire Line + 4550 1800 5900 1800 +Wire Wire Line + 5900 1800 5900 2450 +Wire Wire Line + 4550 2300 5650 2300 +Wire Wire Line + 5650 2300 5650 2550 +Wire Wire Line + 5650 2550 5900 2550 +Wire Wire Line + 6800 2500 7250 2500 +Wire Wire Line + 7250 2500 7250 2800 +Wire Wire Line + 7250 2800 5750 2800 +Wire Wire Line + 5750 2800 5750 2950 +Wire Wire Line + 5750 2950 5950 2950 +Wire Wire Line + 4550 2800 5300 2800 +Wire Wire Line + 5300 2800 5300 3050 +Wire Wire Line + 5300 3050 5950 3050 +Wire Wire Line + 6850 3000 7300 3000 +Wire Wire Line + 7300 3000 7300 3200 +Wire Wire Line + 7300 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 3350 +Wire Wire Line + 4550 3250 5650 3250 +Wire Wire Line + 5650 3250 5650 3450 +Wire Wire Line + 5650 3450 5950 3450 +Wire Wire Line + 6850 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 4550 3750 5900 3750 +Wire Wire Line + 5900 3750 5900 4000 +Wire Wire Line + 4500 4100 5900 4100 +Wire Wire Line + 4500 4100 4500 4150 +Wire Wire Line + 4500 4150 4550 4150 +Wire Wire Line + 4550 4150 4550 4250 +Wire Wire Line + 6800 4050 6800 4200 +Wire Wire Line + 6800 4200 5850 4200 +Wire Wire Line + 5850 4200 5850 4350 +Wire Wire Line + 4550 4750 5350 4750 +Wire Wire Line + 5350 4750 5350 4450 +Wire Wire Line + 5350 4450 5850 4450 +Wire Wire Line + 6750 4400 6900 4400 +Wire Wire Line + 6900 4400 6900 4550 +Wire Wire Line + 6900 4550 5850 4550 +Wire Wire Line + 5850 4550 5850 4700 +Wire Wire Line + 4550 5250 5850 5250 +Wire Wire Line + 5850 5250 5850 4800 +Wire Wire Line + 6750 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 3750 +Wire Wire Line + 8800 3700 8800 3350 +Wire Wire Line + 8800 3350 9050 3350 +Wire Wire Line + 9950 3300 10750 3300 +Wire Wire Line + 10100 3300 10100 3600 +Wire Wire Line + 10100 3600 10150 3600 +Connection ~ 10100 3300 +Wire Wire Line + 10750 3600 10900 3600 +Wire Wire Line + 2600 1200 9050 1200 +Wire Wire Line + 9050 1200 9050 3250 +Wire Wire Line + 2050 5650 2050 1650 +Wire Wire Line + 2050 1650 3650 1650 +Connection ~ 2050 5650 +Wire Wire Line + 3650 2650 2050 2650 +Connection ~ 2050 2650 +Wire Wire Line + 3650 3600 2050 3600 +Connection ~ 2050 3600 +Wire Wire Line + 3650 4600 2050 4600 +Connection ~ 2050 4600 +Wire Wire Line + 2750 5650 3100 5650 +Wire Wire Line + 3100 5650 3100 5400 +Wire Wire Line + 3100 5400 2150 5400 +Wire Wire Line + 2150 5400 2150 2150 +Wire Wire Line + 2150 2150 3650 2150 +Wire Wire Line + 3650 3100 2150 3100 +Wire Wire Line + 2150 3100 2150 3150 +Connection ~ 2150 3150 +Wire Wire Line + 3650 4100 2150 4100 +Connection ~ 2150 4100 +Wire Wire Line + 3650 5100 2150 5100 +Connection ~ 2150 5100 +Wire Wire Line + 2050 6100 2050 5850 +Wire Wire Line + 2050 5850 2850 5850 +Connection ~ 2050 6100 +Wire Wire Line + 2750 6150 3000 6150 +Wire Wire Line + 2100 6600 2100 6250 +Wire Wire Line + 2100 6250 3200 6250 +Connection ~ 2100 6600 +Wire Wire Line + 2800 6600 3350 6600 +Wire Wire Line + 2850 5850 2850 1750 +Wire Wire Line + 2850 1750 3650 1750 +Wire Wire Line + 2850 2250 3650 2250 +Connection ~ 2850 2250 +Wire Wire Line + 2850 3700 3650 3700 +Connection ~ 2850 3700 +Wire Wire Line + 2850 4200 3650 4200 +Connection ~ 2850 4200 +Wire Wire Line + 3000 6150 3000 2750 +Wire Wire Line + 3000 2750 3650 2750 +Wire Wire Line + 3000 3200 3650 3200 +Connection ~ 3000 3200 +Wire Wire Line + 3000 4700 3650 4700 +Connection ~ 3000 4700 +Wire Wire Line + 3000 5200 3650 5200 +Connection ~ 3000 5200 +Wire Wire Line + 3200 6250 3200 1850 +Wire Wire Line + 3200 1850 3650 1850 +Wire Wire Line + 3200 2350 3650 2350 +Connection ~ 3200 2350 +Wire Wire Line + 3200 2850 3650 2850 +Connection ~ 3200 2850 +Wire Wire Line + 3200 3300 3650 3300 +Connection ~ 3200 3300 +Wire Wire Line + 3350 6600 3350 3950 +Wire Wire Line + 3350 3950 3550 3950 +Wire Wire Line + 3550 3950 3550 3800 +Wire Wire Line + 3550 3800 3650 3800 +Wire Wire Line + 3350 4300 3650 4300 +Connection ~ 3350 4300 +Wire Wire Line + 3350 4800 3650 4800 +Connection ~ 3350 4800 +Wire Wire Line + 3350 5300 3650 5300 +Connection ~ 3350 5300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS151/74151.sub b/library/SubcircuitLibrary/SN74LS151/74151.sub new file mode 100644 index 00000000..c53f323b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.sub @@ -0,0 +1,79 @@ +* Subcircuit 74151 +.subckt 74151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74151\74151.cir +.include 4_and.sub +* u5 net-_u1-pad4_ net-_u16-pad1_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad5_ net-_u11-pad1_ 4_and +x2 net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u11-pad2_ 4_and +x3 net-_u2-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad7_ net-_u13-pad2_ 4_and +x4 net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad8_ net-_u14-pad2_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad9_ net-_u12-pad1_ 4_and +x6 net-_u6-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad10_ net-_u12-pad2_ 4_and +x7 net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad11_ net-_u9-pad2_ 4_and +x8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad12_ net-_u10-pad2_ 4_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u14 net-_u13-pad3_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u15 net-_u14-pad3_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u16 net-_u16-pad1_ net-_u15-pad3_ net-_u1-pad13_ d_and +* u17 net-_u1-pad13_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +a1 net-_u1-pad4_ net-_u16-pad1_ u5 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a4 [net-_u13-pad3_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u10-pad1_ u9 +a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a8 [net-_u14-pad3_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a9 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u1-pad13_ u16 +a10 net-_u1-pad13_ net-_u1-pad14_ u17 +a11 net-_u1-pad1_ net-_u2-pad2_ u2 +a12 net-_u2-pad2_ net-_u6-pad2_ u6 +a13 net-_u1-pad2_ net-_u3-pad2_ u3 +a14 net-_u3-pad2_ net-_u7-pad2_ u7 +a15 net-_u1-pad3_ net-_u4-pad2_ u4 +a16 net-_u4-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74151
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml new file mode 100644 index 00000000..8ebb72a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u5><u11 name="type">d_or<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u14><u12 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u12><u9 name="type">d_or<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u10><u15 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u2 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u6><u3 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u3><u7 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u7><u4 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x8></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS151/analysis b/library/SubcircuitLibrary/SN74LS151/analysis new file mode 100644 index 00000000..5c9b0b46 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-00 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS42/7442-cache.lib b/library/SubcircuitLibrary/SN74LS42/7442-cache.lib new file mode 100644 index 00000000..96dd6bbc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442-cache.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS42/7442.cir b/library/SubcircuitLibrary/SN74LS42/7442.cir new file mode 100644 index 00000000..f3018de9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442.cir @@ -0,0 +1,38 @@ +* C:\Users\pt710\eSim-Workspace\7442\7442.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/25 00:31:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U11-Pad1_ 4_and +X2 Net-_U6-Pad3_ Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U12-Pad1_ 4_and +X3 Net-_U1-Pad3_ Net-_U5-Pad3_ Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U13-Pad1_ 4_and +X4 Net-_U6-Pad3_ Net-_U5-Pad3_ Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U14-Pad1_ 4_and +X5 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ Net-_U4-Pad3_ Net-_U15-Pad1_ 4_and +X6 Net-_U6-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ Net-_U4-Pad3_ Net-_U9-Pad1_ 4_and +X7 Net-_U1-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ Net-_U4-Pad3_ Net-_U10-Pad1_ 4_and +X8 Net-_U6-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ Net-_U4-Pad3_ Net-_U16-Pad1_ 4_and +X9 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U8-Pad3_ Net-_U17-Pad1_ 4_and +X10 Net-_U6-Pad3_ Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U8-Pad3_ Net-_U18-Pad1_ 4_and +U1 Net-_U1-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad3_ d_nor +U6 Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U6-Pad3_ d_nor +U2 Net-_U2-Pad1_ Net-_U2-Pad1_ Net-_U2-Pad3_ d_nor +U5 Net-_U2-Pad3_ Net-_U2-Pad3_ Net-_U5-Pad3_ d_nor +U3 Net-_U3-Pad1_ Net-_U3-Pad1_ Net-_U3-Pad3_ d_nor +U7 Net-_U3-Pad3_ Net-_U3-Pad3_ Net-_U7-Pad3_ d_nor +U4 Net-_U4-Pad1_ Net-_U4-Pad1_ Net-_U4-Pad3_ d_nor +U8 Net-_U4-Pad3_ Net-_U4-Pad3_ Net-_U8-Pad3_ d_nor +U11 Net-_U11-Pad1_ Net-_U11-Pad1_ ? d_nor +U12 Net-_U12-Pad1_ Net-_U12-Pad1_ ? d_nor +U13 Net-_U13-Pad1_ Net-_U13-Pad1_ ? d_nor +U14 Net-_U14-Pad1_ Net-_U14-Pad1_ ? d_nor +U15 Net-_U15-Pad1_ Net-_U15-Pad1_ ? d_nor +U9 Net-_U9-Pad1_ Net-_U9-Pad1_ ? d_nor +U10 Net-_U10-Pad1_ Net-_U10-Pad1_ ? d_nor +U16 Net-_U16-Pad1_ Net-_U16-Pad1_ ? d_nor +U17 Net-_U17-Pad1_ Net-_U17-Pad1_ ? d_nor +U18 Net-_U18-Pad1_ Net-_U18-Pad1_ ? d_nor + +.end diff --git a/library/SubcircuitLibrary/SN74LS42/7442.cir.out b/library/SubcircuitLibrary/SN74LS42/7442.cir.out new file mode 100644 index 00000000..c533de51 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442.cir.out @@ -0,0 +1,35 @@ +* c:\users\pt710\esim-workspace\lm318\lm318.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_c1-pad2_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +r1 +15v net-_q1-pad1_ 10k +r2 +15v net-_c1-pad2_ 10k +q8 net-_q1-pad3_ net-_q8-pad2_ +15v Q2N2907A +r7 +15v net-_q8-pad2_ 1k +q2 gnd net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_c1-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +r3 net-_q2-pad3_ gnd 1k +q7 net-_c1-pad1_ net-_c1-pad2_ net-_q7-pad3_ Q2N2222 +r6 net-_q7-pad3_ gnd 1k +q3 +15v net-_c1-pad1_ net-_q3-pad3_ Q2N2222 +q6 out net-_q3-pad3_ +15v Q2N2907A +r4 out gnd 10k +d1 net-_c1-pad1_ out 1N4148 +d2 ? gnd 1N4148 +r5 net-_c1-pad1_ +15v 10k +* u2 out plot_v1 +c1 net-_c1-pad1_ net-_c1-pad2_ 50p +v1 net-_q5-pad2_ net-_q1-pad2_ sine(0 1 0 0 0) +.tran 10e-06 10e-03 1e-06 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out) +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS42/7442.pro b/library/SubcircuitLibrary/SN74LS42/7442.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS42/7442.proj b/library/SubcircuitLibrary/SN74LS42/7442.proj new file mode 100644 index 00000000..773ca67d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442.proj @@ -0,0 +1 @@ +schematicFile LM348.sch diff --git a/library/SubcircuitLibrary/SN74LS42/7442.sch b/library/SubcircuitLibrary/SN74LS42/7442.sch new file mode 100644 index 00000000..376df495 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:7442-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X1 +U 1 1 67E04AC9 +P 5250 950 +F 0 "X1" H 5300 900 60 0000 C CNN +F 1 "4_and" H 5350 1050 60 0000 C CNN +F 2 "" H 5250 950 60 0000 C CNN +F 3 "" H 5250 950 60 0000 C CNN + 1 5250 950 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 67E04B24 +P 5250 1500 +F 0 "X2" H 5300 1450 60 0000 C CNN +F 1 "4_and" H 5350 1600 60 0000 C CNN +F 2 "" H 5250 1500 60 0000 C CNN +F 3 "" H 5250 1500 60 0000 C CNN + 1 5250 1500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 67E04B55 +P 5250 2000 +F 0 "X3" H 5300 1950 60 0000 C CNN +F 1 "4_and" H 5350 2100 60 0000 C CNN +F 2 "" H 5250 2000 60 0000 C CNN +F 3 "" H 5250 2000 60 0000 C CNN + 1 5250 2000 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 67E04B78 +P 5250 2500 +F 0 "X4" H 5300 2450 60 0000 C CNN +F 1 "4_and" H 5350 2600 60 0000 C CNN +F 2 "" H 5250 2500 60 0000 C CNN +F 3 "" H 5250 2500 60 0000 C CNN + 1 5250 2500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 67E04BF5 +P 5250 3000 +F 0 "X5" H 5300 2950 60 0000 C CNN +F 1 "4_and" H 5350 3100 60 0000 C CNN +F 2 "" H 5250 3000 60 0000 C CNN +F 3 "" H 5250 3000 60 0000 C CNN + 1 5250 3000 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 67E04C1C +P 5250 3550 +F 0 "X6" H 5300 3500 60 0000 C CNN +F 1 "4_and" H 5350 3650 60 0000 C CNN +F 2 "" H 5250 3550 60 0000 C CNN +F 3 "" H 5250 3550 60 0000 C CNN + 1 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 67E04C53 +P 5250 4100 +F 0 "X7" H 5300 4050 60 0000 C CNN +F 1 "4_and" H 5350 4200 60 0000 C CNN +F 2 "" H 5250 4100 60 0000 C CNN +F 3 "" H 5250 4100 60 0000 C CNN + 1 5250 4100 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 67E04CB4 +P 5250 4650 +F 0 "X8" H 5300 4600 60 0000 C CNN +F 1 "4_and" H 5350 4750 60 0000 C CNN +F 2 "" H 5250 4650 60 0000 C CNN +F 3 "" H 5250 4650 60 0000 C CNN + 1 5250 4650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 67E04CFB +P 5250 5200 +F 0 "X9" H 5300 5150 60 0000 C CNN +F 1 "4_and" H 5350 5300 60 0000 C CNN +F 2 "" H 5250 5200 60 0000 C CNN +F 3 "" H 5250 5200 60 0000 C CNN + 1 5250 5200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 67E04D68 +P 5250 5700 +F 0 "X10" H 5300 5650 60 0000 C CNN +F 1 "4_and" H 5350 5800 60 0000 C CNN +F 2 "" H 5250 5700 60 0000 C CNN +F 3 "" H 5250 5700 60 0000 C CNN + 1 5250 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U1 +U 1 1 67E04E09 +P 1600 1150 +F 0 "U1" H 1600 1150 60 0000 C CNN +F 1 "d_nor" H 1650 1250 60 0000 C CNN +F 2 "" H 1600 1150 60 0000 C CNN +F 3 "" H 1600 1150 60 0000 C CNN + 1 1600 1150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 67E04E3A +P 2950 1750 +F 0 "U6" H 2950 1750 60 0000 C CNN +F 1 "d_nor" H 3000 1850 60 0000 C CNN +F 2 "" H 2950 1750 60 0000 C CNN +F 3 "" H 2950 1750 60 0000 C CNN + 1 2950 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U2 +U 1 1 67E04E6F +P 1600 2400 +F 0 "U2" H 1600 2400 60 0000 C CNN +F 1 "d_nor" H 1650 2500 60 0000 C CNN +F 2 "" H 1600 2400 60 0000 C CNN +F 3 "" H 1600 2400 60 0000 C CNN + 1 1600 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 67E04EA6 +P 2900 2950 +F 0 "U5" H 2900 2950 60 0000 C CNN +F 1 "d_nor" H 2950 3050 60 0000 C CNN +F 2 "" H 2900 2950 60 0000 C CNN +F 3 "" H 2900 2950 60 0000 C CNN + 1 2900 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U3 +U 1 1 67E04EE3 +P 1650 3750 +F 0 "U3" H 1650 3750 60 0000 C CNN +F 1 "d_nor" H 1700 3850 60 0000 C CNN +F 2 "" H 1650 3750 60 0000 C CNN +F 3 "" H 1650 3750 60 0000 C CNN + 1 1650 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 67E04F16 +P 3000 4300 +F 0 "U7" H 3000 4300 60 0000 C CNN +F 1 "d_nor" H 3050 4400 60 0000 C CNN +F 2 "" H 3000 4300 60 0000 C CNN +F 3 "" H 3000 4300 60 0000 C CNN + 1 3000 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 67E04F5B +P 1650 5050 +F 0 "U4" H 1650 5050 60 0000 C CNN +F 1 "d_nor" H 1700 5150 60 0000 C CNN +F 2 "" H 1650 5050 60 0000 C CNN +F 3 "" H 1650 5050 60 0000 C CNN + 1 1650 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 67E04F9A +P 3050 5550 +F 0 "U8" H 3050 5550 60 0000 C CNN +F 1 "d_nor" H 3100 5650 60 0000 C CNN +F 2 "" H 3050 5550 60 0000 C CNN +F 3 "" H 3050 5550 60 0000 C CNN + 1 3050 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 67E04FDD +P 6900 950 +F 0 "U11" H 6900 950 60 0000 C CNN +F 1 "d_nor" H 6950 1050 60 0000 C CNN +F 2 "" H 6900 950 60 0000 C CNN +F 3 "" H 6900 950 60 0000 C CNN + 1 6900 950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 67E05032 +P 6900 1550 +F 0 "U12" H 6900 1550 60 0000 C CNN +F 1 "d_nor" H 6950 1650 60 0000 C CNN +F 2 "" H 6900 1550 60 0000 C CNN +F 3 "" H 6900 1550 60 0000 C CNN + 1 6900 1550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U13 +U 1 1 67E05083 +P 6900 2100 +F 0 "U13" H 6900 2100 60 0000 C CNN +F 1 "d_nor" H 6950 2200 60 0000 C CNN +F 2 "" H 6900 2100 60 0000 C CNN +F 3 "" H 6900 2100 60 0000 C CNN + 1 6900 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 67E050D4 +P 6900 2550 +F 0 "U14" H 6900 2550 60 0000 C CNN +F 1 "d_nor" H 6950 2650 60 0000 C CNN +F 2 "" H 6900 2550 60 0000 C CNN +F 3 "" H 6900 2550 60 0000 C CNN + 1 6900 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 67E05121 +P 6900 3000 +F 0 "U15" H 6900 3000 60 0000 C CNN +F 1 "d_nor" H 6950 3100 60 0000 C CNN +F 2 "" H 6900 3000 60 0000 C CNN +F 3 "" H 6900 3000 60 0000 C CNN + 1 6900 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U9 +U 1 1 67E0516A +P 6850 3500 +F 0 "U9" H 6850 3500 60 0000 C CNN +F 1 "d_nor" H 6900 3600 60 0000 C CNN +F 2 "" H 6850 3500 60 0000 C CNN +F 3 "" H 6850 3500 60 0000 C CNN + 1 6850 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 67E051C3 +P 6850 4100 +F 0 "U10" H 6850 4100 60 0000 C CNN +F 1 "d_nor" H 6900 4200 60 0000 C CNN +F 2 "" H 6850 4100 60 0000 C CNN +F 3 "" H 6850 4100 60 0000 C CNN + 1 6850 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 67E05216 +P 6900 4700 +F 0 "U16" H 6900 4700 60 0000 C CNN +F 1 "d_nor" H 6950 4800 60 0000 C CNN +F 2 "" H 6900 4700 60 0000 C CNN +F 3 "" H 6900 4700 60 0000 C CNN + 1 6900 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 67E05267 +P 6900 5200 +F 0 "U17" H 6900 5200 60 0000 C CNN +F 1 "d_nor" H 6950 5300 60 0000 C CNN +F 2 "" H 6900 5200 60 0000 C CNN +F 3 "" H 6900 5200 60 0000 C CNN + 1 6900 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U18 +U 1 1 67E052BA +P 6900 5750 +F 0 "U18" H 6900 5750 60 0000 C CNN +F 1 "d_nor" H 6950 5850 60 0000 C CNN +F 2 "" H 6900 5750 60 0000 C CNN +F 3 "" H 6900 5750 60 0000 C CNN + 1 6900 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1150 1050 1050 1050 +Wire Wire Line + 1050 1050 1050 1150 +Wire Wire Line + 1050 1150 1150 1150 +Wire Wire Line + 2500 1650 2400 1650 +Wire Wire Line + 2400 1650 2400 1750 +Wire Wire Line + 2400 1750 2500 1750 +Wire Wire Line + 2050 1100 3500 1100 +Wire Wire Line + 2250 1100 2250 1700 +Wire Wire Line + 2250 1700 2400 1700 +Connection ~ 2400 1700 +Wire Wire Line + 1150 2300 1000 2300 +Wire Wire Line + 1000 2300 1000 2400 +Wire Wire Line + 1000 2400 1150 2400 +Wire Wire Line + 2450 2850 2300 2850 +Wire Wire Line + 2300 2850 2300 2950 +Wire Wire Line + 2300 2950 2450 2950 +Wire Wire Line + 2050 2350 3700 2350 +Wire Wire Line + 2250 2350 2250 2900 +Wire Wire Line + 2250 2900 2300 2900 +Connection ~ 2300 2900 +Wire Wire Line + 1200 3650 1050 3650 +Wire Wire Line + 1050 3650 1050 3750 +Wire Wire Line + 1050 3750 1200 3750 +Wire Wire Line + 2550 4200 2450 4200 +Wire Wire Line + 2450 4200 2450 4300 +Wire Wire Line + 2450 4300 2550 4300 +Wire Wire Line + 2300 3700 2300 4250 +Wire Wire Line + 2300 4250 2450 4250 +Connection ~ 2450 4250 +Wire Wire Line + 1200 4950 1050 4950 +Wire Wire Line + 1050 4950 1050 5050 +Wire Wire Line + 1050 5050 1200 5050 +Wire Wire Line + 2600 5450 2500 5450 +Wire Wire Line + 2500 5450 2500 5550 +Wire Wire Line + 2500 5550 2600 5550 +Wire Wire Line + 2350 5000 2350 5500 +Wire Wire Line + 2350 5500 2500 5500 +Connection ~ 2500 5500 +Wire Wire Line + 6450 850 6300 850 +Wire Wire Line + 6300 850 6300 950 +Wire Wire Line + 5750 950 6450 950 +Connection ~ 6300 950 +Wire Wire Line + 6450 1450 6300 1450 +Wire Wire Line + 6300 1450 6300 1550 +Wire Wire Line + 6300 1550 6450 1550 +Wire Wire Line + 5750 1500 6300 1500 +Connection ~ 6300 1500 +Wire Wire Line + 5750 2000 6450 2000 +Wire Wire Line + 6300 2000 6300 2100 +Wire Wire Line + 6300 2100 6450 2100 +Connection ~ 6300 2000 +Wire Wire Line + 6450 2450 6300 2450 +Wire Wire Line + 6300 2450 6300 2550 +Wire Wire Line + 6300 2550 6450 2550 +Wire Wire Line + 5750 2500 6300 2500 +Connection ~ 6300 2500 +Wire Wire Line + 6450 2900 6300 2900 +Wire Wire Line + 6300 2900 6300 3000 +Wire Wire Line + 5750 3000 6450 3000 +Wire Wire Line + 6400 3400 6300 3400 +Wire Wire Line + 6300 3400 6300 3550 +Wire Wire Line + 6300 3500 6400 3500 +Connection ~ 6300 3000 +Wire Wire Line + 6300 3550 5750 3550 +Connection ~ 6300 3500 +Wire Wire Line + 5750 4100 6400 4100 +Wire Wire Line + 6400 4000 6250 4000 +Wire Wire Line + 6250 4000 6250 4100 +Connection ~ 6250 4100 +Wire Wire Line + 6450 4600 6350 4600 +Wire Wire Line + 6350 4600 6350 4700 +Wire Wire Line + 6350 4700 6450 4700 +Wire Wire Line + 5750 4650 6350 4650 +Connection ~ 6350 4650 +Wire Wire Line + 6300 5100 6450 5100 +Wire Wire Line + 6300 5100 6300 5200 +Wire Wire Line + 5750 5200 6450 5200 +Connection ~ 6300 5200 +Wire Wire Line + 6450 5650 6350 5650 +Wire Wire Line + 6350 5650 6350 5750 +Wire Wire Line + 6350 5750 6450 5750 +Wire Wire Line + 5750 5700 6350 5700 +Connection ~ 6350 5700 +Wire Wire Line + 3400 1100 3400 800 +Wire Wire Line + 3400 800 4850 800 +Connection ~ 2250 1100 +Wire Wire Line + 3400 1350 3400 5550 +Wire Wire Line + 3400 1350 4850 1350 +Connection ~ 2250 2350 +Connection ~ 2300 3700 +Wire Wire Line + 3450 4250 3850 4250 +Connection ~ 2350 5000 +Wire Wire Line + 3400 4500 4850 4500 +Wire Wire Line + 3400 5550 4850 5550 +Wire Wire Line + 3500 5050 4850 5050 +Wire Wire Line + 3500 3950 4850 3950 +Wire Wire Line + 3400 2250 4850 2250 +Wire Wire Line + 4850 2250 4850 2350 +Connection ~ 3400 1700 +Wire Wire Line + 3400 3400 4850 3400 +Connection ~ 3400 2250 +Connection ~ 3400 3400 +Connection ~ 3400 4500 +Wire Wire Line + 3500 1100 3500 5050 +Wire Wire Line + 3500 1850 4850 1850 +Connection ~ 3400 1100 +Wire Wire Line + 3500 2850 4850 2850 +Connection ~ 3500 1850 +Connection ~ 3500 2850 +Connection ~ 3500 3950 +Wire Wire Line + 3700 900 3700 5650 +Wire Wire Line + 3700 900 4850 900 +Wire Wire Line + 4850 1450 3700 1450 +Connection ~ 3700 1450 +Wire Wire Line + 3700 2950 4850 2950 +Connection ~ 3700 2350 +Wire Wire Line + 3700 3500 4850 3500 +Connection ~ 3700 2950 +Wire Wire Line + 3700 5150 4850 5150 +Connection ~ 3700 3500 +Wire Wire Line + 3700 5650 4850 5650 +Connection ~ 3700 5150 +Wire Wire Line + 3350 2900 3600 2900 +Wire Wire Line + 3600 1950 3600 4600 +Wire Wire Line + 3600 1950 4850 1950 +Wire Wire Line + 3600 2450 4850 2450 +Connection ~ 3600 2450 +Wire Wire Line + 3600 4050 4850 4050 +Connection ~ 3600 2900 +Wire Wire Line + 3600 4600 4850 4600 +Connection ~ 3600 4050 +Wire Wire Line + 4250 2050 4850 2050 +Connection ~ 4250 2050 +Wire Wire Line + 2100 3700 4250 3700 +Wire Wire Line + 4250 1000 4250 5750 +Wire Wire Line + 4250 1000 4850 1000 +Wire Wire Line + 4250 1550 4850 1550 +Connection ~ 4250 1550 +Wire Wire Line + 4250 2550 4850 2550 +Connection ~ 4250 2550 +Wire Wire Line + 4250 5250 4850 5250 +Connection ~ 4250 3700 +Wire Wire Line + 4250 5750 4850 5750 +Connection ~ 4250 5250 +Wire Wire Line + 3850 3050 3850 4700 +Wire Wire Line + 3850 3050 4850 3050 +Wire Wire Line + 3850 4700 4850 4700 +Connection ~ 3850 4250 +Wire Wire Line + 4850 4150 3850 4150 +Wire Wire Line + 3850 4150 3850 4100 +Connection ~ 3850 4100 +Wire Wire Line + 4850 3600 3850 3600 +Connection ~ 3850 3600 +Wire Wire Line + 4850 5350 3500 5350 +Wire Wire Line + 3500 5350 3500 5850 +Wire Wire Line + 3500 5850 4850 5850 +Connection ~ 3500 5500 +Wire Wire Line + 2100 5000 4600 5000 +Wire Wire Line + 4600 5000 4600 1100 +Wire Wire Line + 4600 1100 4850 1100 +Wire Wire Line + 4600 1650 4850 1650 +Connection ~ 4600 1650 +Wire Wire Line + 4850 2150 4600 2150 +Connection ~ 4600 2150 +Wire Wire Line + 4850 2650 4600 2650 +Wire Wire Line + 4600 2650 4600 2700 +Connection ~ 4600 2700 +Wire Wire Line + 4850 3150 4600 3150 +Connection ~ 4600 3150 +Wire Wire Line + 4850 3700 4600 3700 +Connection ~ 4600 3700 +Wire Wire Line + 4850 4250 4600 4250 +Connection ~ 4600 4250 +Wire Wire Line + 4850 4800 4600 4800 +Connection ~ 4600 4800 +Wire Wire Line + 800 1100 1050 1100 +Connection ~ 1050 1100 +Wire Wire Line + 850 2350 1000 2350 +Connection ~ 1000 2350 +Wire Wire Line + 900 3700 1050 3700 +Connection ~ 1050 3700 +Wire Wire Line + 900 5000 1050 5000 +Connection ~ 1050 5000 +Wire Wire Line + 7300 4050 7800 4050 +Wire Wire Line + 7300 3450 7800 3450 +Wire Wire Line + 7350 2950 7800 2950 +Wire Wire Line + 7350 2500 7800 2500 +Wire Wire Line + 7350 2050 7800 2050 +Wire Wire Line + 7350 1500 7800 1500 +Wire Wire Line + 7350 900 7800 900 +Wire Wire Line + 7800 5700 7350 5700 +Wire Wire Line + 7800 5150 7350 5150 +Wire Wire Line + 7800 4650 7350 4650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS42/7442_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS42/7442_Previous_Values.xml new file mode 100644 index 00000000..b601edcc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/7442_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">1mv</v1><v1 name="Source type">1</v1><v1 name="Source type">sine<field1 name="Offset Value" /><field2 name="Amplitude">1</field2><field3 name="Frequency" /><field4 name="Delay Time" /><field5 name="Damping Factor" /></v1></source><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">true</field2><field3 name="Oct">false</field3><field4 name="Start Frequency">10</field4><field5 name="Stop Frequency">1</field5><field6 name="No. of points">10</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Meg</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">us</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS42/analysis b/library/SubcircuitLibrary/SN74LS42/analysis new file mode 100644 index 00000000..dd369dec --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42/analysis @@ -0,0 +1 @@ +.tran 10e-06 10e-03 1e-06
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib b/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib new file mode 100644 index 00000000..44055200 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib @@ -0,0 +1,92 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.cir b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir new file mode 100644 index 00000000..454fdb10 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir @@ -0,0 +1,19 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\7429\7429.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/12/25 14:38:38 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U6 Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U6-Pad3_ d_and +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U5-Pad3_ d_and +U9 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad4_ d_nand +U7 Net-_U2-Pad2_ Net-_U6-Pad3_ Net-_U1-Pad5_ d_nand +U8 Net-_U2-Pad2_ Net-_U5-Pad3_ Net-_U1-Pad6_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out new file mode 100644 index 00000000..182d14b6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out @@ -0,0 +1,44 @@ +* c:\fossee\esim\library\subcircuitlibrary\7429\7429.cir + +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u6 net-_u1-pad2_ net-_u4-pad2_ net-_u6-pad3_ d_and +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_and +* u9 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad4_ d_nand +* u7 net-_u2-pad2_ net-_u6-pad3_ net-_u1-pad5_ d_nand +* u8 net-_u2-pad2_ net-_u5-pad3_ net-_u1-pad6_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u6-pad3_ u6 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5 +a6 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u1-pad4_ u9 +a7 [net-_u2-pad2_ net-_u6-pad3_ ] net-_u1-pad5_ u7 +a8 [net-_u2-pad2_ net-_u5-pad3_ ] net-_u1-pad6_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.pro b/library/SubcircuitLibrary/SN74LVC1G29/7429.pro new file mode 100644 index 00000000..3d81b09e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.pro @@ -0,0 +1,83 @@ +update=05/12/25 17:58:53 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.sch b/library/SubcircuitLibrary/SN74LVC1G29/7429.sch new file mode 100644 index 00000000..56a2da46 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.sch @@ -0,0 +1,273 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 6821B961 +P 2600 2100 +F 0 "U2" H 2600 2000 60 0000 C CNN +F 1 "d_inverter" H 2600 2250 60 0000 C CNN +F 2 "" H 2650 2050 60 0000 C CNN +F 3 "" H 2650 2050 60 0000 C CNN + 1 2600 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6821B9A6 +P 3600 2600 +F 0 "U3" H 3600 2500 60 0000 C CNN +F 1 "d_inverter" H 3600 2750 60 0000 C CNN +F 2 "" H 3650 2550 60 0000 C CNN +F 3 "" H 3650 2550 60 0000 C CNN + 1 3600 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 6821B9C3 +P 5100 3050 +F 0 "U6" H 5100 3050 60 0000 C CNN +F 1 "d_and" H 5150 3150 60 0000 C CNN +F 2 "" H 5100 3050 60 0000 C CNN +F 3 "" H 5100 3050 60 0000 C CNN + 1 5100 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6821B9DE +P 3600 3550 +F 0 "U4" H 3600 3450 60 0000 C CNN +F 1 "d_inverter" H 3600 3700 60 0000 C CNN +F 2 "" H 3650 3500 60 0000 C CNN +F 3 "" H 3650 3500 60 0000 C CNN + 1 3600 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 6821BA03 +P 5050 4100 +F 0 "U5" H 5050 4100 60 0000 C CNN +F 1 "d_and" H 5100 4200 60 0000 C CNN +F 2 "" H 5050 4100 60 0000 C CNN +F 3 "" H 5050 4100 60 0000 C CNN + 1 5050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U9 +U 1 1 6821BA2A +P 7500 2100 +F 0 "U9" H 7500 2100 60 0000 C CNN +F 1 "d_nand" H 7550 2200 60 0000 C CNN +F 2 "" H 7500 2100 60 0000 C CNN +F 3 "" H 7500 2100 60 0000 C CNN + 1 7500 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6821BA51 +P 7450 3150 +F 0 "U7" H 7450 3150 60 0000 C CNN +F 1 "d_nand" H 7500 3250 60 0000 C CNN +F 2 "" H 7450 3150 60 0000 C CNN +F 3 "" H 7450 3150 60 0000 C CNN + 1 7450 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 6821BA7A +P 7450 4150 +F 0 "U8" H 7450 4150 60 0000 C CNN +F 1 "d_nand" H 7500 4250 60 0000 C CNN +F 2 "" H 7450 4150 60 0000 C CNN +F 3 "" H 7450 4150 60 0000 C CNN + 1 7450 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6821BAA5 +P 1750 2100 +F 0 "U1" H 1800 2200 30 0000 C CNN +F 1 "PORT" H 1750 2100 30 0000 C CNN +F 2 "" H 1750 2100 60 0000 C CNN +F 3 "" H 1750 2100 60 0000 C CNN + 1 1750 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6821BB1D +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6821BB4A +P 1750 3550 +F 0 "U1" H 1800 3650 30 0000 C CNN +F 1 "PORT" H 1750 3550 30 0000 C CNN +F 2 "" H 1750 3550 60 0000 C CNN +F 3 "" H 1750 3550 60 0000 C CNN + 3 1750 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6821BBE9 +P 8500 2050 +F 0 "U1" H 8550 2150 30 0000 C CNN +F 1 "PORT" H 8500 2050 30 0000 C CNN +F 2 "" H 8500 2050 60 0000 C CNN +F 3 "" H 8500 2050 60 0000 C CNN + 4 8500 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6821BC47 +P 8500 3100 +F 0 "U1" H 8550 3200 30 0000 C CNN +F 1 "PORT" H 8500 3100 30 0000 C CNN +F 2 "" H 8500 3100 60 0000 C CNN +F 3 "" H 8500 3100 60 0000 C CNN + 5 8500 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6821BC84 +P 8500 4100 +F 0 "U1" H 8550 4200 30 0000 C CNN +F 1 "PORT" H 8500 4100 30 0000 C CNN +F 2 "" H 8500 4100 60 0000 C CNN +F 3 "" H 8500 4100 60 0000 C CNN + 6 8500 4100 + -1 0 0 1 +$EndComp +Wire Wire Line + 2000 2100 2300 2100 +Wire Wire Line + 2000 2550 3300 2550 +Wire Wire Line + 3300 2550 3300 2600 +Wire Wire Line + 2000 3550 3300 3550 +Wire Wire Line + 3000 2550 3000 4000 +Wire Wire Line + 3000 2950 4650 2950 +Connection ~ 3000 2550 +Wire Wire Line + 3900 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 3050 +Wire Wire Line + 3000 4000 4600 4000 +Connection ~ 3000 2950 +Wire Wire Line + 2500 3550 2500 4100 +Wire Wire Line + 2500 4100 4600 4100 +Connection ~ 2500 3550 +Wire Wire Line + 2900 2100 6200 2100 +Wire Wire Line + 6200 2100 6200 2000 +Wire Wire Line + 6200 2000 7050 2000 +Wire Wire Line + 3900 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2100 +Wire Wire Line + 6300 2100 7050 2100 +Wire Wire Line + 5550 3000 6100 3000 +Wire Wire Line + 6100 3000 6100 3150 +Wire Wire Line + 6100 3150 7000 3150 +Wire Wire Line + 6750 2000 6750 4050 +Wire Wire Line + 6750 3050 7000 3050 +Connection ~ 6750 2000 +Wire Wire Line + 5500 4050 5900 4050 +Wire Wire Line + 5900 4050 5900 4150 +Wire Wire Line + 5900 4150 7000 4150 +Wire Wire Line + 6750 4050 7000 4050 +Connection ~ 6750 3050 +Wire Wire Line + 7950 2050 8250 2050 +Wire Wire Line + 7900 3100 8250 3100 +Wire Wire Line + 7900 4100 8250 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.sub b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub new file mode 100644 index 00000000..a3c8ad39 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub @@ -0,0 +1,38 @@ +* Subcircuit 7429 +.subckt 7429 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\fossee\esim\library\subcircuitlibrary\7429\7429.cir +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u6 net-_u1-pad2_ net-_u4-pad2_ net-_u6-pad3_ d_and +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_and +* u9 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad4_ d_nand +* u7 net-_u2-pad2_ net-_u6-pad3_ net-_u1-pad5_ d_nand +* u8 net-_u2-pad2_ net-_u5-pad3_ net-_u1-pad6_ d_nand +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u6-pad3_ u6 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5 +a6 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u1-pad4_ u9 +a7 [net-_u2-pad2_ net-_u6-pad3_ ] net-_u1-pad5_ u7 +a8 [net-_u2-pad2_ net-_u5-pad3_ ] net-_u1-pad6_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 7429
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml new file mode 100644 index 00000000..1a454041 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC1G29/analysis b/library/SubcircuitLibrary/SN74LVC1G29/analysis new file mode 100644 index 00000000..58ce5800 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/analysis @@ -0,0 +1 @@ +.tran 10e-03 10e-00 0e-03
\ No newline at end of file |