1 files changed, 93 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.cir.out b/library/SubcircuitLibrary/HD74LS139/74139.cir.out
new file mode 100644
index 00000000..21304303
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.cir.out
@@ -0,0 +1,93 @@
+* c:\fossee\esim\library\subcircuitlibrary\74139\74139.cir
+
+.include 3_and.sub
+x5 net-_u3-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and
+* u13  net-_u13-pad1_ net-_u1-pad7_ d_inverter
+x6 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u14-pad1_ 3_and
+* u14  net-_u14-pad1_ net-_u1-pad8_ d_inverter
+x7 net-_u2-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u18-pad1_ 3_and
+* u18  net-_u18-pad1_ net-_u1-pad9_ d_inverter
+x8 net-_u2-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u15-pad1_ 3_and
+* u15  net-_u15-pad1_ net-_u1-pad10_ d_inverter
+x1 net-_u11-pad1_ net-_u10-pad1_ net-_u7-pad2_ net-_u19-pad1_ 3_and
+* u19  net-_u19-pad1_ net-_u1-pad11_ d_inverter
+x2 net-_u7-pad2_ net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad1_ 3_and
+* u16  net-_u16-pad1_ net-_u1-pad12_ d_inverter
+x3 net-_u7-pad2_ net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad1_ 3_and
+* u17  net-_u17-pad1_ net-_u1-pad13_ d_inverter
+x4 net-_u7-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u12-pad1_ 3_and
+* u12  net-_u12-pad1_ net-_u1-pad14_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u5  net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u6  net-_u4-pad2_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad4_ net-_u7-pad2_ d_inverter
+* u9  net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8  net-_u1-pad6_ net-_u10-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+a1 net-_u13-pad1_ net-_u1-pad7_ u13
+a2 net-_u14-pad1_ net-_u1-pad8_ u14
+a3 net-_u18-pad1_ net-_u1-pad9_ u18
+a4 net-_u15-pad1_ net-_u1-pad10_ u15
+a5 net-_u19-pad1_ net-_u1-pad11_ u19
+a6 net-_u16-pad1_ net-_u1-pad12_ u16
+a7 net-_u17-pad1_ net-_u1-pad13_ u17
+a8 net-_u12-pad1_ net-_u1-pad14_ u12
+a9 net-_u1-pad1_ net-_u2-pad2_ u2
+a10 net-_u1-pad2_ net-_u3-pad2_ u3
+a11 net-_u3-pad2_ net-_u5-pad2_ u5
+a12 net-_u1-pad3_ net-_u4-pad2_ u4
+a13 net-_u4-pad2_ net-_u6-pad2_ u6
+a14 net-_u1-pad4_ net-_u7-pad2_ u7
+a15 net-_u1-pad5_ net-_u11-pad1_ u9
+a16 net-_u11-pad1_ net-_u11-pad2_ u11
+a17 net-_u1-pad6_ net-_u10-pad1_ u8
+a18 net-_u10-pad1_ net-_u10-pad2_ u10
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end