diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn74ls375')
15 files changed, 1337 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib new file mode 100644 index 00000000..ba413bed --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dlatch +# +DEF d_dlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dlatch" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X EN 2 -550 -300 200 R 50 50 1 1 I +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir new file mode 100644 index 00000000..6b47a2b0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir @@ -0,0 +1,15 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\375\375.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 23:29:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ ? ? Net-_U1-Pad3_ Net-_U1-Pad10_ d_dlatch +U3 Net-_U1-Pad4_ Net-_U1-Pad2_ ? ? Net-_U1-Pad5_ Net-_U1-Pad11_ d_dlatch +U4 Net-_U1-Pad6_ Net-_U1-Pad2_ ? ? Net-_U1-Pad7_ Net-_U1-Pad12_ d_dlatch +U5 Net-_U1-Pad8_ Net-_U1-Pad2_ ? ? Net-_U1-Pad9_ Net-_U1-Pad13_ d_dlatch +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out new file mode 100644 index 00000000..1b07f6fd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.cir.out @@ -0,0 +1,28 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch +* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch +* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch +* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2 +a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3 +a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4 +a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch new file mode 100644 index 00000000..2d5ef983 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sch @@ -0,0 +1,308 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:375-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dlatch U2 +U 1 1 6835F8D0 +P 3100 3000 +F 0 "U2" H 3100 3000 60 0000 C CNN +F 1 "d_dlatch" H 3100 3150 60 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 1 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U3 +U 1 1 6835F917 +P 4750 3000 +F 0 "U3" H 4750 3000 60 0000 C CNN +F 1 "d_dlatch" H 4750 3150 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U4 +U 1 1 6835F948 +P 6450 3000 +F 0 "U4" H 6450 3000 60 0000 C CNN +F 1 "d_dlatch" H 6450 3150 60 0000 C CNN +F 2 "" H 6450 3000 60 0000 C CNN +F 3 "" H 6450 3000 60 0000 C CNN + 1 6450 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U5 +U 1 1 6835F97D +P 8150 3000 +F 0 "U5" H 8150 3000 60 0000 C CNN +F 1 "d_dlatch" H 8150 3150 60 0000 C CNN +F 2 "" H 8150 3000 60 0000 C CNN +F 3 "" H 8150 3000 60 0000 C CNN + 1 8150 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 3300 2550 4350 +Wire Wire Line + 2550 4350 7600 4350 +Wire Wire Line + 7600 4350 7600 3300 +Wire Wire Line + 5900 3300 5850 3300 +Wire Wire Line + 5850 3300 5850 4350 +Connection ~ 5850 4350 +Wire Wire Line + 4200 3300 4000 3300 +Wire Wire Line + 4000 3300 4000 4350 +Connection ~ 4000 4350 +Wire Wire Line + 2550 2650 1950 2650 +Wire Wire Line + 1950 2650 1950 1750 +Wire Wire Line + 4200 2650 4000 2650 +Wire Wire Line + 4000 2650 4000 1650 +Wire Wire Line + 5900 2650 5700 2650 +Wire Wire Line + 5700 2650 5700 1650 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 1650 +Wire Wire Line + 3650 2650 3800 2650 +Wire Wire Line + 3800 2650 3800 4950 +Wire Wire Line + 5300 2650 5600 2650 +Wire Wire Line + 5600 2650 5600 5050 +Wire Wire Line + 7000 2650 7250 2650 +Wire Wire Line + 7250 2650 7250 5050 +Wire Wire Line + 8700 2650 9000 2650 +Wire Wire Line + 9000 2650 9000 5100 +$Comp +L PORT U1 +U 1 1 6835FA8C +P 1700 1750 +F 0 "U1" H 1750 1850 30 0000 C CNN +F 1 "PORT" H 1700 1750 30 0000 C CNN +F 2 "" H 1700 1750 60 0000 C CNN +F 3 "" H 1700 1750 60 0000 C CNN + 1 1700 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835FADB +P 3750 1650 +F 0 "U1" H 3800 1750 30 0000 C CNN +F 1 "PORT" H 3750 1650 30 0000 C CNN +F 2 "" H 3750 1650 60 0000 C CNN +F 3 "" H 3750 1650 60 0000 C CNN + 4 3750 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835FB28 +P 5450 1650 +F 0 "U1" H 5500 1750 30 0000 C CNN +F 1 "PORT" H 5450 1650 30 0000 C CNN +F 2 "" H 5450 1650 60 0000 C CNN +F 3 "" H 5450 1650 60 0000 C CNN + 6 5450 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835FB6B +P 7150 1650 +F 0 "U1" H 7200 1750 30 0000 C CNN +F 1 "PORT" H 7150 1650 30 0000 C CNN +F 2 "" H 7150 1650 60 0000 C CNN +F 3 "" H 7150 1650 60 0000 C CNN + 8 7150 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835FBC2 +P 2300 4350 +F 0 "U1" H 2350 4450 30 0000 C CNN +F 1 "PORT" H 2300 4350 30 0000 C CNN +F 2 "" H 2300 4350 60 0000 C CNN +F 3 "" H 2300 4350 60 0000 C CNN + 2 2300 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835FC17 +P 3550 4950 +F 0 "U1" H 3600 5050 30 0000 C CNN +F 1 "PORT" H 3550 4950 30 0000 C CNN +F 2 "" H 3550 4950 60 0000 C CNN +F 3 "" H 3550 4950 60 0000 C CNN + 3 3550 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835FC84 +P 5350 5050 +F 0 "U1" H 5400 5150 30 0000 C CNN +F 1 "PORT" H 5350 5050 30 0000 C CNN +F 2 "" H 5350 5050 60 0000 C CNN +F 3 "" H 5350 5050 60 0000 C CNN + 5 5350 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835FCDF +P 7000 5050 +F 0 "U1" H 7050 5150 30 0000 C CNN +F 1 "PORT" H 7000 5050 30 0000 C CNN +F 2 "" H 7000 5050 60 0000 C CNN +F 3 "" H 7000 5050 60 0000 C CNN + 7 7000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835FD3C +P 8750 5100 +F 0 "U1" H 8800 5200 30 0000 C CNN +F 1 "PORT" H 8750 5100 30 0000 C CNN +F 2 "" H 8750 5100 60 0000 C CNN +F 3 "" H 8750 5100 60 0000 C CNN + 9 8750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 3300 3650 4650 +Wire Wire Line + 3650 4650 3400 4650 +Wire Wire Line + 5300 3300 5300 4700 +Wire Wire Line + 5300 4700 5150 4700 +Wire Wire Line + 7000 3300 7000 4700 +Wire Wire Line + 7000 4700 6850 4700 +Wire Wire Line + 8700 3300 8700 4650 +Wire Wire Line + 8700 4650 8550 4650 +$Comp +L PORT U1 +U 10 1 6835FE64 +P 3150 4650 +F 0 "U1" H 3200 4750 30 0000 C CNN +F 1 "PORT" H 3150 4650 30 0000 C CNN +F 2 "" H 3150 4650 60 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 10 3150 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6835FEC7 +P 4900 4700 +F 0 "U1" H 4950 4800 30 0000 C CNN +F 1 "PORT" H 4900 4700 30 0000 C CNN +F 2 "" H 4900 4700 60 0000 C CNN +F 3 "" H 4900 4700 60 0000 C CNN + 11 4900 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6835FF20 +P 6600 4700 +F 0 "U1" H 6650 4800 30 0000 C CNN +F 1 "PORT" H 6600 4700 30 0000 C CNN +F 2 "" H 6600 4700 60 0000 C CNN +F 3 "" H 6600 4700 60 0000 C CNN + 12 6600 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6835FF77 +P 8300 4650 +F 0 "U1" H 8350 4750 30 0000 C CNN +F 1 "PORT" H 8300 4650 30 0000 C CNN +F 2 "" H 8300 4650 60 0000 C CNN +F 3 "" H 8300 4650 60 0000 C CNN + 13 8300 4650 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub new file mode 100644 index 00000000..2ebb644d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub @@ -0,0 +1,22 @@ +* Subcircuit 375 +.subckt 375 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch +* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch +* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch +* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch +a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2 +a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3 +a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4 +a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends 375
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml new file mode 100644 index 00000000..2eb57a73 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_dlatch<field1 name="Enter Data Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for Data Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_dlatch<field12 name="Enter Data Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_dlatch<field23 name="Enter Data Delay (default=1.0e-9)" /><field24 name="Enter Enable Delay (default=1.0e-9)" /><field25 name="Enter Set Delay (default=1.0e-9)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter IC (default=0)" /><field28 name="Enter value for Data Load (default=1.0e-12)" /><field29 name="Enter value for Enable Load (default=1.0e-12)" /><field30 name="Enter value for Set Load (default=1.0e-12)" /><field31 name="Enter value for Reset Load (default=1.0e-12)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_dlatch<field34 name="Enter Data Delay (default=1.0e-9)" /><field35 name="Enter Enable Delay (default=1.0e-9)" /><field36 name="Enter Set Delay (default=1.0e-9)" /><field37 name="Enter Reset Delay (default=1.0)" /><field38 name="Enter IC (default=0)" /><field39 name="Enter value for Data Load (default=1.0e-12)" /><field40 name="Enter value for Enable Load (default=1.0e-12)" /><field41 name="Enter value for Set Load (default=1.0e-12)" /><field42 name="Enter value for Reset Load (default=1.0e-12)" /><field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis new file mode 100644 index 00000000..f496aec4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/analysis @@ -0,0 +1 @@ +.tran 1e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib new file mode 100644 index 00000000..3154fa3d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 373 +# +DEF 373 X 0 40 Y Y 1 F N +F0 "X" -50 -200 60 H V C CNN +F1 "373" -50 700 60 H V C CNN +F2 "" -50 700 60 H I C CNN +F3 "" -50 700 60 H I C CNN +DRAW +S 200 650 -300 -150 0 1 0 N +X do 1 -500 600 200 R 50 50 1 1 I +X en 2 -500 150 200 R 50 50 1 1 I +X Q0 3 400 600 200 L 50 50 1 1 O +X d2 4 -500 500 200 R 50 50 1 1 I +X Q1 5 400 500 200 L 50 50 1 1 O +X d3 6 -500 400 200 R 50 50 1 1 I +X Q2 7 400 400 200 L 50 50 1 1 O +X d4 8 -500 300 200 R 50 50 1 1 I +X Q3 9 400 300 200 L 50 50 1 1 O +X Q0_1 10 400 200 200 L 50 50 1 1 O +X Q0_2 11 400 100 200 L 50 50 1 1 O +X Q0_3 12 400 0 200 L 50 50 1 1 O +X Q0_4 13 400 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_5 +# +DEF adc_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir new file mode 100644 index 00000000..4054588f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir @@ -0,0 +1,31 @@ +* C:\Users\Shanthipriya\eSim-Workspace\375_ic3\375_ic3.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 23:44:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v2 1D GND pulse +v3 2D GND pulse +v4 3D GND pulse +v5 4D GND pulse +v1 E GND pulse +U4 Q0 plot_v1 +U5 Q1 plot_v1 +U6 Q2 plot_v1 +U7 Q3 plot_v1 +U8 Q0_1 plot_v1 +U9 Q0_2 plot_v1 +U10 Q0_3 plot_v1 +U3 Q0_4 plot_v1 +U1 1D E 2D 3D 4D Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_5 +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Q0 Q1 Q2 Q3 Q0_1 Q0_2 Q0_3 Q0_4 dac_bridge_8 +X1 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U2-Pad1_ Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad9_ Net-_U2-Pad3_ Net-_U1-Pad10_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ 373 +U13 1D plot_v1 +U14 E plot_v1 +U15 2D plot_v1 +U11 3D plot_v1 +U12 4D plot_v1 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out new file mode 100644 index 00000000..0e2b2b72 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.cir.out @@ -0,0 +1,43 @@ +* c:\users\shanthipriya\esim-workspace\375_ic3\375_ic3.cir + +.include 375.sub +v2 1d gnd pulse(0 5 0 1n 1n 4m 8m) +v3 2d gnd pulse(0 5 0 1n 1n 8m 16m) +v4 3d gnd pulse(0 5 0 1n 1n 16m 32m) +v5 4d gnd pulse(0 5 0 1n 1n 32m 64m) +v1 e gnd pulse(0 5 0 1n 1n 2m 4m) +* u4 q0 plot_v1 +* u5 q1 plot_v1 +* u6 q2 plot_v1 +* u7 q3 plot_v1 +* u8 q0_1 plot_v1 +* u9 q0_2 plot_v1 +* u10 q0_3 plot_v1 +* u3 q0_4 plot_v1 +* u1 1d e 2d 3d 4d net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ adc_bridge_5 +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ q0 q1 q2 q3 q0_1 q0_2 q0_3 q0_4 dac_bridge_8 +x1 net-_u1-pad6_ net-_u1-pad7_ net-_u2-pad1_ net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad9_ net-_u2-pad3_ net-_u1-pad10_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ 375 +* u13 1d plot_v1 +* u14 e plot_v1 +* u15 2d plot_v1 +* u11 3d plot_v1 +* u12 4d plot_v1 +a1 [1d e 2d 3d 4d ] [net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] [q0 q1 q2 q3 q0_1 q0_2 q0_3 q0_4 ] u2 +* Schematic Name: adc_bridge_5, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(1d)+6 v(e)+12v(q0)+18v(q0_1) +plot v(2d)+6 v(e)+12v(q1)+18 v(q0_2) +plot v(3d)+6 v(e)+12v(q2)+18v(q0_3) +plot v(4d)6 v(e)+12v(q3)+18v(q0_4) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj new file mode 100644 index 00000000..07f4ec98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.proj @@ -0,0 +1 @@ +schematicFile 375_ic3.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch new file mode 100644 index 00000000..142db262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375.sch @@ -0,0 +1,550 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:375_ic3-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 2250 2600 3550 2600 +Wire Wire Line + 1750 1950 3650 1950 +Wire Wire Line + 1750 3450 3500 3450 +Wire Wire Line + 2800 4850 1750 4850 +Wire Wire Line + 1750 6300 2900 6300 +$Comp +L pulse v2 +U 1 1 6835FCBB +P 1750 2400 +F 0 "v2" H 1550 2500 60 0000 C CNN +F 1 "pulse" H 1550 2350 60 0000 C CNN +F 2 "R1" H 1450 2400 60 0000 C CNN +F 3 "" H 1750 2400 60 0000 C CNN + 1 1750 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6835FCBC +P 1750 3000 +F 0 "#PWR01" H 1750 2750 50 0001 C CNN +F 1 "GND" H 1750 2850 50 0000 C CNN +F 2 "" H 1750 3000 50 0001 C CNN +F 3 "" H 1750 3000 50 0001 C CNN + 1 1750 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 3000 1750 2850 +$Comp +L pulse v3 +U 1 1 6835FCBD +P 1750 3900 +F 0 "v3" H 1550 4000 60 0000 C CNN +F 1 "pulse" H 1550 3850 60 0000 C CNN +F 2 "R1" H 1450 3900 60 0000 C CNN +F 3 "" H 1750 3900 60 0000 C CNN + 1 1750 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6835FCBE +P 1750 4500 +F 0 "#PWR02" H 1750 4250 50 0001 C CNN +F 1 "GND" H 1750 4350 50 0000 C CNN +F 2 "" H 1750 4500 50 0001 C CNN +F 3 "" H 1750 4500 50 0001 C CNN + 1 1750 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 4500 1750 4350 +$Comp +L pulse v4 +U 1 1 6835FCBF +P 1750 5300 +F 0 "v4" H 1550 5400 60 0000 C CNN +F 1 "pulse" H 1550 5250 60 0000 C CNN +F 2 "R1" H 1450 5300 60 0000 C CNN +F 3 "" H 1750 5300 60 0000 C CNN + 1 1750 5300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 6835FCC0 +P 1750 5900 +F 0 "#PWR03" H 1750 5650 50 0001 C CNN +F 1 "GND" H 1750 5750 50 0000 C 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0000 C CNN +F 2 "" H 2600 3350 60 0000 C CNN +F 3 "" H 2600 3350 60 0000 C CNN + 1 2600 3350 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 68360D2A +P 2150 4650 +F 0 "U11" H 2150 5150 60 0000 C CNN +F 1 "plot_v1" H 2350 5000 60 0000 C CNN +F 2 "" H 2150 4650 60 0000 C CNN +F 3 "" H 2150 4650 60 0000 C CNN + 1 2150 4650 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 68360D89 +P 2150 6000 +F 0 "U12" H 2150 6500 60 0000 C CNN +F 1 "plot_v1" H 2350 6350 60 0000 C CNN +F 2 "" H 2150 6000 60 0000 C CNN +F 3 "" H 2150 6000 60 0000 C CNN + 1 2150 6000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml new file mode 100644 index 00000000..5035a68a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/sn74ls375_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">32m</field5><field5 name="Period">64m</field5></v5><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v1></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\375</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
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