diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls72')
37 files changed, 2524 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis new file mode 100644 index 00000000..c178a1dc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/analysis @@ -0,0 +1 @@ +.tran 1e-09 5e-06 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib new file mode 100644 index 00000000..1cdee83e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir new file mode 100644 index 00000000..f3277b9f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72\internal72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:40:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ d_nand +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U7 Net-_U5-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_dff +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_dff +U6 Net-_U1-Pad2_ Net-_U6-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ ? ? Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out new file mode 100644 index 00000000..ec11a6c2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir + +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch new file mode 100644 index 00000000..a5f97c98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:internal72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 68314F2B +P 4150 2800 +F 0 "U3" H 4150 2800 60 0000 C CNN +F 1 "d_nand" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68314FDD +P 4150 3350 +F 0 "U4" H 4150 3350 60 0000 C CNN +F 1 "d_nand" H 4200 3450 60 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 1 4150 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68315038 +P 5250 3100 +F 0 "U5" H 5250 3100 60 0000 C CNN +F 1 "d_nand" H 5300 3200 60 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 2750 4800 2750 +Wire Wire Line + 4800 2750 4800 3000 +Wire Wire Line + 4600 3300 4800 3300 +Wire Wire Line + 4800 3300 4800 3100 +$Comp +L d_inverter U2 +U 1 1 68315089 +P 3200 3250 +F 0 "U2" H 3200 3150 60 0000 C CNN +F 1 "d_inverter" H 3200 3400 60 0000 C CNN +F 2 "" H 3250 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3200 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 3250 3700 3250 +Wire Wire Line + 3700 2800 2600 2800 +Wire Wire Line + 2650 3250 2900 3250 +$Comp +L d_dff U7 +U 1 1 683150F6 +P 6850 3400 +F 0 "U7" H 6850 3400 60 0000 C CNN +F 1 "d_dff" H 6850 3550 60 0000 C CNN +F 2 "" H 6850 3400 60 0000 C CNN +F 3 "" H 6850 3400 60 0000 C CNN + 1 6850 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 68315165 +P 8650 3400 +F 0 "U8" H 8650 3400 60 0000 C CNN +F 1 "d_dff" H 8650 3550 60 0000 C CNN +F 2 "" H 8650 3400 60 0000 C CNN +F 3 "" H 8650 3400 60 0000 C CNN + 1 8650 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3050 6300 3050 +Wire Wire Line + 3700 3350 3400 3350 +Wire Wire Line + 3400 3350 3400 4300 +Wire Wire Line + 3400 4300 7650 4300 +Wire Wire Line + 7400 3050 8100 3050 +Wire Wire Line + 7650 4300 7650 3050 +Connection ~ 7650 3050 +Wire Wire Line + 7400 3700 7700 3700 +Wire Wire Line + 7700 3700 7700 1950 +Wire Wire Line + 7700 1950 3400 1950 +Wire Wire Line + 3400 1950 3400 2700 +Wire Wire Line + 3400 2700 3700 2700 +Wire Wire Line + 6300 3700 2600 3700 +$Comp +L d_inverter U6 +U 1 1 68315227 +P 6300 4750 +F 0 "U6" H 6300 4650 60 0000 C CNN +F 1 "d_inverter" H 6300 4900 60 0000 C CNN +F 2 "" H 6350 4700 60 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6300 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3700 +Connection ~ 5550 3700 +Wire Wire Line + 6600 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 3700 +Wire Wire Line + 7900 3700 8100 3700 +Wire Wire Line + 6850 4200 8650 4200 +Wire Wire Line + 8650 4000 8650 5000 +Connection ~ 8650 4200 +Wire Wire Line + 6850 2750 6850 2350 +Wire Wire Line + 6850 2350 8650 2350 +Wire Wire Line + 8650 1400 8650 2750 +Connection ~ 8650 2350 +Wire Wire Line + 6850 4200 6850 4000 +$Comp +L PORT U1 +U 1 1 683153A5 +P 2350 2800 +F 0 "U1" H 2400 2900 30 0000 C CNN +F 1 "PORT" H 2350 2800 30 0000 C CNN +F 2 "" H 2350 2800 60 0000 C CNN +F 3 "" H 2350 2800 60 0000 C CNN + 1 2350 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 683153DC +P 2400 3250 +F 0 "U1" H 2450 3350 30 0000 C CNN +F 1 "PORT" H 2400 3250 30 0000 C CNN +F 2 "" H 2400 3250 60 0000 C CNN +F 3 "" H 2400 3250 60 0000 C CNN + 3 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6831542D +P 2350 3700 +F 0 "U1" H 2400 3800 30 0000 C CNN +F 1 "PORT" H 2350 3700 30 0000 C CNN +F 2 "" H 2350 3700 60 0000 C CNN +F 3 "" H 2350 3700 60 0000 C CNN + 2 2350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6831548B +P 8400 5000 +F 0 "U1" H 8450 5100 30 0000 C CNN +F 1 "PORT" H 8400 5000 30 0000 C CNN +F 2 "" H 8400 5000 60 0000 C CNN +F 3 "" H 8400 5000 60 0000 C CNN + 7 8400 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68315516 +P 8400 1400 +F 0 "U1" H 8450 1500 30 0000 C CNN +F 1 "PORT" H 8400 1400 30 0000 C CNN +F 2 "" H 8400 1400 60 0000 C CNN +F 3 "" H 8400 1400 60 0000 C CNN + 6 8400 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68315583 +P 9450 3050 +F 0 "U1" H 9500 3150 30 0000 C CNN +F 1 "PORT" H 9450 3050 30 0000 C CNN +F 2 "" H 9450 3050 60 0000 C CNN +F 3 "" H 9450 3050 60 0000 C CNN + 8 9450 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 683155FA +P 9450 3700 +F 0 "U1" H 9500 3800 30 0000 C CNN +F 1 "PORT" H 9450 3700 30 0000 C CNN +F 2 "" H 9450 3700 60 0000 C CNN +F 3 "" H 9450 3700 60 0000 C CNN + 9 9450 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6831563D +P 7050 5450 +F 0 "U1" H 7100 5550 30 0000 C CNN +F 1 "PORT" H 7050 5450 30 0000 C CNN +F 2 "" H 7050 5450 60 0000 C CNN +F 3 "" H 7050 5450 60 0000 C CNN + 4 7050 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68315682 +P 7050 5650 +F 0 "U1" H 7100 5750 30 0000 C CNN +F 1 "PORT" H 7050 5650 30 0000 C CNN +F 2 "" H 7050 5650 60 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 5 7050 5650 + 1 0 0 -1 +$EndComp +NoConn ~ 7300 5450 +NoConn ~ 7300 5650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub new file mode 100644 index 00000000..4ff0c262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72.sub @@ -0,0 +1,34 @@ +* Subcircuit internal72 +.subckt internal72 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends internal72
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml new file mode 100644 index 00000000..ec31c02b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internal72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /></u3><u3 name="type">d_srlatch<field1 name="Enter SR Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for SR Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_srlatch<field12 name="Enter SR Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for SR Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u6><u2 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_and<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_dff<field13 name="Enter Clk Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Clk Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">d_dff<field23 name="Enter Clk Delay (default=1.0e-9)" /><field24 name="Enter Set Delay (default=1.0e-9)" /><field25 name="Enter Reset Delay (default=1.0)" /><field26 name="Enter IC (default=0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter value for Clk Load (default=1.0e-12)" /><field29 name="Enter value for Set Load (default=1.0e-12)" /><field30 name="Enter value for Reset Load (default=1.0e-12)" /><field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib new file mode 100644 index 00000000..1cdee83e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir new file mode 100644 index 00000000..f3277b9f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72\internal72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:40:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ d_nand +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U7 Net-_U5-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_dff +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_dff +U6 Net-_U1-Pad2_ Net-_U6-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ ? ? Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out new file mode 100644 index 00000000..ec11a6c2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir + +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch new file mode 100644 index 00000000..a5f97c98 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:internal72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 68314F2B +P 4150 2800 +F 0 "U3" H 4150 2800 60 0000 C CNN +F 1 "d_nand" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68314FDD +P 4150 3350 +F 0 "U4" H 4150 3350 60 0000 C CNN +F 1 "d_nand" H 4200 3450 60 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 1 4150 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68315038 +P 5250 3100 +F 0 "U5" H 5250 3100 60 0000 C CNN +F 1 "d_nand" H 5300 3200 60 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 2750 4800 2750 +Wire Wire Line + 4800 2750 4800 3000 +Wire Wire Line + 4600 3300 4800 3300 +Wire Wire Line + 4800 3300 4800 3100 +$Comp +L d_inverter U2 +U 1 1 68315089 +P 3200 3250 +F 0 "U2" H 3200 3150 60 0000 C CNN +F 1 "d_inverter" H 3200 3400 60 0000 C CNN +F 2 "" H 3250 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3200 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 3250 3700 3250 +Wire Wire Line + 3700 2800 2600 2800 +Wire Wire Line + 2650 3250 2900 3250 +$Comp +L d_dff U7 +U 1 1 683150F6 +P 6850 3400 +F 0 "U7" H 6850 3400 60 0000 C CNN +F 1 "d_dff" H 6850 3550 60 0000 C CNN +F 2 "" H 6850 3400 60 0000 C CNN +F 3 "" H 6850 3400 60 0000 C CNN + 1 6850 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 68315165 +P 8650 3400 +F 0 "U8" H 8650 3400 60 0000 C CNN +F 1 "d_dff" H 8650 3550 60 0000 C CNN +F 2 "" H 8650 3400 60 0000 C CNN +F 3 "" H 8650 3400 60 0000 C CNN + 1 8650 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 3050 6300 3050 +Wire Wire Line + 3700 3350 3400 3350 +Wire Wire Line + 3400 3350 3400 4300 +Wire Wire Line + 3400 4300 7650 4300 +Wire Wire Line + 7400 3050 8100 3050 +Wire Wire Line + 7650 4300 7650 3050 +Connection ~ 7650 3050 +Wire Wire Line + 7400 3700 7700 3700 +Wire Wire Line + 7700 3700 7700 1950 +Wire Wire Line + 7700 1950 3400 1950 +Wire Wire Line + 3400 1950 3400 2700 +Wire Wire Line + 3400 2700 3700 2700 +Wire Wire Line + 6300 3700 2600 3700 +$Comp +L d_inverter U6 +U 1 1 68315227 +P 6300 4750 +F 0 "U6" H 6300 4650 60 0000 C CNN +F 1 "d_inverter" H 6300 4900 60 0000 C CNN +F 2 "" H 6350 4700 60 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6300 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3700 +Connection ~ 5550 3700 +Wire Wire Line + 6600 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 3700 +Wire Wire Line + 7900 3700 8100 3700 +Wire Wire Line + 6850 4200 8650 4200 +Wire Wire Line + 8650 4000 8650 5000 +Connection ~ 8650 4200 +Wire Wire Line + 6850 2750 6850 2350 +Wire Wire Line + 6850 2350 8650 2350 +Wire Wire Line + 8650 1400 8650 2750 +Connection ~ 8650 2350 +Wire Wire Line + 6850 4200 6850 4000 +$Comp +L PORT U1 +U 1 1 683153A5 +P 2350 2800 +F 0 "U1" H 2400 2900 30 0000 C CNN +F 1 "PORT" H 2350 2800 30 0000 C CNN +F 2 "" H 2350 2800 60 0000 C CNN +F 3 "" H 2350 2800 60 0000 C CNN + 1 2350 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 683153DC +P 2400 3250 +F 0 "U1" H 2450 3350 30 0000 C CNN +F 1 "PORT" H 2400 3250 30 0000 C CNN +F 2 "" H 2400 3250 60 0000 C CNN +F 3 "" H 2400 3250 60 0000 C CNN + 3 2400 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6831542D +P 2350 3700 +F 0 "U1" H 2400 3800 30 0000 C CNN +F 1 "PORT" H 2350 3700 30 0000 C CNN +F 2 "" H 2350 3700 60 0000 C CNN +F 3 "" H 2350 3700 60 0000 C CNN + 2 2350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6831548B +P 8400 5000 +F 0 "U1" H 8450 5100 30 0000 C CNN +F 1 "PORT" H 8400 5000 30 0000 C CNN +F 2 "" H 8400 5000 60 0000 C CNN +F 3 "" H 8400 5000 60 0000 C CNN + 7 8400 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68315516 +P 8400 1400 +F 0 "U1" H 8450 1500 30 0000 C CNN +F 1 "PORT" H 8400 1400 30 0000 C CNN +F 2 "" H 8400 1400 60 0000 C CNN +F 3 "" H 8400 1400 60 0000 C CNN + 6 8400 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68315583 +P 9450 3050 +F 0 "U1" H 9500 3150 30 0000 C CNN +F 1 "PORT" H 9450 3050 30 0000 C CNN +F 2 "" H 9450 3050 60 0000 C CNN +F 3 "" H 9450 3050 60 0000 C CNN + 8 9450 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 683155FA +P 9450 3700 +F 0 "U1" H 9500 3800 30 0000 C CNN +F 1 "PORT" H 9450 3700 30 0000 C CNN +F 2 "" H 9450 3700 60 0000 C CNN +F 3 "" H 9450 3700 60 0000 C CNN + 9 9450 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6831563D +P 7050 5450 +F 0 "U1" H 7100 5550 30 0000 C CNN +F 1 "PORT" H 7050 5450 30 0000 C CNN +F 2 "" H 7050 5450 60 0000 C CNN +F 3 "" H 7050 5450 60 0000 C CNN + 4 7050 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68315682 +P 7050 5650 +F 0 "U1" H 7100 5750 30 0000 C CNN +F 1 "PORT" H 7050 5650 30 0000 C CNN +F 2 "" H 7050 5650 60 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 5 7050 5650 + 1 0 0 -1 +$EndComp +NoConn ~ 7300 5450 +NoConn ~ 7300 5650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub new file mode 100644 index 00000000..4ff0c262 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.sub @@ -0,0 +1,34 @@ +* Subcircuit internal72 +.subckt internal72 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir +* u3 net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u7 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff +* u8 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff +* u6 net-_u1-pad2_ net-_u6-pad2_ d_inverter +a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5 +a4 net-_u1-pad3_ net-_u2-pad2_ u2 +a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7 +a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8 +a7 net-_u1-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends internal72
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml new file mode 100644 index 00000000..ec31c02b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /></u3><u3 name="type">d_srlatch<field1 name="Enter SR Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for SR Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_srlatch<field12 name="Enter SR Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for SR Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u6><u2 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_and<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_dff<field13 name="Enter Clk Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Clk Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">d_dff<field23 name="Enter Clk Delay (default=1.0e-9)" /><field24 name="Enter Set Delay (default=1.0e-9)" /><field25 name="Enter Reset Delay (default=1.0)" /><field26 name="Enter IC (default=0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter value for Clk Load (default=1.0e-12)" /><field29 name="Enter value for Set Load (default=1.0e-12)" /><field30 name="Enter value for Reset Load (default=1.0e-12)" /><field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir new file mode 100644 index 00000000..2a7b848b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir @@ -0,0 +1,17 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\jkff\jkff.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/13/25 23:38:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_nand +U6 Net-_U4-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad4_ d_nand +U7 Net-_U1-Pad4_ Net-_U5-Pad3_ Net-_U1-Pad5_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out new file mode 100644 index 00000000..03c161c5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.cir.out @@ -0,0 +1,36 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\jkff\jkff.cir + +* u2 net-_u1-pad5_ net-_u1-pad1_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad2_ net-_u5-pad3_ d_nand +* u6 net-_u4-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u7 net-_u1-pad4_ net-_u5-pad3_ net-_u1-pad5_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad5_ net-_u1-pad1_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u6 +a6 [net-_u1-pad4_ net-_u5-pad3_ ] net-_u1-pad5_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch new file mode 100644 index 00000000..82e3efd9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sch @@ -0,0 +1,230 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 68238979 +P 3900 2300 +F 0 "U2" H 3900 2300 60 0000 C CNN +F 1 "d_nand" H 3950 2400 60 0000 C CNN +F 2 "" H 3900 2300 60 0000 C CNN +F 3 "" H 3900 2300 60 0000 C CNN + 1 3900 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6823899E +P 4900 2350 +F 0 "U4" H 4900 2350 60 0000 C CNN +F 1 "d_nand" H 4950 2450 60 0000 C CNN +F 2 "" H 4900 2350 60 0000 C CNN +F 3 "" H 4900 2350 60 0000 C CNN + 1 4900 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 68238A3B +P 3900 3500 +F 0 "U3" H 3900 3500 60 0000 C CNN +F 1 "d_nand" H 3950 3600 60 0000 C CNN +F 2 "" H 3900 3500 60 0000 C CNN +F 3 "" H 3900 3500 60 0000 C CNN + 1 3900 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68238A41 +P 4950 3550 +F 0 "U5" H 4950 3550 60 0000 C CNN +F 1 "d_nand" H 5000 3650 60 0000 C CNN +F 2 "" H 4950 3550 60 0000 C CNN +F 3 "" H 4950 3550 60 0000 C CNN + 1 4950 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 2250 4350 2250 +Wire Wire Line + 4500 3450 4350 3450 +$Comp +L d_nand U6 +U 1 1 68238A9E +P 6300 2400 +F 0 "U6" H 6300 2400 60 0000 C CNN +F 1 "d_nand" H 6350 2500 60 0000 C CNN +F 2 "" H 6300 2400 60 0000 C CNN +F 3 "" H 6300 2400 60 0000 C CNN + 1 6300 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 68238B01 +P 6300 3500 +F 0 "U7" H 6300 3500 60 0000 C CNN +F 1 "d_nand" H 6350 3600 60 0000 C CNN +F 2 "" H 6300 3500 60 0000 C CNN +F 3 "" H 6300 3500 60 0000 C CNN + 1 6300 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3450 2200 3450 1950 +Wire Wire Line + 3450 1950 7250 1950 +Wire Wire Line + 6750 2350 7600 2350 +Wire Wire Line + 6750 3450 7650 3450 +Wire Wire Line + 7250 1950 7250 3450 +Connection ~ 7250 3450 +Wire Wire Line + 7100 2350 7100 3850 +Wire Wire Line + 7100 3850 3450 3850 +Wire Wire Line + 3450 3850 3450 3500 +Connection ~ 7100 2350 +Wire Wire Line + 7000 2350 7000 3050 +Wire Wire Line + 7000 3050 5850 3050 +Wire Wire Line + 5850 3050 5850 3400 +Connection ~ 7000 2350 +Wire Wire Line + 5850 2400 5850 2800 +Wire Wire Line + 5850 2800 6900 2800 +Wire Wire Line + 6900 2800 6900 3450 +Connection ~ 6900 3450 +Wire Wire Line + 5850 2300 5350 2300 +Wire Wire Line + 5850 3500 5400 3500 +Wire Wire Line + 4450 2350 4400 2350 +Wire Wire Line + 4400 2350 4400 3550 +Wire Wire Line + 4400 3550 4500 3550 +Wire Wire Line + 3450 2300 3000 2300 +Wire Wire Line + 3450 3400 3000 3400 +Wire Wire Line + 4400 2800 3000 2800 +Connection ~ 4400 2800 +$Comp +L PORT U1 +U 1 1 68238C95 +P 2750 2300 +F 0 "U1" H 2800 2400 30 0000 C CNN +F 1 "PORT" H 2750 2300 30 0000 C CNN +F 2 "" H 2750 2300 60 0000 C CNN +F 3 "" H 2750 2300 60 0000 C CNN + 1 2750 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68238CDA +P 2750 2800 +F 0 "U1" H 2800 2900 30 0000 C CNN +F 1 "PORT" H 2750 2800 30 0000 C CNN +F 2 "" H 2750 2800 60 0000 C CNN +F 3 "" H 2750 2800 60 0000 C CNN + 2 2750 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68238D13 +P 2750 3400 +F 0 "U1" H 2800 3500 30 0000 C CNN +F 1 "PORT" H 2750 3400 30 0000 C CNN +F 2 "" H 2750 3400 60 0000 C CNN +F 3 "" H 2750 3400 60 0000 C CNN + 3 2750 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68238D5C +P 7850 2350 +F 0 "U1" H 7900 2450 30 0000 C CNN +F 1 "PORT" H 7850 2350 30 0000 C CNN +F 2 "" H 7850 2350 60 0000 C CNN +F 3 "" H 7850 2350 60 0000 C CNN + 4 7850 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68238DF5 +P 7900 3450 +F 0 "U1" H 7950 3550 30 0000 C CNN +F 1 "PORT" H 7900 3450 30 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 5 7900 3450 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub new file mode 100644 index 00000000..2d292618 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff.sub @@ -0,0 +1,30 @@ +* Subcircuit jkff +.subckt jkff net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\jkff\jkff.cir +* u2 net-_u1-pad5_ net-_u1-pad1_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad2_ net-_u5-pad3_ d_nand +* u6 net-_u4-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u7 net-_u1-pad4_ net-_u5-pad3_ net-_u1-pad5_ d_nand +a1 [net-_u1-pad5_ net-_u1-pad1_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u6 +a6 [net-_u1-pad4_ net-_u5-pad3_ ] net-_u1-pad5_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends jkff
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml new file mode 100644 index 00000000..2493eac7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/jkff_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib new file mode 100644 index 00000000..d4d3e35d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# internal72 +# +DEF internal72 x 0 40 Y Y 1 F N +F0 "x" 0 -150 60 H V C CNN +F1 "internal72" 0 650 60 H V C CNN +F2 "" 0 -150 60 H I C CNN +F3 "" 0 -150 60 H I C CNN +DRAW +S 200 550 -250 -100 0 1 0 N +X j 1 -450 500 200 R 50 50 1 1 I +X clk 2 -450 400 200 R 50 50 1 1 I +X k 3 -450 300 200 R 50 50 1 1 I +X vcc 4 -450 0 200 R 50 50 1 1 I +X gnd 5 400 450 200 L 50 50 1 1 O +X pre 6 -450 200 200 R 50 50 1 1 I +X clr 7 -450 100 200 R 50 50 1 1 I +X Q 8 400 350 200 L 50 50 1 1 O +X Qnot 9 400 250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib new file mode 100644 index 00000000..00ebd155 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72-rescue.lib @@ -0,0 +1,25 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# internal72-RESCUE-72 +# +DEF internal72-RESCUE-72 x 0 40 Y Y 1 F N +F0 "x" 0 -150 60 H V C CNN +F1 "internal72-RESCUE-72" 0 650 60 H V C CNN +F2 "" 0 -150 60 H I C CNN +F3 "" 0 -150 60 H I C CNN +DRAW +S 200 550 -250 -100 0 1 0 N +X j 1 -450 500 200 R 50 50 1 1 I +X k 2 -450 300 200 R 50 50 1 1 I +X clk 3 -450 400 200 R 50 50 1 1 I +X pre 4 -450 200 200 R 50 50 1 1 I +X gnd 5 400 450 200 L 50 50 1 1 O +X vcc 6 -450 0 200 R 50 50 1 1 I +X clr 7 -450 100 200 R 50 50 1 1 I +X Q 8 400 350 200 L 50 50 1 1 O +X Qnot 9 400 250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir new file mode 100644 index 00000000..cbc2fbb8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir @@ -0,0 +1,24 @@ +* C:\Users\Shanthipriya\eSim-Workspace\72\72.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 09:48:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Qnot plot_v1 +U7 Q plot_v1 +U3 k plot_v1 +U1 j plot_v1 +U2 clk plot_v1 +v3 k GND pulse +v2 clk GND pulse +v1 j GND pulse +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Q Qnot dac_bridge_2 +U5 j clk k Net-_U5-Pad4_ Net-_U5-Pad5_ Net-_U5-Pad6_ adc_bridge_3 +x1 Net-_U5-Pad4_ Net-_U5-Pad5_ Net-_U5-Pad6_ ? ? Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_U6-Pad1_ Net-_U6-Pad2_ internal72 +v4 pre GND DC +U4 pre clr Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2 +v5 clr GND DC + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out new file mode 100644 index 00000000..f43756bd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.cir.out @@ -0,0 +1,36 @@ +* c:\users\shanthipriya\esim-workspace\72\72.cir + +.include internal72.sub +* u8 qnot plot_v1 +* u7 q plot_v1 +* u3 k plot_v1 +* u1 j plot_v1 +* u2 clk plot_v1 +v3 k gnd pulse(5 0 0.3u 1n 1n 1u 2.1u) +v2 clk gnd pulse(0 5 0.1u 1n 1n 20n 45n) +v1 j gnd pulse(0 5 0.5u 1n 1n 1u 2.1u) +* u6 net-_u6-pad1_ net-_u6-pad2_ q qnot dac_bridge_2 +* u5 j clk k net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ adc_bridge_3 +x1 net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ ? ? net-_u4-pad3_ net-_u4-pad4_ net-_u6-pad1_ net-_u6-pad2_ internal72 +v4 pre gnd dc 0 +* u4 pre clr net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +v5 clr gnd dc 0 +a1 [net-_u6-pad1_ net-_u6-pad2_ ] [q qnot ] u6 +a2 [j clk k ] [net-_u5-pad4_ net-_u5-pad5_ net-_u5-pad6_ ] u5 +a3 [pre clr ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 1e-09 5e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(qnot)+6 v(q)+12 v(k)+18 v(j)+24 v(clk) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro new file mode 100644 index 00000000..ae6dd82f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.pro @@ -0,0 +1,74 @@ +update=05/23/25 21:51:07 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=72-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj new file mode 100644 index 00000000..a16f094e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.proj @@ -0,0 +1 @@ +schematicFile 72.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch new file mode 100644 index 00000000..658788a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72.sch @@ -0,0 +1,375 @@ +EESchema Schematic File Version 2 +LIBS:72-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:72-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 8450 3250 +Wire Wire Line + 8450 2850 8450 3250 +Wire Wire Line + 8350 2850 8450 2850 +Text GLabel 8350 2850 0 60 Input ~ 0 +Qnot +Connection ~ 7850 3150 +Wire Wire Line + 7850 2800 7850 3150 +Wire Wire Line + 7550 2800 7850 2800 +Text GLabel 7550 2800 0 60 Input ~ 0 +Q +Connection ~ 2250 2750 +Wire Wire Line + 1850 2750 2250 2750 +Text GLabel 1850 2750 0 60 Input ~ 0 +k +Connection ~ 1050 2550 +Wire Wire Line + 650 2550 1050 2550 +Text GLabel 650 2550 0 60 Input ~ 0 +j +Connection ~ 1600 2600 +Wire Wire Line + 1300 2600 1600 2600 +Text GLabel 1300 2600 0 60 Input ~ 0 +clk +Wire Wire Line + 8650 3250 7400 3250 +Wire Wire Line + 8650 2700 8650 3250 +Wire Wire Line + 8000 3150 7400 3150 +Wire Wire Line + 8000 2700 8000 3150 +Connection ~ 2250 3200 +Wire Wire Line + 2250 2250 2250 3200 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U6 +U 1 1 68302144 +P 6850 3200 +F 0 "U6" H 6850 3200 60 0000 C CNN +F 1 "dac_bridge_2" H 6900 3350 60 0000 C CNN +F 2 "" H 6850 3200 60 0000 C CNN +F 3 "" H 6850 3200 60 0000 C CNN + 1 6850 3200 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U5 +U 1 1 68302143 +P 4000 3050 +F 0 "U5" H 4000 3050 60 0000 C CNN +F 1 "adc_bridge_3" H 4000 3200 60 0000 C CNN +F 2 "" H 4000 3050 60 0000 C CNN +F 3 "" H 4000 3050 60 0000 C CNN + 1 4000 3050 + 1 0 0 -1 +$EndComp +$Comp +L internal72 x1 +U 1 1 6831481A +P 5450 3500 +F 0 "x1" H 5450 3350 60 0000 C CNN +F 1 "internal72" H 5450 4150 60 0000 C CNN +F 2 "" H 5450 3350 60 0001 C CNN +F 3 "" H 5450 3350 60 0001 C CNN + 1 5450 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3000 4550 3000 +Wire Wire Line + 5000 3100 4550 3100 +Wire Wire Line + 5000 3200 4550 3200 +Wire Wire Line + 6400 3150 5850 3150 +Wire Wire Line + 6400 3250 5850 3250 +$Comp +L DC v4 +U 1 1 68314951 +P 2400 4950 +F 0 "v4" H 2200 5050 60 0000 C CNN +F 1 "DC" H 2200 4900 60 0000 C CNN +F 2 "R1" H 2100 4950 60 0000 C CNN +F 3 "" H 2400 4950 60 0000 C CNN + 1 2400 4950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 68314998 +P 2400 5750 +F 0 "#PWR04" H 2400 5500 50 0001 C CNN +F 1 "GND" H 2400 5600 50 0000 C CNN +F 2 "" H 2400 5750 50 0001 C CNN +F 3 "" H 2400 5750 50 0001 C CNN + 1 2400 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 5750 2400 5400 +$Comp +L adc_bridge_2 U4 +U 1 1 683149F6 +P 3450 3750 +F 0 "U4" H 3450 3750 60 0000 C CNN +F 1 "adc_bridge_2" H 3450 3900 60 0000 C CNN +F 2 "" H 3450 3750 60 0000 C CNN +F 3 "" H 3450 3750 60 0000 C CNN + 1 3450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 3700 2400 3700 +Wire Wire Line + 2400 3700 2400 4500 +$Comp +L DC v5 +U 1 1 68314ACB +P 3000 4950 +F 0 "v5" H 2800 5050 60 0000 C CNN +F 1 "DC" H 2800 4900 60 0000 C CNN +F 2 "R1" H 2700 4950 60 0000 C CNN +F 3 "" H 3000 4950 60 0000 C CNN + 1 3000 4950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 68314AD1 +P 3000 5950 +F 0 "#PWR05" H 3000 5700 50 0001 C CNN +F 1 "GND" H 3000 5800 50 0000 C CNN +F 2 "" H 3000 5950 50 0001 C CNN +F 3 "" H 3000 5950 50 0001 C CNN + 1 3000 5950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 5400 3000 5950 +Wire Wire Line + 3000 4500 2850 4500 +Wire Wire Line + 2850 4500 2850 3800 +Wire Wire Line + 4000 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3300 +Wire Wire Line + 4250 3300 5000 3300 +Wire Wire Line + 4000 3800 4300 3800 +Wire Wire Line + 4300 3800 4300 3400 +Wire Wire Line + 4300 3400 5000 3400 +Text GLabel 2050 3800 0 60 Input ~ 0 +pre +Wire Wire Line + 2050 3800 2400 3800 +Connection ~ 2400 3800 +Text GLabel 3450 4250 2 60 Input ~ 0 +clr +Wire Wire Line + 3450 4250 2850 4250 +Connection ~ 2850 4250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml new file mode 100644 index 00000000..d2f9a188 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/sn54ls72_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.5u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1u</field5><field5 name="Period">2.1u</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">20n</field5><field5 name="Period">45n</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">0.3u</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1u</field5><field5 name="Period">2.1u</field5></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5></source><model><u5 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u6><u4 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u4><u4 name="type">d_inverter<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_jkff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for JK Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\internal72</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">5</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ns</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
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