diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls48')
79 files changed, 6343 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib new file mode 100644 index 00000000..78d3995f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47-cache.lib @@ -0,0 +1,300 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# a_origin +# +DEF a_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "a_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X a 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# b_origin +# +DEF b_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "b_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X b 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# c_origin +# +DEF c_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "c_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X c 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_origin +# +DEF d_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "d_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -50 0 1 0 N +X x 1 -450 250 200 R 50 50 1 1 I +X y 2 -450 150 200 R 50 50 1 1 I +X z 3 -450 50 200 R 50 50 1 1 I +X d 4 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_7 +# +DEF dac_bridge_7 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_7" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -600 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X OUT1 8 550 50 200 L 50 50 1 1 O +X OUT2 9 550 -50 200 L 50 50 1 1 O +X OUT3 10 550 -150 200 L 50 50 1 1 O +X OUT4 11 550 -250 200 L 50 50 1 1 O +X OUT5 12 550 -350 200 L 50 50 1 1 O +X OUT6 13 550 -450 200 L 50 50 1 1 O +X OUT7 14 550 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# e_origin +# +DEF e_origin X 0 40 Y Y 1 F N +F0 "X" 0 -400 60 H V C CNN +F1 "e_origin" 0 250 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 200 -250 -200 0 1 0 N +X x 1 -450 100 200 R 50 50 1 1 I +X y 2 -450 0 200 R 50 50 1 1 I +X z 3 -450 -100 200 R 50 50 1 1 I +X e 4 450 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# f_origin +# +DEF f_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "f_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X f 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# g_origin +# +DEF g_origin X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "g_origin" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 250 300 -250 -100 0 1 0 N +X w 1 -450 250 200 R 50 50 1 1 I +X x 2 -450 150 200 R 50 50 1 1 I +X y 3 -450 50 200 R 50 50 1 1 I +X z 4 -450 -50 200 R 50 50 1 1 I +X g 5 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir new file mode 100644 index 00000000..a64c338c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir @@ -0,0 +1,31 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls47\74ls47.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:57:49 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U5-Pad1_ a_origin +X5 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U7-Pad1_ c_origin +X6 Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U8-Pad1_ d_origin +X7 Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U11-Pad1_ e_origin +X8 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U9-Pad1_ f_origin +U1 /w /x /y /z Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ ? ? PORT +U3 /w /x /y /z Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4 +X1 /RBI Net-_U3-Pad8_ Net-_U3-Pad7_ Net-_U3-Pad6_ Net-_U4-Pad1_ 4_OR +U4 Net-_U4-Pad1_ Net-_U3-Pad5_ Net-_U4-Pad3_ d_or +X2 /LT /BI Net-_U4-Pad3_ Net-_U10-Pad2_ 3_and +U5 Net-_U5-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_and +U6 Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad2_ d_and +U7 Net-_U7-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U8 Net-_U8-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad4_ d_and +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U9 Net-_U9-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad6_ d_and +U2 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ /LT /BI /RBI adc_bridge_3 +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ Net-_U12-Pad4_ Net-_U11-Pad3_ Net-_U12-Pad6_ Net-_U10-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ dac_bridge_7 +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +X4 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U6-Pad1_ b_origin +X9 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U10-Pad1_ g_origin + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out new file mode 100644 index 00000000..21471ca2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.cir.out @@ -0,0 +1,74 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls47\74ls47.cir + +.include 3_and.sub +.include g_origin.sub +.include e_origin.sub +.include a_origin.sub +.include 4_OR.sub +.include c_origin.sub +.include d_origin.sub +.include b_origin.sub +.include f_origin.sub +x3 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u5-pad1_ a_origin +x5 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u7-pad1_ c_origin +x6 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u8-pad1_ d_origin +x7 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u11-pad1_ e_origin +x8 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u9-pad1_ f_origin +* u1 /w /x /y /z net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? port +* u3 /w /x /y /z net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4 +x1 /rbi net-_u3-pad8_ net-_u3-pad7_ net-_u3-pad6_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u3-pad5_ net-_u4-pad3_ d_or +x2 /lt /bi net-_u4-pad3_ net-_u10-pad2_ 3_and +* u5 net-_u5-pad1_ net-_u10-pad2_ net-_u12-pad1_ d_and +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ d_and +* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u12-pad4_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u12-pad6_ d_and +* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ /lt /bi /rbi adc_bridge_3 +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_7 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +x4 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u6-pad1_ b_origin +x9 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u10-pad1_ g_origin +a1 [/w /x /y /z ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3 +a2 [net-_u4-pad1_ net-_u3-pad5_ ] net-_u4-pad3_ u4 +a3 [net-_u5-pad1_ net-_u10-pad2_ ] net-_u12-pad1_ u5 +a4 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u12-pad2_ u6 +a5 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u7 +a6 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u12-pad4_ u8 +a7 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u12-pad6_ u9 +a9 [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] [/lt /bi /rbi ] u2 +a10 [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ ] [net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u12 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_7, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch new file mode 100644 index 00000000..532d7dd4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sch @@ -0,0 +1,775 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74ls47-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L a_origin X3 +U 1 1 67F6D192 +P 5050 1300 +F 0 "X3" H 5050 1100 60 0000 C CNN +F 1 "a_origin" H 5050 1650 60 0000 C CNN +F 2 "" H 5050 1300 60 0001 C CNN +F 3 "" H 5050 1300 60 0001 C CNN + 1 5050 1300 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0000 C CNN +F 3 "" H 6400 6500 60 0000 C CNN + 1 6400 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5700 6400 5950 6400 +Wire Wire Line + 5950 6750 5950 6500 +Wire Wire Line + 3150 6750 5950 6750 +Wire Wire Line + 6850 6450 7550 6450 +Connection ~ 3750 6750 +Wire Wire Line + 7550 6450 7550 3450 +Wire Wire Line + 7550 3450 7650 3450 +$Comp +L PORT U1 +U 8 1 67F6FCB5 +P 9400 2850 +F 0 "U1" H 9450 2950 30 0000 C CNN +F 1 "PORT" H 9400 2850 30 0000 C CNN +F 2 "" H 9400 2850 60 0000 C CNN +F 3 "" H 9400 2850 60 0000 C CNN + 8 9400 2850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 67F6FD50 +P 9400 2950 +F 0 "U1" H 9450 3050 30 0000 C CNN +F 1 "PORT" H 9400 2950 30 0000 C CNN +F 2 "" H 9400 2950 60 0000 C CNN +F 3 "" H 9400 2950 60 0000 C CNN + 9 9400 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 67F6FDD8 +P 9400 3050 +F 0 "U1" H 9450 3150 30 0000 C CNN +F 1 "PORT" H 9400 3050 30 0000 C CNN +F 2 "" H 9400 3050 60 0000 C CNN +F 3 "" H 9400 3050 60 0000 C CNN + 10 9400 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 67F6FE4F +P 9400 3150 +F 0 "U1" H 9450 3250 30 0000 C CNN +F 1 "PORT" H 9400 3150 30 0000 C CNN +F 2 "" H 9400 3150 60 0000 C CNN +F 3 "" H 9400 3150 60 0000 C CNN + 11 9400 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 67F6FED2 +P 9400 3250 +F 0 "U1" H 9450 3350 30 0000 C CNN +F 1 "PORT" H 9400 3250 30 0000 C CNN +F 2 "" H 9400 3250 60 0000 C CNN +F 3 "" H 9400 3250 60 0000 C CNN + 12 9400 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 67F6FF61 +P 9400 3350 +F 0 "U1" H 9450 3450 30 0000 C CNN +F 1 "PORT" H 9400 3350 30 0000 C CNN +F 2 "" H 9400 3350 60 0000 C CNN +F 3 "" H 9400 3350 60 0000 C CNN + 13 9400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67F6FFE2 +P 9400 3450 +F 0 "U1" H 9450 3550 30 0000 C CNN +F 1 "PORT" H 9400 3450 30 0000 C CNN +F 2 "" H 9400 3450 60 0000 C CNN +F 3 "" H 9400 3450 60 0000 C CNN + 14 9400 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67F70067 +P 9400 4400 +F 0 "U1" H 9450 4500 30 0000 C CNN +F 1 "PORT" H 9400 4400 30 0000 C CNN +F 2 "" H 9400 4400 60 0000 C CNN +F 3 "" H 9400 4400 60 0000 C CNN + 15 9400 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67F700CE +P 9450 4600 +F 0 "U1" H 9500 4700 30 0000 C CNN +F 1 "PORT" H 9450 4600 30 0000 C CNN +F 2 "" H 9450 4600 60 0000 C CNN +F 3 "" H 9450 4600 60 0000 C CNN + 16 9450 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2850 9150 2850 +Wire Wire Line + 8800 2950 9150 2950 +Wire Wire Line + 8800 3050 9150 3050 +Wire Wire Line + 8800 3150 9150 3150 +Wire Wire Line + 8800 3250 9150 3250 +Wire Wire Line + 8800 3350 9150 3350 +Wire Wire Line + 8800 3450 9150 3450 +NoConn ~ 9650 4400 +NoConn ~ 9700 4600 +Connection ~ 3800 1500 +Connection ~ 3700 1400 +Connection ~ 3650 1300 +Wire Wire Line + 3850 2700 3850 1050 +Connection ~ 3850 1050 +$Comp +L b_origin X4 +U 1 1 67F82B41 +P 5100 2250 +F 0 "X4" H 5100 2050 60 0000 C CNN +F 1 "b_origin" H 5100 2600 60 0000 C CNN +F 2 "" H 5100 2250 60 0001 C CNN +F 3 "" H 5100 2250 60 0001 C CNN + 1 5100 2250 + 1 0 0 -1 +$EndComp +$Comp +L g_origin X9 +U 1 1 67F82BE6 +P 5250 6500 +F 0 "X9" H 5250 6300 60 0000 C CNN +F 1 "g_origin" H 5250 6850 60 0000 C CNN +F 2 "" H 5250 6500 60 0001 C CNN +F 3 "" H 5250 6500 60 0001 C CNN + 1 5250 6500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub new file mode 100644 index 00000000..a2e7a0fa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47.sub @@ -0,0 +1,68 @@ +* Subcircuit 74ls47 +.subckt 74ls47 /w /x /y /z net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls47\74ls47.cir +.include 3_and.sub +.include g_origin.sub +.include e_origin.sub +.include a_origin.sub +.include 4_OR.sub +.include c_origin.sub +.include d_origin.sub +.include b_origin.sub +.include f_origin.sub +x3 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u5-pad1_ a_origin +x5 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u7-pad1_ c_origin +x6 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u8-pad1_ d_origin +x7 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u11-pad1_ e_origin +x8 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u9-pad1_ f_origin +* u3 /w /x /y /z net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4 +x1 /rbi net-_u3-pad8_ net-_u3-pad7_ net-_u3-pad6_ net-_u4-pad1_ 4_OR +* u4 net-_u4-pad1_ net-_u3-pad5_ net-_u4-pad3_ d_or +x2 /lt /bi net-_u4-pad3_ net-_u10-pad2_ 3_and +* u5 net-_u5-pad1_ net-_u10-pad2_ net-_u12-pad1_ d_and +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ d_and +* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u12-pad4_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u12-pad6_ d_and +* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ /lt /bi /rbi adc_bridge_3 +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_7 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +x4 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u6-pad1_ b_origin +x9 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u10-pad1_ g_origin +a1 [/w /x /y /z ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3 +a2 [net-_u4-pad1_ net-_u3-pad5_ ] net-_u4-pad3_ u4 +a3 [net-_u5-pad1_ net-_u10-pad2_ ] net-_u12-pad1_ u5 +a4 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u12-pad2_ u6 +a5 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u7 +a6 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u12-pad4_ u8 +a7 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u12-pad6_ u9 +a9 [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] [/lt /bi /rbi ] u2 +a10 [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ ] [net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u12 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_7, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ls47
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml new file mode 100644 index 00000000..dcbdc226 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/74ls47_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u8><u11 name="type">d_and<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_and<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u9><u2 name="type">adc_bridge<field26 name="Enter value for in_low (default=1.0)" /><field27 name="Enter value for in_high (default=2.0)" /><field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /></u2><u12 name="type">dac_bridge<field30 name="Enter value for out_low (default=0.0)" /><field31 name="Enter value for out_high (default=5.0)" /><field32 name="Enter value for out_undef (default=0.5)" /><field33 name="Enter value for input load (default=1.0e-12)" /><field34 name="Enter the Rise Time (default=1.0e-9)" /><field35 name="Enter the Fall Time (default=1.0e-9)" /></u12><u10 name="type">d_and<field36 name="Enter Rise Delay (default=1.0e-9)" /><field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /></u10></model><devicemodel /><subcircuit><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\a_origin</field></x3><x5><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\c_origin</field></x5><x6><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\d_origin</field></x6><x7><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\e_origin</field></x7><x8><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\f_origin</field></x8><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\b_origin</field></x4><x9><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\g_origin</field></x9></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib new file mode 100644 index 00000000..cba52382 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir new file mode 100644 index 00000000..7a7f0ef0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\a_origin\a_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:37:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 /z Net-_U5-Pad2_ d_inverter +X3 /x Net-_U4-Pad2_ /z Net-_X3-Pad4_ 3_and +X1 /w Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U2-Pad2_ /y /z Net-_X2-Pad4_ 3_and +X4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_X4-Pad4_ 3_and +X5 Net-_X3-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_X4-Pad4_ Net-_U1-Pad5_ 4_OR + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out new file mode 100644 index 00000000..0017627e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.cir.out @@ -0,0 +1,35 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\a_origin\a_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x3 /x net-_u4-pad2_ /z net-_x3-pad4_ 3_and +x1 /w net-_u3-pad2_ net-_u4-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ /y /z net-_x2-pad4_ 3_and +x4 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad2_ net-_x4-pad4_ 3_and +x5 net-_x3-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_x4-pad4_ net-_u1-pad5_ 4_OR +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch new file mode 100644 index 00000000..73d001b6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sch @@ -0,0 +1,312 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:a_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4DD6F +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4DDB6 +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4DE11 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4DE68 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E01D +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E060 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E0A1 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67F4E0D4 +P 4800 2300 +F 0 "U5" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 2600 2750 2600 4150 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 3450 2750 3450 4250 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 4800 2600 4800 4350 +Wire Wire Line + 3100 2800 5300 2800 +Connection ~ 3100 2800 +Wire Wire Line + 4100 2900 5300 2900 +Connection ~ 4100 2900 +Wire Wire Line + 4450 3000 5300 3000 +Connection ~ 4450 3000 +$Comp +L 3_and X3 +U 1 1 67F4E3C4 +P 5650 2950 +F 0 "X3" H 5750 2900 60 0000 C CNN +F 1 "3_and" H 5800 3100 60 0000 C CNN +F 2 "" H 5650 2950 60 0000 C CNN +F 3 "" H 5650 2950 60 0000 C CNN + 1 5650 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 3200 5000 3200 +Connection ~ 2350 3200 +Wire Wire Line + 3450 3300 5000 3300 +Connection ~ 3450 3300 +Wire Wire Line + 4100 3400 5000 3400 +Connection ~ 4100 3400 +$Comp +L 3_and X1 +U 1 1 67F4E48C +P 5350 3350 +F 0 "X1" H 5450 3300 60 0000 C CNN +F 1 "3_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5350 3350 60 0000 C CNN +F 3 "" H 5350 3350 60 0000 C CNN + 1 5350 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 3600 5100 3600 +Connection ~ 2600 3600 +Wire Wire Line + 3850 3700 5100 3700 +Connection ~ 3850 3700 +Wire Wire Line + 4450 3800 5100 3800 +Connection ~ 4450 3800 +$Comp +L 3_and X2 +U 1 1 67F4E565 +P 5450 3750 +F 0 "X2" H 5550 3700 60 0000 C CNN +F 1 "3_and" H 5600 3900 60 0000 C CNN +F 2 "" H 5450 3750 60 0000 C CNN +F 3 "" H 5450 3750 60 0000 C CNN + 1 5450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 4150 5300 4150 +Wire Wire Line + 3450 4250 5300 4250 +Wire Wire Line + 4800 4350 5300 4350 +$Comp +L 3_and X4 +U 1 1 67F4E64C +P 5650 4300 +F 0 "X4" H 5750 4250 60 0000 C CNN +F 1 "3_and" H 5800 4450 60 0000 C CNN +F 2 "" H 5650 4300 60 0000 C CNN +F 3 "" H 5650 4300 60 0000 C CNN + 1 5650 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 3800 4450 1550 +Wire Wire Line + 4100 3400 4100 2700 +Wire Wire Line + 3850 3700 3850 1550 +Wire Wire Line + 3100 2800 3100 1550 +Wire Wire Line + 2350 3200 2350 1550 +$Comp +L 4_OR X5 +U 1 1 67F4E827 +P 7000 3450 +F 0 "X5" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 2900 6650 2900 +Wire Wire Line + 6650 2900 6650 3300 +Wire Wire Line + 5850 3300 6100 3300 +Wire Wire Line + 6100 3300 6100 3400 +Wire Wire Line + 6100 3400 6650 3400 +Wire Wire Line + 5950 3700 6050 3700 +Wire Wire Line + 6050 3700 6050 3500 +Wire Wire Line + 6050 3500 6650 3500 +Wire Wire Line + 6150 4250 6650 4250 +Wire Wire Line + 6650 4250 6650 3600 +Wire Wire Line + 7550 3450 7950 3450 +$Comp +L PORT U1 +U 5 1 67F4E9A9 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub new file mode 100644 index 00000000..039707d1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin.sub @@ -0,0 +1,29 @@ +* Subcircuit a_origin +.subckt a_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\a_origin\a_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x3 /x net-_u4-pad2_ /z net-_x3-pad4_ 3_and +x1 /w net-_u3-pad2_ net-_u4-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ /y /z net-_x2-pad4_ 3_and +x4 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad2_ net-_x4-pad4_ 3_and +x5 net-_x3-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_x4-pad4_ net-_u1-pad5_ 4_OR +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends a_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml new file mode 100644 index 00000000..0ea212d8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/a_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis new file mode 100644 index 00000000..f482494a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/analysis @@ -0,0 +1 @@ +.tran 1e-03 32e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib new file mode 100644 index 00000000..6bcc3103 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir new file mode 100644 index 00000000..ed5a9067 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\b_origin\b_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:52:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 /z Net-_U5-Pad2_ d_inverter +X2 Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_U6-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad5_ 4_OR +X1 Net-_U2-Pad2_ /y /z Net-_X1-Pad4_ 3_and +U6 Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad3_ d_and +U8 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad3_ d_and +U7 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out new file mode 100644 index 00000000..6a79abc5 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.cir.out @@ -0,0 +1,44 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\b_origin\b_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x2 net-_u7-pad3_ net-_u8-pad3_ net-_u6-pad3_ net-_x1-pad4_ net-_u1-pad5_ 4_OR +x1 net-_u2-pad2_ /y /z net-_x1-pad4_ 3_and +* u6 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad3_ d_and +* u8 net-_u3-pad2_ net-_u4-pad2_ net-_u8-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +a5 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u6-pad3_ u6 +a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u8-pad3_ u8 +a7 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch new file mode 100644 index 00000000..a040bf91 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sch @@ -0,0 +1,298 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:b_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E18C +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E18D +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E18E +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E18F +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E190 +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E191 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E192 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67F4E193 +P 4800 2300 +F 0 "U5" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67F4E198 +P 7000 3450 +F 0 "X2" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67F4E199 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 6650 3600 6650 4850 +Wire Wire Line + 7550 3450 7950 3450 +Wire Wire Line + 2600 2750 2600 4750 +Wire Wire Line + 2600 3150 5350 3150 +Wire Wire Line + 3450 2750 3450 3550 +Wire Wire Line + 3450 3050 5350 3050 +Wire Wire Line + 3450 3550 5350 3550 +Connection ~ 3450 3050 +Wire Wire Line + 4100 2700 4100 4100 +Wire Wire Line + 4100 3650 5350 3650 +Wire Wire Line + 4100 4100 5300 4100 +Connection ~ 4100 3650 +Wire Wire Line + 4800 2600 4800 4200 +Wire Wire Line + 4800 4200 5300 4200 +Wire Wire Line + 2600 4750 5300 4750 +Connection ~ 2600 3150 +Wire Wire Line + 3850 1550 3850 4850 +Wire Wire Line + 3850 4850 5300 4850 +Wire Wire Line + 4450 1550 4450 4950 +Wire Wire Line + 4450 4950 5300 4950 +Wire Wire Line + 3100 1550 3100 2100 +Wire Wire Line + 2350 1550 2350 2100 +$Comp +L 3_and X1 +U 1 1 67F4E4E1 +P 5650 4900 +F 0 "X1" H 5750 4850 60 0000 C CNN +F 1 "3_and" H 5800 5050 60 0000 C CNN +F 2 "" H 5650 4900 60 0000 C CNN +F 3 "" H 5650 4900 60 0000 C CNN + 1 5650 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E574 +P 5750 4200 +F 0 "U6" H 5750 4200 60 0000 C CNN +F 1 "d_and" H 5800 4300 60 0000 C CNN +F 2 "" H 5750 4200 60 0000 C CNN +F 3 "" H 5750 4200 60 0000 C CNN + 1 5750 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 67F4E5DF +P 5800 3650 +F 0 "U8" H 5800 3650 60 0000 C CNN +F 1 "d_and" H 5850 3750 60 0000 C CNN +F 2 "" H 5800 3650 60 0000 C CNN +F 3 "" H 5800 3650 60 0000 C CNN + 1 5800 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E62C +P 5800 3150 +F 0 "U7" H 5800 3150 60 0000 C CNN +F 1 "d_and" H 5850 3250 60 0000 C CNN +F 2 "" H 5800 3150 60 0000 C CNN +F 3 "" H 5800 3150 60 0000 C CNN + 1 5800 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 3100 6650 3100 +Wire Wire Line + 6650 3100 6650 3300 +Wire Wire Line + 6250 3600 6250 3400 +Wire Wire Line + 6250 3400 6650 3400 +Wire Wire Line + 6200 4150 6500 4150 +Wire Wire Line + 6500 4150 6500 3500 +Wire Wire Line + 6500 3500 6650 3500 +Wire Wire Line + 6650 4850 6150 4850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub new file mode 100644 index 00000000..320abfc6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin.sub @@ -0,0 +1,38 @@ +* Subcircuit b_origin +.subckt b_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\b_origin\b_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 /z net-_u5-pad2_ d_inverter +x2 net-_u7-pad3_ net-_u8-pad3_ net-_u6-pad3_ net-_x1-pad4_ net-_u1-pad5_ 4_OR +x1 net-_u2-pad2_ /y /z net-_x1-pad4_ 3_and +* u6 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad3_ d_and +* u8 net-_u3-pad2_ net-_u4-pad2_ net-_u8-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 /z net-_u5-pad2_ u5 +a5 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u6-pad3_ u6 +a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u8-pad3_ u8 +a7 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends b_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml new file mode 100644 index 00000000..497562ca --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/b_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir new file mode 100644 index 00000000..da0eb176 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\c_origin\c_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:45:18 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /w Net-_U2-Pad2_ d_inverter +U3 /x Net-_U3-Pad2_ d_inverter +U4 /y Net-_U4-Pad2_ d_inverter +U5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U3-Pad2_ /z Net-_U6-Pad3_ d_and +U7 Net-_U2-Pad2_ /x Net-_U7-Pad3_ d_and +U8 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U8-Pad3_ d_or +U9 Net-_U8-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad5_ d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out new file mode 100644 index 00000000..6eb3a7d8 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.cir.out @@ -0,0 +1,44 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\c_origin\c_origin.cir + +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u3-pad2_ /z net-_u6-pad3_ d_and +* u7 net-_u2-pad2_ /x net-_u7-pad3_ d_and +* u8 net-_u5-pad3_ net-_u6-pad3_ net-_u8-pad3_ d_or +* u9 net-_u8-pad3_ net-_u7-pad3_ net-_u1-pad5_ d_or +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u3-pad2_ /z ] net-_u6-pad3_ u6 +a6 [net-_u2-pad2_ /x ] net-_u7-pad3_ u7 +a7 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u8-pad3_ u8 +a8 [net-_u8-pad3_ net-_u7-pad3_ ] net-_u1-pad5_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch new file mode 100644 index 00000000..6fec8e04 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sch @@ -0,0 +1,260 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:c_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E33E +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E33F +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E340 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E341 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E342 +P 2600 2450 +F 0 "U2" H 2600 2350 60 0000 C CNN +F 1 "d_inverter" H 2600 2600 60 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 1 2600 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E343 +P 3450 2450 +F 0 "U3" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E344 +P 4100 2400 +F 0 "U4" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 2100 2600 2100 +Wire Wire Line + 2600 2100 2600 2150 +Connection ~ 2350 2100 +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 4100 2100 +Connection ~ 4450 1950 +Wire Wire Line + 3100 1550 3100 3800 +Wire Wire Line + 2350 1550 2350 2100 +Wire Wire Line + 3450 2900 5400 2900 +Connection ~ 3450 2900 +Wire Wire Line + 4100 3000 5400 3000 +Connection ~ 4100 3000 +Wire Wire Line + 3450 3200 5400 3200 +Connection ~ 3450 3200 +Wire Wire Line + 4450 3300 5400 3300 +Connection ~ 4450 3300 +Wire Wire Line + 2600 3700 5400 3700 +Connection ~ 2600 3700 +Wire Wire Line + 3100 3800 5400 3800 +Wire Wire Line + 3450 3200 3450 2750 +Wire Wire Line + 2600 3700 2600 2750 +Wire Wire Line + 4100 3000 4100 2700 +Wire Wire Line + 4450 3300 4450 1550 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 1550 +$Comp +L d_and U5 +U 1 1 67F4E64B +P 5850 3000 +F 0 "U5" H 5850 3000 60 0000 C CNN +F 1 "d_and" H 5900 3100 60 0000 C CNN +F 2 "" H 5850 3000 60 0000 C CNN +F 3 "" H 5850 3000 60 0000 C CNN + 1 5850 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E6B2 +P 5850 3300 +F 0 "U6" H 5850 3300 60 0000 C CNN +F 1 "d_and" H 5900 3400 60 0000 C CNN +F 2 "" H 5850 3300 60 0000 C CNN +F 3 "" H 5850 3300 60 0000 C CNN + 1 5850 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E707 +P 5850 3800 +F 0 "U7" H 5850 3800 60 0000 C CNN +F 1 "d_and" H 5900 3900 60 0000 C CNN +F 2 "" H 5850 3800 60 0000 C CNN +F 3 "" H 5850 3800 60 0000 C CNN + 1 5850 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 67F4E744 +P 6750 3050 +F 0 "U8" H 6750 3050 60 0000 C CNN +F 1 "d_or" H 6750 3150 60 0000 C CNN +F 2 "" H 6750 3050 60 0000 C CNN +F 3 "" H 6750 3050 60 0000 C CNN + 1 6750 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 3050 6300 3250 +$Comp +L d_or U9 +U 1 1 67F4E7EF +P 7650 3100 +F 0 "U9" H 7650 3100 60 0000 C CNN +F 1 "d_or" H 7650 3200 60 0000 C CNN +F 2 "" H 7650 3100 60 0000 C CNN +F 3 "" H 7650 3100 60 0000 C CNN + 1 7650 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 3750 7200 3750 +Wire Wire Line + 7200 3750 7200 3100 +$Comp +L PORT U1 +U 5 1 67F4E938 +P 8350 3050 +F 0 "U1" H 8400 3150 30 0000 C CNN +F 1 "PORT" H 8350 3050 30 0000 C CNN +F 2 "" H 8350 3050 60 0000 C CNN +F 3 "" H 8350 3050 60 0000 C CNN + 5 8350 3050 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub new file mode 100644 index 00000000..fbe2fd03 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin.sub @@ -0,0 +1,38 @@ +* Subcircuit c_origin +.subckt c_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\c_origin\c_origin.cir +* u2 /w net-_u2-pad2_ d_inverter +* u3 /x net-_u3-pad2_ d_inverter +* u4 /y net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u3-pad2_ /z net-_u6-pad3_ d_and +* u7 net-_u2-pad2_ /x net-_u7-pad3_ d_and +* u8 net-_u5-pad3_ net-_u6-pad3_ net-_u8-pad3_ d_or +* u9 net-_u8-pad3_ net-_u7-pad3_ net-_u1-pad5_ d_or +a1 /w net-_u2-pad2_ u2 +a2 /x net-_u3-pad2_ u3 +a3 /y net-_u4-pad2_ u4 +a4 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u3-pad2_ /z ] net-_u6-pad3_ u6 +a6 [net-_u2-pad2_ /x ] net-_u7-pad3_ u7 +a7 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u8-pad3_ u8 +a8 [net-_u8-pad3_ net-_u7-pad3_ ] net-_u1-pad5_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends c_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml new file mode 100644 index 00000000..4a1451aa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/c_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib new file mode 100644 index 00000000..6bcc3103 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir new file mode 100644 index 00000000..d11eba94 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\d_origin\d_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 00:47:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /x /y /z Net-_U1-Pad4_ PORT +U2 /x Net-_U2-Pad2_ d_inverter +U3 /y Net-_U3-Pad2_ d_inverter +U4 /z Net-_U4-Pad2_ d_inverter +X2 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad4_ 4_OR +U5 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U2-Pad2_ /y Net-_U6-Pad3_ d_and +U7 /y Net-_U4-Pad2_ Net-_U7-Pad3_ d_and +X1 /x Net-_U3-Pad2_ /z Net-_X1-Pad4_ 3_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out new file mode 100644 index 00000000..53010be0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\d_origin\d_origin.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 /x /y /z net-_u1-pad4_ port +* u2 /x net-_u2-pad2_ d_inverter +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x2 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_x1-pad4_ net-_u1-pad4_ 4_OR +* u5 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u2-pad2_ /y net-_u6-pad3_ d_and +* u7 /y net-_u4-pad2_ net-_u7-pad3_ d_and +x1 /x net-_u3-pad2_ /z net-_x1-pad4_ 3_and +a1 /x net-_u2-pad2_ u2 +a2 /y net-_u3-pad2_ u3 +a3 /z net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad2_ /y ] net-_u6-pad3_ u6 +a6 [/y net-_u4-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch new file mode 100644 index 00000000..ec9a3d9e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sch @@ -0,0 +1,270 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:d_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F4E50B +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 1 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F4E50C +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 2 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F4E50D +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 3 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F4E50F +P 3450 2450 +F 0 "U2" H 3450 2350 60 0000 C CNN +F 1 "d_inverter" H 3450 2600 60 0000 C CNN +F 2 "" H 3500 2400 60 0000 C CNN +F 3 "" H 3500 2400 60 0000 C CNN + 1 3450 2450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F4E510 +P 4100 2400 +F 0 "U3" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F4E511 +P 4800 2300 +F 0 "U4" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67F4E512 +P 7050 3400 +F 0 "X2" H 7200 3300 60 0000 C CNN +F 1 "4_OR" H 7200 3500 60 0000 C CNN +F 2 "" H 7050 3400 60 0000 C CNN +F 3 "" H 7050 3400 60 0000 C CNN + 1 7050 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67F4E513 +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F4E754 +P 5650 3000 +F 0 "U5" H 5650 3000 60 0000 C CNN +F 1 "d_and" H 5700 3100 60 0000 C CNN +F 2 "" H 5650 3000 60 0000 C CNN +F 3 "" H 5650 3000 60 0000 C CNN + 1 5650 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F4E7A8 +P 5650 3300 +F 0 "U6" H 5650 3300 60 0000 C CNN +F 1 "d_and" H 5700 3400 60 0000 C CNN +F 2 "" H 5650 3300 60 0000 C CNN +F 3 "" H 5650 3300 60 0000 C CNN + 1 5650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F4E7E1 +P 5700 3600 +F 0 "U7" H 5700 3600 60 0000 C CNN +F 1 "d_and" H 5750 3700 60 0000 C CNN +F 2 "" H 5700 3600 60 0000 C CNN +F 3 "" H 5700 3600 60 0000 C CNN + 1 5700 3600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 67F4E85E +P 5550 4050 +F 0 "X1" H 5650 4000 60 0000 C CNN +F 1 "3_and" H 5700 4200 60 0000 C CNN +F 2 "" H 5550 4050 60 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 2100 3450 2100 +Wire Wire Line + 3450 2100 3450 2150 +Connection ~ 3100 2100 +Wire Wire Line + 4100 2050 3850 2050 +Wire Wire Line + 3850 2050 3850 2100 +Connection ~ 3850 2100 +Wire Wire Line + 4100 2050 4100 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 7600 3400 8000 3400 +Wire Wire Line + 3100 1550 3100 3900 +Wire Wire Line + 3450 2900 5200 2900 +Connection ~ 3450 2900 +Wire Wire Line + 4800 3000 5200 3000 +Connection ~ 4800 3000 +Wire Wire Line + 3450 3200 5200 3200 +Connection ~ 3450 3200 +Wire Wire Line + 3850 3300 5200 3300 +Connection ~ 3850 3300 +Wire Wire Line + 3850 3500 5250 3500 +Connection ~ 3850 3500 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 3100 3900 5200 3900 +Wire Wire Line + 4100 4000 5200 4000 +Connection ~ 4100 4000 +Wire Wire Line + 4450 4100 5200 4100 +Connection ~ 4450 4100 +Wire Wire Line + 4450 4100 4450 1550 +Wire Wire Line + 4100 4000 4100 2700 +Wire Wire Line + 4800 3600 4800 2600 +Wire Wire Line + 3850 1550 3850 3500 +Wire Wire Line + 3450 2750 3450 3200 +Wire Wire Line + 6100 2950 6700 2950 +Wire Wire Line + 6700 2950 6700 3250 +Wire Wire Line + 6100 3250 6550 3250 +Wire Wire Line + 6550 3250 6550 3350 +Wire Wire Line + 6550 3350 6700 3350 +Wire Wire Line + 6150 3550 6150 3450 +Wire Wire Line + 6150 3450 6700 3450 +Wire Wire Line + 6050 4000 6700 4000 +Wire Wire Line + 6700 4000 6700 3550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub new file mode 100644 index 00000000..142ad7c3 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin.sub @@ -0,0 +1,34 @@ +* Subcircuit d_origin +.subckt d_origin /x /y /z net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\d_origin\d_origin.cir +.include 3_and.sub +.include 4_OR.sub +* u2 /x net-_u2-pad2_ d_inverter +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x2 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_x1-pad4_ net-_u1-pad4_ 4_OR +* u5 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad3_ d_and +* u6 net-_u2-pad2_ /y net-_u6-pad3_ d_and +* u7 /y net-_u4-pad2_ net-_u7-pad3_ d_and +x1 /x net-_u3-pad2_ /z net-_x1-pad4_ 3_and +a1 /x net-_u2-pad2_ u2 +a2 /y net-_u3-pad2_ u3 +a3 /z net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad2_ /y ] net-_u6-pad3_ u6 +a6 [/y net-_u4-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends d_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml new file mode 100644 index 00000000..a999d337 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/d_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/eSim b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/eSim new file mode 160000 +Subproject de13d725c1ffd3e0754b22c0070c0a8be8b829e diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir new file mode 100644 index 00000000..6f011078 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir @@ -0,0 +1,16 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\e_origin\e_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:14:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /x /y /z Net-_U1-Pad4_ PORT +U2 /x Net-_U2-Pad2_ d_inverter +U3 /z Net-_U3-Pad2_ d_inverter +U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and +U5 /y Net-_U3-Pad2_ Net-_U5-Pad3_ d_and +U6 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad4_ d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out new file mode 100644 index 00000000..9aa2614a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.cir.out @@ -0,0 +1,32 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\e_origin\e_origin.cir + +* u1 /x /y /z net-_u1-pad4_ port +* u2 /x net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /y net-_u3-pad2_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_or +a1 /x net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/y net-_u3-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch new file mode 100644 index 00000000..6054d4fa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:e_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CA9D +P 3600 2450 +F 0 "U1" H 3650 2550 30 0000 C CNN +F 1 "PORT" H 3600 2450 30 0000 C CNN +F 2 "" H 3600 2450 60 0000 C CNN +F 3 "" H 3600 2450 60 0000 C CNN + 1 3600 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CAC2 +P 3600 2850 +F 0 "U1" H 3650 2950 30 0000 C CNN +F 1 "PORT" H 3600 2850 30 0000 C CNN +F 2 "" H 3600 2850 60 0000 C CNN +F 3 "" H 3600 2850 60 0000 C CNN + 2 3600 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CAED +P 3600 3250 +F 0 "U1" H 3650 3350 30 0000 C CNN +F 1 "PORT" H 3600 3250 30 0000 C CNN +F 2 "" H 3600 3250 60 0000 C CNN +F 3 "" H 3600 3250 60 0000 C CNN + 3 3600 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 2450 4250 2450 +$Comp +L d_inverter U2 +U 1 1 67F6CB20 +P 4550 2450 +F 0 "U2" H 4550 2350 60 0000 C CNN +F 1 "d_inverter" H 4550 2600 60 0000 C CNN +F 2 "" H 4600 2400 60 0000 C CNN +F 3 "" H 4600 2400 60 0000 C CNN + 1 4550 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F6CB80 +P 4600 3250 +F 0 "U3" H 4600 3150 60 0000 C CNN +F 1 "d_inverter" H 4600 3400 60 0000 C CNN +F 2 "" H 4650 3200 60 0000 C CNN +F 3 "" H 4650 3200 60 0000 C CNN + 1 4600 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 3250 4300 3250 +Wire Wire Line + 4850 2450 5600 2450 +Wire Wire Line + 4900 3250 5250 3250 +Wire Wire Line + 5050 3250 5050 2550 +Wire Wire Line + 5050 2550 5600 2550 +Wire Wire Line + 3850 2850 5600 2850 +Wire Wire Line + 5250 3250 5250 2950 +Wire Wire Line + 5250 2950 5600 2950 +Connection ~ 5050 3250 +$Comp +L d_and U4 +U 1 1 67F6CBCC +P 6050 2550 +F 0 "U4" H 6050 2550 60 0000 C CNN +F 1 "d_and" H 6100 2650 60 0000 C CNN +F 2 "" H 6050 2550 60 0000 C CNN +F 3 "" H 6050 2550 60 0000 C CNN + 1 6050 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F6CC03 +P 6050 2950 +F 0 "U5" H 6050 2950 60 0000 C CNN +F 1 "d_and" H 6100 3050 60 0000 C CNN +F 2 "" H 6050 2950 60 0000 C CNN +F 3 "" H 6050 2950 60 0000 C CNN + 1 6050 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 67F6CC38 +P 7200 2600 +F 0 "U6" H 7200 2600 60 0000 C CNN +F 1 "d_or" H 7200 2700 60 0000 C CNN +F 2 "" H 7200 2600 60 0000 C CNN +F 3 "" H 7200 2600 60 0000 C CNN + 1 7200 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 2500 6750 2500 +Wire Wire Line + 6500 2900 6750 2900 +Wire Wire Line + 6750 2900 6750 2600 +Wire Wire Line + 7650 2550 7900 2550 +$Comp +L PORT U1 +U 4 1 67F6CCD0 +P 8150 2550 +F 0 "U1" H 8200 2650 30 0000 C CNN +F 1 "PORT" H 8150 2550 30 0000 C CNN +F 2 "" H 8150 2550 60 0000 C CNN +F 3 "" H 8150 2550 60 0000 C CNN + 4 8150 2550 + -1 0 0 1 +$EndComp +Text Label 3950 2450 0 60 ~ 0 +x +Text Label 4000 2850 0 60 ~ 0 +y +Text Label 3950 3250 0 60 ~ 0 +z +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub new file mode 100644 index 00000000..7be62924 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin.sub @@ -0,0 +1,26 @@ +* Subcircuit e_origin +.subckt e_origin /x /y /z net-_u1-pad4_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\e_origin\e_origin.cir +* u2 /x net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /y net-_u3-pad2_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_or +a1 /x net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/y net-_u3-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends e_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml new file mode 100644 index 00000000..54d54feb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/e_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib new file mode 100644 index 00000000..20f5c6cc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin-cache.lib @@ -0,0 +1,96 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir new file mode 100644 index 00000000..f630a09c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\f_origin\f_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/10/25 01:12:40 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U2 /y Net-_U2-Pad2_ d_inverter +U3 /z Net-_U3-Pad2_ d_inverter +X1 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad5_ 4_OR +U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and +U5 /x Net-_U2-Pad2_ Net-_U5-Pad3_ d_and +U6 /x Net-_U3-Pad2_ Net-_U6-Pad3_ d_and +U7 /w Net-_U2-Pad2_ Net-_U7-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out new file mode 100644 index 00000000..2a00b16f --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.cir.out @@ -0,0 +1,38 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\f_origin\f_origin.cir + +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u2 /y net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +x1 net-_u4-pad3_ net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad5_ 4_OR +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /x net-_u2-pad2_ net-_u5-pad3_ d_and +* u6 /x net-_u3-pad2_ net-_u6-pad3_ d_and +* u7 /w net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /y net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/x net-_u2-pad2_ ] net-_u5-pad3_ u5 +a5 [/x net-_u3-pad2_ ] net-_u6-pad3_ u6 +a6 [/w net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch new file mode 100644 index 00000000..fc4bf555 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sch @@ -0,0 +1,259 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:a_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CCB0 +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CCB1 +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CCB2 +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F6CCB3 +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U2 +U 1 1 67F6CCB6 +P 4100 2400 +F 0 "U2" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67F6CCB7 +P 4800 2300 +F 0 "U3" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +Wire Wire Line + 3850 1550 3850 2100 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 4100 2700 4100 4100 +Wire Wire Line + 3100 1550 3100 3600 +Wire Wire Line + 2350 1550 2350 4000 +$Comp +L 4_OR X1 +U 1 1 67F6CCBC +P 7000 3450 +F 0 "X1" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 2900 6650 3300 +Wire Wire Line + 7550 3450 7950 3450 +$Comp +L PORT U1 +U 5 1 67F6CCBD +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2900 4100 2850 +Wire Wire Line + 4100 2850 5150 2850 +Connection ~ 4100 2900 +Wire Wire Line + 4800 2950 5150 2950 +Connection ~ 4800 2950 +Wire Wire Line + 3100 3250 5150 3250 +Wire Wire Line + 4100 3350 5150 3350 +Connection ~ 4100 3350 +Wire Wire Line + 3100 3600 5150 3600 +Connection ~ 3100 3250 +Wire Wire Line + 4800 3700 5150 3700 +Connection ~ 4800 3700 +Wire Wire Line + 2350 4000 5150 4000 +Wire Wire Line + 4100 4100 5150 4100 +Wire Wire Line + 4450 1950 4450 1550 +Wire Wire Line + 3850 2100 4100 2100 +$Comp +L d_and U4 +U 1 1 67F6D0F4 +P 5600 2950 +F 0 "U4" H 5600 2950 60 0000 C CNN +F 1 "d_and" H 5650 3050 60 0000 C CNN +F 2 "" H 5600 2950 60 0000 C CNN +F 3 "" H 5600 2950 60 0000 C CNN + 1 5600 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67F6D131 +P 5600 3350 +F 0 "U5" H 5600 3350 60 0000 C CNN +F 1 "d_and" H 5650 3450 60 0000 C CNN +F 2 "" H 5600 3350 60 0000 C CNN +F 3 "" H 5600 3350 60 0000 C CNN + 1 5600 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F6D172 +P 5600 3700 +F 0 "U6" H 5600 3700 60 0000 C CNN +F 1 "d_and" H 5650 3800 60 0000 C CNN +F 2 "" H 5600 3700 60 0000 C CNN +F 3 "" H 5600 3700 60 0000 C CNN + 1 5600 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F6D1AD +P 5600 4100 +F 0 "U7" H 5600 4100 60 0000 C CNN +F 1 "d_and" H 5650 4200 60 0000 C CNN +F 2 "" H 5600 4100 60 0000 C CNN +F 3 "" H 5600 4100 60 0000 C CNN + 1 5600 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 2900 6050 2900 +Wire Wire Line + 6050 3300 6350 3300 +Wire Wire Line + 6350 3300 6350 3400 +Wire Wire Line + 6350 3400 6650 3400 +Wire Wire Line + 6050 3650 6050 3500 +Wire Wire Line + 6050 3500 6650 3500 +Wire Wire Line + 6050 4050 6650 4050 +Wire Wire Line + 6650 4050 6650 3600 +Wire Wire Line + 4800 3700 4800 2600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub new file mode 100644 index 00000000..275719f1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin.sub @@ -0,0 +1,32 @@ +* Subcircuit f_origin +.subckt f_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\f_origin\f_origin.cir +.include 4_OR.sub +* u2 /y net-_u2-pad2_ d_inverter +* u3 /z net-_u3-pad2_ d_inverter +x1 net-_u4-pad3_ net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad5_ 4_OR +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad3_ d_and +* u5 /x net-_u2-pad2_ net-_u5-pad3_ d_and +* u6 /x net-_u3-pad2_ net-_u6-pad3_ d_and +* u7 /w net-_u2-pad2_ net-_u7-pad3_ d_and +a1 /y net-_u2-pad2_ u2 +a2 /z net-_u3-pad2_ u3 +a3 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad3_ u4 +a4 [/x net-_u2-pad2_ ] net-_u5-pad3_ u5 +a5 [/x net-_u3-pad2_ ] net-_u6-pad3_ u6 +a6 [/w net-_u2-pad2_ ] net-_u7-pad3_ u7 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends f_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml new file mode 100644 index 00000000..592103c4 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/f_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib new file mode 100644 index 00000000..20f5c6cc --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin-cache.lib @@ -0,0 +1,96 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir new file mode 100644 index 00000000..0a0e3f41 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir @@ -0,0 +1,19 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\g_origin\g_origin.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 01:54:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 /w /x /y /z Net-_U1-Pad5_ PORT +U3 /y Net-_U3-Pad2_ d_inverter +U4 /z Net-_U4-Pad2_ d_inverter +X1 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_U1-Pad5_ 4_OR +U2 /x Net-_U2-Pad2_ d_inverter +U5 Net-_U2-Pad2_ /y Net-_U5-Pad3_ d_and +U6 /y Net-_U4-Pad2_ Net-_U6-Pad3_ d_and +U7 /x Net-_U3-Pad2_ Net-_U7-Pad3_ d_and +U8 /w Net-_U2-Pad2_ Net-_U8-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out new file mode 100644 index 00000000..bb3b0ad0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.cir.out @@ -0,0 +1,42 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir + +.include 4_OR.sub +* u1 /w /x /y /z net-_u1-pad5_ port +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR +* u2 /x net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ /y net-_u5-pad3_ d_and +* u6 /y net-_u4-pad2_ net-_u6-pad3_ d_and +* u7 /x net-_u3-pad2_ net-_u7-pad3_ d_and +* u8 /w net-_u2-pad2_ net-_u8-pad3_ d_and +a1 /y net-_u3-pad2_ u3 +a2 /z net-_u4-pad2_ u4 +a3 /x net-_u2-pad2_ u2 +a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5 +a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6 +a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7 +a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch new file mode 100644 index 00000000..c0ef7cdd --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sch @@ -0,0 +1,272 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:g_origin-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 67F6CE89 +P 2350 1300 +F 0 "U1" H 2400 1400 30 0000 C CNN +F 1 "PORT" H 2350 1300 30 0000 C CNN +F 2 "" H 2350 1300 60 0000 C CNN +F 3 "" H 2350 1300 60 0000 C CNN + 1 2350 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67F6CE8A +P 3100 1300 +F 0 "U1" H 3150 1400 30 0000 C CNN +F 1 "PORT" H 3100 1300 30 0000 C CNN +F 2 "" H 3100 1300 60 0000 C CNN +F 3 "" H 3100 1300 60 0000 C CNN + 2 3100 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67F6CE8B +P 3850 1300 +F 0 "U1" H 3900 1400 30 0000 C CNN +F 1 "PORT" H 3850 1300 30 0000 C CNN +F 2 "" H 3850 1300 60 0000 C CNN +F 3 "" H 3850 1300 60 0000 C CNN + 3 3850 1300 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 67F6CE8C +P 4450 1300 +F 0 "U1" H 4500 1400 30 0000 C CNN +F 1 "PORT" H 4450 1300 30 0000 C CNN +F 2 "" H 4450 1300 60 0000 C CNN +F 3 "" H 4450 1300 60 0000 C CNN + 4 4450 1300 + 0 -1 1 0 +$EndComp +Text Label 2350 1650 3 60 ~ 0 +w +Text Label 3100 1700 3 60 ~ 0 +x +Text Label 3850 1700 3 60 ~ 0 +y +Text Label 4450 1700 3 60 ~ 0 +z +$Comp +L d_inverter U3 +U 1 1 67F6CE8D +P 4100 2400 +F 0 "U3" H 4100 2300 60 0000 C CNN +F 1 "d_inverter" H 4100 2550 60 0000 C CNN +F 2 "" H 4150 2350 60 0000 C CNN +F 3 "" H 4150 2350 60 0000 C CNN + 1 4100 2400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67F6CE8E +P 4800 2300 +F 0 "U4" H 4800 2200 60 0000 C CNN +F 1 "d_inverter" H 4800 2450 60 0000 C CNN +F 2 "" H 4850 2250 60 0000 C CNN +F 3 "" H 4850 2250 60 0000 C CNN + 1 4800 2300 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X1 +U 1 1 67F6CE8F +P 7000 3450 +F 0 "X1" H 7150 3350 60 0000 C CNN +F 1 "4_OR" H 7150 3550 60 0000 C CNN +F 2 "" H 7000 3450 60 0000 C CNN +F 3 "" H 7000 3450 60 0000 C CNN + 1 7000 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67F6CE90 +P 8200 3450 +F 0 "U1" H 8250 3550 30 0000 C CNN +F 1 "PORT" H 8200 3450 30 0000 C CNN +F 2 "" H 8200 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 5 8200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 1550 3850 3500 +Wire Wire Line + 4800 1950 4450 1950 +Connection ~ 4450 1950 +Wire Wire Line + 4800 1950 4800 2000 +Wire Wire Line + 3100 1550 3100 3900 +Wire Wire Line + 2350 1550 2350 4250 +Wire Wire Line + 7550 3450 7950 3450 +Wire Wire Line + 4450 1950 4450 1550 +Wire Wire Line + 3850 2100 4100 2100 +Wire Wire Line + 6650 3600 6650 4300 +$Comp +L d_inverter U2 +U 1 1 67F6CFF0 +P 3350 2350 +F 0 "U2" H 3350 2250 60 0000 C CNN +F 1 "d_inverter" H 3350 2500 60 0000 C CNN +F 2 "" H 3400 2300 60 0000 C CNN +F 3 "" H 3400 2300 60 0000 C CNN + 1 3350 2350 + 0 1 1 0 +$EndComp +Wire Wire Line + 3350 2650 3350 4350 +Wire Wire Line + 3350 3000 5250 3000 +Wire Wire Line + 3850 3100 5250 3100 +Connection ~ 3850 2100 +Wire Wire Line + 3850 3500 5250 3500 +Connection ~ 3850 3100 +Wire Wire Line + 4800 3600 5250 3600 +Connection ~ 4800 3600 +Wire Wire Line + 3100 3900 5250 3900 +Wire Wire Line + 4100 2700 4100 4000 +Wire Wire Line + 4100 4000 5250 4000 +Wire Wire Line + 2350 4250 5250 4250 +Wire Wire Line + 3350 4350 5250 4350 +Connection ~ 3350 3000 +Wire Wire Line + 4800 3600 4800 2600 +$Comp +L d_and U5 +U 1 1 67F6D168 +P 5700 3100 +F 0 "U5" H 5700 3100 60 0000 C CNN +F 1 "d_and" H 5750 3200 60 0000 C CNN +F 2 "" H 5700 3100 60 0000 C CNN +F 3 "" H 5700 3100 60 0000 C CNN + 1 5700 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67F6D1A7 +P 5700 3600 +F 0 "U6" H 5700 3600 60 0000 C CNN +F 1 "d_and" H 5750 3700 60 0000 C CNN +F 2 "" H 5700 3600 60 0000 C CNN +F 3 "" H 5700 3600 60 0000 C CNN + 1 5700 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67F6D1E4 +P 5700 4000 +F 0 "U7" H 5700 4000 60 0000 C CNN +F 1 "d_and" H 5750 4100 60 0000 C CNN +F 2 "" H 5700 4000 60 0000 C CNN +F 3 "" H 5700 4000 60 0000 C CNN + 1 5700 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 67F6D21B +P 5700 4350 +F 0 "U8" H 5700 4350 60 0000 C CNN +F 1 "d_and" H 5750 4450 60 0000 C CNN +F 2 "" H 5700 4350 60 0000 C CNN +F 3 "" H 5700 4350 60 0000 C CNN + 1 5700 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 4300 6150 4300 +Wire Wire Line + 6150 3950 6500 3950 +Wire Wire Line + 6500 3950 6500 3500 +Wire Wire Line + 6500 3500 6650 3500 +Wire Wire Line + 6150 3550 6150 3400 +Wire Wire Line + 6150 3400 6650 3400 +Wire Wire Line + 6150 3050 6650 3050 +Wire Wire Line + 6650 3050 6650 3300 +Wire Wire Line + 3350 2050 3100 2050 +Connection ~ 3100 2050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub new file mode 100644 index 00000000..e87dde76 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin.sub @@ -0,0 +1,36 @@ +* Subcircuit g_origin +.subckt g_origin /w /x /y /z net-_u1-pad5_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir +.include 4_OR.sub +* u3 /y net-_u3-pad2_ d_inverter +* u4 /z net-_u4-pad2_ d_inverter +x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR +* u2 /x net-_u2-pad2_ d_inverter +* u5 net-_u2-pad2_ /y net-_u5-pad3_ d_and +* u6 /y net-_u4-pad2_ net-_u6-pad3_ d_and +* u7 /x net-_u3-pad2_ net-_u7-pad3_ d_and +* u8 /w net-_u2-pad2_ net-_u8-pad3_ d_and +a1 /y net-_u3-pad2_ u3 +a2 /z net-_u4-pad2_ u4 +a3 /x net-_u2-pad2_ u2 +a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5 +a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6 +a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7 +a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends g_origin
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml new file mode 100644 index 00000000..80c572a0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/g_origin_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib new file mode 100644 index 00000000..18dc2f16 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 74_48 +# +DEF 74_48 X 0 40 Y Y 1 F N +F0 "X" -700 100 60 H V C CNN +F1 "74_48" -750 1150 60 H V C CNN +F2 "" -700 350 60 H I C CNN +F3 "" -700 350 60 H I C CNN +DRAW +S -300 1100 -1100 150 0 1 0 N +X w 1 -1300 1050 200 R 50 50 1 1 I +X x 2 -1300 950 200 R 50 50 1 1 I +X y 3 -1300 850 200 R 50 50 1 1 I +X z 4 -1300 750 200 R 50 50 1 1 I +X LT 5 -1300 600 200 R 50 50 1 1 I +X BI 6 -1300 500 200 R 50 50 1 1 I +X RBI 7 -1300 400 200 R 50 50 1 1 I +X a 8 -100 850 200 L 50 50 1 1 O +X b 9 -100 750 200 L 50 50 1 1 O +X c 10 -100 650 200 L 50 50 1 1 O +X d 11 -100 550 200 L 50 50 1 1 O +X e 12 -100 450 200 L 50 50 1 1 O +X f 13 -100 350 200 L 50 50 1 1 O +X g 14 -100 250 200 L 50 50 1 1 O +X GND 15 -1300 250 200 R 50 50 1 1 N +X vcc 16 -100 1000 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir new file mode 100644 index 00000000..bcc8495b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir @@ -0,0 +1,29 @@ +* C:\Users\Shanthipriya\eSim-Workspace\7447\7447.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/11/25 02:00:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v1 W GND pulse +v2 X GND pulse +v3 Y GND pulse +v4 Z GND pulse +v5 Net-_X1-Pad5_ GND DC +v6 Net-_X1-Pad6_ GND DC +v7 Net-_X1-Pad7_ GND DC +U1 Z plot_v1 +U2 Y plot_v1 +U3 X plot_v1 +U4 W plot_v1 +U5 a plot_v1 +U6 b plot_v1 +U7 c plot_v1 +U8 d plot_v1 +U9 e plot_v1 +U10 f plot_v1 +U11 g plot_v1 +X1 W X Y Z Net-_X1-Pad5_ Net-_X1-Pad6_ Net-_X1-Pad7_ a b c d e f g ? ? 74_48 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out new file mode 100644 index 00000000..2f14333c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.cir.out @@ -0,0 +1,32 @@ +* c:\users\shanthipriya\esim-workspace\7447\7447.cir + +.include 74ls47.sub +v1 w gnd pulse(0 5 0 1n 1n 16m 32m) +v2 x gnd pulse(0 5 0 1n 1n 8m 16m) +v3 y gnd pulse(0 5 0 1n 1n 4m 8m) +v4 z gnd pulse(0 5 0 1n 1n 2m 4m) +v5 net-_x1-pad5_ gnd dc 5 +v6 net-_x1-pad6_ gnd dc 5 +v7 net-_x1-pad7_ gnd dc 5 +* u1 z plot_v1 +* u2 y plot_v1 +* u3 x plot_v1 +* u4 w plot_v1 +* u5 a plot_v1 +* u6 b plot_v1 +* u7 c plot_v1 +* u8 d plot_v1 +* u9 e plot_v1 +* u10 f plot_v1 +* u11 g plot_v1 +x1 w x y z net-_x1-pad5_ net-_x1-pad6_ net-_x1-pad7_ a b c d e f g ? ? 74ls47 +.tran 1e-03 32e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(z)+6v(y)+12 v(x)+18 v(w)+24 v(a)+30v(b)+36 v(c)+42v(d)+48 v(e)+54v(f)+60v(g) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj new file mode 100644 index 00000000..4fc1deab --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.proj @@ -0,0 +1 @@ +schematicFile 7447.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch new file mode 100644 index 00000000..fa498ac7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48.sch @@ -0,0 +1,442 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:7448_ic1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pulse v1 +U 1 1 67F6DCAF +P 3000 1200 +F 0 "v1" H 2800 1300 60 0000 C CNN +F 1 "pulse" H 2800 1150 60 0000 C CNN +F 2 "R1" H 2700 1200 60 0000 C CNN +F 3 "" H 3000 1200 60 0000 C CNN + 1 3000 1200 + 0 1 1 0 +$EndComp +$Comp +L pulse v2 +U 1 1 67F6DCF2 +P 3000 1700 +F 0 "v2" H 2800 1800 60 0000 C CNN +F 1 "pulse" H 2800 1650 60 0000 C CNN +F 2 "R1" H 2700 1700 60 0000 C CNN +F 3 "" H 3000 1700 60 0000 C CNN + 1 3000 1700 + 0 1 1 0 +$EndComp +$Comp +L pulse v3 +U 1 1 67F6DD65 +P 3000 2200 +F 0 "v3" H 2800 2300 60 0000 C CNN +F 1 "pulse" H 2800 2150 60 0000 C CNN +F 2 "R1" H 2700 2200 60 0000 C CNN +F 3 "" H 3000 2200 60 0000 C CNN + 1 3000 2200 + 0 1 1 0 +$EndComp +$Comp +L pulse v4 +U 1 1 67F6DD6B +P 3000 2700 +F 0 "v4" H 2800 2800 60 0000 C CNN +F 1 "pulse" H 2800 2650 60 0000 C CNN +F 2 "R1" H 2700 2700 60 0000 C CNN +F 3 "" H 3000 2700 60 0000 C CNN + 1 3000 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3450 1200 5300 1200 +Wire Wire Line + 4700 1200 4700 2400 +Wire Wire Line + 3450 1700 4800 1700 +Wire Wire Line + 4500 1700 4500 2500 +Wire Wire Line + 4500 2500 4700 2500 +Wire Wire Line + 3450 2200 4350 2200 +Wire Wire Line + 4350 2200 4350 2600 +Wire Wire Line + 4350 2600 4700 2600 +Wire Wire Line + 3450 2700 4700 2700 +$Comp +L DC v5 +U 1 1 67F6DE86 +P 3050 3150 +F 0 "v5" H 2850 3250 60 0000 C CNN +F 1 "DC" H 2850 3100 60 0000 C CNN +F 2 "R1" H 2750 3150 60 0000 C CNN +F 3 "" H 3050 3150 60 0000 C CNN + 1 3050 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 67F6DEC1 +P 3050 3650 +F 0 "v6" H 2850 3750 60 0000 C CNN +F 1 "DC" H 2850 3600 60 0000 C CNN +F 2 "R1" H 2750 3650 60 0000 C CNN +F 3 "" H 3050 3650 60 0000 C CNN + 1 3050 3650 + 0 1 1 0 +$EndComp +$Comp +L DC v7 +U 1 1 67F6DF04 +P 3100 4150 +F 0 "v7" H 2900 4250 60 0000 C CNN +F 1 "DC" H 2900 4100 60 0000 C CNN +F 2 "R1" H 2800 4150 60 0000 C CNN +F 3 "" H 3100 4150 60 0000 C CNN + 1 3100 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 3500 3150 3500 2850 +Wire Wire Line + 3500 2850 4700 2850 +Wire Wire Line + 3500 3650 3600 3650 +Wire Wire Line + 3600 3650 3600 2950 +Wire Wire Line + 3600 2950 4700 2950 +Wire Wire Line + 3550 4150 3700 4150 +Wire Wire Line + 3700 4150 3700 3050 +Wire Wire Line + 3700 3050 4700 3050 +$Comp +L GND #PWR01 +U 1 1 67F6DFE6 +P 2450 4300 +F 0 "#PWR01" H 2450 4050 50 0001 C CNN +F 1 "GND" H 2450 4150 50 0000 C CNN +F 2 "" H 2450 4300 50 0001 C CNN +F 3 "" H 2450 4300 50 0001 C CNN + 1 2450 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 4150 2450 4150 +Wire Wire Line + 2450 1200 2450 4300 +Wire Wire Line + 2600 3650 2450 3650 +Connection ~ 2450 4150 +Wire Wire Line + 2600 3150 2450 3150 +Connection ~ 2450 3650 +Wire Wire Line + 2550 2700 2450 2700 +Connection ~ 2450 3150 +Wire Wire Line + 2550 2200 2450 2200 +Connection ~ 2450 2700 +Wire Wire Line + 2550 1700 2450 1700 +Connection ~ 2450 2200 +Wire Wire Line + 2550 1200 2450 1200 +Connection ~ 2450 1700 +$Comp +L plot_v1 U1 +U 1 1 67F6E0F7 +P 3850 1200 +F 0 "U1" H 3850 1700 60 0000 C CNN +F 1 "plot_v1" H 4050 1550 60 0000 C CNN +F 2 "" H 3850 1200 60 0000 C CNN +F 3 "" H 3850 1200 60 0000 C CNN + 1 3850 1200 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 67F6E12E +P 4300 1200 +F 0 "U2" H 4300 1700 60 0000 C CNN +F 1 "plot_v1" H 4500 1550 60 0000 C CNN +F 2 "" H 4300 1200 60 0000 C CNN +F 3 "" H 4300 1200 60 0000 C CNN + 1 4300 1200 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 67F6E18B +P 4800 1250 +F 0 "U3" H 4800 1750 60 0000 C CNN +F 1 "plot_v1" H 5000 1600 60 0000 C CNN +F 2 "" H 4800 1250 60 0000 C CNN +F 3 "" H 4800 1250 60 0000 C CNN + 1 4800 1250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 67F6E1BC +P 5300 1250 +F 0 "U4" H 5300 1750 60 0000 C CNN +F 1 "plot_v1" H 5500 1600 60 0000 C CNN +F 2 "" H 5300 1250 60 0000 C CNN +F 3 "" H 5300 1250 60 0000 C CNN + 1 5300 1250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 1000 3850 2700 +Connection ~ 3850 2700 +Wire Wire Line + 4300 1000 4300 2200 +Connection ~ 4300 2200 +Wire Wire Line + 4800 1700 4800 1050 +Connection ~ 4500 1700 +Wire Wire Line + 5300 1200 5300 1050 +Connection ~ 4700 1200 +Text GLabel 5050 1350 0 60 Input ~ 0 +W +Wire Wire Line + 5050 1350 5150 1350 +Wire Wire Line + 5150 1350 5150 1200 +Connection ~ 5150 1200 +Text GLabel 4500 1550 0 60 Input ~ 0 +X +Wire Wire Line + 4500 1550 4800 1550 +Connection ~ 4800 1550 +Text GLabel 4150 1900 0 60 Input ~ 0 +Y +Wire Wire Line + 4150 1900 4300 1900 +Connection ~ 4300 1900 +Text GLabel 3650 2450 0 60 Input ~ 0 +Z +Wire Wire Line + 3650 2450 3850 2450 +Connection ~ 3850 2450 +$Comp +L plot_v1 U5 +U 1 1 67F6E42E +P 6300 2800 +F 0 "U5" H 6300 3300 60 0000 C CNN +F 1 "plot_v1" H 6500 3150 60 0000 C CNN +F 2 "" H 6300 2800 60 0000 C CNN +F 3 "" H 6300 2800 60 0000 C CNN + 1 6300 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 67F6E47D +P 6750 2800 +F 0 "U6" H 6750 3300 60 0000 C CNN +F 1 "plot_v1" H 6950 3150 60 0000 C CNN +F 2 "" H 6750 2800 60 0000 C CNN +F 3 "" H 6750 2800 60 0000 C CNN + 1 6750 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 67F6E4BA +P 7150 2800 +F 0 "U7" H 7150 3300 60 0000 C CNN +F 1 "plot_v1" H 7350 3150 60 0000 C CNN +F 2 "" H 7150 2800 60 0000 C CNN +F 3 "" H 7150 2800 60 0000 C CNN + 1 7150 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 67F6E4FB +P 7550 2800 +F 0 "U8" H 7550 3300 60 0000 C CNN +F 1 "plot_v1" H 7750 3150 60 0000 C CNN +F 2 "" H 7550 2800 60 0000 C CNN +F 3 "" H 7550 2800 60 0000 C CNN + 1 7550 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 67F6E53C +P 8000 2800 +F 0 "U9" H 8000 3300 60 0000 C CNN +F 1 "plot_v1" H 8200 3150 60 0000 C CNN +F 2 "" H 8000 2800 60 0000 C CNN +F 3 "" H 8000 2800 60 0000 C CNN + 1 8000 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 67F6E57F +P 8400 2800 +F 0 "U10" H 8400 3300 60 0000 C CNN +F 1 "plot_v1" H 8600 3150 60 0000 C CNN +F 2 "" H 8400 2800 60 0000 C CNN +F 3 "" H 8400 2800 60 0000 C CNN + 1 8400 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 67F6E5BC +P 8800 2800 +F 0 "U11" H 8800 3300 60 0000 C CNN +F 1 "plot_v1" H 9000 3150 60 0000 C CNN +F 2 "" H 8800 2800 60 0000 C CNN +F 3 "" H 8800 2800 60 0000 C CNN + 1 8800 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 2600 5900 2600 +Wire Wire Line + 6750 2600 6750 2700 +Wire Wire Line + 6750 2700 5900 2700 +Wire Wire Line + 7150 2600 7150 2800 +Wire Wire Line + 7150 2800 5900 2800 +Wire Wire Line + 7550 2600 7550 2900 +Wire Wire Line + 7550 2900 5900 2900 +Wire Wire Line + 8000 2600 8000 3000 +Wire Wire Line + 8000 3000 5900 3000 +Wire Wire Line + 8400 2600 8400 3100 +Wire Wire Line + 8400 3100 5900 3100 +Wire Wire Line + 8800 2600 8800 3200 +Wire Wire Line + 8800 3200 5900 3200 +Text GLabel 6100 3300 0 60 Input ~ 0 +a +Wire Wire Line + 6100 3300 6150 3300 +Wire Wire Line + 6150 3300 6150 2600 +Connection ~ 6150 2600 +Text GLabel 6050 3500 0 60 Input ~ 0 +b +Wire Wire Line + 6050 3500 6300 3500 +Wire Wire Line + 6300 3500 6300 2700 +Connection ~ 6300 2700 +Text GLabel 6450 3350 0 60 Input ~ 0 +c +Wire Wire Line + 6450 3350 6550 3350 +Wire Wire Line + 6550 3350 6550 2800 +Connection ~ 6550 2800 +Text GLabel 6550 3550 0 60 Input ~ 0 +d +Wire Wire Line + 6550 3550 6700 3550 +Wire Wire Line + 6700 3550 6700 2900 +Connection ~ 6700 2900 +Text GLabel 6850 3350 0 60 Input ~ 0 +e +Wire Wire Line + 6850 3350 6900 3350 +Wire Wire Line + 6900 3350 6900 3000 +Connection ~ 6900 3000 +Text GLabel 6950 3500 0 60 Input ~ 0 +f +Wire Wire Line + 6950 3500 7050 3500 +Wire Wire Line + 7050 3500 7050 3100 +Connection ~ 7050 3100 +Text GLabel 7250 3400 0 60 Input ~ 0 +g +Wire Wire Line + 7250 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3200 +Connection ~ 7300 3200 +$Comp +L 74_48 X? +U 1 1 67F82B18 +P 6000 3450 +F 0 "X?" H 5250 3500 60 0000 C CNN +F 1 "74_48" H 5250 4650 60 0000 C CNN +F 2 "" H 6000 3450 60 0001 C CNN +F 3 "" H 6000 3450 60 0001 C CNN + 1 6000 3450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml new file mode 100644 index 00000000..96049e0e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls48/sn54ls48_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7></source><model /><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls47</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">32</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
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