diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/54act11030')
22 files changed, 1708 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib new file mode 100644 index 00000000..391547eb --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 74_1030 +# +DEF 74_1030 X 0 40 Y Y 1 F N +F0 "X" -150 -350 60 H V C CNN +F1 "74_1030" -150 600 60 H V C CNN +F2 "" -150 600 60 H I C CNN +F3 "" -150 600 60 H I C CNN +DRAW +S 100 550 -350 -250 0 1 0 N +X A1 1 -550 500 200 R 50 50 1 1 I +X A2 2 -550 400 200 R 50 50 1 1 I +X A3 3 -550 300 200 R 50 50 1 1 I +X A4 4 -550 200 200 R 50 50 1 1 I +X A5 5 -550 100 200 R 50 50 1 1 I +X A6 6 -550 0 200 R 50 50 1 1 I +X A7 7 -550 -100 200 R 50 50 1 1 I +X A8 8 -550 -200 200 R 50 50 1 1 I +X OUT 9 300 200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir new file mode 100644 index 00000000..be5e3da1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir @@ -0,0 +1,30 @@ +* C:\Users\Shanthipriya\eSim-Workspace\030\030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 13:20:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ Net-_U10-Pad1_ 74_1030 +U9 A1 A2 A3 A4 A5 A6 A7 A8 Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ Net-_U9-Pad15_ Net-_U9-Pad16_ adc_bridge_8 +U10 Net-_U10-Pad1_ OUT dac_bridge_1 +v1 A1 GND pulse +v2 A2 GND pulse +v3 A3 GND pulse +v4 A4 GND pulse +v5 A5 GND pulse +v6 A6 GND pulse +v7 A7 GND pulse +v8 A8 GND pulse +U11 OUT plot_v1 +U1 A1 plot_v1 +U2 A2 plot_v1 +U3 A3 plot_v1 +U4 A4 plot_v1 +U5 A5 plot_v1 +U6 A6 plot_v1 +U7 A7 plot_v1 +U8 A8 plot_v1 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out new file mode 100644 index 00000000..75b8bced --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.cir.out @@ -0,0 +1,39 @@ +* c:\users\shanthipriya\esim-workspace\030\030.cir + +.include 74_1030.sub +x1 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ net-_u10-pad1_ 74_1030 +* u9 a1 a2 a3 a4 a5 a6 a7 a8 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ adc_bridge_8 +* u10 net-_u10-pad1_ out dac_bridge_1 +v1 a1 gnd pulse(0 5 0 1n 1n 2m 4m) +v2 a2 gnd pulse(0 5 0 1n 1n 4m 8m) +v3 a3 gnd pulse(0 5 0 1n 1n 8m 16m) +v4 a4 gnd pulse(0 5 0 1n 1n 16m 32m) +v5 a5 gnd pulse(0 5 0 1n 1n 32m 64m) +v6 a6 gnd pulse(0 5 0 1n 1n 64 128m) +v7 a7 gnd pulse(0 5 0 1n 1n 128m 256m) +v8 a8 gnd pulse(0 5 0 1n 1n 256m 512m) +* u11 out plot_v1 +* u1 a1 plot_v1 +* u2 a2 plot_v1 +* u3 a3 plot_v1 +* u4 a4 plot_v1 +* u5 a5 plot_v1 +* u6 a6 plot_v1 +* u7 a7 plot_v1 +* u8 a8 plot_v1 +a1 [a1 a2 a3 a4 a5 a6 a7 a8 ] [net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ ] u9 +a2 [net-_u10-pad1_ ] [out ] u10 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-03 300e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out)+6 v(a1)+12 v(a2)+18 v(a3)+24 v(a4)+30 v(a5)+36v(a6)+42 v(a7)+48 v(a8) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj new file mode 100644 index 00000000..57fa3d19 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.proj @@ -0,0 +1 @@ +schematicFile 030.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch new file mode 100644 index 00000000..bbd27c39 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030.sch @@ -0,0 +1,481 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 74_1030 X1 +U 1 1 68380FB2 +P 6050 3750 +F 0 "X1" H 5900 3400 60 0000 C CNN +F 1 "74_1030" H 5900 4350 60 0000 C CNN +F 2 "" H 5900 4350 60 0001 C CNN +F 3 "" H 5900 4350 60 0001 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U9 +U 1 1 68380FD5 +P 4950 3300 +F 0 "U9" H 4950 3300 60 0000 C CNN +F 1 "adc_bridge_8" H 4950 3450 60 0000 C CNN +F 2 "" H 4950 3300 60 0000 C CNN +F 3 "" H 4950 3300 60 0000 C CNN + 1 4950 3300 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 68381012 +P 6950 3600 +F 0 "U10" H 6950 3600 60 0000 C CNN +F 1 "dac_bridge_1" H 6950 3750 60 0000 C CNN +F 2 "" H 6950 3600 60 0000 C CNN +F 3 "" H 6950 3600 60 0000 C CNN + 1 6950 3600 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 68381047 +P 950 5950 +F 0 "v1" H 750 6050 60 0000 C CNN +F 1 "pulse" H 750 5900 60 0000 C CNN +F 2 "R1" H 650 5950 60 0000 C CNN +F 3 "" H 950 5950 60 0000 C CNN + 1 950 5950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6838112C +P 950 6750 +F 0 "#PWR01" H 950 6500 50 0001 C CNN +F 1 "GND" H 950 6600 50 0000 C CNN +F 2 "" H 950 6750 50 0001 C CNN +F 3 "" H 950 6750 50 0001 C CNN + 1 950 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 6750 950 6400 +$Comp +L pulse v2 +U 1 1 68381175 +P 1350 6200 +F 0 "v2" H 1150 6300 60 0000 C CNN +F 1 "pulse" H 1150 6150 60 0000 C CNN +F 2 "R1" H 1050 6200 60 0000 C CNN +F 3 "" H 1350 6200 60 0000 C CNN + 1 1350 6200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6838117B +P 1350 7000 +F 0 "#PWR02" H 1350 6750 50 0001 C CNN +F 1 "GND" H 1350 6850 50 0000 C CNN +F 2 "" H 1350 7000 50 0001 C CNN +F 3 "" H 1350 7000 50 0001 C CNN + 1 1350 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 7000 1350 6650 +$Comp +L pulse v3 +U 1 1 683811BA +P 1850 5950 +F 0 "v3" H 1650 6050 60 0000 C CNN +F 1 "pulse" H 1650 5900 60 0000 C CNN +F 2 "R1" H 1550 5950 60 0000 C CNN +F 3 "" H 1850 5950 60 0000 C CNN + 1 1850 5950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 683811C0 +P 1850 6750 +F 0 "#PWR03" H 1850 6500 50 0001 C CNN +F 1 "GND" H 1850 6600 50 0000 C CNN +F 2 "" H 1850 6750 50 0001 C CNN +F 3 "" H 1850 6750 50 0001 C CNN + 1 1850 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1850 6750 1850 6400 +$Comp +L pulse v4 +U 1 1 683811C7 +P 2250 6200 +F 0 "v4" H 2050 6300 60 0000 C CNN +F 1 "pulse" H 2050 6150 60 0000 C CNN +F 2 "R1" H 1950 6200 60 0000 C CNN +F 3 "" H 2250 6200 60 0000 C CNN + 1 2250 6200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 683811CD +P 2250 7000 +F 0 "#PWR04" H 2250 6750 50 0001 C CNN +F 1 "GND" H 2250 6850 50 0000 C CNN +F 2 "" H 2250 7000 50 0001 C CNN +F 3 "" H 2250 7000 50 0001 C CNN + 1 2250 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2250 7000 2250 6650 +$Comp +L pulse v5 +U 1 1 6838126E +P 2650 5850 +F 0 "v5" H 2450 5950 60 0000 C CNN +F 1 "pulse" H 2450 5800 60 0000 C CNN +F 2 "R1" H 2350 5850 60 0000 C CNN +F 3 "" H 2650 5850 60 0000 C CNN + 1 2650 5850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 68381274 +P 2650 6650 +F 0 "#PWR05" H 2650 6400 50 0001 C CNN +F 1 "GND" H 2650 6500 50 0000 C CNN +F 2 "" H 2650 6650 50 0001 C CNN +F 3 "" H 2650 6650 50 0001 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 6650 2650 6300 +$Comp +L pulse v6 +U 1 1 6838127B +P 3050 6100 +F 0 "v6" H 2850 6200 60 0000 C CNN +F 1 "pulse" H 2850 6050 60 0000 C CNN +F 2 "R1" H 2750 6100 60 0000 C CNN +F 3 "" H 3050 6100 60 0000 C CNN + 1 3050 6100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 68381281 +P 3050 6900 +F 0 "#PWR06" H 3050 6650 50 0001 C CNN +F 1 "GND" H 3050 6750 50 0000 C CNN +F 2 "" H 3050 6900 50 0001 C CNN +F 3 "" H 3050 6900 50 0001 C CNN + 1 3050 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 6900 3050 6550 +$Comp +L pulse v7 +U 1 1 68381288 +P 3550 5850 +F 0 "v7" H 3350 5950 60 0000 C CNN +F 1 "pulse" H 3350 5800 60 0000 C CNN +F 2 "R1" H 3250 5850 60 0000 C CNN +F 3 "" H 3550 5850 60 0000 C CNN + 1 3550 5850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 6838128E +P 3550 6650 +F 0 "#PWR07" H 3550 6400 50 0001 C CNN +F 1 "GND" H 3550 6500 50 0000 C CNN +F 2 "" H 3550 6650 50 0001 C CNN +F 3 "" H 3550 6650 50 0001 C CNN + 1 3550 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 6650 3550 6300 +$Comp +L pulse v8 +U 1 1 68381295 +P 3950 6100 +F 0 "v8" H 3750 6200 60 0000 C CNN +F 1 "pulse" H 3750 6050 60 0000 C CNN +F 2 "R1" H 3650 6100 60 0000 C CNN +F 3 "" H 3950 6100 60 0000 C CNN + 1 3950 6100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 6838129B +P 3950 6900 +F 0 "#PWR08" H 3950 6650 50 0001 C CNN +F 1 "GND" H 3950 6750 50 0000 C CNN +F 2 "" H 3950 6900 50 0001 C CNN +F 3 "" H 3950 6900 50 0001 C CNN + 1 3950 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 6900 3950 6550 +Wire Wire Line + 3950 5650 3950 3950 +Wire Wire Line + 3950 3950 4350 3950 +Wire Wire Line + 3500 2700 3500 5400 +Wire Wire Line + 3500 3850 4350 3850 +Wire Wire Line + 3500 5400 3550 5400 +Wire Wire Line + 3050 5650 3050 3750 +Wire Wire Line + 3050 3750 4350 3750 +Wire Wire Line + 2650 5400 2650 3650 +Wire Wire Line + 2650 3650 4350 3650 +Wire Wire Line + 2250 3550 4350 3550 +Wire Wire Line + 1850 2700 1850 5500 +Wire Wire Line + 1850 3450 4350 3450 +Wire Wire Line + 1350 5750 1350 3350 +Wire Wire Line + 1350 3350 4350 3350 +Wire Wire Line + 950 2650 950 5500 +Wire Wire Line + 950 3250 4350 3250 +Connection ~ 950 3250 +Wire Wire Line + 1400 2650 1400 3350 +Connection ~ 1400 3350 +Connection ~ 1850 3450 +Connection ~ 2250 3550 +Wire Wire Line + 2250 2700 2250 5750 +Wire Wire Line + 2700 2700 2700 3650 +Connection ~ 2700 3650 +Wire Wire Line + 3150 2750 3150 3750 +Connection ~ 3150 3750 +Connection ~ 3500 3850 +Wire Wire Line + 3950 2750 3950 4000 +Connection ~ 3950 4000 +Text GLabel 750 3000 0 60 Input ~ 0 +A1 +Wire Wire Line + 750 3000 950 3000 +Connection ~ 950 3000 +Text GLabel 1200 3000 0 60 Input ~ 0 +A2 +Text GLabel 1650 3050 0 60 Input ~ 0 +A3 +Text GLabel 2050 3050 0 60 Input ~ 0 +A4 +Text GLabel 2450 3050 0 60 Input ~ 0 +A5 +Text GLabel 2950 3050 0 60 Input ~ 0 +A6 +Text GLabel 3350 3100 0 60 Input ~ 0 +A7 +Text GLabel 3700 3100 0 60 Input ~ 0 +A8 +Wire Wire Line + 1200 3000 1400 3000 +Connection ~ 1400 3000 +Wire Wire Line + 1650 3050 1850 3050 +Connection ~ 1850 3050 +Wire Wire Line + 2050 3050 2250 3050 +Connection ~ 2250 3050 +Wire Wire Line + 2450 3050 2700 3050 +Connection ~ 2700 3050 +Wire Wire Line + 2950 3050 3150 3050 +Connection ~ 3150 3050 +Wire Wire Line + 3350 3100 3500 3100 +Connection ~ 3500 3100 +Wire Wire Line + 3700 3100 3950 3100 +Connection ~ 3950 3100 +$Comp +L plot_v1 U11 +U 1 1 68381BED +P 8600 3650 +F 0 "U11" H 8600 4150 60 0000 C CNN +F 1 "plot_v1" H 8800 4000 60 0000 C CNN +F 2 "" H 8600 3650 60 0000 C CNN +F 3 "" H 8600 3650 60 0000 C CNN + 1 8600 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8600 3450 8600 3550 +Wire Wire Line + 8600 3550 7500 3550 +$Comp +L plot_v1 U1 +U 1 1 68381CC3 +P 950 2850 +F 0 "U1" H 950 3350 60 0000 C CNN +F 1 "plot_v1" H 1150 3200 60 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 1 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 68381D1C +P 1400 2850 +F 0 "U2" H 1400 3350 60 0000 C CNN +F 1 "plot_v1" H 1600 3200 60 0000 C CNN +F 2 "" H 1400 2850 60 0000 C CNN +F 3 "" H 1400 2850 60 0000 C CNN + 1 1400 2850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 68381D5D +P 1850 2900 +F 0 "U3" H 1850 3400 60 0000 C CNN +F 1 "plot_v1" H 2050 3250 60 0000 C CNN +F 2 "" H 1850 2900 60 0000 C CNN +F 3 "" H 1850 2900 60 0000 C CNN + 1 1850 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 68381DAE +P 2250 2900 +F 0 "U4" H 2250 3400 60 0000 C CNN +F 1 "plot_v1" H 2450 3250 60 0000 C CNN +F 2 "" H 2250 2900 60 0000 C CNN +F 3 "" H 2250 2900 60 0000 C CNN + 1 2250 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 68381DED +P 2700 2900 +F 0 "U5" H 2700 3400 60 0000 C CNN +F 1 "plot_v1" H 2900 3250 60 0000 C CNN +F 2 "" H 2700 2900 60 0000 C CNN +F 3 "" H 2700 2900 60 0000 C CNN + 1 2700 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 68381E26 +P 3150 2950 +F 0 "U6" H 3150 3450 60 0000 C CNN +F 1 "plot_v1" H 3350 3300 60 0000 C CNN +F 2 "" H 3150 2950 60 0000 C CNN +F 3 "" H 3150 2950 60 0000 C CNN + 1 3150 2950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 68381E61 +P 3500 2900 +F 0 "U7" H 3500 3400 60 0000 C CNN +F 1 "plot_v1" H 3700 3250 60 0000 C CNN +F 2 "" H 3500 2900 60 0000 C CNN +F 3 "" H 3500 2900 60 0000 C CNN + 1 3500 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 68381EC5 +P 3950 2950 +F 0 "U8" H 3950 3450 60 0000 C CNN +F 1 "plot_v1" H 4150 3300 60 0000 C CNN +F 2 "" H 3950 2950 60 0000 C CNN +F 3 "" H 3950 2950 60 0000 C CNN + 1 3950 2950 + 1 0 0 -1 +$EndComp +Text GLabel 7750 3200 0 60 Input ~ 0 +OUT +Wire Wire Line + 7750 3200 7900 3200 +Wire Wire Line + 7900 3200 7900 3550 +Connection ~ 7900 3550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml new file mode 100644 index 00000000..d86518a7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/54act11030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">8m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">8m</field5><field5 name="Period">16m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">16m</field5><field5 name="Period">32m</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">32m</field5><field5 name="Period">64m</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">64</field5><field5 name="Period">128m</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">128m</field5><field5 name="Period">256m</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">256m</field5><field5 name="Period">512m</field5></v8></source><model><u9 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">300</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir new file mode 100644 index 00000000..7e1232c1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030\74_1030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 21:55:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_nand +U5 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_nand +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_nand +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad9_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out new file mode 100644 index 00000000..27abdd10 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch new file mode 100644 index 00000000..c5547636 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sch @@ -0,0 +1,256 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6835E69D +P 4550 2300 +F 0 "U2" H 4550 2300 60 0000 C CNN +F 1 "d_nand" H 4600 2400 60 0000 C CNN +F 2 "" H 4550 2300 60 0000 C CNN +F 3 "" H 4550 2300 60 0000 C CNN + 1 4550 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6835E6D9 +P 4550 2500 +F 0 "U3" H 4550 2500 60 0000 C CNN +F 1 "d_nand" H 4600 2600 60 0000 C CNN +F 2 "" H 4550 2500 60 0000 C CNN +F 3 "" H 4550 2500 60 0000 C CNN + 1 4550 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6835E714 +P 4550 2700 +F 0 "U4" H 4550 2700 60 0000 C CNN +F 1 "d_nand" H 4600 2800 60 0000 C CNN +F 2 "" H 4550 2700 60 0000 C CNN +F 3 "" H 4550 2700 60 0000 C CNN + 1 4550 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 6835E790 +P 4550 2900 +F 0 "U5" H 4550 2900 60 0000 C CNN +F 1 "d_nand" H 4600 3000 60 0000 C CNN +F 2 "" H 4550 2900 60 0000 C CNN +F 3 "" H 4550 2900 60 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 6835E7DD +P 5550 2400 +F 0 "U6" H 5550 2400 60 0000 C CNN +F 1 "d_nand" H 5600 2500 60 0000 C CNN +F 2 "" H 5550 2400 60 0000 C CNN +F 3 "" H 5550 2400 60 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6835E828 +P 5550 2800 +F 0 "U7" H 5550 2800 60 0000 C CNN +F 1 "d_nand" H 5600 2900 60 0000 C CNN +F 2 "" H 5550 2800 60 0000 C CNN +F 3 "" H 5550 2800 60 0000 C CNN + 1 5550 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 6835E851 +P 6600 2600 +F 0 "U8" H 6600 2600 60 0000 C CNN +F 1 "d_nand" H 6650 2700 60 0000 C CNN +F 2 "" H 6600 2600 60 0000 C CNN +F 3 "" H 6600 2600 60 0000 C CNN + 1 6600 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 2250 5100 2250 +Wire Wire Line + 5100 2250 5100 2300 +Wire Wire Line + 5000 2450 5100 2450 +Wire Wire Line + 5100 2450 5100 2400 +Wire Wire Line + 5000 2650 5100 2650 +Wire Wire Line + 5100 2650 5100 2700 +Wire Wire Line + 5000 2850 5100 2850 +Wire Wire Line + 5100 2850 5100 2800 +Wire Wire Line + 6000 2350 6150 2350 +Wire Wire Line + 6150 2350 6150 2500 +Wire Wire Line + 6000 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 2600 +$Comp +L PORT U1 +U 1 1 6835E8E4 +P 3850 2200 +F 0 "U1" H 3900 2300 30 0000 C CNN +F 1 "PORT" H 3850 2200 30 0000 C CNN +F 2 "" H 3850 2200 60 0000 C CNN +F 3 "" H 3850 2200 60 0000 C CNN + 1 3850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835E93D +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835E97C +P 3850 2400 +F 0 "U1" H 3900 2500 30 0000 C CNN +F 1 "PORT" H 3850 2400 30 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 3 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835E9BD +P 3850 2500 +F 0 "U1" H 3900 2600 30 0000 C CNN +F 1 "PORT" H 3850 2500 30 0000 C CNN +F 2 "" H 3850 2500 60 0000 C CNN +F 3 "" H 3850 2500 60 0000 C CNN + 4 3850 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835E9FE +P 3850 2600 +F 0 "U1" H 3900 2700 30 0000 C CNN +F 1 "PORT" H 3850 2600 30 0000 C CNN +F 2 "" H 3850 2600 60 0000 C CNN +F 3 "" H 3850 2600 60 0000 C CNN + 5 3850 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835EA45 +P 3850 2700 +F 0 "U1" H 3900 2800 30 0000 C CNN +F 1 "PORT" H 3850 2700 30 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 6 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835EA7E +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 7 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835EACB +P 3850 2900 +F 0 "U1" H 3900 3000 30 0000 C CNN +F 1 "PORT" H 3850 2900 30 0000 C CNN +F 2 "" H 3850 2900 60 0000 C CNN +F 3 "" H 3850 2900 60 0000 C CNN + 8 3850 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835EB2B +P 7300 2550 +F 0 "U1" H 7350 2650 30 0000 C CNN +F 1 "PORT" H 7300 2550 30 0000 C CNN +F 2 "" H 7300 2550 60 0000 C CNN +F 3 "" H 7300 2550 60 0000 C CNN + 9 7300 2550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub new file mode 100644 index 00000000..f5fa4db7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030.sub @@ -0,0 +1,34 @@ +* Subcircuit 74_1030 +.subckt 74_1030 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74_1030
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml new file mode 100644 index 00000000..598bf495 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_1030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib new file mode 100644 index 00000000..ce6d8814 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir new file mode 100644 index 00000000..7e1232c1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir @@ -0,0 +1,18 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74_1030\74_1030.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/25 21:55:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_nand +U5 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_nand +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_nand +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad9_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out new file mode 100644 index 00000000..27abdd10 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch new file mode 100644 index 00000000..c5547636 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sch @@ -0,0 +1,256 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6835E69D +P 4550 2300 +F 0 "U2" H 4550 2300 60 0000 C CNN +F 1 "d_nand" H 4600 2400 60 0000 C CNN +F 2 "" H 4550 2300 60 0000 C CNN +F 3 "" H 4550 2300 60 0000 C CNN + 1 4550 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6835E6D9 +P 4550 2500 +F 0 "U3" H 4550 2500 60 0000 C CNN +F 1 "d_nand" H 4600 2600 60 0000 C CNN +F 2 "" H 4550 2500 60 0000 C CNN +F 3 "" H 4550 2500 60 0000 C CNN + 1 4550 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 6835E714 +P 4550 2700 +F 0 "U4" H 4550 2700 60 0000 C CNN +F 1 "d_nand" H 4600 2800 60 0000 C CNN +F 2 "" H 4550 2700 60 0000 C CNN +F 3 "" H 4550 2700 60 0000 C CNN + 1 4550 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 6835E790 +P 4550 2900 +F 0 "U5" H 4550 2900 60 0000 C CNN +F 1 "d_nand" H 4600 3000 60 0000 C CNN +F 2 "" H 4550 2900 60 0000 C CNN +F 3 "" H 4550 2900 60 0000 C CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 6835E7DD +P 5550 2400 +F 0 "U6" H 5550 2400 60 0000 C CNN +F 1 "d_nand" H 5600 2500 60 0000 C CNN +F 2 "" H 5550 2400 60 0000 C CNN +F 3 "" H 5550 2400 60 0000 C CNN + 1 5550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6835E828 +P 5550 2800 +F 0 "U7" H 5550 2800 60 0000 C CNN +F 1 "d_nand" H 5600 2900 60 0000 C CNN +F 2 "" H 5550 2800 60 0000 C CNN +F 3 "" H 5550 2800 60 0000 C CNN + 1 5550 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 6835E851 +P 6600 2600 +F 0 "U8" H 6600 2600 60 0000 C CNN +F 1 "d_nand" H 6650 2700 60 0000 C CNN +F 2 "" H 6600 2600 60 0000 C CNN +F 3 "" H 6600 2600 60 0000 C CNN + 1 6600 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 2250 5100 2250 +Wire Wire Line + 5100 2250 5100 2300 +Wire Wire Line + 5000 2450 5100 2450 +Wire Wire Line + 5100 2450 5100 2400 +Wire Wire Line + 5000 2650 5100 2650 +Wire Wire Line + 5100 2650 5100 2700 +Wire Wire Line + 5000 2850 5100 2850 +Wire Wire Line + 5100 2850 5100 2800 +Wire Wire Line + 6000 2350 6150 2350 +Wire Wire Line + 6150 2350 6150 2500 +Wire Wire Line + 6000 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 2600 +$Comp +L PORT U1 +U 1 1 6835E8E4 +P 3850 2200 +F 0 "U1" H 3900 2300 30 0000 C CNN +F 1 "PORT" H 3850 2200 30 0000 C CNN +F 2 "" H 3850 2200 60 0000 C CNN +F 3 "" H 3850 2200 60 0000 C CNN + 1 3850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6835E93D +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6835E97C +P 3850 2400 +F 0 "U1" H 3900 2500 30 0000 C CNN +F 1 "PORT" H 3850 2400 30 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 3 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6835E9BD +P 3850 2500 +F 0 "U1" H 3900 2600 30 0000 C CNN +F 1 "PORT" H 3850 2500 30 0000 C CNN +F 2 "" H 3850 2500 60 0000 C CNN +F 3 "" H 3850 2500 60 0000 C CNN + 4 3850 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6835E9FE +P 3850 2600 +F 0 "U1" H 3900 2700 30 0000 C CNN +F 1 "PORT" H 3850 2600 30 0000 C CNN +F 2 "" H 3850 2600 60 0000 C CNN +F 3 "" H 3850 2600 60 0000 C CNN + 5 3850 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6835EA45 +P 3850 2700 +F 0 "U1" H 3900 2800 30 0000 C CNN +F 1 "PORT" H 3850 2700 30 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 6 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6835EA7E +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 7 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6835EACB +P 3850 2900 +F 0 "U1" H 3900 3000 30 0000 C CNN +F 1 "PORT" H 3850 2900 30 0000 C CNN +F 2 "" H 3850 2900 60 0000 C CNN +F 3 "" H 3850 2900 60 0000 C CNN + 8 3850 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6835EB2B +P 7300 2550 +F 0 "U1" H 7350 2650 30 0000 C CNN +F 1 "PORT" H 7300 2550 30 0000 C CNN +F 2 "" H 7300 2550 60 0000 C CNN +F 3 "" H 7300 2550 60 0000 C CNN + 9 7300 2550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub new file mode 100644 index 00000000..f5fa4db7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030.sub @@ -0,0 +1,34 @@ +* Subcircuit 74_1030 +.subckt 74_1030 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74_1030
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml new file mode 100644 index 00000000..598bf495 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/74_154act11030_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis b/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis new file mode 100644 index 00000000..f05a6cd0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/54act11030/analysis @@ -0,0 +1 @@ +.tran 1e-03 300e-03 0e-00
\ No newline at end of file |