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diff --git a/library/SubcircuitLibrary/bidirectional_shift_reg/mux4.cir.out b/library/SubcircuitLibrary/bidirectional_shift_reg/mux4.cir.out
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+++ b/library/SubcircuitLibrary/bidirectional_shift_reg/mux4.cir.out
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+* c:\fossee\esim\library\subcircuitlibrary\mux4\mux4.cir
+
+.include 3_and.sub
+.include 4_OR.sub
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_x1-pad4_ 3_and
+x2 net-_u1-pad1_ net-_u3-pad2_ net-_u1-pad3_ net-_x2-pad4_ 3_and
+x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_x3-pad4_ 3_and
+x4 net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ net-_x4-pad4_ 3_and
+x5 net-_x1-pad4_ net-_x2-pad4_ net-_x3-pad4_ net-_x4-pad4_ net-_u1-pad7_ 4_OR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 net-_u1-pad2_ net-_u3-pad2_ u3
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end