1 files changed, 88 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out
new file mode 100644
index 00000000..081abd5c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out
@@ -0,0 +1,88 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc257a\sn74lvc257a.cir
+
+* u3  net-_u1-pad1_ net-_u17-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u2  net-_u1-pad2_ net-_u10-pad1_ d_buffer
+* u5  net-_u11-pad1_ net-_u1-pad3_ net-_u13-pad1_ d_and
+* u6  net-_u10-pad1_ net-_u1-pad4_ net-_u13-pad2_ d_and
+* u7  net-_u11-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
+* u8  net-_u10-pad1_ net-_u1-pad6_ net-_u14-pad2_ d_and
+* u9  net-_u11-pad1_ net-_u1-pad7_ net-_u15-pad1_ d_and
+* u10  net-_u10-pad1_ net-_u1-pad8_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u1-pad9_ net-_u11-pad3_ d_and
+* u12  net-_u10-pad1_ net-_u1-pad10_ net-_u12-pad3_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or
+* u16  net-_u11-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_or
+* u17  net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ d_tristate
+* u18  net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate
+* u19  net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ d_tristate
+* u20  net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ d_tristate
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u1-pad1_ net-_u17-pad2_ u3
+a2 net-_u1-pad2_ net-_u11-pad1_ u4
+a3 net-_u1-pad2_ net-_u10-pad1_ u2
+a4 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u13-pad1_ u5
+a5 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u13-pad2_ u6
+a6 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u7
+a7 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u14-pad2_ u8
+a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u15-pad1_ u9
+a9 [net-_u10-pad1_ net-_u1-pad8_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u1-pad9_ ] net-_u11-pad3_ u11
+a11 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u12-pad3_ u12
+a12 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a14 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16
+a16 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ u17
+a17 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u18
+a18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ u19
+a19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ u20
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end