diff options
115 files changed, 10680 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib b/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib new file mode 100644 index 00000000..340f2a85 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B-cache.lib @@ -0,0 +1,132 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_srff +# +DEF d_srff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.cir b/library/SubcircuitLibrary/74LS95B/74LS95B.cir new file mode 100644 index 00000000..edb7331b --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LS95B\74LS95B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/25 17:25:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q0 ? d_srff +U21 Net-_U19-Pad2_ Net-_U18-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q2 ? d_srff +U26 Net-_U24-Pad2_ Net-_U23-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q3 ? d_srff +U6 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U11-Pad3_ d_or +U3 Net-_U12-Pad2_ /CP1 Net-_U3-Pad3_ d_and +U4 /S /CP2 Net-_U4-Pad3_ d_and +U8 Net-_U10-Pad3_ Net-_U7-Pad3_ Net-_U11-Pad2_ d_nor +U7 /Ds Net-_U12-Pad2_ Net-_U7-Pad3_ d_and +U10 Net-_U10-Pad1_ /P0 Net-_U10-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U12-Pad3_ Net-_U13-Pad3_ d_nor +U12 /Q0 Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U15 Net-_U10-Pad1_ /P1 Net-_U13-Pad1_ d_and +U18 Net-_U18-Pad1_ Net-_U17-Pad3_ Net-_U18-Pad3_ d_nor +U17 /Q1 Net-_U12-Pad2_ Net-_U17-Pad3_ d_and +U20 Net-_U10-Pad1_ /P2 Net-_U18-Pad1_ d_and +U23 Net-_U23-Pad1_ Net-_U22-Pad3_ Net-_U23-Pad3_ d_nor +U22 /Q2 Net-_U12-Pad2_ Net-_U22-Pad3_ d_and +U25 Net-_U10-Pad1_ /P3 Net-_U23-Pad1_ d_and +U9 Net-_U11-Pad2_ Net-_U11-Pad1_ d_inverter +U14 Net-_U13-Pad3_ Net-_U14-Pad2_ d_inverter +U19 Net-_U18-Pad3_ Net-_U19-Pad2_ d_inverter +U24 Net-_U23-Pad3_ Net-_U24-Pad2_ d_inverter +U2 /S Net-_U12-Pad2_ d_inverter +U5 Net-_U12-Pad2_ Net-_U10-Pad1_ d_inverter +U1 /Ds /P0 /P1 /P2 /P3 /S /VCC /CP2 /CP1 /Q3 /Q2 /Q1 /Q0 Net-_U1-Pad14_ PORT +U16 Net-_U14-Pad2_ Net-_U13-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad14_ /VCC /Q1 ? d_srff + +.end diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out b/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out new file mode 100644 index 00000000..647f9803 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B.cir.out @@ -0,0 +1,112 @@ +* c:\fossee\esim\library\subcircuitlibrary\74ls95b\74ls95b.cir + +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? d_srff +* u21 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? d_srff +* u26 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? d_srff +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u11-pad3_ d_or +* u3 net-_u12-pad2_ /cp1 net-_u3-pad3_ d_and +* u4 /s /cp2 net-_u4-pad3_ d_and +* u8 net-_u10-pad3_ net-_u7-pad3_ net-_u11-pad2_ d_nor +* u7 /ds net-_u12-pad2_ net-_u7-pad3_ d_and +* u10 net-_u10-pad1_ /p0 net-_u10-pad3_ d_and +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor +* u12 /q0 net-_u12-pad2_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ /p1 net-_u13-pad1_ d_and +* u18 net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_nor +* u17 /q1 net-_u12-pad2_ net-_u17-pad3_ d_and +* u20 net-_u10-pad1_ /p2 net-_u18-pad1_ d_and +* u23 net-_u23-pad1_ net-_u22-pad3_ net-_u23-pad3_ d_nor +* u22 /q2 net-_u12-pad2_ net-_u22-pad3_ d_and +* u25 net-_u10-pad1_ /p3 net-_u23-pad1_ d_and +* u9 net-_u11-pad2_ net-_u11-pad1_ d_inverter +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u19 net-_u18-pad3_ net-_u19-pad2_ d_inverter +* u24 net-_u23-pad3_ net-_u24-pad2_ d_inverter +* u2 /s net-_u12-pad2_ d_inverter +* u5 net-_u12-pad2_ net-_u10-pad1_ d_inverter +* u1 /ds /p0 /p1 /p2 /p3 /s /vcc /cp2 /cp1 /q3 /q2 /q1 /q0 net-_u1-pad14_ port +* u16 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? d_srff +a1 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? u11 +a2 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? u21 +a3 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? u26 +a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u11-pad3_ u6 +a5 [net-_u12-pad2_ /cp1 ] net-_u3-pad3_ u3 +a6 [/s /cp2 ] net-_u4-pad3_ u4 +a7 [net-_u10-pad3_ net-_u7-pad3_ ] net-_u11-pad2_ u8 +a8 [/ds net-_u12-pad2_ ] net-_u7-pad3_ u7 +a9 [net-_u10-pad1_ /p0 ] net-_u10-pad3_ u10 +a10 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a11 [/q0 net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u10-pad1_ /p1 ] net-_u13-pad1_ u15 +a13 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18 +a14 [/q1 net-_u12-pad2_ ] net-_u17-pad3_ u17 +a15 [net-_u10-pad1_ /p2 ] net-_u18-pad1_ u20 +a16 [net-_u23-pad1_ net-_u22-pad3_ ] net-_u23-pad3_ u23 +a17 [/q2 net-_u12-pad2_ ] net-_u22-pad3_ u22 +a18 [net-_u10-pad1_ /p3 ] net-_u23-pad1_ u25 +a19 net-_u11-pad2_ net-_u11-pad1_ u9 +a20 net-_u13-pad3_ net-_u14-pad2_ u14 +a21 net-_u18-pad3_ net-_u19-pad2_ u19 +a22 net-_u23-pad3_ net-_u24-pad2_ u24 +a23 /s net-_u12-pad2_ u2 +a24 net-_u12-pad2_ net-_u10-pad1_ u5 +a25 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? u16 +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u21 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u26 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u16 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.pro b/library/SubcircuitLibrary/74LS95B/74LS95B.pro new file mode 100644 index 00000000..e3dbe802 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B.pro @@ -0,0 +1,83 @@ +update=03/18/25 10:43:53 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Spice +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.sch b/library/SubcircuitLibrary/74LS95B/74LS95B.sch new file mode 100644 index 00000000..22b21dc8 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B.sch @@ -0,0 +1,737 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74LS95B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_srff U11 +U 1 1 67D8FAFD +P 3850 5300 +F 0 "U11" H 3850 5300 60 0000 C CNN +F 1 "d_srff" H 3900 5450 60 0000 C CNN +F 2 "" H 3850 5300 60 0000 C CNN +F 3 "" H 3850 5300 60 0000 C CNN + 1 3850 5300 + 1 0 0 1 +$EndComp +$Comp +L d_srff U21 +U 1 1 67D8FAFF +P 7900 5300 +F 0 "U21" H 7900 5300 60 0000 C CNN +F 1 "d_srff" H 7950 5450 60 0000 C CNN +F 2 "" H 7900 5300 60 0000 C CNN +F 3 "" H 7900 5300 60 0000 C CNN + 1 7900 5300 + 1 0 0 1 +$EndComp +$Comp +L d_srff U26 +U 1 1 67D8FB00 +P 9950 5300 +F 0 "U26" H 9950 5300 60 0000 C CNN +F 1 "d_srff" H 10000 5450 60 0000 C CNN +F 2 "" H 9950 5300 60 0000 C CNN +F 3 "" H 9950 5300 60 0000 C CNN + 1 9950 5300 + 1 0 0 1 +$EndComp +$Comp +L d_or U6 +U 1 1 67D8FB01 +P 2300 4150 +F 0 "U6" H 2300 4150 60 0000 C CNN +F 1 "d_or" H 2300 4250 60 0000 C CNN +F 2 "" H 2300 4150 60 0000 C CNN +F 3 "" H 2300 4150 60 0000 C CNN + 1 2300 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 67D8FB02 +P 1400 3950 +F 0 "U3" H 1400 3950 60 0000 C CNN +F 1 "d_and" H 1450 4050 60 0000 C CNN +F 2 "" H 1400 3950 60 0000 C CNN +F 3 "" H 1400 3950 60 0000 C CNN + 1 1400 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 67D8FB03 +P 1400 4300 +F 0 "U4" H 1400 4300 60 0000 C CNN +F 1 "d_and" H 1450 4400 60 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 1 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 67D8FB04 +P 2750 2850 +F 0 "U8" H 2750 2850 60 0000 C CNN +F 1 "d_nor" H 2800 2950 60 0000 C CNN +F 2 "" H 2750 2850 60 0000 C CNN +F 3 "" H 2750 2850 60 0000 C CNN + 1 2750 2850 + 0 1 1 0 +$EndComp +$Comp +L d_and U7 +U 1 1 67D8FB05 +P 2700 1950 +F 0 "U7" H 2700 1950 60 0000 C CNN +F 1 "d_and" H 2750 2050 60 0000 C CNN +F 2 "" H 2700 1950 60 0000 C CNN +F 3 "" H 2700 1950 60 0000 C CNN + 1 2700 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 67D8FB06 +P 3000 1950 +F 0 "U10" H 3000 1950 60 0000 C CNN +F 1 "d_and" H 3050 2050 60 0000 C CNN +F 2 "" H 3000 1950 60 0000 C CNN +F 3 "" H 3000 1950 60 0000 C CNN + 1 3000 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_nor U13 +U 1 1 67D8FB07 +P 4850 2850 +F 0 "U13" H 4850 2850 60 0000 C CNN +F 1 "d_nor" H 4900 2950 60 0000 C CNN +F 2 "" H 4850 2850 60 0000 C CNN +F 3 "" H 4850 2850 60 0000 C CNN + 1 4850 2850 + 0 1 1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 67D8FB08 +P 4800 1950 +F 0 "U12" H 4800 1950 60 0000 C CNN +F 1 "d_and" H 4850 2050 60 0000 C CNN +F 2 "" H 4800 1950 60 0000 C CNN +F 3 "" H 4800 1950 60 0000 C CNN + 1 4800 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_and U15 +U 1 1 67D8FB09 +P 5100 1950 +F 0 "U15" H 5100 1950 60 0000 C CNN +F 1 "d_and" H 5150 2050 60 0000 C CNN +F 2 "" H 5100 1950 60 0000 C CNN +F 3 "" H 5100 1950 60 0000 C CNN + 1 5100 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_nor U18 +U 1 1 67D8FB0A +P 6900 2850 +F 0 "U18" H 6900 2850 60 0000 C CNN +F 1 "d_nor" H 6950 2950 60 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 1 6900 2850 + 0 1 1 0 +$EndComp +$Comp +L d_and U17 +U 1 1 67D8FB0B +P 6850 1950 +F 0 "U17" H 6850 1950 60 0000 C CNN +F 1 "d_and" H 6900 2050 60 0000 C CNN +F 2 "" H 6850 1950 60 0000 C CNN +F 3 "" H 6850 1950 60 0000 C CNN + 1 6850 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_and U20 +U 1 1 67D8FB0C +P 7150 1950 +F 0 "U20" H 7150 1950 60 0000 C CNN +F 1 "d_and" H 7200 2050 60 0000 C CNN +F 2 "" H 7150 1950 60 0000 C CNN +F 3 "" H 7150 1950 60 0000 C CNN + 1 7150 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_nor U23 +U 1 1 67D8FB0D +P 8900 2850 +F 0 "U23" H 8900 2850 60 0000 C CNN +F 1 "d_nor" H 8950 2950 60 0000 C CNN +F 2 "" H 8900 2850 60 0000 C CNN +F 3 "" H 8900 2850 60 0000 C CNN + 1 8900 2850 + 0 1 1 0 +$EndComp +$Comp +L d_and U22 +U 1 1 67D8FB0E +P 8850 1950 +F 0 "U22" H 8850 1950 60 0000 C CNN +F 1 "d_and" H 8900 2050 60 0000 C CNN +F 2 "" H 8850 1950 60 0000 C CNN +F 3 "" H 8850 1950 60 0000 C CNN + 1 8850 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_and U25 +U 1 1 67D8FB0F +P 9150 1950 +F 0 "U25" H 9150 1950 60 0000 C CNN +F 1 "d_and" H 9200 2050 60 0000 C CNN +F 2 "" H 9150 1950 60 0000 C CNN +F 3 "" H 9150 1950 60 0000 C CNN + 1 9150 1950 + 0 -1 1 0 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67D8FB10 +P 2800 5400 +F 0 "U9" H 2800 5300 60 0000 C CNN +F 1 "d_inverter" H 2800 5550 60 0000 C CNN +F 2 "" H 2850 5350 60 0000 C CNN +F 3 "" H 2850 5350 60 0000 C CNN + 1 2800 5400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U14 +U 1 1 67D8FB11 +P 4900 5350 +F 0 "U14" H 4900 5250 60 0000 C CNN +F 1 "d_inverter" H 4900 5500 60 0000 C CNN +F 2 "" H 4950 5300 60 0000 C CNN +F 3 "" H 4950 5300 60 0000 C CNN + 1 4900 5350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 67D8FB12 +P 6900 5400 +F 0 "U19" H 6900 5300 60 0000 C CNN +F 1 "d_inverter" H 6900 5550 60 0000 C CNN +F 2 "" H 6950 5350 60 0000 C CNN +F 3 "" H 6950 5350 60 0000 C CNN + 1 6900 5400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 67D8FB13 +P 8950 5400 +F 0 "U24" H 8950 5300 60 0000 C CNN +F 1 "d_inverter" H 8950 5550 60 0000 C CNN +F 2 "" H 9000 5350 60 0000 C CNN +F 3 "" H 9000 5350 60 0000 C CNN + 1 8950 5400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U2 +U 1 1 67D8FB14 +P 1300 1100 +F 0 "U2" H 1300 1000 60 0000 C CNN +F 1 "d_inverter" H 1300 1250 60 0000 C CNN +F 2 "" H 1350 1050 60 0000 C CNN +F 3 "" H 1350 1050 60 0000 C CNN + 1 1300 1100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67D8FB15 +P 2050 1100 +F 0 "U5" H 2050 1000 60 0000 C CNN +F 1 "d_inverter" H 2050 1250 60 0000 C CNN +F 2 "" H 2100 1050 60 0000 C CNN +F 3 "" H 2100 1050 60 0000 C CNN + 1 2050 1100 + 1 0 0 -1 +$EndComp +Text Label 10000 4500 0 60 ~ 0 +VCC +Text Label 4700 6300 0 60 ~ 0 +Q0 +Text Label 8700 6200 0 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+U 4 1 67D9036E +P 7550 700 +F 0 "U1" H 7600 800 30 0000 C CNN +F 1 "PORT" H 7550 700 30 0000 C CNN +F 2 "" H 7550 700 60 0000 C CNN +F 3 "" H 7550 700 60 0000 C CNN + 4 7550 700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67D905AD +P 9550 750 +F 0 "U1" H 9600 850 30 0000 C CNN +F 1 "PORT" H 9550 750 30 0000 C CNN +F 2 "" H 9550 750 60 0000 C CNN +F 3 "" H 9550 750 60 0000 C CNN + 5 9550 750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67D908EC +P 650 800 +F 0 "U1" H 700 900 30 0000 C CNN +F 1 "PORT" H 650 800 30 0000 C CNN +F 2 "" H 650 800 60 0000 C CNN +F 3 "" H 650 800 60 0000 C CNN + 6 650 800 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 67D910F2 +P 650 4650 +F 0 "U1" H 700 4750 30 0000 C CNN +F 1 "PORT" H 650 4650 30 0000 C CNN +F 2 "" H 650 4650 60 0000 C CNN +F 3 "" H 650 4650 60 0000 C CNN + 8 650 4650 + 0 1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 67D91351 +P 650 3650 +F 0 "U1" H 700 3750 30 0000 C CNN +F 1 "PORT" H 650 3650 30 0000 C CNN +F 2 "" H 650 3650 60 0000 C CNN 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60 0000 C CNN +F 3 "" H 10375 4500 60 0000 C CNN + 7 10375 4500 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B.sub b/library/SubcircuitLibrary/74LS95B/74LS95B.sub new file mode 100644 index 00000000..5d893f01 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B.sub @@ -0,0 +1,106 @@ +* Subcircuit 74LS95B +.subckt 74LS95B /ds /p0 /p1 /p2 /p3 /s /vcc /cp2 /cp1 /q3 /q2 /q1 /q0 net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74ls95b\74ls95b.cir +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? d_srff +* u21 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? d_srff +* u26 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? d_srff +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u11-pad3_ d_or +* u3 net-_u12-pad2_ /cp1 net-_u3-pad3_ d_and +* u4 /s /cp2 net-_u4-pad3_ d_and +* u8 net-_u10-pad3_ net-_u7-pad3_ net-_u11-pad2_ d_nor +* u7 /ds net-_u12-pad2_ net-_u7-pad3_ d_and +* u10 net-_u10-pad1_ /p0 net-_u10-pad3_ d_and +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor +* u12 /q0 net-_u12-pad2_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ /p1 net-_u13-pad1_ d_and +* u18 net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_nor +* u17 /q1 net-_u12-pad2_ net-_u17-pad3_ d_and +* u20 net-_u10-pad1_ /p2 net-_u18-pad1_ d_and +* u23 net-_u23-pad1_ net-_u22-pad3_ net-_u23-pad3_ d_nor +* u22 /q2 net-_u12-pad2_ net-_u22-pad3_ d_and +* u25 net-_u10-pad1_ /p3 net-_u23-pad1_ d_and +* u9 net-_u11-pad2_ net-_u11-pad1_ d_inverter +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u19 net-_u18-pad3_ net-_u19-pad2_ d_inverter +* u24 net-_u23-pad3_ net-_u24-pad2_ d_inverter +* u2 /s net-_u12-pad2_ d_inverter +* u5 net-_u12-pad2_ net-_u10-pad1_ d_inverter +* u16 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? d_srff +a1 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q0 ? u11 +a2 net-_u19-pad2_ net-_u18-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q2 ? u21 +a3 net-_u24-pad2_ net-_u23-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q3 ? u26 +a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u11-pad3_ u6 +a5 [net-_u12-pad2_ /cp1 ] net-_u3-pad3_ u3 +a6 [/s /cp2 ] net-_u4-pad3_ u4 +a7 [net-_u10-pad3_ net-_u7-pad3_ ] net-_u11-pad2_ u8 +a8 [/ds net-_u12-pad2_ ] net-_u7-pad3_ u7 +a9 [net-_u10-pad1_ /p0 ] net-_u10-pad3_ u10 +a10 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a11 [/q0 net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u10-pad1_ /p1 ] net-_u13-pad1_ u15 +a13 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18 +a14 [/q1 net-_u12-pad2_ ] net-_u17-pad3_ u17 +a15 [net-_u10-pad1_ /p2 ] net-_u18-pad1_ u20 +a16 [net-_u23-pad1_ net-_u22-pad3_ ] net-_u23-pad3_ u23 +a17 [/q2 net-_u12-pad2_ ] net-_u22-pad3_ u22 +a18 [net-_u10-pad1_ /p3 ] net-_u23-pad1_ u25 +a19 net-_u11-pad2_ net-_u11-pad1_ u9 +a20 net-_u13-pad3_ net-_u14-pad2_ u14 +a21 net-_u18-pad3_ net-_u19-pad2_ u19 +a22 net-_u23-pad3_ net-_u24-pad2_ u24 +a23 /s net-_u12-pad2_ u2 +a24 net-_u12-pad2_ net-_u10-pad1_ u5 +a25 net-_u14-pad2_ net-_u13-pad3_ net-_u11-pad3_ net-_u1-pad14_ /vcc /q1 ? u16 +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u21 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u26 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u16 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends 74LS95B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml b/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml new file mode 100644 index 00000000..661514d9 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/74LS95B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u11 name="type">d_srff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u11><u16 name="type">d_srff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for SR Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u16><u21 name="type">d_srff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for SR Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u21><u26 name="type">d_srff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for SR Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u26><u6 name="type">d_or<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u6><u3 name="type">d_and<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_and<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_nor<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_and<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u10><u13 name="type">d_nor<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_and<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_and<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u15><u18 name="type">d_nor<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u18><u17 name="type">d_and<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u17><u20 name="type">d_and<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u20><u23 name="type">d_nor<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u23><u22 name="type">d_and<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_and<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u25><u9 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u19><u24 name="type">d_inverter<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u24><u2 name="type">d_inverter<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_inverter<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u5><u27 name="type">adc_bridge<field94 name="Enter value for in_low (default=1.0)">0</field94><field95 name="Enter value for in_high (default=2.0)">3.3</field95><field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">adc_bridge<field98 name="Enter value for in_low (default=1.0)">0</field98><field99 name="Enter value for in_high (default=2.0)">3.3</field99><field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">adc_bridge<field102 name="Enter value for in_low (default=1.0)">0</field102><field103 name="Enter value for in_high (default=2.0)">3.3</field103><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">adc_bridge<field106 name="Enter value for in_low (default=1.0)">0</field106><field107 name="Enter value for in_high (default=2.0)">3.3</field107><field108 name="Enter Rise Delay (default=1.0e-9)" /><field109 name="Enter Fall Delay (default=1.0e-9)" /></u30></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LS95B/analysis b/library/SubcircuitLibrary/74LS95B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74LS95B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib new file mode 100644 index 00000000..e73e9677 --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib @@ -0,0 +1,118 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dlatch +# +DEF d_dlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dlatch" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X EN 2 -550 -300 200 R 50 50 1 1 I +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir new file mode 100644 index 00000000..bdb59d4c --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir @@ -0,0 +1,37 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74VHC373-D\74VHC373-D.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/19/25 15:22:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad2_ Net-_U10-Pad2_ ? ? ? Net-_U4-Pad6_ d_dlatch +U13 Net-_U1-Pad9_ Net-_U10-Pad2_ ? ? ? Net-_U13-Pad6_ d_dlatch +U10 Net-_U1-Pad7_ Net-_U10-Pad2_ ? ? ? Net-_U10-Pad6_ d_dlatch +U16 Net-_U1-Pad11_ Net-_U10-Pad2_ ? ? ? Net-_U16-Pad6_ d_dlatch +U19 Net-_U1-Pad13_ Net-_U10-Pad2_ ? ? ? Net-_U19-Pad6_ d_dlatch +U22 Net-_U1-Pad15_ Net-_U10-Pad2_ ? ? ? Net-_U22-Pad6_ d_dlatch +U25 Net-_U1-Pad17_ Net-_U10-Pad2_ ? ? ? Net-_U25-Pad6_ d_dlatch +U7 Net-_U1-Pad5_ Net-_U10-Pad2_ ? ? ? Net-_U7-Pad6_ d_dlatch +U5 Net-_U4-Pad6_ Net-_U11-Pad2_ Net-_U5-Pad3_ d_tristate +U8 Net-_U7-Pad6_ Net-_U11-Pad2_ Net-_U8-Pad3_ d_tristate +U11 Net-_U10-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_tristate +U14 Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate +U17 Net-_U16-Pad6_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_tristate +U20 Net-_U19-Pad6_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_tristate +U23 Net-_U22-Pad6_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_tristate +U26 Net-_U25-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_tristate +U6 Net-_U5-Pad3_ Net-_U1-Pad4_ d_inverter +U9 Net-_U8-Pad3_ Net-_U1-Pad6_ d_inverter +U12 Net-_U11-Pad3_ Net-_U1-Pad8_ d_inverter +U15 Net-_U14-Pad3_ Net-_U1-Pad10_ d_inverter +U18 Net-_U17-Pad3_ Net-_U1-Pad12_ d_inverter +U21 Net-_U20-Pad3_ Net-_U1-Pad14_ d_inverter +U24 Net-_U23-Pad3_ Net-_U1-Pad16_ d_inverter +U27 Net-_U26-Pad3_ Net-_U1-Pad18_ d_inverter +U3 Net-_U1-Pad3_ Net-_U11-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U10-Pad2_ d_buffer +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ GND GND PORT + +.end diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out new file mode 100644 index 00000000..0c1dfc21 --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out @@ -0,0 +1,116 @@ +* c:\fossee\esim\library\subcircuitlibrary\74vhc373-d\74vhc373-d.cir + +* u4 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ d_dlatch +* u13 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ d_dlatch +* u10 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ d_dlatch +* u16 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ d_dlatch +* u19 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ d_dlatch +* u22 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ d_dlatch +* u25 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ d_dlatch +* u7 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ d_dlatch +* u5 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ d_tristate +* u8 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ d_tristate +* u11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ d_tristate +* u14 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u17 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ d_tristate +* u20 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ d_tristate +* u23 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ d_tristate +* u26 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ d_tristate +* u6 net-_u5-pad3_ net-_u1-pad4_ d_inverter +* u9 net-_u8-pad3_ net-_u1-pad6_ d_inverter +* u12 net-_u11-pad3_ net-_u1-pad8_ d_inverter +* u15 net-_u14-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u17-pad3_ net-_u1-pad12_ d_inverter +* u21 net-_u20-pad3_ net-_u1-pad14_ d_inverter +* u24 net-_u23-pad3_ net-_u1-pad16_ d_inverter +* u27 net-_u26-pad3_ net-_u1-pad18_ d_inverter +* u3 net-_u1-pad3_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_buffer +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd port +a1 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ u4 +a2 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ u13 +a3 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ u10 +a4 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ u16 +a5 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ u19 +a6 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ u22 +a7 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ u25 +a8 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ u7 +a9 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ u5 +a10 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ u8 +a11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ u11 +a12 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ u14 +a13 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ u17 +a14 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ u20 +a15 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ u23 +a16 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ u26 +a17 net-_u5-pad3_ net-_u1-pad4_ u6 +a18 net-_u8-pad3_ net-_u1-pad6_ u9 +a19 net-_u11-pad3_ net-_u1-pad8_ u12 +a20 net-_u14-pad3_ net-_u1-pad10_ u15 +a21 net-_u17-pad3_ net-_u1-pad12_ u18 +a22 net-_u20-pad3_ net-_u1-pad14_ u21 +a23 net-_u23-pad3_ net-_u1-pad16_ u24 +a24 net-_u26-pad3_ net-_u1-pad18_ u27 +a25 net-_u1-pad3_ net-_u11-pad2_ u3 +a26 net-_u1-pad1_ net-_u10-pad2_ u2 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u10 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u22 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch new file mode 100644 index 00000000..73904330 --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch @@ -0,0 +1,719 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74VHC373-D-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dlatch U4 +U 1 1 68036DC1 +P 1350 2575 +F 0 "U4" H 1350 2575 60 0000 C CNN +F 1 "d_dlatch" H 1350 2725 60 0000 C CNN +F 2 "" H 1350 2575 60 0000 C CNN +F 3 "" H 1350 2575 60 0000 C CNN + 1 1350 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U13 +U 1 1 68036DC2 +P 5150 2575 +F 0 "U13" H 5150 2575 60 0000 C CNN +F 1 "d_dlatch" H 5150 2725 60 0000 C CNN +F 2 "" H 5150 2575 60 0000 C CNN +F 3 "" H 5150 2575 60 0000 C CNN + 1 5150 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U10 +U 1 1 68036DC3 +P 3875 2575 +F 0 "U10" H 3875 2575 60 0000 C CNN +F 1 "d_dlatch" H 3875 2725 60 0000 C CNN +F 2 "" H 3875 2575 60 0000 C CNN +F 3 "" H 3875 2575 60 0000 C CNN + 1 3875 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U16 +U 1 1 68036DC4 +P 6350 2575 +F 0 "U16" H 6350 2575 60 0000 C CNN +F 1 "d_dlatch" H 6350 2725 60 0000 C CNN +F 2 "" H 6350 2575 60 0000 C CNN +F 3 "" H 6350 2575 60 0000 C CNN + 1 6350 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U19 +U 1 1 68036DC5 +P 7575 2575 +F 0 "U19" H 7575 2575 60 0000 C CNN +F 1 "d_dlatch" H 7575 2725 60 0000 C CNN +F 2 "" H 7575 2575 60 0000 C CNN +F 3 "" H 7575 2575 60 0000 C CNN + 1 7575 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U22 +U 1 1 68036DC6 +P 8875 2575 +F 0 "U22" H 8875 2575 60 0000 C CNN +F 1 "d_dlatch" H 8875 2725 60 0000 C CNN +F 2 "" H 8875 2575 60 0000 C CNN +F 3 "" H 8875 2575 60 0000 C CNN + 1 8875 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U25 +U 1 1 68036DC7 +P 10250 2575 +F 0 "U25" H 10250 2575 60 0000 C CNN +F 1 "d_dlatch" H 10250 2725 60 0000 C CNN +F 2 "" H 10250 2575 60 0000 C CNN +F 3 "" H 10250 2575 60 0000 C CNN + 1 10250 2575 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U7 +U 1 1 68036DC8 +P 2600 2575 +F 0 "U7" H 2600 2575 60 0000 C CNN +F 1 "d_dlatch" H 2600 2725 60 0000 C CNN +F 2 "" H 2600 2575 60 0000 C CNN +F 3 "" H 2600 2575 60 0000 C CNN + 1 2600 2575 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 3825 9700 3825 +Wire Wire Line + 9700 3825 9700 2875 +Wire Wire Line + 8325 2875 8325 3825 +Connection ~ 8325 3825 +Wire Wire Line + 7025 2875 7025 3825 +Connection ~ 7025 3825 +Wire Wire Line + 5800 2875 5800 3825 +Connection ~ 5800 3825 +Wire Wire Line + 4600 2875 4600 3825 +Connection ~ 4600 3825 +Wire Wire Line + 3325 2875 3325 3825 +Connection ~ 3325 3825 +Wire Wire Line + 2050 2875 2050 3825 +Connection ~ 2050 3825 +Wire Wire Line + 1775 3825 1775 3325 +Wire Wire Line + 1775 3325 800 3325 +Wire Wire Line + 800 3325 800 2875 +Connection ~ 1775 3825 +$Comp +L d_tristate U5 +U 1 1 68036DC9 +P 1550 4975 +F 0 "U5" H 1300 5225 60 0000 C CNN +F 1 "d_tristate" H 1350 5425 60 0000 C CNN +F 2 "" H 1450 5325 60 0000 C CNN +F 3 "" H 1450 5325 60 0000 C CNN + 1 1550 4975 + 0 1 1 0 +$EndComp +Wire Wire Line + 1900 2875 1900 4375 +$Comp +L d_tristate U8 +U 1 1 68036DCA +P 2825 4950 +F 0 "U8" H 2575 5200 60 0000 C CNN +F 1 "d_tristate" H 2625 5400 60 0000 C CNN +F 2 "" H 2725 5300 60 0000 C CNN +F 3 "" H 2725 5300 60 0000 C CNN + 1 2825 4950 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U11 +U 1 1 68036DCB +P 4075 4975 +F 0 "U11" H 3825 5225 60 0000 C CNN +F 1 "d_tristate" H 3875 5425 60 0000 C CNN +F 2 "" H 3975 5325 60 0000 C CNN +F 3 "" H 3975 5325 60 0000 C CNN + 1 4075 4975 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U14 +U 1 1 68036DCC +P 5350 4925 +F 0 "U14" H 5100 5175 60 0000 C CNN +F 1 "d_tristate" H 5150 5375 60 0000 C CNN +F 2 "" H 5250 5275 60 0000 C CNN +F 3 "" H 5250 5275 60 0000 C CNN + 1 5350 4925 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U17 +U 1 1 68036DCD +P 6550 4925 +F 0 "U17" H 6300 5175 60 0000 C CNN +F 1 "d_tristate" H 6350 5375 60 0000 C CNN +F 2 "" H 6450 5275 60 0000 C CNN +F 3 "" H 6450 5275 60 0000 C CNN + 1 6550 4925 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U20 +U 1 1 68036DCE +P 7775 4925 +F 0 "U20" H 7525 5175 60 0000 C CNN +F 1 "d_tristate" H 7575 5375 60 0000 C CNN +F 2 "" H 7675 5275 60 0000 C CNN +F 3 "" H 7675 5275 60 0000 C CNN + 1 7775 4925 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U23 +U 1 1 68036DCF +P 9075 4925 +F 0 "U23" H 8825 5175 60 0000 C CNN +F 1 "d_tristate" H 8875 5375 60 0000 C CNN +F 2 "" H 8975 5275 60 0000 C CNN +F 3 "" H 8975 5275 60 0000 C CNN + 1 9075 4925 + 0 1 1 0 +$EndComp +Wire Wire Line + 3175 4350 3175 2875 +Wire Wire Line + 3175 2875 3150 2875 +Wire Wire Line + 4425 4375 4425 2875 +Wire Wire Line + 6900 4325 6900 2875 +Wire Wire Line + 5700 4325 5700 2875 +Wire Wire Line + 8125 4325 8125 2875 +Wire Wire Line + 9425 4325 9425 2875 +$Comp +L d_tristate U26 +U 1 1 68036DD0 +P 10450 4925 +F 0 "U26" H 10200 5175 60 0000 C CNN +F 1 "d_tristate" H 10250 5375 60 0000 C CNN +F 2 "" H 10350 5275 60 0000 C CNN +F 3 "" H 10350 5275 60 0000 C CNN + 1 10450 4925 + 0 1 1 0 +$EndComp +Wire Wire Line + 10800 4325 10800 2875 +$Comp +L d_inverter U6 +U 1 1 68036DD1 +P 1900 5950 +F 0 "U6" H 1900 5850 60 0000 C CNN +F 1 "d_inverter" H 1900 6100 60 0000 C CNN +F 2 "" H 1950 5900 60 0000 C CNN +F 3 "" H 1950 5900 60 0000 C CNN + 1 1900 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68036DD2 +P 3175 5950 +F 0 "U9" H 3175 5850 60 0000 C CNN +F 1 "d_inverter" H 3175 6100 60 0000 C CNN +F 2 "" H 3225 5900 60 0000 C CNN +F 3 "" H 3225 5900 60 0000 C CNN + 1 3175 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68036DD3 +P 4425 5950 +F 0 "U12" H 4425 5850 60 0000 C CNN +F 1 "d_inverter" H 4425 6100 60 0000 C CNN +F 2 "" H 4475 5900 60 0000 C CNN +F 3 "" H 4475 5900 60 0000 C CNN + 1 4425 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 68036DD4 +P 5700 5950 +F 0 "U15" H 5700 5850 60 0000 C CNN +F 1 "d_inverter" H 5700 6100 60 0000 C CNN +F 2 "" H 5750 5900 60 0000 C CNN +F 3 "" H 5750 5900 60 0000 C CNN + 1 5700 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U18 +U 1 1 68036DD5 +P 6900 5950 +F 0 "U18" H 6900 5850 60 0000 C CNN +F 1 "d_inverter" H 6900 6100 60 0000 C CNN +F 2 "" H 6950 5900 60 0000 C CNN +F 3 "" H 6950 5900 60 0000 C CNN + 1 6900 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U21 +U 1 1 68036DD6 +P 8125 5950 +F 0 "U21" H 8125 5850 60 0000 C CNN +F 1 "d_inverter" H 8125 6100 60 0000 C CNN +F 2 "" H 8175 5900 60 0000 C CNN +F 3 "" H 8175 5900 60 0000 C CNN + 1 8125 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 68036DD7 +P 9425 5950 +F 0 "U24" H 9425 5850 60 0000 C CNN +F 1 "d_inverter" H 9425 6100 60 0000 C CNN +F 2 "" H 9475 5900 60 0000 C CNN +F 3 "" H 9475 5900 60 0000 C CNN + 1 9425 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U27 +U 1 1 68036DD8 +P 10800 5950 +F 0 "U27" H 10800 5850 60 0000 C CNN +F 1 "d_inverter" H 10800 6100 60 0000 C CNN +F 2 "" H 10850 5900 60 0000 C CNN +F 3 "" H 10850 5900 60 0000 C CNN + 1 10800 5950 + 0 1 1 0 +$EndComp +Wire Wire Line + 1900 5650 1900 5525 +Wire Wire Line + 3175 5500 3175 5650 +Wire Wire Line + 4425 5525 4425 5650 +Wire Wire Line + 5700 5475 5700 5650 +Wire Wire Line + 6900 5475 6900 5650 +Wire Wire Line + 8125 5475 8125 5650 +Wire Wire Line + 9425 5475 9425 5650 +Wire Wire Line + 10800 5475 10800 5650 +Wire Wire Line + 10500 5575 10500 4875 +Wire Wire Line + 1400 5575 10500 5575 +Wire Wire Line + 1600 4925 1600 5575 +Connection ~ 1600 5575 +Wire Wire Line + 2875 4900 2875 5575 +Connection ~ 2875 5575 +Wire Wire Line + 4125 4925 4125 5575 +Connection ~ 4125 5575 +Wire Wire Line + 5400 4875 5400 5575 +Connection ~ 5400 5575 +Wire Wire Line + 6600 4875 6600 5575 +Connection ~ 6600 5575 +Wire Wire Line + 7825 4875 7825 5575 +Connection ~ 7825 5575 +Wire Wire Line + 9125 4875 9125 5575 +Connection ~ 9125 5575 +$Comp +L d_inverter U3 +U 1 1 68036DD9 +P 1100 5575 +F 0 "U3" H 1100 5475 60 0000 C CNN +F 1 "d_inverter" H 1100 5725 60 0000 C CNN +F 2 "" H 1150 5525 60 0000 C CNN +F 3 "" H 1150 5525 60 0000 C CNN + 1 1100 5575 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 6250 1900 6350 +Wire Wire Line + 800 5575 800 5800 +Wire Wire Line + 800 5800 1300 5800 +Wire Wire Line + 1300 5800 1300 5825 +$Comp +L d_buffer U2 +U 1 1 68036DE5 +P 1050 3825 +F 0 "U2" H 1050 3775 60 0000 C CNN +F 1 "d_buffer" H 1050 3875 60 0000 C CNN +F 2 "" H 1050 3825 60 0000 C CNN +F 3 "" H 1050 3825 60 0000 C CNN + 1 1050 3825 + 1 0 0 -1 +$EndComp +Wire Wire Line + 550 3950 550 3825 +$Comp +L PORT U1 +U 3 1 680374BD +P 1300 6075 +F 0 "U1" H 1350 6175 30 0000 C CNN +F 1 "PORT" H 1300 6075 30 0000 C CNN +F 2 "" H 1300 6075 60 0000 C CNN +F 3 "" H 1300 6075 60 0000 C CNN + 3 1300 6075 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 68037704 +P 800 1800 +F 0 "U1" H 850 1900 30 0000 C CNN +F 1 "PORT" H 800 1800 30 0000 C CNN +F 2 "" H 800 1800 60 0000 C CNN +F 3 "" H 800 1800 60 0000 C CNN + 2 800 1800 + 0 1 1 0 +$EndComp +Wire Wire Line + 800 2225 800 2050 +$Comp +L PORT U1 +U 5 1 680378F4 +P 2050 1775 +F 0 "U1" H 2100 1875 30 0000 C CNN +F 1 "PORT" H 2050 1775 30 0000 C CNN +F 2 "" H 2050 1775 60 0000 C CNN +F 3 "" H 2050 1775 60 0000 C CNN + 5 2050 1775 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 680379E4 +P 3325 1775 +F 0 "U1" H 3375 1875 30 0000 C CNN +F 1 "PORT" H 3325 1775 30 0000 C CNN +F 2 "" H 3325 1775 60 0000 C CNN +F 3 "" H 3325 1775 60 0000 C CNN + 7 3325 1775 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 68037AA2 +P 4600 1775 +F 0 "U1" H 4650 1875 30 0000 C CNN +F 1 "PORT" H 4600 1775 30 0000 C CNN +F 2 "" H 4600 1775 60 0000 C CNN +F 3 "" H 4600 1775 60 0000 C CNN + 9 4600 1775 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 68037C2C +P 5800 1775 +F 0 "U1" H 5850 1875 30 0000 C CNN +F 1 "PORT" H 5800 1775 30 0000 C CNN +F 2 "" H 5800 1775 60 0000 C CNN +F 3 "" H 5800 1775 60 0000 C CNN + 11 5800 1775 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 68037CF5 +P 7025 1775 +F 0 "U1" H 7075 1875 30 0000 C CNN +F 1 "PORT" H 7025 1775 30 0000 C CNN +F 2 "" H 7025 1775 60 0000 C CNN +F 3 "" H 7025 1775 60 0000 C CNN + 13 7025 1775 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 68037D90 +P 8325 1725 +F 0 "U1" H 8375 1825 30 0000 C CNN +F 1 "PORT" H 8325 1725 30 0000 C CNN +F 2 "" H 8325 1725 60 0000 C CNN +F 3 "" H 8325 1725 60 0000 C CNN + 15 8325 1725 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 17 1 68037E63 +P 9700 1725 +F 0 "U1" H 9750 1825 30 0000 C CNN +F 1 "PORT" H 9700 1725 30 0000 C CNN +F 2 "" H 9700 1725 60 0000 C CNN +F 3 "" H 9700 1725 60 0000 C CNN + 17 9700 1725 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 680382FD +P 550 4200 +F 0 "U1" H 600 4300 30 0000 C CNN +F 1 "PORT" H 550 4200 30 0000 C CNN +F 2 "" H 550 4200 60 0000 C CNN +F 3 "" H 550 4200 60 0000 C CNN + 1 550 4200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 18 1 680389CC +P 10425 6250 +F 0 "U1" H 10475 6350 30 0000 C CNN +F 1 "PORT" H 10425 6250 30 0000 C CNN +F 2 "" H 10425 6250 60 0000 C CNN +F 3 "" H 10425 6250 60 0000 C CNN + 18 10425 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 68038A85 +P 8975 6250 +F 0 "U1" H 9025 6350 30 0000 C CNN +F 1 "PORT" H 8975 6250 30 0000 C CNN +F 2 "" H 8975 6250 60 0000 C CNN +F 3 "" H 8975 6250 60 0000 C CNN + 16 8975 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68038BCA +P 7675 6250 +F 0 "U1" H 7725 6350 30 0000 C CNN +F 1 "PORT" H 7675 6250 30 0000 C CNN +F 2 "" H 7675 6250 60 0000 C CNN +F 3 "" H 7675 6250 60 0000 C CNN + 14 7675 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68038C2D +P 6400 6250 +F 0 "U1" H 6450 6350 30 0000 C CNN +F 1 "PORT" H 6400 6250 30 0000 C CNN +F 2 "" H 6400 6250 60 0000 C CNN +F 3 "" H 6400 6250 60 0000 C CNN + 12 6400 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68038CBA +P 5250 6250 +F 0 "U1" H 5300 6350 30 0000 C CNN +F 1 "PORT" H 5250 6250 30 0000 C CNN +F 2 "" H 5250 6250 60 0000 C CNN +F 3 "" H 5250 6250 60 0000 C CNN + 10 5250 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68038D9C +P 4125 6250 +F 0 "U1" H 4175 6350 30 0000 C CNN +F 1 "PORT" H 4125 6250 30 0000 C CNN +F 2 "" H 4125 6250 60 0000 C CNN +F 3 "" H 4125 6250 60 0000 C CNN + 8 4125 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68038E2F +P 2800 6250 +F 0 "U1" H 2850 6350 30 0000 C CNN +F 1 "PORT" H 2800 6250 30 0000 C CNN +F 2 "" H 2800 6250 60 0000 C CNN +F 3 "" H 2800 6250 60 0000 C CNN + 6 2800 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68038E9A +P 1575 6350 +F 0 "U1" H 1625 6450 30 0000 C CNN +F 1 "PORT" H 1575 6350 30 0000 C CNN +F 2 "" H 1575 6350 60 0000 C CNN +F 3 "" H 1575 6350 60 0000 C CNN + 4 1575 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 2225 2050 2025 +Wire Wire Line + 3325 2025 3325 2225 +Wire Wire Line + 4600 2025 4600 2225 +Wire Wire Line + 5800 2025 5800 2225 +Wire Wire Line + 7025 2025 7025 2225 +Wire Wire Line + 8325 2225 8325 1975 +Wire Wire Line + 9700 1975 9700 2225 +Wire Wire Line + 10675 6250 10800 6250 +Wire Wire Line + 9225 6250 9425 6250 +Wire Wire Line + 7925 6250 8125 6250 +Wire Wire Line + 6650 6250 6900 6250 +Wire Wire Line + 5500 6250 5700 6250 +Wire Wire Line + 4375 6250 4425 6250 +Wire Wire Line + 3050 6250 3175 6250 +Wire Wire Line + 1900 6350 1825 6350 +$Comp +L PORT U1 +U 19 1 6803F5A5 +P 8950 850 +F 0 "U1" H 9000 950 30 0000 C CNN +F 1 "PORT" H 8950 850 30 0000 C CNN +F 2 "" H 8950 850 60 0000 C CNN +F 3 "" H 8950 850 60 0000 C CNN + 19 8950 850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 6803F642 +P 8950 1200 +F 0 "U1" H 9000 1300 30 0000 C CNN +F 1 "PORT" H 8950 1200 30 0000 C CNN +F 2 "" H 8950 1200 60 0000 C CNN +F 3 "" H 8950 1200 60 0000 C CNN + 20 8950 1200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 6803F749 +P 9550 850 +F 0 "#PWR01" H 9550 600 50 0001 C CNN +F 1 "eSim_GND" H 9550 700 50 0000 C CNN +F 2 "" H 9550 850 50 0001 C CNN +F 3 "" H 9550 850 50 0001 C CNN + 1 9550 850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR02 +U 1 1 6803F7E5 +P 9500 1200 +F 0 "#PWR02" H 9500 950 50 0001 C CNN +F 1 "eSim_GND" H 9500 1050 50 0000 C CNN +F 2 "" H 9500 1200 50 0001 C CNN +F 3 "" H 9500 1200 50 0001 C CNN + 1 9500 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9200 1200 9500 1200 +Wire Wire Line + 9550 850 9200 850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub new file mode 100644 index 00000000..e78fc2ff --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub @@ -0,0 +1,110 @@ +* Subcircuit 74VHC373-D +.subckt 74VHC373-D net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd +* c:\fossee\esim\library\subcircuitlibrary\74vhc373-d\74vhc373-d.cir +* u4 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ d_dlatch +* u13 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ d_dlatch +* u10 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ d_dlatch +* u16 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ d_dlatch +* u19 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ d_dlatch +* u22 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ d_dlatch +* u25 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ d_dlatch +* u7 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ d_dlatch +* u5 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ d_tristate +* u8 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ d_tristate +* u11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ d_tristate +* u14 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u17 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ d_tristate +* u20 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ d_tristate +* u23 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ d_tristate +* u26 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ d_tristate +* u6 net-_u5-pad3_ net-_u1-pad4_ d_inverter +* u9 net-_u8-pad3_ net-_u1-pad6_ d_inverter +* u12 net-_u11-pad3_ net-_u1-pad8_ d_inverter +* u15 net-_u14-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u17-pad3_ net-_u1-pad12_ d_inverter +* u21 net-_u20-pad3_ net-_u1-pad14_ d_inverter +* u24 net-_u23-pad3_ net-_u1-pad16_ d_inverter +* u27 net-_u26-pad3_ net-_u1-pad18_ d_inverter +* u3 net-_u1-pad3_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_buffer +a1 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ u4 +a2 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ u13 +a3 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ u10 +a4 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ u16 +a5 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ u19 +a6 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ u22 +a7 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ u25 +a8 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ u7 +a9 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ u5 +a10 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ u8 +a11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ u11 +a12 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ u14 +a13 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ u17 +a14 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ u20 +a15 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ u23 +a16 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ u26 +a17 net-_u5-pad3_ net-_u1-pad4_ u6 +a18 net-_u8-pad3_ net-_u1-pad6_ u9 +a19 net-_u11-pad3_ net-_u1-pad8_ u12 +a20 net-_u14-pad3_ net-_u1-pad10_ u15 +a21 net-_u17-pad3_ net-_u1-pad12_ u18 +a22 net-_u20-pad3_ net-_u1-pad14_ u21 +a23 net-_u23-pad3_ net-_u1-pad16_ u24 +a24 net-_u26-pad3_ net-_u1-pad18_ u27 +a25 net-_u1-pad3_ net-_u11-pad2_ u3 +a26 net-_u1-pad1_ net-_u10-pad2_ u2 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u10 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u22 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74VHC373-D
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml new file mode 100644 index 00000000..7eccc7ec --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_dlatch<field1 name="Enter Data Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for Data Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u4><u13 name="type">d_dlatch<field12 name="Enter Data Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u13><u10 name="type">d_dlatch<field23 name="Enter Data Delay (default=1.0e-9)" /><field24 name="Enter Enable Delay (default=1.0e-9)" /><field25 name="Enter Set Delay (default=1.0e-9)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter IC (default=0)" /><field28 name="Enter value for Data Load (default=1.0e-12)" /><field29 name="Enter value for Enable Load (default=1.0e-12)" /><field30 name="Enter value for Set Load (default=1.0e-12)" /><field31 name="Enter value for Reset Load (default=1.0e-12)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u10><u16 name="type">d_dlatch<field34 name="Enter Data Delay (default=1.0e-9)" /><field35 name="Enter Enable Delay (default=1.0e-9)" /><field36 name="Enter Set Delay (default=1.0e-9)" /><field37 name="Enter Reset Delay (default=1.0)" /><field38 name="Enter IC (default=0)" /><field39 name="Enter value for Data Load (default=1.0e-12)" /><field40 name="Enter value for Enable Load (default=1.0e-12)" /><field41 name="Enter value for Set Load (default=1.0e-12)" /><field42 name="Enter value for Reset Load (default=1.0e-12)" /><field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /></u16><u19 name="type">d_dlatch<field45 name="Enter Data Delay (default=1.0e-9)" /><field46 name="Enter Enable Delay (default=1.0e-9)" /><field47 name="Enter Set Delay (default=1.0e-9)" /><field48 name="Enter Reset Delay (default=1.0)" /><field49 name="Enter IC (default=0)" /><field50 name="Enter value for Data Load (default=1.0e-12)" /><field51 name="Enter value for Enable Load (default=1.0e-12)" /><field52 name="Enter value for Set Load (default=1.0e-12)" /><field53 name="Enter value for Reset Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /><field55 name="Enter Fall Delay (default=1.0e-9)" /></u19><u22 name="type">d_dlatch<field56 name="Enter Data Delay (default=1.0e-9)" /><field57 name="Enter Enable Delay (default=1.0e-9)" /><field58 name="Enter Set Delay (default=1.0e-9)" /><field59 name="Enter Reset Delay (default=1.0)" /><field60 name="Enter IC (default=0)" /><field61 name="Enter value for Data Load (default=1.0e-12)" /><field62 name="Enter value for Enable Load (default=1.0e-12)" /><field63 name="Enter value for Set Load (default=1.0e-12)" /><field64 name="Enter value for Reset Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u22><u25 name="type">d_dlatch<field67 name="Enter Data Delay (default=1.0e-9)" /><field68 name="Enter Enable Delay (default=1.0e-9)" /><field69 name="Enter Set Delay (default=1.0e-9)" /><field70 name="Enter Reset Delay (default=1.0)" /><field71 name="Enter IC (default=0)" /><field72 name="Enter value for Data Load (default=1.0e-12)" /><field73 name="Enter value for Enable Load (default=1.0e-12)" /><field74 name="Enter value for Set Load (default=1.0e-12)" /><field75 name="Enter value for Reset Load (default=1.0e-12)" /><field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /></u25><u7 name="type">d_dlatch<field78 name="Enter Data Delay (default=1.0e-9)" /><field79 name="Enter Enable Delay (default=1.0e-9)" /><field80 name="Enter Set Delay (default=1.0e-9)" /><field81 name="Enter Reset Delay (default=1.0)" /><field82 name="Enter IC (default=0)" /><field83 name="Enter value for Data Load (default=1.0e-12)" /><field84 name="Enter value for Enable Load (default=1.0e-12)" /><field85 name="Enter value for Set Load (default=1.0e-12)" /><field86 name="Enter value for Reset Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u7><u5 name="type">d_tristate<field89 name="Enter Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /><field91 name="Enter Enable Load (default=1.0e-12)" /></u5><u8 name="type">d_tristate<field92 name="Enter Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /><field94 name="Enter Enable Load (default=1.0e-12)" /></u8><u11 name="type">d_tristate<field95 name="Enter Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /><field97 name="Enter Enable Load (default=1.0e-12)" /></u11><u14 name="type">d_tristate<field98 name="Enter Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Enable Load (default=1.0e-12)" /></u14><u17 name="type">d_tristate<field101 name="Enter Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Enable Load (default=1.0e-12)" /></u17><u20 name="type">d_tristate<field104 name="Enter Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /><field106 name="Enter Enable Load (default=1.0e-12)" /></u20><u23 name="type">d_tristate<field107 name="Enter Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /><field109 name="Enter Enable Load (default=1.0e-12)" /></u23><u26 name="type">d_tristate<field110 name="Enter Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /><field112 name="Enter Enable Load (default=1.0e-12)" /></u26><u6 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u9><u12 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u15><u18 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u18><u21 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u24><u27 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u27><u3 name="type">d_inverter<field137 name="Enter Rise Delay (default=1.0e-9)" /><field138 name="Enter Fall Delay (default=1.0e-9)" /><field139 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_buffer<field140 name="Enter Rise Delay (default=1.0e-9)" /><field141 name="Enter Fall Delay (default=1.0e-9)" /><field142 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74VHC373-D/analysis b/library/SubcircuitLibrary/74VHC373-D/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74VHC373-D/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A-cache.lib b/library/SubcircuitLibrary/CA3160A/CA3160A-cache.lib new file mode 100644 index 00000000..8ffbd3d6 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A-cache.lib @@ -0,0 +1,201 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A.cir b/library/SubcircuitLibrary/CA3160A/CA3160A.cir new file mode 100644 index 00000000..c72c6eb5 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A.cir @@ -0,0 +1,41 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CA3160A\CA3160A.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/26/25 14:47:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +R2 Net-_R2-Pad1_ Net-_D4-Pad2_ 40k +U2 Net-_R2-Pad1_ Net-_R1-Pad2_ zener +R3 Net-_R2-Pad1_ Net-_M8-Pad3_ 5k +M1 Net-_D1-Pad1_ Net-_D1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M3-Pad1_ Net-_D1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M4 Net-_M2-Pad3_ Net-_D4-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P +M6 Net-_M6-Pad1_ Net-_D1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M7 Net-_M7-Pad1_ Net-_D4-Pad2_ Net-_M6-Pad1_ Net-_M6-Pad1_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P +M5 Net-_M5-Pad1_ Net-_M5-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P +R5 Net-_M2-Pad1_ Net-_Q1-Pad1_ 1k +R7 Net-_M5-Pad1_ Net-_C1-Pad2_ 1k +Q1 Net-_Q1-Pad1_ Net-_M2-Pad1_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_C1-Pad2_ Net-_M2-Pad1_ Net-_Q2-Pad3_ eSim_NPN +R6 Net-_Q1-Pad3_ Net-_M8-Pad3_ 1k +R8 Net-_Q2-Pad3_ Net-_M8-Pad3_ 1k +Q3 Net-_M7-Pad1_ Net-_C1-Pad2_ Net-_M8-Pad3_ eSim_NPN +M8 Net-_M8-Pad1_ Net-_M7-Pad1_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_N +M9 Net-_M8-Pad1_ Net-_M7-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +U3 Net-_R4-Pad2_ Net-_M2-Pad2_ zener +U4 Net-_R4-Pad1_ Net-_M2-Pad3_ zener +R4 Net-_R4-Pad1_ Net-_R4-Pad2_ 10 +R1 Net-_M1-Pad3_ Net-_R1-Pad2_ 10 +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +U5 Net-_R4-Pad1_ Net-_M5-Pad2_ zener +R9 Net-_M7-Pad1_ Net-_C1-Pad1_ 2k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +U1 Net-_M2-Pad2_ Net-_M5-Pad2_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_M7-Pad1_ Net-_M8-Pad3_ Net-_M8-Pad1_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A.cir.out b/library/SubcircuitLibrary/CA3160A/CA3160A.cir.out new file mode 100644 index 00000000..2110d504 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A.cir.out @@ -0,0 +1,58 @@ +* c:\fossee\esim\library\subcircuitlibrary\ca3160a\ca3160a.cir + +.include NPN.lib +.include PMOS-5um.lib +.include NMOS-5um.lib +.include schottky.lib +d2 net-_d1-pad2_ net-_d2-pad2_ 1N5819 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N5819 +d4 net-_d3-pad2_ net-_d4-pad2_ 1N5819 +r2 net-_r2-pad1_ net-_d4-pad2_ 40k +* u2 net-_r2-pad1_ net-_r1-pad2_ zener +r3 net-_r2-pad1_ net-_m8-pad3_ 5k +m1 net-_d1-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m4 net-_m2-pad3_ net-_d4-pad2_ net-_m3-pad1_ net-_m3-pad1_ mos_p W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_d4-pad2_ net-_m6-pad1_ net-_m6-pad1_ mos_p W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1 +r5 net-_m2-pad1_ net-_q1-pad1_ 1k +r7 net-_m5-pad1_ net-_c1-pad2_ 1k +q1 net-_q1-pad1_ net-_m2-pad1_ net-_q1-pad3_ Q2N2222 +q2 net-_c1-pad2_ net-_m2-pad1_ net-_q2-pad3_ Q2N2222 +r6 net-_q1-pad3_ net-_m8-pad3_ 1k +r8 net-_q2-pad3_ net-_m8-pad3_ 1k +q3 net-_m7-pad1_ net-_c1-pad2_ net-_m8-pad3_ Q2N2222 +m8 net-_m8-pad1_ net-_m7-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_n W=100u L=100u M=1 +m9 net-_m8-pad1_ net-_m7-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +* u3 net-_r4-pad2_ net-_m2-pad2_ zener +* u4 net-_r4-pad1_ net-_m2-pad3_ zener +r4 net-_r4-pad1_ net-_r4-pad2_ 10 +r1 net-_m1-pad3_ net-_r1-pad2_ 10 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N5819 +* u5 net-_r4-pad1_ net-_m5-pad2_ zener +r9 net-_m7-pad1_ net-_c1-pad1_ 2k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +* u1 net-_m2-pad2_ net-_m5-pad2_ net-_q1-pad3_ net-_q2-pad3_ net-_m7-pad1_ net-_m8-pad3_ net-_m8-pad1_ net-_m1-pad3_ port +a1 net-_r2-pad1_ net-_r1-pad2_ u2 +a2 net-_r4-pad2_ net-_m2-pad2_ u3 +a3 net-_r4-pad1_ net-_m2-pad3_ u4 +a4 net-_r4-pad1_ net-_m5-pad2_ u5 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=8.3 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A.pro b/library/SubcircuitLibrary/CA3160A/CA3160A.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A.sch b/library/SubcircuitLibrary/CA3160A/CA3160A.sch new file mode 100644 index 00000000..4a875be4 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A.sch @@ -0,0 +1,705 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CA3130-cache +LIBS:CA3130A_Test-cache +EELAYER 25 0 +EELAYER END +$Descr B 17000 11000 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D2 +U 1 1 680CA884 +P 5225 3725 +F 0 "D2" H 5225 3825 50 0000 C CNN +F 1 "eSim_Diode" H 5225 3625 50 0000 C CNN +F 2 "" H 5225 3725 60 0000 C CNN +F 3 "" H 5225 3725 60 0000 C CNN + 1 5225 3725 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 680CA885 +P 5225 4100 +F 0 "D3" H 5225 4200 50 0000 C CNN +F 1 "eSim_Diode" H 5225 4000 50 0000 C CNN +F 2 "" H 5225 4100 60 0000 C CNN +F 3 "" H 5225 4100 60 0000 C CNN + 1 5225 4100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 680CA886 +P 5225 4500 +F 0 "D4" H 5225 4600 50 0000 C CNN +F 1 "eSim_Diode" H 5225 4400 50 0000 C CNN +F 2 "" H 5225 4500 60 0000 C CNN +F 3 "" H 5225 4500 60 0000 C CNN + 1 5225 4500 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 680CA887 +P 4425 4875 +F 0 "R2" H 4475 5005 50 0000 C CNN +F 1 "40k" H 4475 4825 50 0000 C CNN +F 2 "" H 4475 4855 30 0000 C CNN +F 3 "" V 4475 4925 30 0000 C CNN + 1 4425 4875 + 1 0 0 -1 +$EndComp +$Comp +L zener U2 +U 1 1 680CA888 +P 4000 4150 +F 0 "U2" H 3950 4050 60 0000 C CNN +F 1 "zener" H 4000 4250 60 0000 C CNN +F 2 "" H 4050 4150 60 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4000 4150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 680CA889 +P 4450 5275 +F 0 "R3" H 4500 5405 50 0000 C CNN +F 1 "5k" H 4500 5225 50 0000 C CNN +F 2 "" H 4500 5255 30 0000 C CNN +F 3 "" V 4500 5325 30 0000 C CNN + 1 4450 5275 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M1 +U 1 1 680CA88A +P 5375 2700 +F 0 "M1" H 5325 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5425 2850 50 0000 R CNN +F 2 "" H 5625 2800 29 0000 C CNN +F 3 "" H 5425 2700 60 0000 C CNN + 1 5375 2700 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 680CA88B +P 6575 2700 +F 0 "M3" H 6525 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 6625 2850 50 0000 R CNN +F 2 "" H 6825 2800 29 0000 C CNN +F 3 "" H 6625 2700 60 0000 C CNN + 1 6575 2700 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 680CA88C +P 6575 3350 +F 0 "M4" H 6525 3400 50 0000 R CNN +F 1 "eSim_MOS_P" H 6625 3500 50 0000 R CNN +F 2 "" H 6825 3450 29 0000 C CNN +F 3 "" H 6625 3350 60 0000 C CNN + 1 6575 3350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 680CA88D +P 8850 2625 +F 0 "M6" H 8800 2675 50 0000 R CNN +F 1 "eSim_MOS_P" H 8900 2775 50 0000 R CNN +F 2 "" H 9100 2725 29 0000 C CNN +F 3 "" H 8900 2625 60 0000 C CNN + 1 8850 2625 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 680CA88E +P 8850 3400 +F 0 "M7" H 8800 3450 50 0000 R CNN +F 1 "eSim_MOS_P" H 8900 3550 50 0000 R CNN +F 2 "" H 9100 3500 29 0000 C CNN +F 3 "" H 8900 3400 60 0000 C CNN + 1 8850 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 680CA88F +P 5700 6050 +F 0 "M2" H 5650 6100 50 0000 R CNN +F 1 "eSim_MOS_P" H 5750 6200 50 0000 R CNN +F 2 "" H 5950 6150 29 0000 C CNN +F 3 "" H 5750 6050 60 0000 C CNN + 1 5700 6050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 680CA890 +P 6925 6050 +F 0 "M5" H 6875 6100 50 0000 R CNN +F 1 "eSim_MOS_P" H 6975 6200 50 0000 R CNN +F 2 "" H 7175 6150 29 0000 C CNN +F 3 "" H 6975 6050 60 0000 C CNN + 1 6925 6050 + -1 0 0 1 +$EndComp +$Comp +L resistor R5 +U 1 1 680CA891 +P 5800 6700 +F 0 "R5" H 5850 6830 50 0000 C CNN +F 1 "1k" H 5850 6650 50 0000 C CNN +F 2 "" H 5850 6680 30 0000 C CNN +F 3 "" V 5850 6750 30 0000 C CNN + 1 5800 6700 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 680CA892 +P 6725 6700 +F 0 "R7" H 6775 6830 50 0000 C CNN +F 1 "1k" H 6775 6650 50 0000 C CNN +F 2 "" H 6775 6680 30 0000 C CNN +F 3 "" V 6775 6750 30 0000 C CNN + 1 6725 6700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 680CA893 +P 5950 7200 +F 0 "Q1" H 5850 7250 50 0000 R CNN +F 1 "eSim_NPN" H 5900 7350 50 0000 R CNN +F 2 "" H 6150 7300 29 0000 C CNN +F 3 "" H 5950 7200 60 0000 C CNN + 1 5950 7200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 680CA894 +P 6675 7200 +F 0 "Q2" H 6575 7250 50 0000 R CNN +F 1 "eSim_NPN" H 6625 7350 50 0000 R CNN +F 2 "" H 6875 7300 29 0000 C CNN +F 3 "" H 6675 7200 60 0000 C CNN + 1 6675 7200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 680CA895 +P 5800 7725 +F 0 "R6" H 5850 7855 50 0000 C CNN +F 1 "1k" H 5850 7675 50 0000 C CNN +F 2 "" H 5850 7705 30 0000 C CNN +F 3 "" V 5850 7775 30 0000 C CNN + 1 5800 7725 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 680CA896 +P 6725 7725 +F 0 "R8" H 6775 7855 50 0000 C CNN +F 1 "1k" H 6775 7675 50 0000 C CNN +F 2 "" H 6775 7705 30 0000 C CNN +F 3 "" V 6775 7775 30 0000 C CNN + 1 6725 7725 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 680CA897 +P 8900 6950 +F 0 "Q3" H 8800 7000 50 0000 R CNN +F 1 "eSim_NPN" H 8850 7100 50 0000 R CNN +F 2 "" H 9100 7050 29 0000 C CNN +F 3 "" H 8900 6950 60 0000 C CNN + 1 8900 6950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 680CA898 +P 10375 6225 +F 0 "M8" H 10375 6075 50 0000 R CNN +F 1 "eSim_MOS_N" H 10475 6175 50 0000 R CNN +F 2 "" H 10675 5925 29 0000 C CNN +F 3 "" H 10475 6025 60 0000 C CNN + 1 10375 6225 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M9 +U 1 1 680CA899 +P 10425 5750 +F 0 "M9" H 10375 5800 50 0000 R CNN +F 1 "eSim_MOS_P" H 10475 5900 50 0000 R CNN +F 2 "" H 10675 5850 29 0000 C CNN +F 3 "" H 10475 5750 60 0000 C CNN + 1 10425 5750 + 1 0 0 1 +$EndComp +$Comp +L zener U3 +U 1 1 680CA89D +P 5600 5375 +F 0 "U3" H 5550 5275 60 0000 C CNN +F 1 "zener" H 5600 5475 60 0000 C CNN +F 2 "" H 5650 5375 60 0000 C CNN +F 3 "" H 5650 5375 60 0000 C CNN + 1 5600 5375 + -1 0 0 1 +$EndComp +$Comp +L zener U4 +U 1 1 680CA89E +P 6425 5250 +F 0 "U4" H 6375 5150 60 0000 C CNN +F 1 "zener" H 6425 5350 60 0000 C CNN +F 2 "" H 6475 5250 60 0000 C CNN +F 3 "" H 6475 5250 60 0000 C CNN + 1 6425 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 680CA8A0 +P 5750 5125 +F 0 "R4" H 5800 5255 50 0000 C CNN +F 1 "10" H 5800 5075 50 0000 C CNN +F 2 "" H 5800 5105 30 0000 C CNN +F 3 "" V 5800 5175 30 0000 C CNN + 1 5750 5125 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 680CA8A1 +P 3950 3600 +F 0 "R1" H 4000 3730 50 0000 C CNN +F 1 "10" H 4000 3550 50 0000 C CNN +F 2 "" H 4000 3580 30 0000 C CNN +F 3 "" V 4000 3650 30 0000 C CNN + 1 3950 3600 + 0 1 1 0 +$EndComp +Wire Wire Line + 4000 2175 12250 2175 +Wire Wire Line + 5225 4350 5225 4250 +Wire Wire Line + 5225 3950 5225 3875 +Wire Wire Line + 5225 2900 5225 3200 +Wire Wire Line + 5225 4650 5225 4825 +Wire Wire Line + 4625 4825 8300 4825 +Wire Wire Line + 4325 4825 4000 4825 +Wire Wire Line + 4000 4350 4000 5225 +Wire Wire Line + 4000 5225 4350 5225 +Connection ~ 4000 4825 +Wire Wire Line + 5125 2550 5125 2400 +Wire Wire Line + 5125 2400 5225 2400 +Wire Wire Line + 5225 2175 5225 2500 +Connection ~ 5225 2400 +Wire Wire Line + 6825 2375 6825 2550 +Wire Wire Line + 6825 2375 6725 2375 +Wire Wire Line + 6725 2175 6725 2500 +Connection ~ 6725 2375 +Wire Wire Line + 6825 3200 6825 3050 +Wire Wire Line + 6825 3050 6725 3050 +Wire Wire Line + 6725 2900 6725 3150 +Connection ~ 6725 3050 +Wire Wire Line + 5525 2700 6425 2700 +Wire Wire Line + 9100 2475 9100 2325 +Wire Wire Line + 9100 2325 9000 2325 +Wire Wire Line + 9000 2175 9000 2425 +Connection ~ 9000 2325 +Wire Wire Line + 9100 3250 9100 3100 +Wire Wire Line + 9100 3100 9000 3100 +Wire Wire Line + 9000 2825 9000 3200 +Connection ~ 9000 3100 +Wire Wire Line + 8300 4825 8300 3400 +Wire Wire Line + 8300 3400 8700 3400 +Connection ~ 5225 4825 +Wire Wire Line + 6425 3350 6050 3350 +Wire Wire Line + 6050 3350 6050 4825 +Connection ~ 6050 4825 +Wire Wire Line + 8700 2625 7975 2625 +Wire Wire Line + 7975 2625 7975 3000 +Wire Wire Line + 7975 3000 5225 3000 +Connection ~ 5225 3000 +Wire Wire Line + 4650 5225 4925 5225 +Wire Wire Line + 4925 5225 4925 8075 +Wire Wire Line + 5950 5600 5950 5900 +Wire Wire Line + 3150 6050 5550 6050 +Wire Wire Line + 5150 5375 5150 6050 +Connection ~ 5150 6050 +Wire Wire Line + 6675 5750 6675 5900 +Wire Wire Line + 6675 5750 6775 5750 +Connection ~ 6775 5750 +Wire Wire Line + 8125 5375 8125 6475 +Wire Wire Line + 8125 6050 7075 6050 +Connection ~ 8125 6050 +Wire Wire Line + 5850 6900 5850 7000 +Wire Wire Line + 6775 6900 6775 7000 +Wire Wire Line + 5850 7400 5850 7625 +Wire Wire Line + 6775 7400 6775 7625 +Wire Wire Line + 6150 7200 6475 7200 +Wire Wire Line + 5850 6250 5850 6600 +Wire Wire Line + 6775 6600 6775 6250 +Wire Wire Line + 4925 8075 9700 8075 +Wire Wire Line + 5850 7925 5850 8075 +Connection ~ 5850 8075 +Wire Wire Line + 6775 7925 6775 8075 +Connection ~ 6775 8075 +Wire Wire Line + 5850 7525 5425 7525 +Wire Wire Line + 5425 7525 5425 8450 +Connection ~ 5850 7525 +Wire Wire Line + 6775 7525 7225 7525 +Connection ~ 6775 7525 +Wire Wire Line + 6775 6950 8700 6950 +Connection ~ 6775 6950 +Wire Wire Line + 9000 8075 9000 7150 +Wire Wire Line + 9000 3600 9000 6750 +Wire Wire Line + 9700 8075 9700 7250 +Wire Wire Line + 9700 7250 10750 7250 +Connection ~ 9000 8075 +Wire Wire Line + 10575 5950 10575 6225 +Connection ~ 10575 6075 +Wire Wire Line + 10575 6625 10575 7250 +Wire Wire Line + 10675 6575 10675 6825 +Wire Wire Line + 10675 6825 10575 6825 +Connection ~ 10575 6825 +Wire Wire Line + 9950 6425 10275 6425 +Wire Wire Line + 9950 5750 9950 6425 +Wire Wire Line + 9950 5750 10275 5750 +Wire Wire Line + 9000 6075 9950 6075 +Connection ~ 9000 6075 +Connection ~ 9950 6075 +Wire Wire Line + 9475 6075 9475 8750 +Connection ~ 9475 6075 +Connection ~ 9000 2175 +Connection ~ 6725 2175 +Connection ~ 5225 2175 +Wire Wire Line + 10575 2175 10575 5550 +Wire Wire Line + 10675 5600 10675 5325 +Wire Wire Line + 10675 5325 10575 5325 +Connection ~ 10575 5325 +Connection ~ 10575 7250 +Connection ~ 10575 2175 +Wire Wire Line + 5300 5375 5150 5375 +Wire Wire Line + 5850 6550 6325 6550 +Wire Wire Line + 6325 6550 6325 7200 +Connection ~ 6325 7200 +Connection ~ 5850 6550 +Wire Wire Line + 5950 2700 5950 3000 +Connection ~ 5950 3000 +Connection ~ 5950 2700 +Wire Wire Line + 5850 5850 5850 5750 +Connection ~ 5950 5750 +Wire Wire Line + 5800 5375 5800 5325 +Wire Wire Line + 4000 3850 4000 3800 +Wire Wire Line + 4000 2175 4000 3500 +$Comp +L eSim_Diode D1 +U 1 1 680CA8A2 +P 5225 3350 +F 0 "D1" H 5225 3450 50 0000 C CNN +F 1 "eSim_Diode" H 5225 3250 50 0000 C CNN +F 2 "" H 5225 3350 60 0000 C CNN +F 3 "" H 5225 3350 60 0000 C CNN + 1 5225 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 5225 3575 5225 3500 +$Comp +L zener U5 +U 1 1 680CA8A3 +P 7825 5375 +F 0 "U5" H 7775 5275 60 0000 C CNN +F 1 "zener" H 7825 5475 60 0000 C CNN +F 2 "" H 7875 5375 60 0000 C CNN +F 3 "" H 7875 5375 60 0000 C CNN + 1 7825 5375 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 680CA8A4 +P 8350 6300 +F 0 "R9" H 8400 6430 50 0000 C CNN +F 1 "2k" H 8400 6250 50 0000 C CNN +F 2 "" H 8400 6280 30 0000 C CNN +F 3 "" V 8400 6350 30 0000 C CNN + 1 8350 6300 + 0 1 1 0 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 680CA8A5 +P 8400 6750 +F 0 "C1" H 8425 6850 50 0000 L CNN +F 1 "30p" H 8425 6650 50 0000 L CNN +F 2 "" H 8400 6750 50 0001 C CNN +F 3 "" H 8400 6750 50 0001 C CNN + 1 8400 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8400 6950 8400 6900 +Connection ~ 8400 6950 +Wire Wire Line + 8400 6600 8400 6500 +Wire Wire Line + 8400 5925 8400 6200 +Wire Wire Line + 8400 5925 9000 5925 +Connection ~ 9000 5925 +Wire Wire Line + 5850 5750 5950 5750 +Wire Wire Line + 5950 5600 6775 5600 +Wire Wire Line + 6775 5600 6775 5850 +Wire Wire Line + 6725 3550 6725 5600 +Connection ~ 6725 5600 +Wire Wire Line + 6425 5550 6425 5600 +Connection ~ 6425 5600 +Wire Wire Line + 5800 5025 7625 5025 +Wire Wire Line + 6425 5025 6425 5050 +Wire Wire Line + 7625 5025 7625 5375 +Connection ~ 6425 5025 +Wire Wire Line + 10575 6075 11325 6075 +Wire Wire Line + 8125 6475 3150 6475 +Wire Wire Line + 7225 7525 7225 8450 +$Comp +L PORT U1 +U 4 1 680CC45E +P 7225 8700 +F 0 "U1" H 7275 8800 30 0000 C CNN +F 1 "PORT" H 7225 8700 30 0000 C CNN +F 2 "" H 7225 8700 60 0000 C CNN +F 3 "" H 7225 8700 60 0000 C CNN + 4 7225 8700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 680CC557 +P 5425 8700 +F 0 "U1" H 5475 8800 30 0000 C CNN +F 1 "PORT" H 5425 8700 30 0000 C CNN +F 2 "" H 5425 8700 60 0000 C CNN +F 3 "" H 5425 8700 60 0000 C CNN + 3 5425 8700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 680CC740 +P 2900 6475 +F 0 "U1" H 2950 6575 30 0000 C CNN +F 1 "PORT" H 2900 6475 30 0000 C CNN +F 2 "" H 2900 6475 60 0000 C CNN +F 3 "" H 2900 6475 60 0000 C CNN + 2 2900 6475 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 680CC79D +P 2900 6050 +F 0 "U1" H 2950 6150 30 0000 C CNN +F 1 "PORT" H 2900 6050 30 0000 C CNN +F 2 "" H 2900 6050 60 0000 C CNN +F 3 "" H 2900 6050 60 0000 C CNN + 1 2900 6050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 680CC952 +P 9475 9000 +F 0 "U1" H 9525 9100 30 0000 C CNN +F 1 "PORT" H 9475 9000 30 0000 C CNN +F 2 "" H 9475 9000 60 0000 C CNN +F 3 "" H 9475 9000 60 0000 C CNN + 5 9475 9000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 680CCB00 +P 11000 7250 +F 0 "U1" H 11050 7350 30 0000 C CNN +F 1 "PORT" H 11000 7250 30 0000 C CNN +F 2 "" H 11000 7250 60 0000 C CNN +F 3 "" H 11000 7250 60 0000 C CNN + 6 11000 7250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 680CCC35 +P 11575 6075 +F 0 "U1" H 11625 6175 30 0000 C CNN +F 1 "PORT" H 11575 6075 30 0000 C CNN +F 2 "" H 11575 6075 60 0000 C CNN +F 3 "" H 11575 6075 60 0000 C CNN + 7 11575 6075 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 680CCE3F +P 12500 2175 +F 0 "U1" H 12550 2275 30 0000 C CNN +F 1 "PORT" H 12500 2175 30 0000 C CNN +F 2 "" H 12500 2175 60 0000 C CNN +F 3 "" H 12500 2175 60 0000 C CNN + 8 12500 2175 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A.sub b/library/SubcircuitLibrary/CA3160A/CA3160A.sub new file mode 100644 index 00000000..023f73a7 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A.sub @@ -0,0 +1,52 @@ +* Subcircuit CA3160A +.subckt CA3160A net-_m2-pad2_ net-_m5-pad2_ net-_q1-pad3_ net-_q2-pad3_ net-_m7-pad1_ net-_m8-pad3_ net-_m8-pad1_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\ca3160a\ca3160a.cir +.include NPN.lib +.include PMOS-5um.lib +.include NMOS-5um.lib +.include schottky.lib +d2 net-_d1-pad2_ net-_d2-pad2_ 1N5819 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N5819 +d4 net-_d3-pad2_ net-_d4-pad2_ 1N5819 +r2 net-_r2-pad1_ net-_d4-pad2_ 40k +* u2 net-_r2-pad1_ net-_r1-pad2_ zener +r3 net-_r2-pad1_ net-_m8-pad3_ 5k +m1 net-_d1-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m4 net-_m2-pad3_ net-_d4-pad2_ net-_m3-pad1_ net-_m3-pad1_ mos_p W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_d1-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_d4-pad2_ net-_m6-pad1_ net-_m6-pad1_ mos_p W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_p W=100u L=100u M=1 +r5 net-_m2-pad1_ net-_q1-pad1_ 1k +r7 net-_m5-pad1_ net-_c1-pad2_ 1k +q1 net-_q1-pad1_ net-_m2-pad1_ net-_q1-pad3_ Q2N2222 +q2 net-_c1-pad2_ net-_m2-pad1_ net-_q2-pad3_ Q2N2222 +r6 net-_q1-pad3_ net-_m8-pad3_ 1k +r8 net-_q2-pad3_ net-_m8-pad3_ 1k +q3 net-_m7-pad1_ net-_c1-pad2_ net-_m8-pad3_ Q2N2222 +m8 net-_m8-pad1_ net-_m7-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_n W=100u L=100u M=1 +m9 net-_m8-pad1_ net-_m7-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_p W=100u L=100u M=1 +* u3 net-_r4-pad2_ net-_m2-pad2_ zener +* u4 net-_r4-pad1_ net-_m2-pad3_ zener +r4 net-_r4-pad1_ net-_r4-pad2_ 10 +r1 net-_m1-pad3_ net-_r1-pad2_ 10 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N5819 +* u5 net-_r4-pad1_ net-_m5-pad2_ zener +r9 net-_m7-pad1_ net-_c1-pad1_ 2k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +a1 net-_r2-pad1_ net-_r1-pad2_ u2 +a2 net-_r4-pad2_ net-_m2-pad2_ u3 +a3 net-_r4-pad1_ net-_m2-pad3_ u4 +a4 net-_r4-pad1_ net-_m5-pad2_ u5 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=8.3 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=20.0e-3 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends CA3160A
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3160A/CA3160A_Previous_Values.xml b/library/SubcircuitLibrary/CA3160A/CA3160A_Previous_Values.xml new file mode 100644 index 00000000..708d33a1 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/CA3160A_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">8.3</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">20.0e-3</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">20.0e-3</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">20.0e-3</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u4><u5 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)">5.6</field16><field17 name="Enter Breakdown Current (default=2.0e-2)">20.0e-3</field17><field18 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field18><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u5></model><devicemodel><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib</field></d3><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib</field></d4><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m4><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m6><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m7><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m2><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m5><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m8><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m9><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3160A/NMOS-5um.lib b/library/SubcircuitLibrary/CA3160A/NMOS-5um.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CA3160A/NPN.lib b/library/SubcircuitLibrary/CA3160A/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/CA3160A/PMOS-5um.lib b/library/SubcircuitLibrary/CA3160A/PMOS-5um.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CA3160A/analysis b/library/SubcircuitLibrary/CA3160A/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CA3160A/schottky.lib b/library/SubcircuitLibrary/CA3160A/schottky.lib new file mode 100644 index 00000000..9579f735 --- /dev/null +++ b/library/SubcircuitLibrary/CA3160A/schottky.lib @@ -0,0 +1 @@ +.model 1N5819 D(IS=390n RS=0.115 BV=40.0 IBV=1.00m CJO=203p M=0.333 N=1.70 TT=4.32u) diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib b/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib new file mode 100644 index 00000000..ae0c7685 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B-cache.lib @@ -0,0 +1,168 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.cir b/library/SubcircuitLibrary/CD4066B/CD4066B.cir new file mode 100644 index 00000000..9e2c34d0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B.cir @@ -0,0 +1,22 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4066B\CD4066B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/09/25 14:21:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ d_inverter +U7 Net-_U4-Pad2_ Net-_U6-Pad1_ d_inverter +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ ? eSim_MOS_P +M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ ? eSim_MOS_N +M2 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N +M4 Net-_M4-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ ? eSim_MOS_P +M5 Net-_M4-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad3_ eSim_MOS_N +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ adc_bridge_1 +U6 Net-_U6-Pad1_ Net-_M1-Pad2_ dac_bridge_1 +U5 Net-_U4-Pad2_ Net-_M3-Pad2_ dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M4-Pad1_ GND PORT + +.end diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out b/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out new file mode 100644 index 00000000..c304a2c8 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B.cir.out @@ -0,0 +1,43 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4066b\cd4066b.cir + +.include NMOS-0.5um.lib +.include PMOS-0.5um.lib +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u6-pad1_ d_inverter +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ ? mos_p W=100u L=5u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ ? mos_n W=100u L=5u M=1 +m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_n W=100u L=5u M=1 +m4 net-_m4-pad1_ net-_m1-pad2_ net-_m1-pad1_ ? mos_p W=100u L=5u M=1 +m5 net-_m4-pad1_ net-_m3-pad2_ net-_m1-pad1_ net-_m1-pad3_ mos_n W=100u L=5u M=1 +* u2 net-_u1-pad1_ net-_u2-pad2_ adc_bridge_1 +* u6 net-_u6-pad1_ net-_m1-pad2_ dac_bridge_1 +* u5 net-_u4-pad2_ net-_m3-pad2_ dac_bridge_1 +* u1 net-_u1-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m4-pad1_ gnd port +a1 net-_u2-pad2_ net-_u3-pad2_ u3 +a2 net-_u3-pad2_ net-_u4-pad2_ u4 +a3 net-_u4-pad2_ net-_u6-pad1_ u7 +a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] u2 +a5 [net-_u6-pad1_ ] [net-_m1-pad2_ ] u6 +a6 [net-_u4-pad2_ ] [net-_m3-pad2_ ] u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.pro b/library/SubcircuitLibrary/CD4066B/CD4066B.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.sch b/library/SubcircuitLibrary/CD4066B/CD4066B.sch new file mode 100644 index 00000000..d91e6739 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B.sch @@ -0,0 +1,367 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4066B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 681D78A2 +P 3600 4450 +F 0 "U3" H 3600 4350 60 0000 C CNN +F 1 "d_inverter" H 3600 4600 60 0000 C CNN +F 2 "" H 3650 4400 60 0000 C CNN +F 3 "" H 3650 4400 60 0000 C CNN + 1 3600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 681D78A3 +P 4400 4450 +F 0 "U4" H 4400 4350 60 0000 C CNN +F 1 "d_inverter" H 4400 4600 60 0000 C CNN +F 2 "" H 4450 4400 60 0000 C CNN +F 3 "" H 4450 4400 60 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 681D78A4 +P 5325 4450 +F 0 "U7" H 5325 4350 60 0000 C CNN +F 1 "d_inverter" H 5325 4600 60 0000 C CNN +F 2 "" H 5375 4400 60 0000 C CNN +F 3 "" H 5375 4400 60 0000 C CNN + 1 5325 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 4450 4100 4450 +Wire Wire Line + 4700 4450 5025 4450 +$Comp +L eSim_MOS_P M1 +U 1 1 681D78A5 +P 6200 3800 +F 0 "M1" H 6150 3850 50 0000 R CNN +F 1 "eSim_MOS_P" H 6250 3950 50 0000 R CNN +F 2 "" H 6450 3900 29 0000 C CNN +F 3 "" H 6250 3800 60 0000 C CNN + 1 6200 3800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 681D78A6 +P 7375 3600 +F 0 "M3" H 7375 3450 50 0000 R CNN +F 1 "eSim_MOS_N" H 7475 3550 50 0000 R CNN +F 2 "" H 7675 3300 29 0000 C CNN +F 3 "" H 7475 3400 60 0000 C CNN + 1 7375 3600 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6350 4000 6350 4150 +Wire Wire Line + 7175 4150 7175 4000 +Wire Wire Line + 6350 4150 7175 4150 +$Comp +L eSim_MOS_N M2 +U 1 1 681D78A7 +P 6525 4525 +F 0 "M2" H 6525 4375 50 0000 R CNN +F 1 "eSim_MOS_N" H 6625 4475 50 0000 R CNN +F 2 "" H 6825 4225 29 0000 C CNN +F 3 "" H 6625 4325 60 0000 C CNN + 1 6525 4525 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6725 4925 6725 5200 +Wire Wire Line + 6725 4975 6825 4975 +Wire Wire Line + 6825 4975 6825 4875 +Connection ~ 6725 4975 +Wire Wire Line + 6725 4150 6725 4525 +Connection ~ 6725 4150 +Wire Wire Line + 5725 4725 6425 4725 +Wire Wire Line + 5725 2875 5725 4725 +Wire Wire Line + 6050 3800 5725 3800 +Connection ~ 5725 3800 +Wire Wire Line + 6350 3600 6350 3450 +Wire Wire Line + 6350 3450 7175 3450 +Wire Wire Line + 7175 3450 7175 3600 +$Comp +L eSim_MOS_P M4 +U 1 1 681D78A8 +P 8425 3475 +F 0 "M4" H 8375 3525 50 0000 R CNN +F 1 "eSim_MOS_P" H 8475 3625 50 0000 R CNN +F 2 "" H 8675 3575 29 0000 C CNN +F 3 "" H 8475 3475 60 0000 C CNN + 1 8425 3475 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 681D78A9 +P 8625 4325 +F 0 "M5" H 8625 4175 50 0000 R CNN +F 1 "eSim_MOS_N" H 8725 4275 50 0000 R CNN +F 2 "" H 8925 4025 29 0000 C CNN +F 3 "" H 8725 4125 60 0000 C CNN + 1 8625 4325 + 0 1 -1 0 +$EndComp +Wire Wire Line + 8100 3625 8225 3625 +Wire Wire Line + 8100 3625 8100 4125 +Wire Wire Line + 8100 4125 8225 4125 +Wire Wire Line + 7675 4025 8275 4025 +Wire Wire Line + 8175 3725 8275 3725 +Wire Wire Line + 8625 3625 8700 3625 +Wire Wire Line + 8700 3625 8700 4125 +Wire Wire Line + 8700 4125 8625 4125 +Wire Wire Line + 7675 4025 7675 4400 +Wire Wire Line + 7675 4400 6725 4400 +Connection ~ 6725 4400 +Wire Wire Line + 5725 2875 8425 2875 +Wire Wire Line + 8425 2875 8425 3325 +Wire Wire Line + 8425 5700 8425 4425 +Connection ~ 4850 4450 +Wire Wire Line + 4850 5700 8425 5700 +Wire Wire Line + 7475 3800 7475 5700 +Connection ~ 7475 5700 +Connection ~ 8700 3925 +Connection ~ 5725 4450 +Wire Wire Line + 6775 2350 6775 3450 +Connection ~ 6775 3450 +Wire Wire Line + 6775 3075 7850 3075 +Wire Wire Line + 7850 3075 7850 3850 +Wire Wire Line + 7850 3850 8100 3850 +Connection ~ 8100 3850 +Connection ~ 6775 3075 +Wire Wire Line + 3300 4450 3150 4450 +Wire Wire Line + 5675 3950 5675 4450 +Wire Wire Line + 5675 4450 5725 4450 +Wire Wire Line + 5375 3950 5675 3950 +Wire Wire Line + 3150 4450 3150 4475 +$Comp +L adc_bridge_1 U2 +U 1 1 681D78B2 +P 2600 4525 +F 0 "U2" H 2600 4525 60 0000 C CNN +F 1 "adc_bridge_1" H 2600 4675 60 0000 C CNN +F 2 "" H 2600 4525 60 0000 C CNN +F 3 "" H 2600 4525 60 0000 C CNN + 1 2600 4525 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5375 3875 5375 3950 +Wire Wire Line + 5625 4450 5625 4100 +Wire Wire Line + 5625 4100 4225 4100 +Wire Wire Line + 4225 4100 4225 3875 +Wire Wire Line + 4850 4450 4850 4500 +Wire Wire Line + 4850 5700 4850 5650 +$Comp +L dac_bridge_1 U6 +U 1 1 681D78B5 +P 4825 3925 +F 0 "U6" H 4825 3925 60 0000 C CNN +F 1 "dac_bridge_1" H 4825 4075 60 0000 C CNN +F 2 "" H 4825 3925 60 0000 C CNN +F 3 "" H 4825 3925 60 0000 C CNN + 1 4825 3925 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U5 +U 1 1 681D78B6 +P 4800 5100 +F 0 "U5" H 4800 5100 60 0000 C CNN +F 1 "dac_bridge_1" H 4800 5250 60 0000 C CNN +F 2 "" H 4800 5100 60 0000 C CNN +F 3 "" H 4800 5100 60 0000 C CNN + 1 4800 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 8700 3925 9675 3925 +Wire Wire Line + 6775 2350 5900 2350 +Wire Wire Line + 2000 4475 1775 4475 +$Comp +L PORT U1 +U 2 1 681D7CCF +P 5650 2350 +F 0 "U1" H 5700 2450 30 0000 C CNN +F 1 "PORT" H 5650 2350 30 0000 C CNN +F 2 "" H 5650 2350 60 0000 C CNN +F 3 "" H 5650 2350 60 0000 C CNN + 2 5650 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 681D7E66 +P 9925 3925 +F 0 "U1" H 9975 4025 30 0000 C CNN +F 1 "PORT" H 9925 3925 30 0000 C CNN +F 2 "" H 9925 3925 60 0000 C CNN +F 3 "" H 9925 3925 60 0000 C CNN + 4 9925 3925 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 681D7F45 +P 1525 4475 +F 0 "U1" H 1575 4575 30 0000 C CNN +F 1 "PORT" H 1525 4475 30 0000 C CNN +F 2 "" H 1525 4475 60 0000 C CNN +F 3 "" H 1525 4475 60 0000 C CNN + 1 1525 4475 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 681D808E +P 6725 5450 +F 0 "U1" H 6775 5550 30 0000 C CNN +F 1 "PORT" H 6725 5450 30 0000 C CNN +F 2 "" H 6725 5450 60 0000 C CNN +F 3 "" H 6725 5450 60 0000 C CNN + 3 6725 5450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 681DC295 +P 8550 1900 +F 0 "U1" H 8600 2000 30 0000 C CNN +F 1 "PORT" H 8550 1900 30 0000 C CNN +F 2 "" H 8550 1900 60 0000 C CNN +F 3 "" H 8550 1900 60 0000 C CNN + 5 8550 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 681DC2F8 +P 9000 1900 +F 0 "#PWR01" H 9000 1650 50 0001 C CNN +F 1 "eSim_GND" H 9000 1750 50 0000 C CNN +F 2 "" H 9000 1900 50 0001 C CNN +F 3 "" H 9000 1900 50 0001 C CNN + 1 9000 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 1900 8800 1900 +$Comp +L PWR_FLAG #FLG02 +U 1 1 681DC50D +P 8875 1850 +F 0 "#FLG02" H 8875 1925 50 0001 C CNN +F 1 "PWR_FLAG" H 8875 2000 50 0000 C CNN +F 2 "" H 8875 1850 50 0001 C CNN +F 3 "" H 8875 1850 50 0001 C CNN + 1 8875 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8875 1850 8875 1900 +Connection ~ 8875 1900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B.sub b/library/SubcircuitLibrary/CD4066B/CD4066B.sub new file mode 100644 index 00000000..cddaccc7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B.sub @@ -0,0 +1,37 @@ +* Subcircuit CD4066B +.subckt CD4066B net-_u1-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m4-pad1_ gnd +* c:\fossee\esim\library\subcircuitlibrary\cd4066b\cd4066b.cir +.include NMOS-0.5um.lib +.include PMOS-0.5um.lib +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u6-pad1_ d_inverter +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ ? mos_p W=100u L=5u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ ? mos_n W=100u L=5u M=1 +m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_n W=100u L=5u M=1 +m4 net-_m4-pad1_ net-_m1-pad2_ net-_m1-pad1_ ? mos_p W=100u L=5u M=1 +m5 net-_m4-pad1_ net-_m3-pad2_ net-_m1-pad1_ net-_m1-pad3_ mos_n W=100u L=5u M=1 +* u2 net-_u1-pad1_ net-_u2-pad2_ adc_bridge_1 +* u6 net-_u6-pad1_ net-_m1-pad2_ dac_bridge_1 +* u5 net-_u4-pad2_ net-_m3-pad2_ dac_bridge_1 +a1 net-_u2-pad2_ net-_u3-pad2_ u3 +a2 net-_u3-pad2_ net-_u4-pad2_ u4 +a3 net-_u4-pad2_ net-_u6-pad1_ u7 +a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] u2 +a5 [net-_u6-pad1_ ] [net-_m1-pad2_ ] u6 +a6 [net-_u4-pad2_ ] [net-_m3-pad2_ ] u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4066B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml b/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml new file mode 100644 index 00000000..c471f4de --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/CD4066B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u7><u2 name="type">adc_bridge<field10 name="Enter value for in_low (default=1.0)">0</field10><field11 name="Enter value for in_high (default=2.0)">5</field11><field12 name="Enter Rise Delay (default=1.0e-9)" /><field13 name="Enter Fall Delay (default=1.0e-9)" /></u2><u6 name="type">dac_bridge<field14 name="Enter value for out_low (default=0.0)"> 0</field14><field15 name="Enter value for out_high (default=5.0)"> 5</field15><field16 name="Enter value for out_undef (default=0.5)" /><field17 name="Enter value for input load (default=1.0e-12)" /><field18 name="Enter the Rise Time (default=1.0e-9)" /><field19 name="Enter the Fall Time (default=1.0e-9)" /></u6><u5 name="type">dac_bridge<field20 name="Enter value for out_low (default=0.0)"> 0</field20><field21 name="Enter value for out_high (default=5.0)"> 5</field21><field22 name="Enter value for out_undef (default=0.5)" /><field23 name="Enter value for input load (default=1.0e-12)" /><field24 name="Enter the Rise Time (default=1.0e-9)" /><field25 name="Enter the Fall Time (default=1.0e-9)" /></u5></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m3><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m2><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m4><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field>100u</field><field>5u</field><field>1</field></m5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib b/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib b/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4066B/analysis b/library/SubcircuitLibrary/CD4066B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4066B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13600/D.lib b/library/SubcircuitLibrary/LM13600/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM13600/LM13600-cache.lib b/library/SubcircuitLibrary/LM13600/LM13600-cache.lib new file mode 100644 index 00000000..a55473b8 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM13600/LM13600.cir b/library/SubcircuitLibrary/LM13600/LM13600.cir new file mode 100644 index 00000000..4b22c535 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600.cir @@ -0,0 +1,30 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM13600\LM13600.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/26/25 18:13:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_NPN +Q7 Net-_Q12-Pad3_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_NPN +Q4 Net-_Q1-Pad3_ Net-_Q2-Pad1_ Net-_D2-Pad1_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_Q10-Pad2_ Net-_D4-Pad2_ Net-_Q1-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D4 Net-_D1-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q3 Net-_Q1-Pad1_ Net-_D3-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q5 Net-_Q11-Pad2_ Net-_Q1-Pad1_ Net-_D3-Pad2_ eSim_PNP +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q8 Net-_Q10-Pad2_ Net-_D5-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D5-Pad2_ eSim_PNP +D5 Net-_D3-Pad1_ Net-_D5-Pad2_ eSim_Diode +Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_D6-Pad1_ eSim_NPN +Q9 Net-_Q11-Pad2_ Net-_D6-Pad1_ Net-_D2-Pad2_ eSim_NPN +D6 Net-_D6-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q12 Net-_D3-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_D3-Pad1_ Net-_Q12-Pad3_ Net-_Q13-Pad3_ eSim_NPN +U1 Net-_D1-Pad1_ Net-_D1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad2_ Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_D2-Pad2_ Net-_D3-Pad1_ Net-_D4-Pad2_ Net-_D4-Pad2_ Net-_Q12-Pad2_ Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad2_ Net-_Q13-Pad3_ Net-_Q13-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM13600/LM13600.cir.out b/library/SubcircuitLibrary/LM13600/LM13600.cir.out new file mode 100644 index 00000000..5ca38beb --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600.cir.out @@ -0,0 +1,34 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm13600\lm13600.cir + +.include NPN.lib +.include D.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222 +q7 net-_q12-pad3_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222 +q4 net-_q1-pad3_ net-_q2-pad1_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q10-pad2_ net-_d4-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148 +q3 net-_q1-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q5 net-_q11-pad2_ net-_q1-pad1_ net-_d3-pad2_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q8 net-_q10-pad2_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d2-pad2_ Q2N2222 +d6 net-_d6-pad1_ net-_d2-pad2_ 1N4148 +q12 net-_d3-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q13 net-_d3-pad1_ net-_q12-pad3_ net-_q13-pad3_ Q2N2222 +* u1 net-_d1-pad1_ net-_d1-pad1_ net-_d1-pad2_ net-_d1-pad2_ net-_q2-pad1_ net-_q2-pad1_ net-_d2-pad2_ net-_d3-pad1_ net-_d4-pad2_ net-_d4-pad2_ net-_q12-pad2_ net-_q10-pad1_ net-_q10-pad1_ net-_q12-pad2_ net-_q13-pad3_ net-_q13-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM13600/LM13600.pro b/library/SubcircuitLibrary/LM13600/LM13600.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM13600/LM13600.sch b/library/SubcircuitLibrary/LM13600/LM13600.sch new file mode 100644 index 00000000..c2af105d --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600.sch @@ -0,0 +1,619 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM13600-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 680CD3CA +P 3850 5225 +F 0 "Q2" H 3750 5275 50 0000 R CNN +F 1 "eSim_NPN" H 3800 5375 50 0000 R CNN +F 2 "" H 4050 5325 29 0000 C CNN +F 3 "" H 3850 5225 60 0000 C CNN + 1 3850 5225 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 680CD3CB +P 4825 5225 +F 0 "Q7" H 4725 5275 50 0000 R CNN +F 1 "eSim_NPN" H 4775 5375 50 0000 R CNN +F 2 "" H 5025 5325 29 0000 C CNN +F 3 "" H 4825 5225 60 0000 C CNN + 1 4825 5225 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 680CD3CC +P 4275 4750 +F 0 "Q4" H 4175 4800 50 0000 R CNN +F 1 "eSim_NPN" H 4225 4900 50 0000 R CNN +F 2 "" H 4475 4850 29 0000 C CNN +F 3 "" H 4275 4750 60 0000 C CNN + 1 4275 4750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 680CD3CD +P 4275 5600 +F 0 "D2" H 4275 5700 50 0000 C CNN +F 1 "eSim_Diode" H 4275 5500 50 0000 C CNN +F 2 "" H 4275 5600 60 0000 C CNN +F 3 "" H 4275 5600 60 0000 C CNN + 1 4275 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 680CD3CE +P 3850 3775 +F 0 "Q1" H 3750 3825 50 0000 R CNN +F 1 "eSim_NPN" H 3800 3925 50 0000 R CNN +F 2 "" H 4050 3875 29 0000 C CNN +F 3 "" H 3850 3775 60 0000 C CNN + 1 3850 3775 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 680CD3CF +P 4775 3775 +F 0 "Q6" H 4675 3825 50 0000 R CNN +F 1 "eSim_NPN" H 4725 3925 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+Wire Wire Line + 5825 2625 5400 2625 +Connection ~ 5400 2625 +Wire Wire Line + 6125 2050 6125 2425 +Wire Wire Line + 5700 2300 6125 2300 +Connection ~ 6125 2300 +Wire Wire Line + 4675 3575 4675 2975 +Wire Wire Line + 4675 2975 5400 2975 +Wire Wire Line + 3950 2150 3950 1600 +Wire Wire Line + 4675 1800 4675 1600 +Wire Wire Line + 3125 1600 7750 1600 +Wire Wire Line + 5400 1600 5400 2100 +Wire Wire Line + 6125 1600 6125 1750 +$Comp +L eSim_NPN Q11 +U 1 1 680CD3D8 +P 6025 4250 +F 0 "Q11" H 5925 4300 50 0000 R CNN +F 1 "eSim_NPN" H 5975 4400 50 0000 R CNN +F 2 "" H 6225 4350 29 0000 C CNN +F 3 "" H 6025 4250 60 0000 C CNN + 1 6025 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 680CD3D9 +P 5500 4750 +F 0 "Q9" H 5400 4800 50 0000 R CNN +F 1 "eSim_NPN" H 5450 4900 50 0000 R CNN +F 2 "" H 5700 4850 29 0000 C CNN +F 3 "" H 5500 4750 60 0000 C CNN + 1 5500 4750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 680CD3DA +P 6125 5300 +F 0 "D6" H 6125 5400 50 0000 C CNN +F 1 "eSim_Diode" H 6125 5200 50 0000 C CNN +F 2 "" H 6125 5300 60 0000 C CNN +F 3 "" H 6125 5300 60 0000 C CNN + 1 6125 5300 + 0 1 1 0 +$EndComp +Wire Wire Line + 6125 2825 6125 4050 +Wire Wire Line + 4675 2875 5275 2875 +Wire Wire Line + 5275 2875 5275 3300 +Wire Wire Line + 5275 3300 5400 3300 +Wire Wire Line + 5400 3300 5400 4550 +Wire Wire Line + 6125 4450 6125 5150 +Wire Wire Line + 5700 4750 6125 4750 +Connection ~ 6125 4750 +$Comp +L eSim_NPN Q12 +U 1 1 680CD3DB +P 7100 2500 +F 0 "Q12" H 7000 2550 50 0000 R CNN +F 1 "eSim_NPN" H 7050 2650 50 0000 R CNN +F 2 "" H 7300 2600 29 0000 C CNN +F 3 "" H 7100 2500 60 0000 C CNN + 1 7100 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 680CD3DC +P 7650 2950 +F 0 "Q13" H 7550 3000 50 0000 R CNN +F 1 "eSim_NPN" H 7600 3100 50 0000 R CNN +F 2 "" H 7850 3050 29 0000 C CNN +F 3 "" H 7650 2950 60 0000 C CNN + 1 7650 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7200 2700 7200 2950 +Wire Wire Line + 7200 2950 7450 2950 +Wire Wire Line + 4925 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Line + 2925 3625 3050 3625 +Wire Wire Line + 3050 3625 3050 3925 +Wire Wire Line + 3050 3925 2925 3925 +Connection ~ 3050 3775 +Wire Wire Line + 2925 4575 3150 4575 +Wire Wire Line + 3150 4575 3150 4925 +Wire Wire Line + 3150 4925 2925 4925 +Connection ~ 3150 4750 +Wire Wire Line + 6400 2925 6400 2750 +Wire Wire Line + 6400 2750 6750 2750 +Wire Wire Line + 6750 2750 6750 2925 +Connection ~ 6575 2750 +$Comp +L PORT U1 +U 1 1 680CDA55 +P 2675 2925 +F 0 "U1" H 2725 3025 30 0000 C CNN +F 1 "PORT" H 2675 2925 30 0000 C CNN +F 2 "" H 2675 2925 60 0000 C CNN +F 3 "" H 2675 2925 60 0000 C CNN + 1 2675 2925 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 680CDAF2 +P 2675 3200 +F 0 "U1" H 2725 3300 30 0000 C CNN +F 1 "PORT" H 2675 3200 30 0000 C CNN +F 2 "" H 2675 3200 60 0000 C CNN +F 3 "" H 2675 3200 60 0000 C CNN + 2 2675 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 680CDBB9 +P 2675 3625 +F 0 "U1" H 2725 3725 30 0000 C CNN +F 1 "PORT" H 2675 3625 30 0000 C CNN +F 2 "" H 2675 3625 60 0000 C CNN +F 3 "" H 2675 3625 60 0000 C CNN + 3 2675 3625 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 680CDBFE +P 2675 3925 +F 0 "U1" H 2725 4025 30 0000 C CNN +F 1 "PORT" H 2675 3925 30 0000 C CNN +F 2 "" H 2675 3925 60 0000 C CNN +F 3 "" H 2675 3925 60 0000 C CNN + 4 2675 3925 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 680CDCD5 +P 2675 4575 +F 0 "U1" H 2725 4675 30 0000 C CNN +F 1 "PORT" H 2675 4575 30 0000 C CNN +F 2 "" H 2675 4575 60 0000 C CNN +F 3 "" H 2675 4575 60 0000 C CNN + 5 2675 4575 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 680CDD22 +P 2675 4925 +F 0 "U1" H 2725 5025 30 0000 C CNN +F 1 "PORT" H 2675 4925 30 0000 C CNN +F 2 "" H 2675 4925 60 0000 C CNN +F 3 "" H 2675 4925 60 0000 C CNN + 6 2675 4925 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 680CDE3D +P 2675 5950 +F 0 "U1" H 2725 6050 30 0000 C CNN +F 1 "PORT" H 2675 5950 30 0000 C CNN +F 2 "" H 2675 5950 60 0000 C CNN +F 3 "" H 2675 5950 60 0000 C CNN + 7 2675 5950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 680CE171 +P 6400 3175 +F 0 "U1" H 6450 3275 30 0000 C CNN +F 1 "PORT" H 6400 3175 30 0000 C CNN +F 2 "" H 6400 3175 60 0000 C CNN +F 3 "" H 6400 3175 60 0000 C CNN + 11 6400 3175 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 680CE204 +P 6750 3175 +F 0 "U1" H 6800 3275 30 0000 C CNN +F 1 "PORT" H 6750 3175 30 0000 C CNN +F 2 "" H 6750 3175 60 0000 C CNN +F 3 "" H 6750 3175 60 0000 C CNN + 14 6750 3175 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 680CE2B9 +P 5825 3575 +F 0 "U1" H 5875 3675 30 0000 C CNN +F 1 "PORT" H 5825 3575 30 0000 C CNN +F 2 "" H 5825 3575 60 0000 C CNN +F 3 "" H 5825 3575 60 0000 C CNN + 9 5825 3575 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 680CE31E +P 8625 3200 +F 0 "U1" H 8675 3300 30 0000 C CNN +F 1 "PORT" H 8625 3200 30 0000 C CNN +F 2 "" H 8625 3200 60 0000 C CNN +F 3 "" H 8625 3200 60 0000 C CNN + 15 8625 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 680CE3F7 +P 2875 1600 +F 0 "U1" H 2925 1700 30 0000 C CNN +F 1 "PORT" H 2875 1600 30 0000 C CNN +F 2 "" H 2875 1600 60 0000 C CNN +F 3 "" H 2875 1600 60 0000 C CNN + 8 2875 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 680CE6FB +P 5850 3925 +F 0 "U1" H 5900 4025 30 0000 C CNN +F 1 "PORT" H 5850 3925 30 0000 C CNN +F 2 "" H 5850 3925 60 0000 C CNN +F 3 "" H 5850 3925 60 0000 C CNN + 10 5850 3925 + -1 0 0 1 +$EndComp +Wire Wire Line + 5575 3575 5575 3925 +Wire Wire Line + 5575 3925 5600 3925 +Connection ~ 5575 3775 +Wire Wire Line + 6125 3625 6400 3625 +Connection ~ 6125 3625 +$Comp +L PORT U1 +U 12 1 680CEB4A +P 6650 3450 +F 0 "U1" H 6700 3550 30 0000 C CNN +F 1 "PORT" H 6650 3450 30 0000 C CNN +F 2 "" H 6650 3450 60 0000 C CNN +F 3 "" H 6650 3450 60 0000 C CNN + 12 6650 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 680CEBB3 +P 6650 3800 +F 0 "U1" H 6700 3900 30 0000 C CNN +F 1 "PORT" H 6650 3800 30 0000 C CNN +F 2 "" H 6650 3800 60 0000 C CNN +F 3 "" H 6650 3800 60 0000 C CNN + 13 6650 3800 + -1 0 0 1 +$EndComp +Wire Wire Line + 6400 3450 6400 3800 +Connection ~ 6400 3625 +$Comp +L PORT U1 +U 16 1 680CEFCB +P 8625 3600 +F 0 "U1" H 8675 3700 30 0000 C CNN +F 1 "PORT" H 8625 3600 30 0000 C CNN +F 2 "" H 8625 3600 60 0000 C CNN +F 3 "" H 8625 3600 60 0000 C CNN + 16 8625 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 8375 3200 8375 3600 +Connection ~ 8375 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM13600/LM13600.sub b/library/SubcircuitLibrary/LM13600/LM13600.sub new file mode 100644 index 00000000..b0502057 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600.sub @@ -0,0 +1,28 @@ +* Subcircuit LM13600 +.subckt LM13600 net-_d1-pad1_ net-_d1-pad1_ net-_d1-pad2_ net-_d1-pad2_ net-_q2-pad1_ net-_q2-pad1_ net-_d2-pad2_ net-_d3-pad1_ net-_d4-pad2_ net-_d4-pad2_ net-_q12-pad2_ net-_q10-pad1_ net-_q10-pad1_ net-_q12-pad2_ net-_q13-pad3_ net-_q13-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\lm13600\lm13600.cir +.include NPN.lib +.include D.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222 +q7 net-_q12-pad3_ net-_d2-pad1_ net-_d2-pad2_ Q2N2222 +q4 net-_q1-pad3_ net-_q2-pad1_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q10-pad2_ net-_d4-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148 +q3 net-_q1-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q5 net-_q11-pad2_ net-_q1-pad1_ net-_d3-pad2_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q8 net-_q10-pad2_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d2-pad2_ Q2N2222 +d6 net-_d6-pad1_ net-_d2-pad2_ 1N4148 +q12 net-_d3-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q13 net-_d3-pad1_ net-_q12-pad3_ net-_q13-pad3_ Q2N2222 +* Control Statements + +.ends LM13600
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13600/LM13600_Previous_Values.xml b/library/SubcircuitLibrary/LM13600/LM13600_Previous_Values.xml new file mode 100644 index 00000000..892063e9 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/LM13600_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13600/NPN.lib b/library/SubcircuitLibrary/LM13600/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM13600/PNP.lib b/library/SubcircuitLibrary/LM13600/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM13600/analysis b/library/SubcircuitLibrary/LM13600/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM13600/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386M/14_lm386-cache.lib b/library/SubcircuitLibrary/LM386M/14_lm386-cache.lib new file mode 100644 index 00000000..828a89d6 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM386M/14_lm386.cir b/library/SubcircuitLibrary/LM386M/14_lm386.cir new file mode 100644 index 00000000..b85613cf --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\14_lm386\14_lm386.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/25 17:23:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q5 Net-_Q4-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q6 Net-_Q1-Pad1_ Net-_Q6-Pad2_ Net-_Q5-Pad2_ eSim_PNP +Q7 Net-_D2-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q8 Net-_Q10-Pad2_ Net-_D2-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R1 Net-_Q1-Pad2_ Net-_Q1-Pad1_ 50k +R4 Net-_Q2-Pad3_ Net-_R4-Pad2_ 150 +R5 Net-_R4-Pad2_ Net-_Q5-Pad3_ 1.35k +R6 Net-_Q5-Pad3_ Net-_Q10-Pad1_ 15k +R3 Net-_R2-Pad2_ Net-_Q2-Pad3_ 15k +R2 Net-_Q9-Pad1_ Net-_R2-Pad2_ 15k +R7 Net-_Q6-Pad2_ Net-_Q1-Pad1_ 50k +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R8 Net-_Q9-Pad1_ Net-_D1-Pad1_ 1.35k +Q9 Net-_Q9-Pad1_ Net-_D1-Pad1_ Net-_Q10-Pad1_ eSim_NPN +U1 Net-_Q5-Pad3_ Net-_Q1-Pad2_ Net-_Q6-Pad2_ Net-_Q1-Pad1_ Net-_Q10-Pad1_ Net-_Q9-Pad1_ Net-_R2-Pad2_ Net-_R4-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM386M/14_lm386.cir.out b/library/SubcircuitLibrary/LM386M/14_lm386.cir.out new file mode 100644 index 00000000..cfe04457 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386.cir.out @@ -0,0 +1,35 @@ +* c:\fossee\esim\library\subcircuitlibrary\14_lm386\14_lm386.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q6 net-_q1-pad1_ net-_q6-pad2_ net-_q5-pad2_ Q2N2907A +q7 net-_d2-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q10-pad2_ net-_d2-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q1-pad1_ Q2N2222 +r1 net-_q1-pad2_ net-_q1-pad1_ 50k +r4 net-_q2-pad3_ net-_r4-pad2_ 150 +r5 net-_r4-pad2_ net-_q5-pad3_ 1.35k +r6 net-_q5-pad3_ net-_q10-pad1_ 15k +r3 net-_r2-pad2_ net-_q2-pad3_ 15k +r2 net-_q9-pad1_ net-_r2-pad2_ 15k +r7 net-_q6-pad2_ net-_q1-pad1_ 50k +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r8 net-_q9-pad1_ net-_d1-pad1_ 1.35k +q9 net-_q9-pad1_ net-_d1-pad1_ net-_q10-pad1_ Q2N2222 +* u1 net-_q5-pad3_ net-_q1-pad2_ net-_q6-pad2_ net-_q1-pad1_ net-_q10-pad1_ net-_q9-pad1_ net-_r2-pad2_ net-_r4-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM386M/14_lm386.pro b/library/SubcircuitLibrary/LM386M/14_lm386.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM386M/14_lm386.sch b/library/SubcircuitLibrary/LM386M/14_lm386.sch new file mode 100644 index 00000000..0f98ae05 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386.sch @@ -0,0 +1,483 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:14_lm386-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 67D410DA +P 3650 3350 +F 0 "Q2" H 3550 3400 50 0000 R CNN +F 1 "eSim_PNP" H 3600 3500 50 0000 R CNN +F 2 "" H 3850 3450 29 0000 C CNN +F 3 "" H 3650 3350 60 0000 C CNN + 1 3650 3350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 67D410DB +P 2800 3900 +F 0 "Q1" H 2700 3950 50 0000 R CNN +F 1 "eSim_PNP" H 2750 4050 50 0000 R CNN +F 2 "" H 3000 4000 29 0000 C CNN +F 3 "" H 2800 3900 60 0000 C CNN + 1 2800 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67D410DC +P 3850 4750 +F 0 "Q3" H 3750 4800 50 0000 R CNN +F 1 "eSim_NPN" H 3800 4900 50 0000 R CNN +F 2 "" H 4050 4850 29 0000 C CNN +F 3 "" H 3850 4750 60 0000 C CNN + 1 3850 4750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 67D410DD +P 5500 3300 +F 0 "Q5" H 5400 3350 50 0000 R CNN +F 1 "eSim_PNP" H 5450 3450 50 0000 R CNN +F 2 "" H 5700 3400 29 0000 C CNN +F 3 "" H 5500 3300 60 0000 C CNN + 1 5500 3300 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67D410DE +P 5300 4750 +F 0 "Q4" H 5200 4800 50 0000 R CNN +F 1 "eSim_NPN" H 5250 4900 50 0000 R CNN +F 2 "" H 5500 4850 29 0000 C CNN +F 3 "" H 5300 4750 60 0000 C CNN + 1 5300 4750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 67D410DF +P 6300 3950 +F 0 "Q6" H 6200 4000 50 0000 R CNN +F 1 "eSim_PNP" H 6250 4100 50 0000 R CNN +F 2 "" H 6500 4050 29 0000 C CNN +F 3 "" H 6300 3950 60 0000 C CNN + 1 6300 3950 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 67D410E0 +P 7900 4750 +F 0 "Q7" H 7800 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7850 4900 50 0000 R CNN +F 2 "" H 8100 4850 29 0000 C CNN +F 3 "" H 7900 4750 60 0000 C CNN + 1 7900 4750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 67D410E1 +P 8400 3550 +F 0 "Q8" H 8300 3600 50 0000 R CNN +F 1 "eSim_PNP" H 8350 3700 50 0000 R CNN +F 2 "" H 8600 3650 29 0000 C CNN +F 3 "" H 8400 3550 60 0000 C CNN + 1 8400 3550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 67D410E2 +P 8800 4750 +F 0 "Q10" H 8700 4800 50 0000 R CNN +F 1 "eSim_NPN" H 8750 4900 50 0000 R CNN +F 2 "" H 9000 4850 29 0000 C CNN +F 3 "" H 8800 4750 60 0000 C CNN + 1 8800 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 3550 3750 4550 +Wire Wire Line + 4050 4750 5100 4750 +Wire Wire Line + 5700 3300 6200 3300 +Wire Wire Line + 6200 3300 6200 3750 +Wire Wire Line + 5400 4550 5400 3500 +Wire Wire Line + 2900 3700 2900 3350 +Wire Wire Line + 2900 3350 3450 3350 +$Comp +L resistor R1 +U 1 1 67D410E3 +P 2300 4500 +F 0 "R1" H 2350 4630 50 0000 C CNN +F 1 "50k" H 2350 4450 50 0000 C CNN +F 2 "" H 2350 4480 30 0000 C CNN +F 3 "" V 2350 4550 30 0000 C CNN + 1 2300 4500 + 0 -1 1 0 +$EndComp +Wire Wire Line + 2250 4400 2250 3900 +Wire Wire Line + 2050 3900 2600 3900 +Wire Wire Line + 2250 4700 2250 5450 +Wire Wire Line + 2250 5450 9800 5450 +Wire Wire Line + 2900 4100 2900 5450 +Connection ~ 2900 5450 +Wire Wire Line + 3750 4950 3750 5450 +Connection ~ 3750 5450 +Wire Wire Line + 5400 4950 5400 5450 +Connection ~ 5400 5450 +Wire Wire Line + 6200 4150 6200 5450 +Connection ~ 6200 5450 +Wire Wire Line + 8000 4950 8000 5450 +Connection ~ 8000 5450 +Wire Wire Line + 8900 4950 8900 5450 +Connection ~ 8900 5450 +$Comp +L resistor R4 +U 1 1 67D410E4 +P 4100 3000 +F 0 "R4" H 4150 3130 50 0000 C CNN +F 1 "150" H 4150 2950 50 0000 C CNN +F 2 "" H 4150 2980 30 0000 C CNN +F 3 "" V 4150 3050 30 0000 C CNN + 1 4100 3000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 67D410E5 +P 4800 3000 +F 0 "R5" H 4850 3130 50 0000 C CNN +F 1 "1.35k" H 4850 2950 50 0000 C CNN +F 2 "" H 4850 2980 30 0000 C CNN +F 3 "" V 4850 3050 30 0000 C CNN + 1 4800 3000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 67D410E6 +P 5950 3000 +F 0 "R6" H 6000 3130 50 0000 C CNN +F 1 "15k" H 6000 2950 50 0000 C CNN +F 2 "" H 6000 2980 30 0000 C CNN +F 3 "" V 6000 3050 30 0000 C CNN + 1 5950 3000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67D410E7 +P 3800 2300 +F 0 "R3" H 3850 2430 50 0000 C CNN +F 1 "15k" H 3850 2250 50 0000 C CNN +F 2 "" H 3850 2280 30 0000 C CNN +F 3 "" V 3850 2350 30 0000 C CNN + 1 3800 2300 + 0 -1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67D410E8 +P 3800 1700 +F 0 "R2" H 3850 1830 50 0000 C CNN +F 1 "15k" H 3850 1650 50 0000 C CNN +F 2 "" H 3850 1680 30 0000 C CNN +F 3 "" V 3850 1750 30 0000 C CNN + 1 3800 1700 + 0 -1 1 0 +$EndComp +Wire Wire Line + 3750 3150 3750 2500 +Wire Wire Line + 4000 2950 3750 2950 +Connection ~ 3750 2950 +Wire Wire Line + 4300 2950 4700 2950 +Wire Wire Line + 5000 2950 5850 2950 +Wire Wire Line + 5400 2650 5400 3100 +Connection ~ 5400 2950 +Wire Wire Line + 3750 2200 3750 1900 +Wire Wire Line + 6500 3950 7350 3950 +Wire Wire Line + 3750 4200 4600 4200 +Wire Wire Line + 4600 4200 4600 4750 +Connection ~ 4600 4750 +Connection ~ 3750 4200 +Wire Wire Line + 5400 4350 5900 4350 +Wire Wire Line + 5900 4350 5900 4750 +Wire Wire Line + 5900 4750 7700 4750 +Connection ~ 5400 4350 +$Comp +L resistor R7 +U 1 1 67D410E9 +P 6950 4450 +F 0 "R7" H 7000 4580 50 0000 C CNN +F 1 "50k" H 7000 4400 50 0000 C CNN +F 2 "" H 7000 4430 30 0000 C CNN +F 3 "" V 7000 4500 30 0000 C CNN + 1 6950 4450 + 0 -1 1 0 +$EndComp +Wire Wire Line + 6900 4350 6900 3950 +Connection ~ 6900 3950 +Wire Wire Line + 6900 4650 6900 5450 +Connection ~ 6900 5450 +Wire Wire Line + 8500 3750 8500 4750 +Wire Wire Line + 8500 4750 8600 4750 +$Comp +L eSim_Diode D2 +U 1 1 67D410EA +P 8000 3250 +F 0 "D2" H 8000 3350 50 0000 C CNN +F 1 "eSim_Diode" H 8000 3150 50 0000 C CNN +F 2 "" H 8000 3250 60 0000 C CNN +F 3 "" H 8000 3250 60 0000 C CNN + 1 8000 3250 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67D410EB +P 8000 2400 +F 0 "D1" H 8000 2500 50 0000 C CNN +F 1 "eSim_Diode" H 8000 2300 50 0000 C CNN +F 2 "" H 8000 2400 60 0000 C CNN +F 3 "" H 8000 2400 60 0000 C CNN + 1 8000 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8000 4550 8000 3400 +Wire Wire Line + 8200 3550 8000 3550 +Connection ~ 8000 3550 +Wire Wire Line + 3750 1600 3750 1350 +Wire Wire Line + 3750 1350 9400 1350 +$Comp +L resistor R8 +U 1 1 67D410EC +P 8050 1750 +F 0 "R8" H 8100 1880 50 0000 C CNN +F 1 "1.35k" H 8100 1700 50 0000 C CNN +F 2 "" H 8100 1730 30 0000 C CNN +F 3 "" V 8100 1800 30 0000 C CNN + 1 8050 1750 + 0 -1 1 0 +$EndComp +Wire Wire Line + 8000 2250 8000 1950 +Wire Wire Line + 8000 1650 8000 1350 +Connection ~ 8000 1350 +Wire Wire Line + 8000 3100 8000 2550 +Wire Wire Line + 6150 2950 9750 2950 +$Comp +L eSim_NPN Q9 +U 1 1 67D410ED +P 8800 2100 +F 0 "Q9" H 8700 2150 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2250 50 0000 R CNN +F 2 "" H 9000 2200 29 0000 C CNN +F 3 "" H 8800 2100 60 0000 C CNN + 1 8800 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8900 1900 8900 1350 +Connection ~ 8900 1350 +Wire Wire Line + 8900 2300 8900 4550 +Connection ~ 8900 2950 +Wire Wire Line + 8600 2100 8000 2100 +Connection ~ 8000 2100 +Connection ~ 2250 3900 +Wire Wire Line + 8500 3350 8500 3300 +Wire Wire Line + 8500 3300 8900 3300 +Connection ~ 8900 3300 +Wire Wire Line + 3450 2100 3750 2100 +Connection ~ 3750 2100 +Wire Wire Line + 4500 2600 4500 2950 +Connection ~ 4500 2950 +$Comp +L PORT U1 +U 1 1 67D423C8 +P 5400 2400 +F 0 "U1" H 5450 2500 30 0000 C CNN +F 1 "PORT" H 5400 2400 30 0000 C CNN +F 2 "" H 5400 2400 60 0000 C CNN +F 3 "" H 5400 2400 60 0000 C CNN + 1 5400 2400 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67D4256B +P 1800 3900 +F 0 "U1" H 1850 4000 30 0000 C CNN +F 1 "PORT" H 1800 3900 30 0000 C CNN +F 2 "" H 1800 3900 60 0000 C CNN +F 3 "" H 1800 3900 60 0000 C CNN + 2 1800 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67D42704 +P 7600 3950 +F 0 "U1" H 7650 4050 30 0000 C CNN +F 1 "PORT" H 7600 3950 30 0000 C CNN +F 2 "" H 7600 3950 60 0000 C CNN +F 3 "" H 7600 3950 60 0000 C CNN + 3 7600 3950 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67D4281E +P 10050 5450 +F 0 "U1" H 10100 5550 30 0000 C CNN +F 1 "PORT" H 10050 5450 30 0000 C CNN +F 2 "" H 10050 5450 60 0000 C CNN +F 3 "" H 10050 5450 60 0000 C CNN + 4 10050 5450 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67D429BF +P 10000 2950 +F 0 "U1" H 10050 3050 30 0000 C CNN +F 1 "PORT" H 10000 2950 30 0000 C CNN +F 2 "" H 10000 2950 60 0000 C CNN +F 3 "" H 10000 2950 60 0000 C CNN + 5 10000 2950 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67D42B85 +P 9650 1350 +F 0 "U1" H 9700 1450 30 0000 C CNN +F 1 "PORT" H 9650 1350 30 0000 C CNN +F 2 "" H 9650 1350 60 0000 C CNN +F 3 "" H 9650 1350 60 0000 C CNN + 6 9650 1350 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67D42CF4 +P 3200 2100 +F 0 "U1" H 3250 2200 30 0000 C CNN +F 1 "PORT" H 3200 2100 30 0000 C CNN +F 2 "" H 3200 2100 60 0000 C CNN +F 3 "" H 3200 2100 60 0000 C CNN + 7 3200 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67D42E04 +P 4500 2350 +F 0 "U1" H 4550 2450 30 0000 C CNN +F 1 "PORT" H 4500 2350 30 0000 C CNN +F 2 "" H 4500 2350 60 0000 C CNN +F 3 "" H 4500 2350 60 0000 C CNN + 8 4500 2350 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM386M/14_lm386.sub b/library/SubcircuitLibrary/LM386M/14_lm386.sub new file mode 100644 index 00000000..3123dfcd --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386.sub @@ -0,0 +1,29 @@ +* Subcircuit 14_lm386 +.subckt 14_lm386 net-_q5-pad3_ net-_q1-pad2_ net-_q6-pad2_ net-_q1-pad1_ net-_q10-pad1_ net-_q9-pad1_ net-_r2-pad2_ net-_r4-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\14_lm386\14_lm386.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q6 net-_q1-pad1_ net-_q6-pad2_ net-_q5-pad2_ Q2N2907A +q7 net-_d2-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q10-pad2_ net-_d2-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q1-pad1_ Q2N2222 +r1 net-_q1-pad2_ net-_q1-pad1_ 50k +r4 net-_q2-pad3_ net-_r4-pad2_ 150 +r5 net-_r4-pad2_ net-_q5-pad3_ 1.35k +r6 net-_q5-pad3_ net-_q10-pad1_ 15k +r3 net-_r2-pad2_ net-_q2-pad3_ 15k +r2 net-_q9-pad1_ net-_r2-pad2_ 15k +r7 net-_q6-pad2_ net-_q1-pad1_ 50k +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r8 net-_q9-pad1_ net-_d1-pad1_ 1.35k +q9 net-_q9-pad1_ net-_d1-pad1_ net-_q10-pad1_ Q2N2222 +* Control Statements + +.ends 14_lm386
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386M/14_lm386_Previous_Values.xml b/library/SubcircuitLibrary/LM386M/14_lm386_Previous_Values.xml new file mode 100644 index 00000000..0cb696f5 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/14_lm386_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386M/D.lib b/library/SubcircuitLibrary/LM386M/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM386M/NPN.lib b/library/SubcircuitLibrary/LM386M/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM386M/PNP.lib b/library/SubcircuitLibrary/LM386M/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM386M/analysis b/library/SubcircuitLibrary/LM386M/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM386M/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib new file mode 100644 index 00000000..136c4de9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A-cache.lib @@ -0,0 +1,123 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir new file mode 100644 index 00000000..3881f6bd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir @@ -0,0 +1,30 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC257A\SN74LVC257A.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/10/25 11:05:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U17-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter +U2 Net-_U1-Pad2_ Net-_U10-Pad1_ d_buffer +U5 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U13-Pad1_ d_and +U6 Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad2_ d_and +U7 Net-_U11-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and +U8 Net-_U10-Pad1_ Net-_U1-Pad6_ Net-_U14-Pad2_ d_and +U9 Net-_U11-Pad1_ Net-_U1-Pad7_ Net-_U15-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad8_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and +U12 Net-_U10-Pad1_ Net-_U1-Pad10_ Net-_U12-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U16 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_or +U17 Net-_U13-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad11_ d_tristate +U18 Net-_U14-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad12_ d_tristate +U19 Net-_U15-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad13_ d_tristate +U20 Net-_U16-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad14_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out new file mode 100644 index 00000000..081abd5c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.cir.out @@ -0,0 +1,88 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74lvc257a\sn74lvc257a.cir + +* u3 net-_u1-pad1_ net-_u17-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u11-pad1_ d_inverter +* u2 net-_u1-pad2_ net-_u10-pad1_ d_buffer +* u5 net-_u11-pad1_ net-_u1-pad3_ net-_u13-pad1_ d_and +* u6 net-_u10-pad1_ net-_u1-pad4_ net-_u13-pad2_ d_and +* u7 net-_u11-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and +* u8 net-_u10-pad1_ net-_u1-pad6_ net-_u14-pad2_ d_and +* u9 net-_u11-pad1_ net-_u1-pad7_ net-_u15-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad8_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u12 net-_u10-pad1_ net-_u1-pad10_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u16 net-_u11-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_or +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ d_tristate +* u18 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate +* u19 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ d_tristate +* u20 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u1-pad1_ net-_u17-pad2_ u3 +a2 net-_u1-pad2_ net-_u11-pad1_ u4 +a3 net-_u1-pad2_ net-_u10-pad1_ u2 +a4 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u13-pad1_ u5 +a5 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u13-pad2_ u6 +a6 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u7 +a7 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u14-pad2_ u8 +a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u15-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad8_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a11 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u12-pad3_ u12 +a12 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a16 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ u17 +a17 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u18 +a18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ u19 +a19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch new file mode 100644 index 00000000..5d0f9cf3 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sch @@ -0,0 +1,543 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 681EE269 +P 2950 1375 +F 0 "U3" H 2950 1275 60 0000 C CNN +F 1 "d_inverter" H 2950 1525 60 0000 C CNN +F 2 "" H 3000 1325 60 0000 C CNN +F 3 "" H 3000 1325 60 0000 C CNN + 1 2950 1375 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 681EE2AE +P 2950 1875 +F 0 "U4" H 2950 1775 60 0000 C CNN +F 1 "d_inverter" H 2950 2025 60 0000 C CNN +F 2 "" H 3000 1825 60 0000 C CNN +F 3 "" H 3000 1825 60 0000 C CNN + 1 2950 1875 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 681EE2D0 +P 2350 2250 +F 0 "U2" H 2350 2200 60 0000 C CNN +F 1 "d_buffer" H 2350 2300 60 0000 C CNN +F 2 "" H 2350 2250 60 0000 C CNN +F 3 "" H 2350 2250 60 0000 C CNN + 1 2350 2250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 681EE388 +P 4125 2900 +F 0 "U5" H 4125 2900 60 0000 C CNN +F 1 "d_and" H 4175 3000 60 0000 C CNN +F 2 "" H 4125 2900 60 0000 C CNN +F 3 "" H 4125 2900 60 0000 C CNN + 1 4125 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 681EE3BF +P 4125 3300 +F 0 "U6" H 4125 3300 60 0000 C CNN +F 1 "d_and" H 4175 3400 60 0000 C CNN +F 2 "" H 4125 3300 60 0000 C CNN +F 3 "" H 4125 3300 60 0000 C CNN + 1 4125 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 681EE3EC +P 4125 3675 +F 0 "U7" H 4125 3675 60 0000 C CNN +F 1 "d_and" H 4175 3775 60 0000 C CNN +F 2 "" H 4125 3675 60 0000 C CNN +F 3 "" H 4125 3675 60 0000 C CNN + 1 4125 3675 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 681EE513 +P 4125 4150 +F 0 "U8" H 4125 4150 60 0000 C CNN +F 1 "d_and" H 4175 4250 60 0000 C CNN +F 2 "" H 4125 4150 60 0000 C CNN +F 3 "" H 4125 4150 60 0000 C CNN + 1 4125 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 681EE519 +P 4125 4550 +F 0 "U9" H 4125 4550 60 0000 C CNN +F 1 "d_and" H 4175 4650 60 0000 C CNN +F 2 "" H 4125 4550 60 0000 C CNN +F 3 "" H 4125 4550 60 0000 C CNN + 1 4125 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 681EE51F +P 4125 4925 +F 0 "U10" H 4125 4925 60 0000 C CNN +F 1 "d_and" H 4175 5025 60 0000 C CNN +F 2 "" H 4125 4925 60 0000 C CNN +F 3 "" H 4125 4925 60 0000 C CNN + 1 4125 4925 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 681EE576 +P 4125 5275 +F 0 "U11" H 4125 5275 60 0000 C CNN +F 1 "d_and" H 4175 5375 60 0000 C CNN +F 2 "" H 4125 5275 60 0000 C CNN +F 3 "" H 4125 5275 60 0000 C CNN + 1 4125 5275 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 681EE60E +P 4125 5675 +F 0 "U12" H 4125 5675 60 0000 C CNN +F 1 "d_and" H 4175 5775 60 0000 C CNN +F 2 "" H 4125 5675 60 0000 C CNN +F 3 "" H 4125 5675 60 0000 C CNN + 1 4125 5675 + 1 0 0 -1 +$EndComp +$Comp +L d_or U13 +U 1 1 681EE688 +P 5250 3100 +F 0 "U13" H 5250 3100 60 0000 C CNN +F 1 "d_or" H 5250 3200 60 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U14 +U 1 1 681EE6D3 +P 5250 3925 +F 0 "U14" H 5250 3925 60 0000 C CNN +F 1 "d_or" H 5250 4025 60 0000 C CNN +F 2 "" H 5250 3925 60 0000 C CNN +F 3 "" H 5250 3925 60 0000 C CNN + 1 5250 3925 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 681EE789 +P 5250 4700 +F 0 "U15" H 5250 4700 60 0000 C CNN +F 1 "d_or" H 5250 4800 60 0000 C CNN +F 2 "" H 5250 4700 60 0000 C CNN +F 3 "" H 5250 4700 60 0000 C CNN + 1 5250 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_or U16 +U 1 1 681EE813 +P 5250 5450 +F 0 "U16" H 5250 5450 60 0000 C CNN +F 1 "d_or" H 5250 5550 60 0000 C CNN +F 2 "" H 5250 5450 60 0000 C CNN +F 3 "" H 5250 5450 60 0000 C CNN + 1 5250 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U17 +U 1 1 681EE8AC +P 6600 2700 +F 0 "U17" H 6350 2950 60 0000 C CNN +F 1 "d_tristate" H 6400 3150 60 0000 C CNN +F 2 "" H 6500 3050 60 0000 C CNN +F 3 "" H 6500 3050 60 0000 C CNN + 1 6600 2700 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U18 +U 1 1 681EE982 +P 6600 3525 +F 0 "U18" H 6350 3775 60 0000 C CNN +F 1 "d_tristate" H 6400 3975 60 0000 C CNN +F 2 "" H 6500 3875 60 0000 C CNN +F 3 "" H 6500 3875 60 0000 C CNN + 1 6600 3525 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U19 +U 1 1 681EEAAC +P 6600 4300 +F 0 "U19" H 6350 4550 60 0000 C CNN +F 1 "d_tristate" H 6400 4750 60 0000 C CNN +F 2 "" H 6500 4650 60 0000 C CNN +F 3 "" H 6500 4650 60 0000 C CNN + 1 6600 4300 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U20 +U 1 1 681EEB14 +P 6600 5050 +F 0 "U20" H 6350 5300 60 0000 C CNN +F 1 "d_tristate" H 6400 5500 60 0000 C CNN +F 2 "" H 6500 5400 60 0000 C CNN +F 3 "" H 6500 5400 60 0000 C CNN + 1 6600 5050 + 1 0 0 1 +$EndComp +Wire Wire Line + 4575 2850 4575 3000 +Wire Wire Line + 4575 3000 4800 3000 +Wire Wire Line + 4800 3100 4575 3100 +Wire Wire Line + 4575 3100 4575 3250 +Wire Wire Line + 4575 3625 4575 3825 +Wire Wire Line + 4575 3825 4800 3825 +Wire Wire Line + 4800 3925 4575 3925 +Wire Wire Line + 4575 3925 4575 4100 +Wire Wire Line + 4575 4500 4575 4600 +Wire Wire Line + 4575 4600 4800 4600 +Wire Wire Line + 4800 4700 4575 4700 +Wire Wire Line + 4575 4700 4575 4875 +Wire Wire Line + 4575 5225 4575 5350 +Wire Wire Line + 4575 5350 4800 5350 +Wire Wire Line + 4800 5450 4575 5450 +Wire Wire Line + 4575 5450 4575 5625 +Wire Wire Line + 6000 5400 5700 5400 +Wire Wire Line + 6000 4650 5700 4650 +Wire Wire Line + 6000 3875 5700 3875 +Wire Wire Line + 6000 3050 5700 3050 +Wire Wire Line + 3250 1875 3475 1875 +Wire Wire Line + 3475 1875 3475 5175 +Wire Wire Line + 3475 5175 3675 5175 +Wire Wire Line + 3675 3575 3475 3575 +Connection ~ 3475 3575 +Wire Wire Line + 3675 2800 3475 2800 +Connection ~ 3475 2800 +Wire Wire Line + 3675 4450 3475 4450 +Connection ~ 3475 4450 +Wire Wire Line + 3000 2250 3100 2250 +Wire Wire Line + 3100 2250 3100 5575 +Wire Wire Line + 3100 5575 3675 5575 +Wire Wire Line + 3675 4825 3100 4825 +Connection ~ 3100 4825 +Wire Wire Line + 3675 4050 3100 4050 +Connection ~ 3100 4050 +Wire Wire Line + 3675 3200 3100 3200 +Connection ~ 3100 3200 +Wire Wire Line + 2425 2900 3675 2900 +Wire Wire Line + 3675 3300 2425 3300 +Wire Wire Line + 3675 3675 2425 3675 +Wire Wire Line + 3675 4150 2425 4150 +Wire Wire Line + 3675 4550 2425 4550 +Wire Wire Line + 3675 5275 2425 5275 +Wire Wire Line + 3675 5675 2425 5675 +Wire Wire Line + 3250 1375 7375 1375 +Wire Wire Line + 7375 1375 7375 5100 +Wire Wire Line + 7375 5100 6550 5100 +Wire Wire Line + 6550 4350 6550 4300 +Wire Wire Line + 6550 4300 7375 4300 +Connection ~ 7375 4300 +Wire Wire Line + 6550 3575 6550 3475 +Wire Wire Line + 6550 3475 7375 3475 +Connection ~ 7375 3475 +Wire Wire Line + 6550 2750 6550 2625 +Wire Wire Line + 6550 2625 7375 2625 +Connection ~ 7375 2625 +Wire Wire Line + 7150 3050 8075 3050 +Wire Wire Line + 7150 3875 8075 3875 +Wire Wire Line + 7150 4650 8075 4650 +Wire Wire Line + 7150 5400 8075 5400 +Wire Wire Line + 1375 1375 2650 1375 +Wire Wire Line + 2650 1875 1375 1875 +Wire Wire Line + 1850 2250 1675 2250 +Wire Wire Line + 1675 2250 1675 1875 +Connection ~ 1675 1875 +$Comp +L PORT U1 +U 1 1 681F1778 +P 1125 1375 +F 0 "U1" H 1175 1475 30 0000 C CNN +F 1 "PORT" H 1125 1375 30 0000 C CNN +F 2 "" H 1125 1375 60 0000 C CNN +F 3 "" H 1125 1375 60 0000 C CNN + 1 1125 1375 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 681F17BB +P 1125 1875 +F 0 "U1" H 1175 1975 30 0000 C CNN +F 1 "PORT" H 1125 1875 30 0000 C CNN +F 2 "" H 1125 1875 60 0000 C CNN +F 3 "" H 1125 1875 60 0000 C CNN + 2 1125 1875 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 681F188F +P 2175 2900 +F 0 "U1" H 2225 3000 30 0000 C CNN +F 1 "PORT" H 2175 2900 30 0000 C CNN +F 2 "" H 2175 2900 60 0000 C CNN +F 3 "" H 2175 2900 60 0000 C CNN + 3 2175 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 681F18D6 +P 2175 3300 +F 0 "U1" H 2225 3400 30 0000 C CNN +F 1 "PORT" H 2175 3300 30 0000 C CNN +F 2 "" H 2175 3300 60 0000 C CNN +F 3 "" H 2175 3300 60 0000 C CNN + 4 2175 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 681F19A9 +P 2175 3675 +F 0 "U1" H 2225 3775 30 0000 C CNN +F 1 "PORT" H 2175 3675 30 0000 C CNN +F 2 "" H 2175 3675 60 0000 C CNN +F 3 "" H 2175 3675 60 0000 C CNN + 5 2175 3675 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 681F19EE +P 2175 4150 +F 0 "U1" H 2225 4250 30 0000 C CNN +F 1 "PORT" H 2175 4150 30 0000 C CNN +F 2 "" H 2175 4150 60 0000 C CNN +F 3 "" H 2175 4150 60 0000 C CNN + 6 2175 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 681F1AE8 +P 2175 4550 +F 0 "U1" H 2225 4650 30 0000 C CNN +F 1 "PORT" H 2175 4550 30 0000 C CNN +F 2 "" H 2175 4550 60 0000 C CNN +F 3 "" H 2175 4550 60 0000 C CNN + 7 2175 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 681F1B99 +P 2175 4925 +F 0 "U1" H 2225 5025 30 0000 C CNN +F 1 "PORT" H 2175 4925 30 0000 C CNN +F 2 "" H 2175 4925 60 0000 C CNN +F 3 "" H 2175 4925 60 0000 C CNN + 8 2175 4925 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2425 4925 3675 4925 +$Comp +L PORT U1 +U 9 1 681F1EEC +P 2175 5275 +F 0 "U1" H 2225 5375 30 0000 C CNN +F 1 "PORT" H 2175 5275 30 0000 C CNN +F 2 "" H 2175 5275 60 0000 C CNN +F 3 "" H 2175 5275 60 0000 C CNN + 9 2175 5275 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 681F1FD7 +P 2175 5675 +F 0 "U1" H 2225 5775 30 0000 C CNN +F 1 "PORT" H 2175 5675 30 0000 C CNN +F 2 "" H 2175 5675 60 0000 C CNN +F 3 "" H 2175 5675 60 0000 C CNN + 10 2175 5675 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 681F2150 +P 8325 3050 +F 0 "U1" H 8375 3150 30 0000 C CNN +F 1 "PORT" H 8325 3050 30 0000 C CNN +F 2 "" H 8325 3050 60 0000 C CNN +F 3 "" H 8325 3050 60 0000 C CNN + 11 8325 3050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 681F21AD +P 8325 3875 +F 0 "U1" H 8375 3975 30 0000 C CNN +F 1 "PORT" H 8325 3875 30 0000 C CNN +F 2 "" H 8325 3875 60 0000 C CNN +F 3 "" H 8325 3875 60 0000 C CNN + 12 8325 3875 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 681F2280 +P 8325 4650 +F 0 "U1" H 8375 4750 30 0000 C CNN +F 1 "PORT" H 8325 4650 30 0000 C CNN +F 2 "" H 8325 4650 60 0000 C CNN +F 3 "" H 8325 4650 60 0000 C CNN + 13 8325 4650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 681F23B7 +P 8325 5400 +F 0 "U1" H 8375 5500 30 0000 C CNN +F 1 "PORT" H 8325 5400 30 0000 C CNN +F 2 "" H 8325 5400 60 0000 C CNN +F 3 "" H 8325 5400 60 0000 C CNN + 14 8325 5400 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub new file mode 100644 index 00000000..99057965 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A.sub @@ -0,0 +1,82 @@ +* Subcircuit SN74LVC257A +.subckt SN74LVC257A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74lvc257a\sn74lvc257a.cir +* u3 net-_u1-pad1_ net-_u17-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u11-pad1_ d_inverter +* u2 net-_u1-pad2_ net-_u10-pad1_ d_buffer +* u5 net-_u11-pad1_ net-_u1-pad3_ net-_u13-pad1_ d_and +* u6 net-_u10-pad1_ net-_u1-pad4_ net-_u13-pad2_ d_and +* u7 net-_u11-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and +* u8 net-_u10-pad1_ net-_u1-pad6_ net-_u14-pad2_ d_and +* u9 net-_u11-pad1_ net-_u1-pad7_ net-_u15-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad8_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u12 net-_u10-pad1_ net-_u1-pad10_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u16 net-_u11-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_or +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ d_tristate +* u18 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate +* u19 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ d_tristate +* u20 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ d_tristate +a1 net-_u1-pad1_ net-_u17-pad2_ u3 +a2 net-_u1-pad2_ net-_u11-pad1_ u4 +a3 net-_u1-pad2_ net-_u10-pad1_ u2 +a4 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u13-pad1_ u5 +a5 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u13-pad2_ u6 +a6 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u7 +a7 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u14-pad2_ u8 +a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u15-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad8_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a11 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u12-pad3_ u12 +a12 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a16 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad11_ u17 +a17 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u18 +a18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad13_ u19 +a19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad14_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Control Statements + +.ends SN74LVC257A
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml new file mode 100644 index 00000000..62f4659b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/SN74LVC257A_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_buffer<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_or<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_or<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_tristate<field46 name="Enter Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Enable Load (default=1.0e-12)" /></u17><u18 name="type">d_tristate<field49 name="Enter Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Enable Load (default=1.0e-12)" /></u18><u19 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u19><u20 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LVC257A/analysis b/library/SubcircuitLibrary/SN74LVC257A/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC257A/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib b/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib new file mode 100644 index 00000000..bf93b556 --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b-cache.lib @@ -0,0 +1,103 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# buffer_4pin +# +DEF buffer_4pin U 0 40 Y Y 1 F N +F0 "U" -100 -175 31 H V C CNN +F1 "buffer_4pin" 175 -250 39 H V C CNN +F2 "" 150 25 60 H V C CNN +F3 "" 150 25 60 H V C CNN +DRAW +P 3 0 1 0 -25 150 350 -25 -25 -200 N +P 4 0 1 0 -25 -200 -175 -275 -175 225 -25 150 N +X A0 1 -375 -25 200 R 50 31 1 1 B +X VCC 2 -25 350 200 D 50 31 1 1 I +X GND 3 -25 -400 200 U 50 31 1 1 I N +X Y0 4 550 -25 200 L 50 31 1 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# tristate_buffer_active_low +# +DEF tristate_buffer_active_low U 0 40 Y Y 1 F N +F0 "U" -75 -175 60 H V C CNN +F1 "tristate_buffer_active_low" 325 -125 31 H V C CNN +F2 "" 0 100 60 H V C CNN +F3 "" 0 100 60 H V C CNN +DRAW +P 5 0 1 0 -250 300 0 200 425 50 -250 -150 -250 300 N +X A0 1 -450 25 200 R 50 50 1 1 B +X EN0 2 0 400 200 D 50 50 1 1 I +X Y0 3 625 50 200 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir new file mode 100644 index 00000000..5ba50773 --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir @@ -0,0 +1,29 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Sn75160b\Sn75160b.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/12/25 13:54:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U1-Pad8_ /TE Net-_U1-Pad3_ tristate_buffer_active_low +U4 Net-_U1-Pad3_ /PE ? Net-_U1-Pad8_ buffer_4pin +U2 Net-_U1-Pad1_ /PE d_buffer +U3 Net-_U1-Pad2_ /TE d_buffer +U9 Net-_U1-Pad7_ /TE Net-_U1-Pad4_ tristate_buffer_active_low +U5 Net-_U1-Pad4_ /PE ? Net-_U1-Pad7_ buffer_4pin +U10 Net-_U1-Pad9_ /TE Net-_U1-Pad5_ tristate_buffer_active_low +U6 Net-_U1-Pad5_ /PE ? Net-_U1-Pad9_ buffer_4pin +U11 Net-_U1-Pad10_ /TE Net-_U1-Pad6_ tristate_buffer_active_low +U7 Net-_U1-Pad6_ /PE ? Net-_U1-Pad10_ buffer_4pin +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ GND GND PORT +U16 Net-_U1-Pad16_ /TE Net-_U1-Pad11_ tristate_buffer_active_low +U12 Net-_U1-Pad11_ /PE ? Net-_U1-Pad16_ buffer_4pin +U17 Net-_U1-Pad15_ /TE Net-_U1-Pad12_ tristate_buffer_active_low +U13 Net-_U1-Pad12_ /PE ? Net-_U1-Pad15_ buffer_4pin +U18 Net-_U1-Pad17_ /TE Net-_U1-Pad13_ tristate_buffer_active_low +U14 Net-_U1-Pad13_ /PE ? Net-_U1-Pad17_ buffer_4pin +U19 Net-_U1-Pad18_ /TE Net-_U1-Pad14_ tristate_buffer_active_low +U15 Net-_U1-Pad14_ /PE ? Net-_U1-Pad18_ buffer_4pin + +.end diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out new file mode 100644 index 00000000..ba93807c --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.cir.out @@ -0,0 +1,84 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn75160b\sn75160b.cir + +* u8 net-_u1-pad8_ /te net-_u1-pad3_ tristate_buffer_active_low +* u4 net-_u1-pad3_ /pe ? net-_u1-pad8_ buffer_4pin +* u2 net-_u1-pad1_ /pe d_buffer +* u3 net-_u1-pad2_ /te d_buffer +* u9 net-_u1-pad7_ /te net-_u1-pad4_ tristate_buffer_active_low +* u5 net-_u1-pad4_ /pe ? net-_u1-pad7_ buffer_4pin +* u10 net-_u1-pad9_ /te net-_u1-pad5_ tristate_buffer_active_low +* u6 net-_u1-pad5_ /pe ? net-_u1-pad9_ buffer_4pin +* u11 net-_u1-pad10_ /te net-_u1-pad6_ tristate_buffer_active_low +* u7 net-_u1-pad6_ /pe ? net-_u1-pad10_ buffer_4pin +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd port +* u16 net-_u1-pad16_ /te net-_u1-pad11_ tristate_buffer_active_low +* u12 net-_u1-pad11_ /pe ? net-_u1-pad16_ buffer_4pin +* u17 net-_u1-pad15_ /te net-_u1-pad12_ tristate_buffer_active_low +* u13 net-_u1-pad12_ /pe ? net-_u1-pad15_ buffer_4pin +* u18 net-_u1-pad17_ /te net-_u1-pad13_ tristate_buffer_active_low +* u14 net-_u1-pad13_ /pe ? net-_u1-pad17_ buffer_4pin +* u19 net-_u1-pad18_ /te net-_u1-pad14_ tristate_buffer_active_low +* u15 net-_u1-pad14_ /pe ? net-_u1-pad18_ buffer_4pin +a1 [net-_u1-pad8_ ] [/te ] [net-_u1-pad3_ ] u8 +a2 [net-_u1-pad3_ ] [/pe ] [? ] [net-_u1-pad8_ ] u4 +a3 net-_u1-pad1_ /pe u2 +a4 net-_u1-pad2_ /te u3 +a5 [net-_u1-pad7_ ] [/te ] [net-_u1-pad4_ ] u9 +a6 [net-_u1-pad4_ ] [/pe ] [? ] [net-_u1-pad7_ ] u5 +a7 [net-_u1-pad9_ ] [/te ] [net-_u1-pad5_ ] u10 +a8 [net-_u1-pad5_ ] [/pe ] [? ] [net-_u1-pad9_ ] u6 +a9 [net-_u1-pad10_ ] [/te ] [net-_u1-pad6_ ] u11 +a10 [net-_u1-pad6_ ] [/pe ] [? ] [net-_u1-pad10_ ] u7 +a11 [net-_u1-pad16_ ] [/te ] [net-_u1-pad11_ ] u16 +a12 [net-_u1-pad11_ ] [/pe ] [? ] [net-_u1-pad16_ ] u12 +a13 [net-_u1-pad15_ ] [/te ] [net-_u1-pad12_ ] u17 +a14 [net-_u1-pad12_ ] [/pe ] [? ] [net-_u1-pad15_ ] u13 +a15 [net-_u1-pad17_ ] [/te ] [net-_u1-pad13_ ] u18 +a16 [net-_u1-pad13_ ] [/pe ] [? ] [net-_u1-pad17_ ] u14 +a17 [net-_u1-pad18_ ] [/te ] [net-_u1-pad14_ ] u19 +a18 [net-_u1-pad14_ ] [/pe ] [? ] [net-_u1-pad18_ ] u15 +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u8 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u4 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u9 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u5 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u10 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u6 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u11 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u7 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u16 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u12 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u17 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u13 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u18 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u14 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u19 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u15 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro b/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch new file mode 100644 index 00000000..adecf4be --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sch @@ -0,0 +1,682 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L tristate_buffer_active_low U8 +U 1 1 67FA2026 +P 3625 3175 +F 0 "U8" H 3550 3000 60 0000 C CNN +F 1 "tristate_buffer_active_low" H 3950 3050 31 0000 C CNN +F 2 "" H 3625 3275 60 0000 C CNN +F 3 "" H 3625 3275 60 0000 C CNN + 1 3625 3175 + -1 0 0 -1 +$EndComp +$Comp +L buffer_4pin U4 +U 1 1 67FA20A9 +P 3375 2350 +F 0 "U4" H 3275 2175 31 0000 C CNN +F 1 "buffer_4pin" H 3550 2100 39 0000 C CNN +F 2 "" H 3525 2375 60 0000 C CNN +F 3 "" H 3525 2375 60 0000 C CNN + 1 3375 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 67FA2105 +P 1900 1275 +F 0 "U2" H 1900 1225 60 0000 C CNN +F 1 "d_buffer" H 1900 1325 60 0000 C CNN +F 2 "" H 1900 1275 60 0000 C CNN +F 3 "" H 1900 1275 60 0000 C CNN + 1 1900 1275 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U3 +U 1 1 67FA213B +P 1900 1800 +F 0 "U3" H 1900 1750 60 0000 C CNN +F 1 "d_buffer" H 1900 1850 60 0000 C CNN +F 2 "" H 1900 1800 60 0000 C CNN +F 3 "" H 1900 1800 60 0000 C CNN + 1 1900 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2000 4550 2000 +Wire Wire Line + 1775 2375 3000 2375 +Wire Wire Line + 2550 1800 2600 1800 +Wire Wire Line + 2600 1800 2600 7225 +Wire Wire Line + 2600 2775 3625 2775 +Wire Wire Line + 3000 3125 2850 3125 +Wire Wire Line + 2850 3125 2850 2375 +Connection ~ 2850 2375 +Wire Wire Line + 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+F 0 "U1" H 5075 3250 30 0000 C CNN +F 1 "PORT" H 5025 3150 30 0000 C CNN +F 2 "" H 5025 3150 60 0000 C CNN +F 3 "" H 5025 3150 60 0000 C CNN + 8 5025 3150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67FA3C3D +P 4925 4650 +F 0 "U1" H 4975 4750 30 0000 C CNN +F 1 "PORT" H 4925 4650 30 0000 C CNN +F 2 "" H 4925 4650 60 0000 C CNN +F 3 "" H 4925 4650 60 0000 C CNN + 7 4925 4650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67FA3DC7 +P 5025 6150 +F 0 "U1" H 5075 6250 30 0000 C CNN +F 1 "PORT" H 5025 6150 30 0000 C CNN +F 2 "" H 5025 6150 60 0000 C CNN +F 3 "" H 5025 6150 60 0000 C CNN + 9 5025 6150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67FA3EEE +P 5025 7600 +F 0 "U1" H 5075 7700 30 0000 C CNN +F 1 "PORT" H 5025 7600 30 0000 C CNN +F 2 "" H 5025 7600 60 0000 C CNN +F 3 "" H 5025 7600 60 0000 C CNN + 10 5025 7600 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67FA4049 +P 8850 2425 +F 0 "U1" H 8900 2525 30 0000 C CNN +F 1 "PORT" H 8850 2425 30 0000 C CNN +F 2 "" H 8850 2425 60 0000 C CNN +F 3 "" H 8850 2425 60 0000 C CNN + 16 8850 2425 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 67FA4226 +P 8750 3925 +F 0 "U1" H 8800 4025 30 0000 C CNN +F 1 "PORT" H 8750 3925 30 0000 C CNN +F 2 "" H 8750 3925 60 0000 C CNN +F 3 "" H 8750 3925 60 0000 C CNN + 15 8750 3925 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 67FA4356 +P 8850 5425 +F 0 "U1" H 8900 5525 30 0000 C CNN +F 1 "PORT" H 8850 5425 30 0000 C CNN +F 2 "" H 8850 5425 60 0000 C CNN +F 3 "" H 8850 5425 60 0000 C CNN + 17 8850 5425 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 67FA4589 +P 8850 6875 +F 0 "U1" H 8900 6975 30 0000 C CNN +F 1 "PORT" H 8850 6875 30 0000 C CNN +F 2 "" H 8850 6875 60 0000 C CNN +F 3 "" H 8850 6875 60 0000 C CNN + 18 8850 6875 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 67FA473F +P 9750 2275 +F 0 "U1" H 9800 2375 30 0000 C CNN +F 1 "PORT" H 9750 2275 30 0000 C CNN +F 2 "" H 9750 2275 60 0000 C CNN +F 3 "" H 9750 2275 60 0000 C CNN + 19 9750 2275 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67FA485A +P 800 1800 +F 0 "U1" H 850 1900 30 0000 C CNN +F 1 "PORT" H 800 1800 30 0000 C CNN +F 2 "" H 800 1800 60 0000 C CNN +F 3 "" H 800 1800 60 0000 C CNN + 2 800 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67FA4CFD +P 5875 6100 +F 0 "U1" H 5925 6200 30 0000 C CNN +F 1 "PORT" H 5875 6100 30 0000 C CNN +F 2 "" H 5875 6100 60 0000 C CNN +F 3 "" H 5875 6100 60 0000 C CNN + 14 5875 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67FA514E +P 5875 4650 +F 0 "U1" H 5925 4750 30 0000 C CNN +F 1 "PORT" H 5875 4650 30 0000 C CNN +F 2 "" H 5875 4650 60 0000 C CNN +F 3 "" H 5875 4650 60 0000 C CNN + 13 5875 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67FA526B +P 5775 3150 +F 0 "U1" H 5825 3250 30 0000 C CNN +F 1 "PORT" H 5775 3150 30 0000 C CNN +F 2 "" H 5775 3150 60 0000 C CNN +F 3 "" H 5775 3150 60 0000 C CNN + 12 5775 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67FA574A +P 5675 1650 +F 0 "U1" H 5725 1750 30 0000 C CNN +F 1 "PORT" H 5675 1650 30 0000 C CNN +F 2 "" H 5675 1650 60 0000 C CNN +F 3 "" H 5675 1650 60 0000 C CNN + 11 5675 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67FA58D8 +P 2050 6850 +F 0 "U1" H 2100 6950 30 0000 C CNN +F 1 "PORT" H 2050 6850 30 0000 C CNN +F 2 "" H 2050 6850 60 0000 C CNN +F 3 "" H 2050 6850 60 0000 C CNN + 6 2050 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67FA5B41 +P 2050 5400 +F 0 "U1" H 2100 5500 30 0000 C CNN +F 1 "PORT" H 2050 5400 30 0000 C CNN +F 2 "" H 2050 5400 60 0000 C CNN +F 3 "" H 2050 5400 60 0000 C CNN + 5 2050 5400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67FA5D52 +P 1950 3900 +F 0 "U1" H 2000 4000 30 0000 C CNN +F 1 "PORT" H 1950 3900 30 0000 C CNN +F 2 "" H 1950 3900 60 0000 C CNN +F 3 "" H 1950 3900 60 0000 C CNN + 4 1950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67FA5F93 +P 1525 2375 +F 0 "U1" H 1575 2475 30 0000 C CNN +F 1 "PORT" H 1525 2375 30 0000 C CNN +F 2 "" H 1525 2375 60 0000 C CNN +F 3 "" H 1525 2375 60 0000 C CNN + 3 1525 2375 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 67FA6271 +P 9750 2575 +F 0 "U1" H 9800 2675 30 0000 C CNN +F 1 "PORT" H 9750 2575 30 0000 C CNN +F 2 "" H 9750 2575 60 0000 C CNN +F 3 "" H 9750 2575 60 0000 C CNN + 20 9750 2575 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10000 2275 10175 2275 +Wire Wire Line + 10175 2275 10175 2575 +Wire Wire Line + 10175 2575 10000 2575 +$Comp +L eSim_GND #PWR01 +U 1 1 67FA6444 +P 10325 2425 +F 0 "#PWR01" H 10325 2175 50 0001 C CNN +F 1 "eSim_GND" H 10325 2275 50 0000 C CNN +F 2 "" H 10325 2425 50 0001 C CNN +F 3 "" H 10325 2425 50 0001 C CNN + 1 10325 2425 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10325 2425 10175 2425 +Connection ~ 10175 2425 +Text Label 2600 2025 0 60 ~ 0 +TE +Text Label 3050 1275 0 60 ~ 0 +PE +Wire Wire Line + 6425 1175 6450 1175 +Wire Wire Line + 7175 1275 8375 1275 +Connection ~ 8375 1275 +Text Label 6450 1175 0 60 ~ 0 +TE +Text Label 8375 1200 0 60 ~ 0 +PE +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub new file mode 100644 index 00000000..fa8e1b0c --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b.sub @@ -0,0 +1,78 @@ +* Subcircuit Sn75160b +.subckt Sn75160b net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd +* c:\fossee\esim\library\subcircuitlibrary\sn75160b\sn75160b.cir +* u8 net-_u1-pad8_ /te net-_u1-pad3_ tristate_buffer_active_low +* u4 net-_u1-pad3_ /pe ? net-_u1-pad8_ buffer_4pin +* u2 net-_u1-pad1_ /pe d_buffer +* u3 net-_u1-pad2_ /te d_buffer +* u9 net-_u1-pad7_ /te net-_u1-pad4_ tristate_buffer_active_low +* u5 net-_u1-pad4_ /pe ? net-_u1-pad7_ buffer_4pin +* u10 net-_u1-pad9_ /te net-_u1-pad5_ tristate_buffer_active_low +* u6 net-_u1-pad5_ /pe ? net-_u1-pad9_ buffer_4pin +* u11 net-_u1-pad10_ /te net-_u1-pad6_ tristate_buffer_active_low +* u7 net-_u1-pad6_ /pe ? net-_u1-pad10_ buffer_4pin +* u16 net-_u1-pad16_ /te net-_u1-pad11_ tristate_buffer_active_low +* u12 net-_u1-pad11_ /pe ? net-_u1-pad16_ buffer_4pin +* u17 net-_u1-pad15_ /te net-_u1-pad12_ tristate_buffer_active_low +* u13 net-_u1-pad12_ /pe ? net-_u1-pad15_ buffer_4pin +* u18 net-_u1-pad17_ /te net-_u1-pad13_ tristate_buffer_active_low +* u14 net-_u1-pad13_ /pe ? net-_u1-pad17_ buffer_4pin +* u19 net-_u1-pad18_ /te net-_u1-pad14_ tristate_buffer_active_low +* u15 net-_u1-pad14_ /pe ? net-_u1-pad18_ buffer_4pin +a1 [net-_u1-pad8_ ] [/te ] [net-_u1-pad3_ ] u8 +a2 [net-_u1-pad3_ ] [/pe ] [? ] [net-_u1-pad8_ ] u4 +a3 net-_u1-pad1_ /pe u2 +a4 net-_u1-pad2_ /te u3 +a5 [net-_u1-pad7_ ] [/te ] [net-_u1-pad4_ ] u9 +a6 [net-_u1-pad4_ ] [/pe ] [? ] [net-_u1-pad7_ ] u5 +a7 [net-_u1-pad9_ ] [/te ] [net-_u1-pad5_ ] u10 +a8 [net-_u1-pad5_ ] [/pe ] [? ] [net-_u1-pad9_ ] u6 +a9 [net-_u1-pad10_ ] [/te ] [net-_u1-pad6_ ] u11 +a10 [net-_u1-pad6_ ] [/pe ] [? ] [net-_u1-pad10_ ] u7 +a11 [net-_u1-pad16_ ] [/te ] [net-_u1-pad11_ ] u16 +a12 [net-_u1-pad11_ ] [/pe ] [? ] [net-_u1-pad16_ ] u12 +a13 [net-_u1-pad15_ ] [/te ] [net-_u1-pad12_ ] u17 +a14 [net-_u1-pad12_ ] [/pe ] [? ] [net-_u1-pad15_ ] u13 +a15 [net-_u1-pad17_ ] [/te ] [net-_u1-pad13_ ] u18 +a16 [net-_u1-pad13_ ] [/pe ] [? ] [net-_u1-pad17_ ] u14 +a17 [net-_u1-pad18_ ] [/te ] [net-_u1-pad14_ ] u19 +a18 [net-_u1-pad14_ ] [/pe ] [? ] [net-_u1-pad18_ ] u15 +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u8 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u4 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u9 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u5 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u10 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u6 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u11 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u7 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u16 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u12 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u17 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u13 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u18 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u14 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low +.model u19 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin +.model u15 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends Sn75160b
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml b/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml new file mode 100644 index 00000000..41acd581 --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/Sn75160b_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u8 name="type">tristate_buffer_active_low<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /><field4 name="Enter Instance ID (Between 0-99)" /></u8><u4 name="type">buffer_4pin<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /><field8 name="Enter Instance ID (Between 0-99)" /></u4><u2 name="type">d_buffer<field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_buffer<field12 name="Enter Rise Delay (default=1.0e-9)" /><field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /></u3><u9 name="type">tristate_buffer_active_low<field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Instance ID (Between 0-99)" /></u9><u5 name="type">buffer_4pin<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /><field22 name="Enter Instance ID (Between 0-99)" /></u5><u10 name="type">tristate_buffer_active_low<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /><field26 name="Enter Instance ID (Between 0-99)" /></u10><u6 name="type">buffer_4pin<field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Instance ID (Between 0-99)" /></u6><u11 name="type">tristate_buffer_active_low<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /><field34 name="Enter Instance ID (Between 0-99)" /></u11><u7 name="type">buffer_4pin<field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /><field37 name="Enter Input Load (default=1.0e-12)" /><field38 name="Enter Instance ID (Between 0-99)" /></u7><u16 name="type">tristate_buffer_active_low<field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Instance ID (Between 0-99)" /></u16><u12 name="type">buffer_4pin<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /><field46 name="Enter Instance ID (Between 0-99)" /></u12><u17 name="type">tristate_buffer_active_low<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /><field50 name="Enter Instance ID (Between 0-99)" /></u17><u13 name="type">buffer_4pin<field51 name="Enter Rise Delay (default=1.0e-9)" /><field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Instance ID (Between 0-99)" /></u13><u18 name="type">tristate_buffer_active_low<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /><field58 name="Enter Instance ID (Between 0-99)" /></u18><u14 name="type">buffer_4pin<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Instance ID (Between 0-99)" /></u14><u19 name="type">tristate_buffer_active_low<field63 name="Enter Rise Delay (default=1.0e-9)" /><field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Instance ID (Between 0-99)" /></u19><u15 name="type">buffer_4pin<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /><field70 name="Enter Instance ID (Between 0-99)" /></u15></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Sn75160b/analysis b/library/SubcircuitLibrary/Sn75160b/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/Sn75160b/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL431_SUB/PowerDiode.lib b/library/SubcircuitLibrary/TL431_SUB/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL431_SUB/ZenerD1N750.lib b/library/SubcircuitLibrary/TL431_SUB/ZenerD1N750.lib new file mode 100644 index 00000000..890c37fe --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub-cache.lib b/library/SubcircuitLibrary/TL431_SUB/tl431_sub-cache.lib new file mode 100644 index 00000000..155677e6 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir new file mode 100644 index 00000000..d4a3caa4 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tl431_sub\tl431_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/29/25 21:28:50 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad1_ /Anode eSim_NPN +Q4 Net-_C1-Pad2_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN +Q9 Net-_C2-Pad2_ Net-_Q9-Pad2_ /Anode eSim_NPN +Q6 Net-_C1-Pad1_ Net-_C1-Pad2_ /Anode eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q2-Pad1_ 2.4k +R3 Net-_R1-Pad1_ Net-_C1-Pad2_ 7.2k +R4 Net-_Q4-Pad3_ /Anode 800 +R7 Net-_Q9-Pad2_ Net-_Q2-Pad1_ 1k +R6 Net-_Q5-Pad3_ Net-_C1-Pad1_ 4k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 20p +Q5 Net-_Q5-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_R1-Pad1_ 3.28k +Q1 /Cathode /Ref Net-_Q1-Pad3_ eSim_NPN +Q3 Net-_C2-Pad2_ Net-_C2-Pad2_ /Ref eSim_NPN +Q7 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q8 Net-_C2-Pad2_ Net-_Q5-Pad1_ Net-_Q8-Pad3_ eSim_PNP +R5 /Cathode Net-_Q7-Pad3_ 800 +R8 /Cathode Net-_Q8-Pad3_ 800 +D1 /Anode Net-_C2-Pad2_ eSim_Diode +C2 /Cathode Net-_C2-Pad2_ 20p +Q10 /Cathode Net-_C2-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R9 Net-_Q10-Pad3_ Net-_Q11-Pad2_ 150 +Q11 /Cathode Net-_Q11-Pad2_ /Anode eSim_NPN +R10 /Anode Net-_Q11-Pad2_ 10k +D2 /Anode /Cathode eSim_Diode +U1 /Cathode /Ref /Anode PORT + +.end diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir.out b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir.out new file mode 100644 index 00000000..40fed526 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.cir.out @@ -0,0 +1,40 @@ +* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir + +.include PNP.lib +.include NPN.lib +.include D.lib +q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222 +q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222 +q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222 +q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222 +r1 net-_r1-pad1_ net-_q2-pad1_ 2.4k +r3 net-_r1-pad1_ net-_c1-pad2_ 7.2k +r4 net-_q4-pad3_ /anode 800 +r7 net-_q9-pad2_ net-_q2-pad1_ 1k +r6 net-_q5-pad3_ net-_c1-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 20p +q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r1-pad1_ 3.28k +q1 /cathode /ref net-_q1-pad3_ Q2N2222 +q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222 +q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A +r5 /cathode net-_q7-pad3_ 800 +r8 /cathode net-_q8-pad3_ 800 +d1 /anode net-_c2-pad2_ 1N4148 +c2 /cathode net-_c2-pad2_ 20p +q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222 +r9 net-_q10-pad3_ net-_q11-pad2_ 150 +q11 /cathode net-_q11-pad2_ /anode Q2N2222 +r10 /anode net-_q11-pad2_ 10k +d2 /anode /cathode 1N4148 +* u1 /cathode /ref /anode port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub.pro b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sch b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sch new file mode 100644 index 00000000..9c921954 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sch @@ -0,0 +1,519 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tl431_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67E78EB3 +P 3500 5250 +F 0 "Q2" H 3400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 3450 5400 50 0000 R CNN +F 2 "" H 3700 5350 29 0000 C CNN +F 3 "" H 3500 5250 60 0000 C CNN + 1 3500 5250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67E78EB4 +P 4850 5250 +F 0 "Q4" H 4750 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4800 5400 50 0000 R CNN +F 2 "" H 5050 5350 29 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 67E78EB5 +P 7200 5650 +F 0 "Q9" H 7100 5700 50 0000 R CNN +F 1 "eSim_NPN" H 7150 5800 50 0000 R CNN +F 2 "" H 7400 5750 29 0000 C CNN +F 3 "" H 7200 5650 60 0000 C CNN + 1 7200 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 67E78EB6 +P 6000 4900 +F 0 "Q6" H 5900 4950 50 0000 R CNN +F 1 "eSim_NPN" H 5950 5050 50 0000 R CNN +F 2 "" H 6200 5000 29 0000 C CNN +F 3 "" H 6000 4900 60 0000 C CNN + 1 6000 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67E78EB7 +P 3450 4550 +F 0 "R1" H 3500 4680 50 0000 C CNN +F 1 "2.4k" H 3500 4500 50 0000 C CNN +F 2 "" H 3500 4530 30 0000 C CNN +F 3 "" V 3500 4600 30 0000 C CNN + 1 3450 4550 + 0 -1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 67E78EB8 +P 5000 4550 +F 0 "R3" H 5050 4680 50 0000 C CNN +F 1 "7.2k" H 5050 4500 50 0000 C CNN +F 2 "" H 5050 4530 30 0000 C CNN +F 3 "" V 5050 4600 30 0000 C CNN + 1 5000 4550 + 0 -1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67E78EB9 +P 5000 5900 +F 0 "R4" H 5050 6030 50 0000 C CNN +F 1 "800" H 5050 5850 50 0000 C CNN +F 2 "" H 5050 5880 30 0000 C CNN +F 3 "" V 5050 5950 30 0000 C CNN + 1 5000 5900 + 0 -1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 67E78EBA +P 6550 5700 +F 0 "R7" H 6600 5830 50 0000 C CNN +F 1 "1k" H 6600 5650 50 0000 C CNN +F 2 "" H 6600 5680 30 0000 C CNN +F 3 "" V 6600 5750 30 0000 C CNN + 1 6550 5700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3400 4750 3400 5050 +Wire Wire Line + 4950 4750 4950 5050 +Wire Wire Line + 3700 5250 4650 5250 +Wire Wire Line + 4950 5450 4950 5800 +Wire Wire Line + 6650 5650 7000 5650 +Wire Wire Line + 3400 4900 4000 4900 +Wire Wire Line + 4000 4900 4000 5250 +Connection ~ 4000 5250 +Connection ~ 3400 4900 +Wire Wire Line + 4300 5650 4300 5250 +Connection ~ 4300 5250 +Wire Wire Line + 3400 4450 3400 4200 +Wire Wire Line + 3400 4200 4950 4200 +Wire Wire Line + 4950 4200 4950 4450 +Wire Wire Line + 4950 4900 5800 4900 +Connection ~ 4950 4900 +$Comp +L resistor R6 +U 1 1 67E78EBB +P 6150 4300 +F 0 "R6" H 6200 4430 50 0000 C CNN +F 1 "4k" H 6200 4250 50 0000 C CNN +F 2 "" H 6200 4280 30 0000 C CNN +F 3 "" V 6200 4350 30 0000 C CNN + 1 6150 4300 + 0 -1 1 0 +$EndComp +Wire Wire Line + 6100 4500 6100 4700 +$Comp +L capacitor_polarised C1 +U 1 1 67E78EBC +P 5450 4700 +F 0 "C1" H 5475 4800 50 0000 L CNN +F 1 "20p" H 5475 4600 50 0000 L CNN +F 2 "" H 5450 4700 50 0001 C CNN +F 3 "" H 5450 4700 50 0001 C CNN + 1 5450 4700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5450 4550 6100 4550 +Connection ~ 6100 4550 +Wire Wire Line + 5450 4850 5450 4900 +Connection ~ 5450 4900 +$Comp +L eSim_NPN Q5 +U 1 1 67E78EBD +P 6000 3800 +F 0 "Q5" H 5900 3850 50 0000 R CNN +F 1 "eSim_NPN" H 5950 3950 50 0000 R CNN +F 2 "" H 6200 3900 29 0000 C CNN +F 3 "" H 6000 3800 60 0000 C CNN + 1 6000 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 4200 6100 4000 +$Comp +L resistor R2 +U 1 1 67E78EBE +P 4100 3950 +F 0 "R2" H 4150 4080 50 0000 C CNN +F 1 "3.28k" H 4150 3900 50 0000 C CNN +F 2 "" H 4150 3930 30 0000 C CNN +F 3 "" V 4150 4000 30 0000 C CNN + 1 4100 3950 + 0 1 1 0 +$EndComp +Wire Wire Line + 4150 4150 4150 4200 +Connection ~ 4150 4200 +$Comp +L eSim_NPN Q1 +U 1 1 67E78EBF +P 3500 3000 +F 0 "Q1" H 3400 3050 50 0000 R CNN +F 1 "eSim_NPN" H 3450 3150 50 0000 R CNN +F 2 "" H 3700 3100 29 0000 C CNN +F 3 "" H 3500 3000 60 0000 C CNN + 1 3500 3000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67E78EC0 +P 4450 3100 +F 0 "Q3" H 4350 3150 50 0000 R CNN +F 1 "eSim_NPN" H 4400 3250 50 0000 R CNN +F 2 "" H 4650 3200 29 0000 C CNN +F 3 "" H 4450 3100 60 0000 C CNN + 1 4450 3100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 67E78EC1 +P 6200 2650 +F 0 "Q7" H 6100 2700 50 0000 R CNN +F 1 "eSim_PNP" H 6150 2800 50 0000 R CNN +F 2 "" H 6400 2750 29 0000 C CNN +F 3 "" H 6200 2650 60 0000 C CNN + 1 6200 2650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 67E78EC2 +P 7200 2650 +F 0 "Q8" H 7100 2700 50 0000 R CNN +F 1 "eSim_PNP" H 7150 2800 50 0000 R CNN +F 2 "" H 7400 2750 29 0000 C CNN +F 3 "" H 7200 2650 60 0000 C CNN + 1 7200 2650 + 1 0 0 1 +$EndComp +$Comp +L resistor R5 +U 1 1 67E78EC3 +P 6050 2050 +F 0 "R5" H 6100 2180 50 0000 C CNN +F 1 "800" H 6100 2000 50 0000 C CNN +F 2 "" H 6100 2030 30 0000 C CNN +F 3 "" V 6100 2100 30 0000 C CNN + 1 6050 2050 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 67E78EC4 +P 7250 2100 +F 0 "R8" H 7300 2230 50 0000 C CNN +F 1 "800" H 7300 2050 50 0000 C CNN +F 2 "" H 7300 2080 30 0000 C CNN +F 3 "" V 7300 2150 30 0000 C CNN + 1 7250 2100 + 0 1 1 0 +$EndComp +Wire Wire Line + 3600 3200 3600 3800 +Wire Wire Line + 6100 2450 6100 2250 +Wire Wire Line + 7300 2450 7300 2300 +Wire Wire Line + 6100 2850 6100 3600 +Wire Wire Line + 6400 2650 7000 2650 +Wire Wire Line + 6700 2650 6700 2950 +Wire Wire Line + 6700 2950 6100 2950 +Connection ~ 6100 2950 +Connection ~ 6700 2650 +Wire Wire Line + 7300 2850 7300 5450 +Wire Wire Line + 4650 3200 7300 3200 +Connection ~ 7300 3200 +Wire Wire Line + 4450 2900 4450 2600 +Wire Wire Line + 4450 2600 5050 2600 +Wire Wire Line + 5050 2600 5050 3200 +Connection ~ 5050 3200 +$Comp +L eSim_Diode D1 +U 1 1 67E78EC5 +P 7600 4400 +F 0 "D1" H 7600 4500 50 0000 C CNN +F 1 "eSim_Diode" H 7600 4300 50 0000 C CNN +F 2 "" H 7600 4400 60 0000 C CNN +F 3 "" H 7600 4400 60 0000 C CNN + 1 7600 4400 + 0 1 -1 0 +$EndComp +$Comp +L capacitor_polarised C2 +U 1 1 67E78EC6 +P 7700 2500 +F 0 "C2" H 7725 2600 50 0000 L CNN +F 1 "20p" H 7725 2400 50 0000 L CNN +F 2 "" H 7700 2500 50 0001 C CNN +F 3 "" H 7700 2500 50 0001 C CNN + 1 7700 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 67E78EC7 +P 8400 3600 +F 0 "Q10" H 8300 3650 50 0000 R CNN +F 1 "eSim_NPN" H 8350 3750 50 0000 R CNN +F 2 "" H 8600 3700 29 0000 C CNN +F 3 "" H 8400 3600 60 0000 C CNN + 1 8400 3600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 67E78EC8 +P 8850 3850 +F 0 "R9" H 8900 3980 50 0000 C CNN +F 1 "150" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3830 30 0000 C CNN +F 3 "" V 8900 3900 30 0000 C CNN + 1 8850 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 67E78EC9 +P 9600 3800 +F 0 "Q11" H 9500 3850 50 0000 R CNN +F 1 "eSim_NPN" H 9550 3950 50 0000 R CNN +F 2 "" H 9800 3900 29 0000 C CNN +F 3 "" H 9600 3800 60 0000 C CNN + 1 9600 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 67E78ECA +P 9200 4300 +F 0 "R10" H 9250 4430 50 0000 C CNN +F 1 "10k" H 9250 4250 50 0000 C CNN +F 2 "" H 9250 4280 30 0000 C CNN +F 3 "" V 9250 4350 30 0000 C CNN + 1 9200 4300 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 67E78ECB +P 10100 4350 +F 0 "D2" H 10100 4450 50 0000 C CNN +F 1 "eSim_Diode" H 10100 4250 50 0000 C CNN +F 2 "" H 10100 4350 60 0000 C CNN +F 3 "" H 10100 4350 60 0000 C CNN + 1 10100 4350 + 0 1 -1 0 +$EndComp +Wire Wire Line + 7300 3600 8200 3600 +Connection ~ 7300 3600 +Wire Wire Line + 7700 2650 7700 3600 +Connection ~ 7700 3600 +Wire Wire Line + 7600 4250 7600 3600 +Connection ~ 7600 3600 +Wire Wire Line + 6350 5650 4300 5650 +Wire Wire Line + 8500 3800 8750 3800 +Wire Wire Line + 9050 3800 9400 3800 +Wire Wire Line + 9250 4100 9250 3800 +Connection ~ 9250 3800 +Wire Wire Line + 10100 6200 10100 4500 +Wire Wire Line + 2650 6200 10100 6200 +Wire Wire Line + 3400 5450 3400 6200 +Connection ~ 3400 6200 +Wire Wire Line + 4950 6100 4950 6200 +Connection ~ 4950 6200 +Wire Wire Line + 7300 5850 7300 6200 +Connection ~ 7300 6200 +Wire Wire Line + 7600 4550 7600 6200 +Connection ~ 7600 6200 +Wire Wire Line + 9700 4000 9700 6200 +Connection ~ 9700 6200 +Wire Wire Line + 9250 4400 9250 4550 +Wire Wire Line + 9250 4550 9700 4550 +Connection ~ 9700 4550 +Wire Wire Line + 9700 1800 9700 3600 +Wire Wire Line + 2200 1800 10100 1800 +Wire Wire Line + 3600 2800 3600 1800 +Connection ~ 3600 1800 +Wire Wire Line + 6100 1950 6100 1800 +Connection ~ 6100 1800 +Wire Wire Line + 7300 2000 7300 1800 +Connection ~ 7300 1800 +Wire Wire Line + 7700 2350 7700 1800 +Connection ~ 7700 1800 +Wire Wire Line + 8500 3400 8500 1800 +Connection ~ 8500 1800 +Wire Wire Line + 10100 1800 10100 4200 +Connection ~ 9700 1800 +Wire Wire Line + 3600 3800 5800 3800 +Wire Wire Line + 4150 3850 4150 3800 +Connection ~ 4150 3800 +Wire Wire Line + 6100 5100 6100 6200 +Connection ~ 6100 6200 +$Comp +L PORT U1 +U 1 1 67E78ECC +P 1950 1800 +F 0 "U1" H 2000 1900 30 0000 C CNN +F 1 "PORT" H 1950 1800 30 0000 C CNN +F 2 "" H 1950 1800 60 0000 C CNN +F 3 "" H 1950 1800 60 0000 C CNN + 1 1950 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67E78ECD +P 2400 3000 +F 0 "U1" H 2450 3100 30 0000 C CNN +F 1 "PORT" H 2400 3000 30 0000 C CNN +F 2 "" H 2400 3000 60 0000 C CNN +F 3 "" H 2400 3000 60 0000 C CNN + 2 2400 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67E78ECE +P 2400 6200 +F 0 "U1" H 2450 6300 30 0000 C CNN +F 1 "PORT" H 2400 6200 30 0000 C CNN +F 2 "" H 2400 6200 60 0000 C CNN +F 3 "" H 2400 6200 60 0000 C CNN + 3 2400 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 3000 3300 3000 +Wire Wire Line + 4250 3200 2975 3200 +Wire Wire Line + 2975 3200 2975 3000 +Connection ~ 2975 3000 +Text Label 2330 1800 0 60 ~ 0 +Cathode +Text Label 2710 3000 0 60 ~ 0 +Ref +Text Label 2850 6200 0 60 ~ 0 +Anode +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sub b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sub new file mode 100644 index 00000000..f26748b7 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub.sub @@ -0,0 +1,34 @@ +* Subcircuit tl431_sub +.subckt tl431_sub /cathode /ref /anode +* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir +.include PNP.lib +.include NPN.lib +.include D.lib +q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222 +q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222 +q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222 +q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222 +r1 net-_r1-pad1_ net-_q2-pad1_ 2.4k +r3 net-_r1-pad1_ net-_c1-pad2_ 7.2k +r4 net-_q4-pad3_ /anode 800 +r7 net-_q9-pad2_ net-_q2-pad1_ 1k +r6 net-_q5-pad3_ net-_c1-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 20p +q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r1-pad1_ 3.28k +q1 /cathode /ref net-_q1-pad3_ Q2N2222 +q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222 +q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A +r5 /cathode net-_q7-pad3_ 800 +r8 /cathode net-_q8-pad3_ 800 +d1 /anode net-_c2-pad2_ 1N4148 +c2 /cathode net-_c2-pad2_ 20p +q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222 +r9 net-_q10-pad3_ net-_q11-pad2_ 150 +q11 /cathode net-_q11-pad2_ /anode Q2N2222 +r10 /anode net-_q11-pad2_ 10k +d2 /anode /cathode 1N4148 +* Control Statements + +.ends tl431_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL431_SUB/tl431_sub_Previous_Values.xml b/library/SubcircuitLibrary/TL431_SUB/tl431_sub_Previous_Values.xml new file mode 100644 index 00000000..4de18244 --- /dev/null +++ b/library/SubcircuitLibrary/TL431_SUB/tl431_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2004/D.lib b/library/SubcircuitLibrary/ULN2004/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ULN2004/NPN.lib b/library/SubcircuitLibrary/ULN2004/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004-cache.lib b/library/SubcircuitLibrary/ULN2004/ULN2004-cache.lib new file mode 100644 index 00000000..2f85177a --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004-cache.lib @@ -0,0 +1,154 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004.cir b/library/SubcircuitLibrary/ULN2004/ULN2004.cir new file mode 100644 index 00000000..4fd8880f --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004.cir @@ -0,0 +1,20 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ULN2004\ULN2004.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 08:54:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 /COM Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 /COM Net-_Q1-Pad3_ GND eSim_NPN +R3 Net-_Q1-Pad3_ GND 3k +R2 Net-_Q1-Pad2_ Net-_Q1-Pad3_ 7.2k +D2 /COM /COM eSim_Diode +D3 GND /COM eSim_Diode +D1 GND Net-_D1-Pad2_ eSim_Diode +C1 /COM GND 15p +R1 Net-_D1-Pad2_ Net-_Q1-Pad2_ 10.5k +U1 Net-_D1-Pad2_ /COM /COM PORT + +.end diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004.cir.out b/library/SubcircuitLibrary/ULN2004/ULN2004.cir.out new file mode 100644 index 00000000..addfb4e7 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004.cir.out @@ -0,0 +1,23 @@ +* c:\fossee\esim\library\subcircuitlibrary\uln2004\uln2004.cir + +.include D.lib +.include NPN.lib +q1 /com net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 /com net-_q1-pad3_ gnd Q2N2222 +r3 net-_q1-pad3_ gnd 3k +r2 net-_q1-pad2_ net-_q1-pad3_ 7.2k +d2 /com /com 1N4148 +d3 gnd /com 1N4148 +d1 gnd net-_d1-pad2_ 1N4148 +c1 /com gnd 15p +r1 net-_d1-pad2_ net-_q1-pad2_ 10.5k +* u1 net-_d1-pad2_ /com /com port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004.pro b/library/SubcircuitLibrary/ULN2004/ULN2004.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004.sch b/library/SubcircuitLibrary/ULN2004/ULN2004.sch new file mode 100644 index 00000000..8b998325 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004.sch @@ -0,0 +1,291 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +LIBS:ULN2001-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 68314AD8 +P 4600 3725 +F 0 "Q1" H 4500 3775 50 0000 R CNN +F 1 "eSim_NPN" H 4550 3875 50 0000 R CNN +F 2 "" H 4800 3825 29 0000 C CNN +F 3 "" H 4600 3725 60 0000 C CNN + 1 4600 3725 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 68314AD9 +P 5475 4225 +F 0 "Q2" H 5375 4275 50 0000 R CNN +F 1 "eSim_NPN" H 5425 4375 50 0000 R CNN +F 2 "" H 5675 4325 29 0000 C CNN +F 3 "" H 5475 4225 60 0000 C CNN + 1 5475 4225 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 68314ADA +P 4975 4675 +F 0 "R3" H 5025 4805 50 0000 C CNN +F 1 "3k" H 5025 4625 50 0000 C CNN +F 2 "" H 5025 4655 30 0000 C CNN +F 3 "" V 5025 4725 30 0000 C CNN + 1 4975 4675 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 68314ADB +P 4275 4475 +F 0 "R2" H 4325 4605 50 0000 C CNN +F 1 "7.2k" H 4325 4425 50 0000 C CNN +F 2 "" H 4325 4455 30 0000 C CNN +F 3 "" V 4325 4525 30 0000 C CNN + 1 4275 4475 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 68314ADC +P 5800 3275 +F 0 "D2" H 5800 3375 50 0000 C CNN +F 1 "eSim_Diode" H 5800 3175 50 0000 C CNN +F 2 "" H 5800 3275 60 0000 C CNN +F 3 "" H 5800 3275 60 0000 C CNN + 1 5800 3275 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 68314ADD +P 6025 4775 +F 0 "D3" H 6025 4875 50 0000 C CNN +F 1 "eSim_Diode" H 6025 4675 50 0000 C CNN +F 2 "" H 6025 4775 60 0000 C CNN +F 3 "" H 6025 4775 60 0000 C CNN + 1 6025 4775 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 68314ADE +P 4925 5150 +F 0 "D1" H 4925 5250 50 0000 C CNN +F 1 "eSim_Diode" H 4925 5050 50 0000 C CNN +F 2 "" H 4925 5150 60 0000 C CNN +F 3 "" H 4925 5150 60 0000 C CNN + 1 4925 5150 + -1 0 0 1 +$EndComp +Wire Wire Line + 5275 4225 4700 4225 +Wire Wire Line + 4700 3925 4700 4625 +Wire Wire Line + 4700 4625 4875 4625 +Connection ~ 4700 4225 +Wire Wire Line + 4475 4425 4700 4425 +Connection ~ 4700 4425 +Wire Wire Line + 5175 4625 5575 4625 +Wire Wire Line + 5575 4425 5575 5475 +Wire Wire Line + 5575 5150 5075 5150 +Connection ~ 5575 4625 +Wire Wire Line + 5575 5025 6025 5025 +Wire Wire Line + 6025 5025 6025 4925 +Connection ~ 5575 5025 +Wire Wire Line + 4400 3725 3875 3725 +Wire Wire Line + 3875 3725 3875 4425 +Wire Wire Line + 3875 4425 4175 4425 +Wire Wire Line + 1625 4100 3350 4100 +Connection ~ 3875 4100 +Wire Wire Line + 2850 5150 4775 5150 +Wire Wire Line + 5575 3275 5575 4025 +Connection ~ 5575 3525 +Wire Wire Line + 6025 3525 6025 4625 +Connection ~ 6025 3525 +Wire Wire Line + 5575 3275 5650 3275 +Wire Wire Line + 5950 3275 6450 3275 +Connection ~ 5575 5150 +Text Label 5575 5300 0 60 ~ 0 +GND +Text Label 6050 3275 0 60 ~ 0 +COM +Text Label 6550 3525 0 60 ~ 0 +OUT +$Comp +L capacitor_polarised C1 +U 1 1 68314AE2 +P 6450 3825 +F 0 "C1" H 6475 3925 50 0000 L CNN +F 1 "15p" H 6475 3725 50 0000 L CNN +F 2 "" H 6450 3825 50 0001 C CNN +F 3 "" H 6450 3825 50 0001 C CNN + 1 6450 3825 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 3025 6450 3675 +Connection ~ 6450 3525 +$Comp +L eSim_GND #PWR01 +U 1 1 68314AE3 +P 5575 5475 +F 0 "#PWR01" H 5575 5225 50 0001 C CNN +F 1 "eSim_GND" H 5575 5325 50 0000 C CNN +F 2 "" H 5575 5475 50 0001 C CNN +F 3 "" H 5575 5475 50 0001 C CNN + 1 5575 5475 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR02 +U 1 1 68314AE4 +P 6450 4050 +F 0 "#PWR02" H 6450 3800 50 0001 C CNN +F 1 "eSim_GND" H 6450 3900 50 0000 C CNN +F 2 "" H 6450 4050 50 0001 C CNN +F 3 "" H 6450 4050 50 0001 C CNN + 1 6450 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 3975 6450 4050 +Connection ~ 6450 3275 +$Comp +L PWR_FLAG #FLG03 +U 1 1 68314AE8 +P 6225 4000 +F 0 "#FLG03" H 6225 4075 50 0001 C CNN +F 1 "PWR_FLAG" H 6225 4150 50 0000 C CNN +F 2 "" H 6225 4000 50 0001 C CNN +F 3 "" H 6225 4000 50 0001 C CNN + 1 6225 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6225 4000 6225 4025 +Wire Wire Line + 6225 4025 6450 4025 +Connection ~ 6450 4025 +$Comp +L resistor R1 +U 1 1 68314AEA +P 3450 4150 +F 0 "R1" H 3500 4280 50 0000 C CNN +F 1 "10.5k" H 3500 4100 50 0000 C CNN +F 2 "" H 3500 4130 30 0000 C CNN +F 3 "" V 3500 4200 30 0000 C CNN + 1 3450 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 4100 3875 4100 +Wire Wire Line + 2850 5150 2850 4100 +Connection ~ 2850 4100 +Wire Wire Line + 4700 3525 6975 3525 +$Comp +L PORT U1 +U 1 1 68314E03 +P 1375 4100 +F 0 "U1" H 1425 4200 30 0000 C CNN +F 1 "PORT" H 1375 4100 30 0000 C CNN +F 2 "" H 1375 4100 60 0000 C CNN +F 3 "" H 1375 4100 60 0000 C CNN + 1 1375 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68314E9A +P 7225 3525 +F 0 "U1" H 7275 3625 30 0000 C CNN +F 1 "PORT" H 7225 3525 30 0000 C CNN +F 2 "" H 7225 3525 60 0000 C CNN +F 3 "" H 7225 3525 60 0000 C CNN + 3 7225 3525 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68314EFA +P 6450 2775 +F 0 "U1" H 6500 2875 30 0000 C CNN +F 1 "PORT" H 6450 2775 30 0000 C CNN +F 2 "" H 6450 2775 60 0000 C CNN +F 3 "" H 6450 2775 60 0000 C CNN + 2 6450 2775 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004.sub b/library/SubcircuitLibrary/ULN2004/ULN2004.sub new file mode 100644 index 00000000..fdcf7c02 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004.sub @@ -0,0 +1,17 @@ +* Subcircuit ULN2004 +.subckt ULN2004 net-_d1-pad2_ /com /com +* c:\fossee\esim\library\subcircuitlibrary\uln2004\uln2004.cir +.include D.lib +.include NPN.lib +q1 /com net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 /com net-_q1-pad3_ gnd Q2N2222 +r3 net-_q1-pad3_ gnd 3k +r2 net-_q1-pad2_ net-_q1-pad3_ 7.2k +d2 /com /com 1N4148 +d3 gnd /com 1N4148 +d1 gnd net-_d1-pad2_ 1N4148 +c1 /com gnd 15p +r1 net-_d1-pad2_ net-_q1-pad2_ 10.5k +* Control Statements + +.ends ULN2004
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2004/ULN2004_Previous_Values.xml b/library/SubcircuitLibrary/ULN2004/ULN2004_Previous_Values.xml new file mode 100644 index 00000000..5bf54ced --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/ULN2004_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2004/analysis b/library/SubcircuitLibrary/ULN2004/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2004/file68313A5F.sch b/library/SubcircuitLibrary/ULN2004/file68313A5F.sch new file mode 100644 index 00000000..a86c6aac --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A5F.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 2 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A60.sch b/library/SubcircuitLibrary/ULN2004/file68313A60.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A60.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A61.sch b/library/SubcircuitLibrary/ULN2004/file68313A61.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A61.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A62.sch b/library/SubcircuitLibrary/ULN2004/file68313A62.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A62.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A63.sch b/library/SubcircuitLibrary/ULN2004/file68313A63.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A63.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A64.sch b/library/SubcircuitLibrary/ULN2004/file68313A64.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A64.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2004/file68313A65.sch b/library/SubcircuitLibrary/ULN2004/file68313A65.sch new file mode 100644 index 00000000..a84e0032 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2004/file68313A65.sch @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ULN2001_SUB-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 8 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tl431/D.lib b/library/SubcircuitLibrary/tl431/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/tl431/NPN.lib b/library/SubcircuitLibrary/tl431/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/tl431/PNP.lib b/library/SubcircuitLibrary/tl431/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/tl431/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/tl431/PowerDiode.lib b/library/SubcircuitLibrary/tl431/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/library/SubcircuitLibrary/tl431/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tl431/ZenerD1N750.lib b/library/SubcircuitLibrary/tl431/ZenerD1N750.lib new file mode 100644 index 00000000..890c37fe --- /dev/null +++ b/library/SubcircuitLibrary/tl431/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/SubcircuitLibrary/tl431/analysis b/library/SubcircuitLibrary/tl431/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib b/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib new file mode 100644 index 00000000..155677e6 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 P +X ~ 2 250 0 100 L 30 30 2 1 P +X ~ 3 250 0 100 L 30 30 3 1 P +X ~ 4 250 0 100 L 30 30 4 1 P +X ~ 5 250 0 100 L 30 30 5 1 P +X ~ 6 250 0 100 L 30 30 6 1 P +X ~ 7 250 0 100 L 30 30 7 1 P +X ~ 8 250 0 100 L 30 30 8 1 P +X ~ 9 250 0 100 L 30 30 9 1 P +X ~ 10 250 0 100 L 30 30 10 1 P +X ~ 11 250 0 100 L 30 30 11 1 P +X ~ 12 250 0 100 L 30 30 12 1 P +X ~ 13 250 0 100 L 30 30 13 1 P +X ~ 14 250 0 100 L 30 30 14 1 P +X ~ 15 250 0 100 L 30 30 15 1 P +X ~ 16 250 0 100 L 30 30 16 1 P +X ~ 17 250 0 100 L 30 30 17 1 P +X ~ 18 250 0 100 L 30 30 18 1 P +X ~ 19 250 0 100 L 30 30 19 1 P +X ~ 20 250 0 100 L 30 30 20 1 P +X ~ 21 250 0 100 L 30 30 21 1 P +X ~ 22 250 0 100 L 30 30 22 1 P +X ~ 23 250 0 100 L 30 30 23 1 P +X ~ 24 250 0 100 L 30 30 24 1 P +X ~ 25 250 0 100 L 30 30 25 1 P +X ~ 26 250 0 100 L 30 30 26 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.cir b/library/SubcircuitLibrary/tl431/tl431_sub.cir new file mode 100644 index 00000000..d4a3caa4 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tl431_sub\tl431_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/29/25 21:28:50 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad1_ /Anode eSim_NPN +Q4 Net-_C1-Pad2_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN +Q9 Net-_C2-Pad2_ Net-_Q9-Pad2_ /Anode eSim_NPN +Q6 Net-_C1-Pad1_ Net-_C1-Pad2_ /Anode eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q2-Pad1_ 2.4k +R3 Net-_R1-Pad1_ Net-_C1-Pad2_ 7.2k +R4 Net-_Q4-Pad3_ /Anode 800 +R7 Net-_Q9-Pad2_ Net-_Q2-Pad1_ 1k +R6 Net-_Q5-Pad3_ Net-_C1-Pad1_ 4k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 20p +Q5 Net-_Q5-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_R1-Pad1_ 3.28k +Q1 /Cathode /Ref Net-_Q1-Pad3_ eSim_NPN +Q3 Net-_C2-Pad2_ Net-_C2-Pad2_ /Ref eSim_NPN +Q7 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q8 Net-_C2-Pad2_ Net-_Q5-Pad1_ Net-_Q8-Pad3_ eSim_PNP +R5 /Cathode Net-_Q7-Pad3_ 800 +R8 /Cathode Net-_Q8-Pad3_ 800 +D1 /Anode Net-_C2-Pad2_ eSim_Diode +C2 /Cathode Net-_C2-Pad2_ 20p +Q10 /Cathode Net-_C2-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R9 Net-_Q10-Pad3_ Net-_Q11-Pad2_ 150 +Q11 /Cathode Net-_Q11-Pad2_ /Anode eSim_NPN +R10 /Anode Net-_Q11-Pad2_ 10k +D2 /Anode /Cathode eSim_Diode +U1 /Cathode /Ref /Anode PORT + +.end diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.cir.out b/library/SubcircuitLibrary/tl431/tl431_sub.cir.out new file mode 100644 index 00000000..40fed526 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub.cir.out @@ -0,0 +1,40 @@ +* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir + +.include PNP.lib +.include NPN.lib +.include D.lib +q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222 +q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222 +q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222 +q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222 +r1 net-_r1-pad1_ net-_q2-pad1_ 2.4k +r3 net-_r1-pad1_ net-_c1-pad2_ 7.2k +r4 net-_q4-pad3_ /anode 800 +r7 net-_q9-pad2_ net-_q2-pad1_ 1k +r6 net-_q5-pad3_ net-_c1-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 20p +q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r1-pad1_ 3.28k +q1 /cathode /ref net-_q1-pad3_ Q2N2222 +q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222 +q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A +r5 /cathode net-_q7-pad3_ 800 +r8 /cathode net-_q8-pad3_ 800 +d1 /anode net-_c2-pad2_ 1N4148 +c2 /cathode net-_c2-pad2_ 20p +q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222 +r9 net-_q10-pad3_ net-_q11-pad2_ 150 +q11 /cathode net-_q11-pad2_ /anode Q2N2222 +r10 /anode net-_q11-pad2_ 10k +d2 /anode /cathode 1N4148 +* u1 /cathode /ref /anode port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.pro b/library/SubcircuitLibrary/tl431/tl431_sub.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.sch b/library/SubcircuitLibrary/tl431/tl431_sub.sch new file mode 100644 index 00000000..9c921954 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub.sch @@ -0,0 +1,519 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tl431_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67E78EB3 +P 3500 5250 +F 0 "Q2" H 3400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 3450 5400 50 0000 R CNN +F 2 "" H 3700 5350 29 0000 C CNN +F 3 "" H 3500 5250 60 0000 C CNN + 1 3500 5250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67E78EB4 +P 4850 5250 +F 0 "Q4" H 4750 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4800 5400 50 0000 R CNN +F 2 "" H 5050 5350 29 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 67E78EB5 +P 7200 5650 +F 0 "Q9" H 7100 5700 50 0000 R CNN +F 1 "eSim_NPN" H 7150 5800 50 0000 R CNN +F 2 "" H 7400 5750 29 0000 C CNN +F 3 "" H 7200 5650 60 0000 C CNN + 1 7200 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 67E78EB6 +P 6000 4900 +F 0 "Q6" H 5900 4950 50 0000 R CNN +F 1 "eSim_NPN" H 5950 5050 50 0000 R CNN +F 2 "" H 6200 5000 29 0000 C CNN +F 3 "" H 6000 4900 60 0000 C CNN + 1 6000 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67E78EB7 +P 3450 4550 +F 0 "R1" H 3500 4680 50 0000 C CNN +F 1 "2.4k" H 3500 4500 50 0000 C CNN +F 2 "" H 3500 4530 30 0000 C CNN +F 3 "" V 3500 4600 30 0000 C CNN + 1 3450 4550 + 0 -1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 67E78EB8 +P 5000 4550 +F 0 "R3" H 5050 4680 50 0000 C CNN +F 1 "7.2k" H 5050 4500 50 0000 C CNN +F 2 "" H 5050 4530 30 0000 C CNN +F 3 "" V 5050 4600 30 0000 C CNN + 1 5000 4550 + 0 -1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67E78EB9 +P 5000 5900 +F 0 "R4" H 5050 6030 50 0000 C CNN +F 1 "800" H 5050 5850 50 0000 C CNN +F 2 "" H 5050 5880 30 0000 C CNN +F 3 "" V 5050 5950 30 0000 C CNN + 1 5000 5900 + 0 -1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 67E78EBA +P 6550 5700 +F 0 "R7" H 6600 5830 50 0000 C CNN +F 1 "1k" H 6600 5650 50 0000 C CNN +F 2 "" H 6600 5680 30 0000 C CNN +F 3 "" V 6600 5750 30 0000 C CNN + 1 6550 5700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3400 4750 3400 5050 +Wire Wire Line + 4950 4750 4950 5050 +Wire Wire Line + 3700 5250 4650 5250 +Wire Wire Line + 4950 5450 4950 5800 +Wire Wire Line + 6650 5650 7000 5650 +Wire Wire Line + 3400 4900 4000 4900 +Wire Wire Line + 4000 4900 4000 5250 +Connection ~ 4000 5250 +Connection ~ 3400 4900 +Wire Wire Line + 4300 5650 4300 5250 +Connection ~ 4300 5250 +Wire Wire Line + 3400 4450 3400 4200 +Wire Wire Line + 3400 4200 4950 4200 +Wire Wire Line + 4950 4200 4950 4450 +Wire Wire Line + 4950 4900 5800 4900 +Connection ~ 4950 4900 +$Comp +L resistor R6 +U 1 1 67E78EBB +P 6150 4300 +F 0 "R6" H 6200 4430 50 0000 C CNN +F 1 "4k" H 6200 4250 50 0000 C CNN +F 2 "" H 6200 4280 30 0000 C CNN +F 3 "" V 6200 4350 30 0000 C CNN + 1 6150 4300 + 0 -1 1 0 +$EndComp +Wire Wire Line + 6100 4500 6100 4700 +$Comp +L capacitor_polarised C1 +U 1 1 67E78EBC +P 5450 4700 +F 0 "C1" H 5475 4800 50 0000 L CNN +F 1 "20p" H 5475 4600 50 0000 L CNN +F 2 "" H 5450 4700 50 0001 C CNN +F 3 "" H 5450 4700 50 0001 C CNN + 1 5450 4700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5450 4550 6100 4550 +Connection ~ 6100 4550 +Wire Wire Line + 5450 4850 5450 4900 +Connection ~ 5450 4900 +$Comp +L eSim_NPN Q5 +U 1 1 67E78EBD +P 6000 3800 +F 0 "Q5" H 5900 3850 50 0000 R CNN +F 1 "eSim_NPN" H 5950 3950 50 0000 R CNN +F 2 "" H 6200 3900 29 0000 C CNN +F 3 "" H 6000 3800 60 0000 C CNN + 1 6000 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 4200 6100 4000 +$Comp +L resistor R2 +U 1 1 67E78EBE +P 4100 3950 +F 0 "R2" H 4150 4080 50 0000 C CNN +F 1 "3.28k" H 4150 3900 50 0000 C CNN +F 2 "" H 4150 3930 30 0000 C CNN +F 3 "" V 4150 4000 30 0000 C CNN + 1 4100 3950 + 0 1 1 0 +$EndComp +Wire Wire Line + 4150 4150 4150 4200 +Connection ~ 4150 4200 +$Comp +L eSim_NPN Q1 +U 1 1 67E78EBF +P 3500 3000 +F 0 "Q1" H 3400 3050 50 0000 R CNN +F 1 "eSim_NPN" H 3450 3150 50 0000 R CNN +F 2 "" H 3700 3100 29 0000 C CNN +F 3 "" H 3500 3000 60 0000 C CNN + 1 3500 3000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67E78EC0 +P 4450 3100 +F 0 "Q3" H 4350 3150 50 0000 R CNN +F 1 "eSim_NPN" H 4400 3250 50 0000 R CNN +F 2 "" H 4650 3200 29 0000 C CNN +F 3 "" H 4450 3100 60 0000 C CNN + 1 4450 3100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 67E78EC1 +P 6200 2650 +F 0 "Q7" H 6100 2700 50 0000 R CNN +F 1 "eSim_PNP" H 6150 2800 50 0000 R CNN +F 2 "" H 6400 2750 29 0000 C CNN +F 3 "" H 6200 2650 60 0000 C CNN + 1 6200 2650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 67E78EC2 +P 7200 2650 +F 0 "Q8" H 7100 2700 50 0000 R CNN +F 1 "eSim_PNP" H 7150 2800 50 0000 R CNN +F 2 "" H 7400 2750 29 0000 C CNN +F 3 "" H 7200 2650 60 0000 C CNN + 1 7200 2650 + 1 0 0 1 +$EndComp +$Comp +L resistor R5 +U 1 1 67E78EC3 +P 6050 2050 +F 0 "R5" H 6100 2180 50 0000 C CNN +F 1 "800" H 6100 2000 50 0000 C CNN +F 2 "" H 6100 2030 30 0000 C CNN +F 3 "" V 6100 2100 30 0000 C CNN + 1 6050 2050 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 67E78EC4 +P 7250 2100 +F 0 "R8" H 7300 2230 50 0000 C CNN +F 1 "800" H 7300 2050 50 0000 C CNN +F 2 "" H 7300 2080 30 0000 C CNN +F 3 "" V 7300 2150 30 0000 C CNN + 1 7250 2100 + 0 1 1 0 +$EndComp +Wire Wire Line + 3600 3200 3600 3800 +Wire Wire Line + 6100 2450 6100 2250 +Wire Wire Line + 7300 2450 7300 2300 +Wire Wire Line + 6100 2850 6100 3600 +Wire Wire Line + 6400 2650 7000 2650 +Wire Wire Line + 6700 2650 6700 2950 +Wire Wire Line + 6700 2950 6100 2950 +Connection ~ 6100 2950 +Connection ~ 6700 2650 +Wire Wire Line + 7300 2850 7300 5450 +Wire Wire Line + 4650 3200 7300 3200 +Connection ~ 7300 3200 +Wire Wire Line + 4450 2900 4450 2600 +Wire Wire Line + 4450 2600 5050 2600 +Wire Wire Line + 5050 2600 5050 3200 +Connection ~ 5050 3200 +$Comp +L eSim_Diode D1 +U 1 1 67E78EC5 +P 7600 4400 +F 0 "D1" H 7600 4500 50 0000 C CNN +F 1 "eSim_Diode" H 7600 4300 50 0000 C CNN +F 2 "" H 7600 4400 60 0000 C CNN +F 3 "" H 7600 4400 60 0000 C CNN + 1 7600 4400 + 0 1 -1 0 +$EndComp +$Comp +L capacitor_polarised C2 +U 1 1 67E78EC6 +P 7700 2500 +F 0 "C2" H 7725 2600 50 0000 L CNN +F 1 "20p" H 7725 2400 50 0000 L CNN +F 2 "" H 7700 2500 50 0001 C CNN +F 3 "" H 7700 2500 50 0001 C CNN + 1 7700 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 67E78EC7 +P 8400 3600 +F 0 "Q10" H 8300 3650 50 0000 R CNN +F 1 "eSim_NPN" H 8350 3750 50 0000 R CNN +F 2 "" H 8600 3700 29 0000 C CNN +F 3 "" H 8400 3600 60 0000 C CNN + 1 8400 3600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 67E78EC8 +P 8850 3850 +F 0 "R9" H 8900 3980 50 0000 C CNN +F 1 "150" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3830 30 0000 C CNN +F 3 "" V 8900 3900 30 0000 C CNN + 1 8850 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 67E78EC9 +P 9600 3800 +F 0 "Q11" H 9500 3850 50 0000 R CNN +F 1 "eSim_NPN" H 9550 3950 50 0000 R CNN +F 2 "" H 9800 3900 29 0000 C CNN +F 3 "" H 9600 3800 60 0000 C CNN + 1 9600 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 67E78ECA +P 9200 4300 +F 0 "R10" H 9250 4430 50 0000 C CNN +F 1 "10k" H 9250 4250 50 0000 C CNN +F 2 "" H 9250 4280 30 0000 C CNN +F 3 "" V 9250 4350 30 0000 C CNN + 1 9200 4300 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 67E78ECB +P 10100 4350 +F 0 "D2" H 10100 4450 50 0000 C CNN +F 1 "eSim_Diode" H 10100 4250 50 0000 C CNN +F 2 "" H 10100 4350 60 0000 C CNN +F 3 "" H 10100 4350 60 0000 C CNN + 1 10100 4350 + 0 1 -1 0 +$EndComp +Wire Wire Line + 7300 3600 8200 3600 +Connection ~ 7300 3600 +Wire Wire Line + 7700 2650 7700 3600 +Connection ~ 7700 3600 +Wire Wire Line + 7600 4250 7600 3600 +Connection ~ 7600 3600 +Wire Wire Line + 6350 5650 4300 5650 +Wire Wire Line + 8500 3800 8750 3800 +Wire Wire Line + 9050 3800 9400 3800 +Wire Wire Line + 9250 4100 9250 3800 +Connection ~ 9250 3800 +Wire Wire Line + 10100 6200 10100 4500 +Wire Wire Line + 2650 6200 10100 6200 +Wire Wire Line + 3400 5450 3400 6200 +Connection ~ 3400 6200 +Wire Wire Line + 4950 6100 4950 6200 +Connection ~ 4950 6200 +Wire Wire Line + 7300 5850 7300 6200 +Connection ~ 7300 6200 +Wire Wire Line + 7600 4550 7600 6200 +Connection ~ 7600 6200 +Wire Wire Line + 9700 4000 9700 6200 +Connection ~ 9700 6200 +Wire Wire Line + 9250 4400 9250 4550 +Wire Wire Line + 9250 4550 9700 4550 +Connection ~ 9700 4550 +Wire Wire Line + 9700 1800 9700 3600 +Wire Wire Line + 2200 1800 10100 1800 +Wire Wire Line + 3600 2800 3600 1800 +Connection ~ 3600 1800 +Wire Wire Line + 6100 1950 6100 1800 +Connection ~ 6100 1800 +Wire Wire Line + 7300 2000 7300 1800 +Connection ~ 7300 1800 +Wire Wire Line + 7700 2350 7700 1800 +Connection ~ 7700 1800 +Wire Wire Line + 8500 3400 8500 1800 +Connection ~ 8500 1800 +Wire Wire Line + 10100 1800 10100 4200 +Connection ~ 9700 1800 +Wire Wire Line + 3600 3800 5800 3800 +Wire Wire Line + 4150 3850 4150 3800 +Connection ~ 4150 3800 +Wire Wire Line + 6100 5100 6100 6200 +Connection ~ 6100 6200 +$Comp +L PORT U1 +U 1 1 67E78ECC +P 1950 1800 +F 0 "U1" H 2000 1900 30 0000 C CNN +F 1 "PORT" H 1950 1800 30 0000 C CNN +F 2 "" H 1950 1800 60 0000 C CNN +F 3 "" H 1950 1800 60 0000 C CNN + 1 1950 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67E78ECD +P 2400 3000 +F 0 "U1" H 2450 3100 30 0000 C CNN +F 1 "PORT" H 2400 3000 30 0000 C CNN +F 2 "" H 2400 3000 60 0000 C CNN +F 3 "" H 2400 3000 60 0000 C CNN + 2 2400 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67E78ECE +P 2400 6200 +F 0 "U1" H 2450 6300 30 0000 C CNN +F 1 "PORT" H 2400 6200 30 0000 C CNN +F 2 "" H 2400 6200 60 0000 C CNN +F 3 "" H 2400 6200 60 0000 C CNN + 3 2400 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 3000 3300 3000 +Wire Wire Line + 4250 3200 2975 3200 +Wire Wire Line + 2975 3200 2975 3000 +Connection ~ 2975 3000 +Text Label 2330 1800 0 60 ~ 0 +Cathode +Text Label 2710 3000 0 60 ~ 0 +Ref +Text Label 2850 6200 0 60 ~ 0 +Anode +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tl431/tl431_sub.sub b/library/SubcircuitLibrary/tl431/tl431_sub.sub new file mode 100644 index 00000000..f26748b7 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub.sub @@ -0,0 +1,34 @@ +* Subcircuit tl431_sub +.subckt tl431_sub /cathode /ref /anode +* c:\fossee\esim\library\subcircuitlibrary\tl431_sub\tl431_sub.cir +.include PNP.lib +.include NPN.lib +.include D.lib +q2 net-_q2-pad1_ net-_q2-pad1_ /anode Q2N2222 +q4 net-_c1-pad2_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222 +q9 net-_c2-pad2_ net-_q9-pad2_ /anode Q2N2222 +q6 net-_c1-pad1_ net-_c1-pad2_ /anode Q2N2222 +r1 net-_r1-pad1_ net-_q2-pad1_ 2.4k +r3 net-_r1-pad1_ net-_c1-pad2_ 7.2k +r4 net-_q4-pad3_ /anode 800 +r7 net-_q9-pad2_ net-_q2-pad1_ 1k +r6 net-_q5-pad3_ net-_c1-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 20p +q5 net-_q5-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_r1-pad1_ 3.28k +q1 /cathode /ref net-_q1-pad3_ Q2N2222 +q3 net-_c2-pad2_ net-_c2-pad2_ /ref Q2N2222 +q7 net-_q5-pad1_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +q8 net-_c2-pad2_ net-_q5-pad1_ net-_q8-pad3_ Q2N2907A +r5 /cathode net-_q7-pad3_ 800 +r8 /cathode net-_q8-pad3_ 800 +d1 /anode net-_c2-pad2_ 1N4148 +c2 /cathode net-_c2-pad2_ 20p +q10 /cathode net-_c2-pad2_ net-_q10-pad3_ Q2N2222 +r9 net-_q10-pad3_ net-_q11-pad2_ 150 +q11 /cathode net-_q11-pad2_ /anode Q2N2222 +r10 /anode net-_q11-pad2_ 10k +d2 /anode /cathode 1N4148 +* Control Statements + +.ends tl431_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml b/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml new file mode 100644 index 00000000..4de18244 --- /dev/null +++ b/library/SubcircuitLibrary/tl431/tl431_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |