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-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42-cache.lib77
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir39
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out95
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.pro73
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sch730
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sub89
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/SN74LS42_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN74LS42_IC/analysis1
8 files changed, 1105 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42-cache.lib b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42-cache.lib
new file mode 100644
index 00000000..00a4e114
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42-cache.lib
@@ -0,0 +1,77 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir
new file mode 100644
index 00000000..7ab1c588
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir
@@ -0,0 +1,39 @@
+* C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS42\SN74LS42.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/17/25 19:43:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5 Net-_U2-Pad4_ Net-_U5-Pad2_ d_inverter
+U9 Net-_U2-Pad7_ Net-_U10-Pad1_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U13 Net-_U12-Pad2_ Net-_U13-Pad2_ d_inverter
+U16 Net-_U15-Pad2_ Net-_U16-Pad2_ d_inverter
+X3 Net-_U15-Pad2_ Net-_U12-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad2_ Net-_U4-Pad1_ 4_and
+X2 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U15-Pad2_ Net-_U6-Pad2_ Net-_U3-Pad1_ 4_and
+X4 Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U6-Pad2_ Net-_U7-Pad1_ 4_and
+X5 Net-_U15-Pad2_ Net-_U10-Pad1_ Net-_U13-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad1_ 4_and
+X6 Net-_U15-Pad2_ Net-_U10-Pad1_ Net-_U6-Pad2_ Net-_U13-Pad2_ Net-_U11-Pad1_ 4_and
+X7 Net-_U15-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad1_ 4_and
+X8 Net-_U6-Pad2_ Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U17-Pad1_ 4_and
+X9 Net-_U5-Pad2_ Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad1_ 4_and
+X10 Net-_U6-Pad2_ Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad1_ 4_and
+X1 Net-_U5-Pad2_ Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U15-Pad2_ Net-_U1-Pad1_ 4_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U3 Net-_U3-Pad1_ Net-_U2-Pad2_ d_inverter
+U4 Net-_U4-Pad1_ Net-_U2-Pad3_ d_inverter
+U7 Net-_U7-Pad1_ Net-_U2-Pad5_ d_inverter
+U8 Net-_U8-Pad1_ Net-_U2-Pad6_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U11-Pad2_ Net-_U12-Pad1_ Net-_U14-Pad2_ Net-_U15-Pad1_ Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U19-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out
new file mode 100644
index 00000000..65f62a09
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out
@@ -0,0 +1,95 @@
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls42\sn74ls42.cir
+
+.include 4_and.sub
+* u5 net-_u2-pad4_ net-_u5-pad2_ d_inverter
+* u9 net-_u2-pad7_ net-_u10-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u13 net-_u12-pad2_ net-_u13-pad2_ d_inverter
+* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter
+x3 net-_u15-pad2_ net-_u12-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u4-pad1_ 4_and
+x2 net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u6-pad2_ net-_u3-pad1_ 4_and
+x4 net-_u15-pad2_ net-_u10-pad2_ net-_u12-pad2_ net-_u6-pad2_ net-_u7-pad1_ 4_and
+x5 net-_u15-pad2_ net-_u10-pad1_ net-_u13-pad2_ net-_u5-pad2_ net-_u8-pad1_ 4_and
+x6 net-_u15-pad2_ net-_u10-pad1_ net-_u6-pad2_ net-_u13-pad2_ net-_u11-pad1_ 4_and
+x7 net-_u15-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u14-pad1_ 4_and
+x8 net-_u6-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad1_ 4_and
+x9 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u18-pad1_ 4_and
+x10 net-_u6-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u19-pad1_ 4_and
+x1 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u1-pad1_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u2-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u2-pad3_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad5_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad6_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u11-pad2_ net-_u12-pad1_ net-_u14-pad2_ net-_u15-pad1_ net-_u17-pad2_ net-_u18-pad2_ net-_u19-pad2_ port
+a1 net-_u2-pad4_ net-_u5-pad2_ u5
+a2 net-_u2-pad7_ net-_u10-pad1_ u9
+a3 net-_u12-pad1_ net-_u12-pad2_ u12
+a4 net-_u15-pad1_ net-_u15-pad2_ u15
+a5 net-_u5-pad2_ net-_u6-pad2_ u6
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u12-pad2_ net-_u13-pad2_ u13
+a8 net-_u15-pad2_ net-_u16-pad2_ u16
+a9 net-_u1-pad1_ net-_u1-pad2_ u1
+a10 net-_u3-pad1_ net-_u2-pad2_ u3
+a11 net-_u4-pad1_ net-_u2-pad3_ u4
+a12 net-_u7-pad1_ net-_u2-pad5_ u7
+a13 net-_u8-pad1_ net-_u2-pad6_ u8
+a14 net-_u11-pad1_ net-_u11-pad2_ u11
+a15 net-_u14-pad1_ net-_u14-pad2_ u14
+a16 net-_u17-pad1_ net-_u17-pad2_ u17
+a17 net-_u18-pad1_ net-_u18-pad2_ u18
+a18 net-_u19-pad1_ net-_u19-pad2_ u19
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.pro b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sch b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sch
new file mode 100644
index 00000000..d8798ef8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sch
@@ -0,0 +1,730 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U5
+U 1 1 68288E17
+P 3150 1700
+F 0 "U5" H 3150 1600 60 0000 C CNN
+F 1 "d_inverter" H 3150 1850 60 0000 C CNN
+F 2 "" H 3200 1650 60 0000 C CNN
+F 3 "" H 3200 1650 60 0000 C CNN
+ 1 3150 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 68288E59
+P 5200 1700
+F 0 "U9" H 5200 1600 60 0000 C CNN
+F 1 "d_inverter" H 5200 1850 60 0000 C CNN
+F 2 "" H 5250 1650 60 0000 C CNN
+F 3 "" H 5250 1650 60 0000 C CNN
+ 1 5200 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 68288E80
+P 6900 1700
+F 0 "U12" H 6900 1600 60 0000 C CNN
+F 1 "d_inverter" H 6900 1850 60 0000 C CNN
+F 2 "" H 6950 1650 60 0000 C CNN
+F 3 "" H 6950 1650 60 0000 C CNN
+ 1 6900 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 68288EA9
+P 8500 1700
+F 0 "U15" H 8500 1600 60 0000 C CNN
+F 1 "d_inverter" H 8500 1850 60 0000 C CNN
+F 2 "" H 8550 1650 60 0000 C CNN
+F 3 "" H 8550 1650 60 0000 C CNN
+ 1 8500 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68289170
+P 3150 2700
+F 0 "U6" H 3150 2600 60 0000 C CNN
+F 1 "d_inverter" H 3150 2850 60 0000 C CNN
+F 2 "" H 3200 2650 60 0000 C CNN
+F 3 "" H 3200 2650 60 0000 C CNN
+ 1 3150 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 68289177
+P 5200 2700
+F 0 "U10" H 5200 2600 60 0000 C CNN
+F 1 "d_inverter" H 5200 2850 60 0000 C CNN
+F 2 "" H 5250 2650 60 0000 C CNN
+F 3 "" H 5250 2650 60 0000 C CNN
+ 1 5200 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 6828917E
+P 6900 2700
+F 0 "U13" H 6900 2600 60 0000 C CNN
+F 1 "d_inverter" H 6900 2850 60 0000 C CNN
+F 2 "" H 6950 2650 60 0000 C CNN
+F 3 "" H 6950 2650 60 0000 C CNN
+ 1 6900 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 68289185
+P 8500 2700
+F 0 "U16" H 8500 2600 60 0000 C CNN
+F 1 "d_inverter" H 8500 2850 60 0000 C CNN
+F 2 "" H 8550 2650 60 0000 C CNN
+F 3 "" H 8550 2650 60 0000 C CNN
+ 1 8500 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X3
+U 1 1 682892B6
+P 2950 4950
+F 0 "X3" H 3000 4900 60 0000 C CNN
+F 1 "4_and" H 3050 5050 60 0000 C CNN
+F 2 "" H 2950 4950 60 0000 C CNN
+F 3 "" H 2950 4950 60 0000 C CNN
+ 1 2950 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 6828933C
+P 1800 4950
+F 0 "X2" H 1850 4900 60 0000 C CNN
+F 1 "4_and" H 1900 5050 60 0000 C CNN
+F 2 "" H 1800 4950 60 0000 C CNN
+F 3 "" H 1800 4950 60 0000 C CNN
+ 1 1800 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X4
+U 1 1 682893A1
+P 4000 4950
+F 0 "X4" H 4050 4900 60 0000 C CNN
+F 1 "4_and" H 4100 5050 60 0000 C CNN
+F 2 "" H 4000 4950 60 0000 C CNN
+F 3 "" H 4000 4950 60 0000 C CNN
+ 1 4000 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X5
+U 1 1 682893EE
+P 5050 4950
+F 0 "X5" H 5100 4900 60 0000 C CNN
+F 1 "4_and" H 5150 5050 60 0000 C CNN
+F 2 "" H 5050 4950 60 0000 C CNN
+F 3 "" H 5050 4950 60 0000 C CNN
+ 1 5050 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X6
+U 1 1 68289441
+P 6100 4950
+F 0 "X6" H 6150 4900 60 0000 C CNN
+F 1 "4_and" H 6200 5050 60 0000 C CNN
+F 2 "" H 6100 4950 60 0000 C CNN
+F 3 "" H 6100 4950 60 0000 C CNN
+ 1 6100 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 682894C6
+P 7150 4950
+F 0 "X7" H 7200 4900 60 0000 C CNN
+F 1 "4_and" H 7250 5050 60 0000 C CNN
+F 2 "" H 7150 4950 60 0000 C CNN
+F 3 "" H 7150 4950 60 0000 C CNN
+ 1 7150 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X8
+U 1 1 68289562
+P 9050 4950
+F 0 "X8" H 9100 4900 60 0000 C CNN
+F 1 "4_and" H 9150 5050 60 0000 C CNN
+F 2 "" H 9050 4950 60 0000 C CNN
+F 3 "" H 9050 4950 60 0000 C CNN
+ 1 9050 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X9
+U 1 1 682895DB
+P 10050 4950
+F 0 "X9" H 10100 4900 60 0000 C CNN
+F 1 "4_and" H 10150 5050 60 0000 C CNN
+F 2 "" H 10050 4950 60 0000 C CNN
+F 3 "" H 10050 4950 60 0000 C CNN
+ 1 10050 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X10
+U 1 1 6828963C
+P 10950 4950
+F 0 "X10" H 11000 4900 60 0000 C CNN
+F 1 "4_and" H 11050 5050 60 0000 C CNN
+F 2 "" H 10950 4950 60 0000 C CNN
+F 3 "" H 10950 4950 60 0000 C CNN
+ 1 10950 4950
+ 0 1 1 0
+$EndComp
+$Comp
+L 4_and X1
+U 1 1 682896A7
+P 800 4950
+F 0 "X1" H 850 4900 60 0000 C CNN
+F 1 "4_and" H 900 5050 60 0000 C CNN
+F 2 "" H 800 4950 60 0000 C CNN
+F 3 "" H 800 4950 60 0000 C CNN
+ 1 800 4950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 3150 2000 3150 2400
+Wire Wire Line
+ 5200 2000 5200 2400
+Wire Wire Line
+ 6900 2400 6900 2000
+Wire Wire Line
+ 8500 2000 8500 2400
+Wire Wire Line
+ 3150 2100 950 2100
+Wire Wire Line
+ 950 2100 950 4550
+Connection ~ 3150 2100
+Wire Wire Line
+ 950 3450 10200 3450
+Wire Wire Line
+ 10200 3450 10200 4550
+Connection ~ 950 3450
+Wire Wire Line
+ 2900 4550 2900 3450
+Connection ~ 2900 3450
+Wire Wire Line
+ 4900 4550 4900 3450
+Connection ~ 4900 3450
+Wire Wire Line
+ 7200 4550 7200 3450
+Connection ~ 7200 3450
+Wire Wire Line
+ 3150 3000 3150 3200
+Wire Wire Line
+ 1650 3200 11100 3200
+Wire Wire Line
+ 1650 3200 1650 4550
+Wire Wire Line
+ 11100 3200 11100 4550
+Connection ~ 3150 3200
+Wire Wire Line
+ 3850 4550 3850 3200
+Connection ~ 3850 3200
+Wire Wire Line
+ 6050 4550 6050 3200
+Connection ~ 6050 3200
+Wire Wire Line
+ 9200 4550 9200 3200
+Connection ~ 9200 3200
+Wire Wire Line
+ 5200 3000 5200 3600
+Wire Wire Line
+ 2800 3600 9100 3600
+Wire Wire Line
+ 2800 3600 2800 4550
+Wire Wire Line
+ 9100 3600 9100 4550
+Connection ~ 5200 3600
+Wire Wire Line
+ 4050 4550 4050 3600
+Connection ~ 4050 3600
+Wire Wire Line
+ 7100 4550 7100 3600
+Connection ~ 7100 3600
+Wire Wire Line
+ 5200 2100 4400 2100
+Wire Wire Line
+ 4400 2100 4400 3800
+Wire Wire Line
+ 850 3800 11000 3800
+Wire Wire Line
+ 850 3800 850 4550
+Connection ~ 5200 2100
+Wire Wire Line
+ 11000 3800 11000 4550
+Connection ~ 4400 3800
+Wire Wire Line
+ 1950 4550 1950 3800
+Connection ~ 1950 3800
+Wire Wire Line
+ 5100 4550 5100 3800
+Connection ~ 5100 3800
+Wire Wire Line
+ 6150 4550 6150 3800
+Connection ~ 6150 3800
+Wire Wire Line
+ 10100 4550 10100 3800
+Connection ~ 10100 3800
+Wire Wire Line
+ 6900 3000 6900 3950
+Wire Wire Line
+ 5000 3950 9000 3950
+Wire Wire Line
+ 5000 3950 5000 4550
+Wire Wire Line
+ 9000 3950 9000 4550
+Connection ~ 6900 3950
+Wire Wire Line
+ 5950 4550 5950 3950
+Connection ~ 5950 3950
+Wire Wire Line
+ 7000 4550 7000 3950
+Connection ~ 7000 3950
+Wire Wire Line
+ 6900 2100 6600 2100
+Wire Wire Line
+ 6600 2100 6600 4000
+Wire Wire Line
+ 750 4000 10900 4000
+Wire Wire Line
+ 750 4000 750 4550
+Connection ~ 6900 2100
+Wire Wire Line
+ 10900 4000 10900 4550
+Connection ~ 6600 4000
+Wire Wire Line
+ 1850 4550 1850 4000
+Connection ~ 1850 4000
+Wire Wire Line
+ 3000 4550 3000 4000
+Connection ~ 3000 4000
+Wire Wire Line
+ 3950 4550 3950 4000
+Connection ~ 3950 4000
+Wire Wire Line
+ 10000 4550 10000 4000
+Connection ~ 10000 4000
+Wire Wire Line
+ 8500 3000 8500 4150
+Wire Wire Line
+ 8500 4150 10800 4150
+Wire Wire Line
+ 10800 4150 10800 4550
+Wire Wire Line
+ 9900 4550 9900 4150
+Connection ~ 9900 4150
+Wire Wire Line
+ 8500 2100 8150 2100
+Wire Wire Line
+ 8150 2100 8150 4350
+Wire Wire Line
+ 650 4350 8900 4350
+Wire Wire Line
+ 8900 4350 8900 4550
+Connection ~ 8500 2100
+Wire Wire Line
+ 650 4350 650 4550
+Connection ~ 8150 4350
+Wire Wire Line
+ 1750 4550 1750 4350
+Connection ~ 1750 4350
+Wire Wire Line
+ 3100 4550 3100 4350
+Connection ~ 3100 4350
+Wire Wire Line
+ 4150 4550 4150 4350
+Connection ~ 4150 4350
+Wire Wire Line
+ 5200 4550 5200 4350
+Connection ~ 5200 4350
+Wire Wire Line
+ 6250 4550 6250 4350
+Connection ~ 6250 4350
+Wire Wire Line
+ 7300 4550 7300 4350
+Connection ~ 7300 4350
+Wire Wire Line
+ 800 5450 800 5700
+Wire Wire Line
+ 1800 5450 1800 5650
+Wire Wire Line
+ 2950 5450 2950 5650
+Wire Wire Line
+ 4000 5450 4000 5650
+Wire Wire Line
+ 5050 5450 5050 5650
+Wire Wire Line
+ 6100 5450 6100 5650
+Wire Wire Line
+ 7150 5450 7150 5650
+Wire Wire Line
+ 9050 5450 9050 5600
+Wire Wire Line
+ 10050 5450 10050 5600
+Wire Wire Line
+ 10950 5450 10950 5600
+$Comp
+L d_inverter U1
+U 1 1 6828BD0C
+P 850 6000
+F 0 "U1" H 850 5900 60 0000 C CNN
+F 1 "d_inverter" H 850 6150 60 0000 C CNN
+F 2 "" H 900 5950 60 0000 C CNN
+F 3 "" H 900 5950 60 0000 C CNN
+ 1 850 6000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 6828BD97
+P 1800 5950
+F 0 "U3" H 1800 5850 60 0000 C CNN
+F 1 "d_inverter" H 1800 6100 60 0000 C CNN
+F 2 "" H 1850 5900 60 0000 C CNN
+F 3 "" H 1850 5900 60 0000 C CNN
+ 1 1800 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 6828BDEA
+P 2950 5950
+F 0 "U4" H 2950 5850 60 0000 C CNN
+F 1 "d_inverter" H 2950 6100 60 0000 C CNN
+F 2 "" H 3000 5900 60 0000 C CNN
+F 3 "" H 3000 5900 60 0000 C CNN
+ 1 2950 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 6828BE43
+P 4000 5950
+F 0 "U7" H 4000 5850 60 0000 C CNN
+F 1 "d_inverter" H 4000 6100 60 0000 C CNN
+F 2 "" H 4050 5900 60 0000 C CNN
+F 3 "" H 4050 5900 60 0000 C CNN
+ 1 4000 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6828BE94
+P 5050 5950
+F 0 "U8" H 5050 5850 60 0000 C CNN
+F 1 "d_inverter" H 5050 6100 60 0000 C CNN
+F 2 "" H 5100 5900 60 0000 C CNN
+F 3 "" H 5100 5900 60 0000 C CNN
+ 1 5050 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 6828BEED
+P 6100 5950
+F 0 "U11" H 6100 5850 60 0000 C CNN
+F 1 "d_inverter" H 6100 6100 60 0000 C CNN
+F 2 "" H 6150 5900 60 0000 C CNN
+F 3 "" H 6150 5900 60 0000 C CNN
+ 1 6100 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 6828BFDA
+P 7150 5950
+F 0 "U14" H 7150 5850 60 0000 C CNN
+F 1 "d_inverter" H 7150 6100 60 0000 C CNN
+F 2 "" H 7200 5900 60 0000 C CNN
+F 3 "" H 7200 5900 60 0000 C CNN
+ 1 7150 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U17
+U 1 1 6828C15F
+P 9050 5900
+F 0 "U17" H 9050 5800 60 0000 C CNN
+F 1 "d_inverter" H 9050 6050 60 0000 C CNN
+F 2 "" H 9100 5850 60 0000 C CNN
+F 3 "" H 9100 5850 60 0000 C CNN
+ 1 9050 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 6828C1C4
+P 10050 5900
+F 0 "U18" H 10050 5800 60 0000 C CNN
+F 1 "d_inverter" H 10050 6050 60 0000 C CNN
+F 2 "" H 10100 5850 60 0000 C CNN
+F 3 "" H 10100 5850 60 0000 C CNN
+ 1 10050 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 6828C25F
+P 10950 5900
+F 0 "U19" H 10950 5800 60 0000 C CNN
+F 1 "d_inverter" H 10950 6050 60 0000 C CNN
+F 2 "" H 11000 5850 60 0000 C CNN
+F 3 "" H 11000 5850 60 0000 C CNN
+ 1 10950 5900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 3150 1400 3150 1200
+Wire Wire Line
+ 5200 1400 5200 1150
+Wire Wire Line
+ 6900 1400 6900 1150
+Wire Wire Line
+ 8500 1400 8500 1150
+Wire Wire Line
+ 850 6300 850 6550
+Wire Wire Line
+ 1800 6250 1800 6500
+Wire Wire Line
+ 2950 6250 2950 6450
+Wire Wire Line
+ 4000 6250 4000 6450
+Wire Wire Line
+ 5050 6250 5050 6400
+Wire Wire Line
+ 6100 6250 6100 6350
+Wire Wire Line
+ 7150 6250 7150 6350
+Wire Wire Line
+ 9050 6200 9050 6300
+Wire Wire Line
+ 10050 6200 10050 6300
+Wire Wire Line
+ 10950 6200 10950 6300
+$Comp
+L PORT U2
+U 4 1 6828D65F
+P 3150 950
+F 0 "U2" H 3200 1050 30 0000 C CNN
+F 1 "PORT" H 3150 950 30 0000 C CNN
+F 2 "" H 3150 950 60 0000 C CNN
+F 3 "" H 3150 950 60 0000 C CNN
+ 4 3150 950
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U2
+U 7 1 6828D706
+P 5200 900
+F 0 "U2" H 5250 1000 30 0000 C CNN
+F 1 "PORT" H 5200 900 30 0000 C CNN
+F 2 "" H 5200 900 60 0000 C CNN
+F 3 "" H 5200 900 60 0000 C CNN
+ 7 5200 900
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U2
+U 9 1 6828D8E5
+P 6900 900
+F 0 "U2" H 6950 1000 30 0000 C CNN
+F 1 "PORT" H 6900 900 30 0000 C CNN
+F 2 "" H 6900 900 60 0000 C CNN
+F 3 "" H 6900 900 60 0000 C CNN
+ 9 6900 900
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U2
+U 11 1 6828D952
+P 8500 900
+F 0 "U2" H 8550 1000 30 0000 C CNN
+F 1 "PORT" H 8500 900 30 0000 C CNN
+F 2 "" H 8500 900 60 0000 C CNN
+F 3 "" H 8500 900 60 0000 C CNN
+ 11 8500 900
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U2
+U 1 1 6828DAF1
+P 850 6800
+F 0 "U2" H 900 6900 30 0000 C CNN
+F 1 "PORT" H 850 6800 30 0000 C CNN
+F 2 "" H 850 6800 60 0000 C CNN
+F 3 "" H 850 6800 60 0000 C CNN
+ 1 850 6800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 2 1 6828DBB8
+P 1800 6750
+F 0 "U2" H 1850 6850 30 0000 C CNN
+F 1 "PORT" H 1800 6750 30 0000 C CNN
+F 2 "" H 1800 6750 60 0000 C CNN
+F 3 "" H 1800 6750 60 0000 C CNN
+ 2 1800 6750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 3 1 6828DCFF
+P 2950 6700
+F 0 "U2" H 3000 6800 30 0000 C CNN
+F 1 "PORT" H 2950 6700 30 0000 C CNN
+F 2 "" H 2950 6700 60 0000 C CNN
+F 3 "" H 2950 6700 60 0000 C CNN
+ 3 2950 6700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 5 1 6828DD7C
+P 4000 6700
+F 0 "U2" H 4050 6800 30 0000 C CNN
+F 1 "PORT" H 4000 6700 30 0000 C CNN
+F 2 "" H 4000 6700 60 0000 C CNN
+F 3 "" H 4000 6700 60 0000 C CNN
+ 5 4000 6700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 6828DEC7
+P 5050 6650
+F 0 "U2" H 5100 6750 30 0000 C CNN
+F 1 "PORT" H 5050 6650 30 0000 C CNN
+F 2 "" H 5050 6650 60 0000 C CNN
+F 3 "" H 5050 6650 60 0000 C CNN
+ 6 5050 6650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 8 1 6828E043
+P 6100 6600
+F 0 "U2" H 6150 6700 30 0000 C CNN
+F 1 "PORT" H 6100 6600 30 0000 C CNN
+F 2 "" H 6100 6600 60 0000 C CNN
+F 3 "" H 6100 6600 60 0000 C CNN
+ 8 6100 6600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 10 1 6828E15A
+P 7150 6600
+F 0 "U2" H 7200 6700 30 0000 C CNN
+F 1 "PORT" H 7150 6600 30 0000 C CNN
+F 2 "" H 7150 6600 60 0000 C CNN
+F 3 "" H 7150 6600 60 0000 C CNN
+ 10 7150 6600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 12 1 6828E377
+P 9050 6550
+F 0 "U2" H 9100 6650 30 0000 C CNN
+F 1 "PORT" H 9050 6550 30 0000 C CNN
+F 2 "" H 9050 6550 60 0000 C CNN
+F 3 "" H 9050 6550 60 0000 C CNN
+ 12 9050 6550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 13 1 6828E4D4
+P 10050 6550
+F 0 "U2" H 10100 6650 30 0000 C CNN
+F 1 "PORT" H 10050 6550 30 0000 C CNN
+F 2 "" H 10050 6550 60 0000 C CNN
+F 3 "" H 10050 6550 60 0000 C CNN
+ 13 10050 6550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 14 1 6828E5A1
+P 10950 6550
+F 0 "U2" H 11000 6650 30 0000 C CNN
+F 1 "PORT" H 10950 6550 30 0000 C CNN
+F 2 "" H 10950 6550 60 0000 C CNN
+F 3 "" H 10950 6550 60 0000 C CNN
+ 14 10950 6550
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 800 5700 850 5700
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sub b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sub
new file mode 100644
index 00000000..7704c278
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.sub
@@ -0,0 +1,89 @@
+* Subcircuit SN74LS42
+.subckt SN74LS42 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u11-pad2_ net-_u12-pad1_ net-_u14-pad2_ net-_u15-pad1_ net-_u17-pad2_ net-_u18-pad2_ net-_u19-pad2_
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls42\sn74ls42.cir
+.include 4_and.sub
+* u5 net-_u2-pad4_ net-_u5-pad2_ d_inverter
+* u9 net-_u2-pad7_ net-_u10-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u13 net-_u12-pad2_ net-_u13-pad2_ d_inverter
+* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter
+x3 net-_u15-pad2_ net-_u12-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u4-pad1_ 4_and
+x2 net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u6-pad2_ net-_u3-pad1_ 4_and
+x4 net-_u15-pad2_ net-_u10-pad2_ net-_u12-pad2_ net-_u6-pad2_ net-_u7-pad1_ 4_and
+x5 net-_u15-pad2_ net-_u10-pad1_ net-_u13-pad2_ net-_u5-pad2_ net-_u8-pad1_ 4_and
+x6 net-_u15-pad2_ net-_u10-pad1_ net-_u6-pad2_ net-_u13-pad2_ net-_u11-pad1_ 4_and
+x7 net-_u15-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u14-pad1_ 4_and
+x8 net-_u6-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad1_ 4_and
+x9 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u18-pad1_ 4_and
+x10 net-_u6-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u19-pad1_ 4_and
+x1 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u1-pad1_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u2-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u2-pad3_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad5_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad6_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+a1 net-_u2-pad4_ net-_u5-pad2_ u5
+a2 net-_u2-pad7_ net-_u10-pad1_ u9
+a3 net-_u12-pad1_ net-_u12-pad2_ u12
+a4 net-_u15-pad1_ net-_u15-pad2_ u15
+a5 net-_u5-pad2_ net-_u6-pad2_ u6
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u12-pad2_ net-_u13-pad2_ u13
+a8 net-_u15-pad2_ net-_u16-pad2_ u16
+a9 net-_u1-pad1_ net-_u1-pad2_ u1
+a10 net-_u3-pad1_ net-_u2-pad2_ u3
+a11 net-_u4-pad1_ net-_u2-pad3_ u4
+a12 net-_u7-pad1_ net-_u2-pad5_ u7
+a13 net-_u8-pad1_ net-_u2-pad6_ u8
+a14 net-_u11-pad1_ net-_u11-pad2_ u11
+a15 net-_u14-pad1_ net-_u14-pad2_ u14
+a16 net-_u17-pad1_ net-_u17-pad2_ u17
+a17 net-_u18-pad1_ net-_u18-pad2_ u18
+a18 net-_u19-pad1_ net-_u19-pad2_ u19
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74LS42 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42_Previous_Values.xml
new file mode 100644
index 00000000..c72368e3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u9><u12 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u10><u13 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u13><u16 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u16><u1 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u1><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u8><u11 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u11><u14 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19></model><devicemodel /><subcircuit><x3><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x2><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x4><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x10><x1><field>C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/analysis b/library/SubcircuitLibrary/SN74LS42_IC/analysis
new file mode 100644
index 00000000..2aa74f3d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS42_IC/analysis
@@ -0,0 +1 @@
+.tran 0.001e-00 16e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-06-30 12:18:19 +0000