diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out new file mode 100644 index 00000000..65f62a09 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS42_IC/SN74LS42.cir.out @@ -0,0 +1,95 @@ +* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls42\sn74ls42.cir + +.include 4_and.sub +* u5 net-_u2-pad4_ net-_u5-pad2_ d_inverter +* u9 net-_u2-pad7_ net-_u10-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u13 net-_u12-pad2_ net-_u13-pad2_ d_inverter +* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter +x3 net-_u15-pad2_ net-_u12-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u4-pad1_ 4_and +x2 net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u6-pad2_ net-_u3-pad1_ 4_and +x4 net-_u15-pad2_ net-_u10-pad2_ net-_u12-pad2_ net-_u6-pad2_ net-_u7-pad1_ 4_and +x5 net-_u15-pad2_ net-_u10-pad1_ net-_u13-pad2_ net-_u5-pad2_ net-_u8-pad1_ 4_and +x6 net-_u15-pad2_ net-_u10-pad1_ net-_u6-pad2_ net-_u13-pad2_ net-_u11-pad1_ 4_and +x7 net-_u15-pad2_ net-_u5-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u14-pad1_ 4_and +x8 net-_u6-pad2_ net-_u10-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad1_ 4_and +x9 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u18-pad1_ 4_and +x10 net-_u6-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad2_ net-_u19-pad1_ 4_and +x1 net-_u5-pad2_ net-_u10-pad1_ net-_u12-pad2_ net-_u15-pad2_ net-_u1-pad1_ 4_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u3 net-_u3-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u4-pad1_ net-_u2-pad3_ d_inverter +* u7 net-_u7-pad1_ net-_u2-pad5_ d_inverter +* u8 net-_u8-pad1_ net-_u2-pad6_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u11-pad2_ net-_u12-pad1_ net-_u14-pad2_ net-_u15-pad1_ net-_u17-pad2_ net-_u18-pad2_ net-_u19-pad2_ port +a1 net-_u2-pad4_ net-_u5-pad2_ u5 +a2 net-_u2-pad7_ net-_u10-pad1_ u9 +a3 net-_u12-pad1_ net-_u12-pad2_ u12 +a4 net-_u15-pad1_ net-_u15-pad2_ u15 +a5 net-_u5-pad2_ net-_u6-pad2_ u6 +a6 net-_u10-pad1_ net-_u10-pad2_ u10 +a7 net-_u12-pad2_ net-_u13-pad2_ u13 +a8 net-_u15-pad2_ net-_u16-pad2_ u16 +a9 net-_u1-pad1_ net-_u1-pad2_ u1 +a10 net-_u3-pad1_ net-_u2-pad2_ u3 +a11 net-_u4-pad1_ net-_u2-pad3_ u4 +a12 net-_u7-pad1_ net-_u2-pad5_ u7 +a13 net-_u8-pad1_ net-_u2-pad6_ u8 +a14 net-_u11-pad1_ net-_u11-pad2_ u11 +a15 net-_u14-pad1_ net-_u14-pad2_ u14 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u18-pad1_ net-_u18-pad2_ u18 +a18 net-_u19-pad1_ net-_u19-pad2_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |