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-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688-cache.lib132
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688.cir25
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688.cir.out61
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688.pro83
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688.sch514
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688.sub55
-rw-r--r--library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN74HC688/analysis1
8 files changed, 872 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74HC688/74688-cache.lib b/library/SubcircuitLibrary/SN74HC688/74688-cache.lib
new file mode 100644
index 00000000..a488b30b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688-cache.lib
@@ -0,0 +1,132 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC688/74688.cir b/library/SubcircuitLibrary/SN74HC688/74688.cir
new file mode 100644
index 00000000..6e028afb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688.cir
@@ -0,0 +1,25 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74688\74688.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/21/25 17:00:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_xnor
+U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U4-Pad3_ d_xnor
+U5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U5-Pad3_ d_xnor
+U6 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U6-Pad3_ d_xnor
+U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U7-Pad3_ d_xnor
+U8 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U8-Pad3_ d_xnor
+U9 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U11-Pad1_ d_xnor
+U10 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U10-Pad3_ d_xnor
+X1 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_X1-Pad4_ 3_and
+X2 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_X2-Pad4_ 3_and
+U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U11-Pad3_ d_and
+X3 Net-_U2-Pad2_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U11-Pad3_ Net-_U12-Pad1_ 4_and
+U12 Net-_U12-Pad1_ Net-_U1-Pad18_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC688/74688.cir.out b/library/SubcircuitLibrary/SN74HC688/74688.cir.out
new file mode 100644
index 00000000..c4cde047
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688.cir.out
@@ -0,0 +1,61 @@
+* c:\fossee\esim\library\subcircuitlibrary\74688\74688.cir
+
+.include 3_and.sub
+.include 4_and.sub
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_xnor
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u4-pad3_ d_xnor
+* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u5-pad3_ d_xnor
+* u6 net-_u1-pad8_ net-_u1-pad9_ net-_u6-pad3_ d_xnor
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u7-pad3_ d_xnor
+* u8 net-_u1-pad12_ net-_u1-pad13_ net-_u8-pad3_ d_xnor
+* u9 net-_u1-pad14_ net-_u1-pad15_ net-_u11-pad1_ d_xnor
+* u10 net-_u1-pad16_ net-_u1-pad17_ net-_u10-pad3_ d_xnor
+x1 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ net-_x1-pad4_ 3_and
+x2 net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_x2-pad4_ 3_and
+* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_and
+x3 net-_u2-pad2_ net-_x1-pad4_ net-_x2-pad4_ net-_u11-pad3_ net-_u12-pad1_ 4_and
+* u12 net-_u12-pad1_ net-_u1-pad18_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u5-pad3_ u5
+a5 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u6-pad3_ u6
+a6 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u7-pad3_ u7
+a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u8-pad3_ u8
+a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u11-pad1_ u9
+a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11
+a11 net-_u12-pad1_ net-_u1-pad18_ u12
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC688/74688.pro b/library/SubcircuitLibrary/SN74HC688/74688.pro
new file mode 100644
index 00000000..b72f7f2d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688.pro
@@ -0,0 +1,83 @@
+update=05/06/25 21:03:17
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/SN74HC688/74688.sch b/library/SubcircuitLibrary/SN74HC688/74688.sch
new file mode 100644
index 00000000..380c98cf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688.sch
@@ -0,0 +1,514 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U2
+U 1 1 680629D0
+P 3700 1200
+F 0 "U2" H 3700 1100 60 0000 C CNN
+F 1 "d_inverter" H 3700 1350 60 0000 C CNN
+F 2 "" H 3750 1150 60 0000 C CNN
+F 3 "" H 3750 1150 60 0000 C CNN
+ 1 3700 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U3
+U 1 1 680629FD
+P 3850 1800
+F 0 "U3" H 3850 1800 60 0000 C CNN
+F 1 "d_xnor" H 3900 1900 47 0000 C CNN
+F 2 "" H 3850 1800 60 0000 C CNN
+F 3 "" H 3850 1800 60 0000 C CNN
+ 1 3850 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U4
+U 1 1 68062A24
+P 3850 2250
+F 0 "U4" H 3850 2250 60 0000 C CNN
+F 1 "d_xnor" H 3900 2350 47 0000 C CNN
+F 2 "" H 3850 2250 60 0000 C CNN
+F 3 "" H 3850 2250 60 0000 C CNN
+ 1 3850 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U5
+U 1 1 68062A49
+P 3850 2700
+F 0 "U5" H 3850 2700 60 0000 C CNN
+F 1 "d_xnor" H 3900 2800 47 0000 C CNN
+F 2 "" H 3850 2700 60 0000 C CNN
+F 3 "" H 3850 2700 60 0000 C CNN
+ 1 3850 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U6
+U 1 1 68062A80
+P 3850 3150
+F 0 "U6" H 3850 3150 60 0000 C CNN
+F 1 "d_xnor" H 3900 3250 47 0000 C CNN
+F 2 "" H 3850 3150 60 0000 C CNN
+F 3 "" H 3850 3150 60 0000 C CNN
+ 1 3850 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U7
+U 1 1 68062AAF
+P 3850 3600
+F 0 "U7" H 3850 3600 60 0000 C CNN
+F 1 "d_xnor" H 3900 3700 47 0000 C CNN
+F 2 "" H 3850 3600 60 0000 C CNN
+F 3 "" H 3850 3600 60 0000 C CNN
+ 1 3850 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U8
+U 1 1 68062AD4
+P 3850 4050
+F 0 "U8" H 3850 4050 60 0000 C CNN
+F 1 "d_xnor" H 3900 4150 47 0000 C CNN
+F 2 "" H 3850 4050 60 0000 C CNN
+F 3 "" H 3850 4050 60 0000 C CNN
+ 1 3850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U9
+U 1 1 68062AFF
+P 3850 4500
+F 0 "U9" H 3850 4500 60 0000 C CNN
+F 1 "d_xnor" H 3900 4600 47 0000 C CNN
+F 2 "" H 3850 4500 60 0000 C CNN
+F 3 "" H 3850 4500 60 0000 C CNN
+ 1 3850 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U10
+U 1 1 68062B2E
+P 3850 4950
+F 0 "U10" H 3850 4950 60 0000 C CNN
+F 1 "d_xnor" H 3900 5050 47 0000 C CNN
+F 2 "" H 3850 4950 60 0000 C CNN
+F 3 "" H 3850 4950 60 0000 C CNN
+ 1 3850 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 68062B5D
+P 5850 2300
+F 0 "X1" H 5950 2250 60 0000 C CNN
+F 1 "3_and" H 6000 2450 60 0000 C CNN
+F 2 "" H 5850 2300 60 0000 C CNN
+F 3 "" H 5850 2300 60 0000 C CNN
+ 1 5850 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 68062B8E
+P 5850 3450
+F 0 "X2" H 5950 3400 60 0000 C CNN
+F 1 "3_and" H 6000 3600 60 0000 C CNN
+F 2 "" H 5850 3450 60 0000 C CNN
+F 3 "" H 5850 3450 60 0000 C CNN
+ 1 5850 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 68062BC5
+P 6000 4750
+F 0 "U11" H 6000 4750 60 0000 C CNN
+F 1 "d_and" H 6050 4850 60 0000 C CNN
+F 2 "" H 6000 4750 60 0000 C CNN
+F 3 "" H 6000 4750 60 0000 C CNN
+ 1 6000 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X3
+U 1 1 68062C02
+P 7750 3400
+F 0 "X3" H 7800 3350 60 0000 C CNN
+F 1 "4_and" H 7850 3500 60 0000 C CNN
+F 2 "" H 7750 3400 60 0000 C CNN
+F 3 "" H 7750 3400 60 0000 C CNN
+ 1 7750 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 68062C3D
+P 8700 3400
+F 0 "U12" H 8700 3300 60 0000 C CNN
+F 1 "d_inverter" H 8700 3550 60 0000 C CNN
+F 2 "" H 8750 3350 60 0000 C CNN
+F 3 "" H 8750 3350 60 0000 C CNN
+ 1 8700 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68062C78
+P 2800 1200
+F 0 "U1" H 2850 1300 30 0000 C CNN
+F 1 "PORT" H 2800 1200 30 0000 C CNN
+F 2 "" H 2800 1200 60 0000 C CNN
+F 3 "" H 2800 1200 60 0000 C CNN
+ 1 2800 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68062CEB
+P 2800 1700
+F 0 "U1" H 2850 1800 30 0000 C CNN
+F 1 "PORT" H 2800 1700 30 0000 C CNN
+F 2 "" H 2800 1700 60 0000 C CNN
+F 3 "" H 2800 1700 60 0000 C CNN
+ 2 2800 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68062D2E
+P 2800 1900
+F 0 "U1" H 2850 2000 30 0000 C CNN
+F 1 "PORT" H 2800 1900 30 0000 C CNN
+F 2 "" H 2800 1900 60 0000 C CNN
+F 3 "" H 2800 1900 60 0000 C CNN
+ 3 2800 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68062D69
+P 2800 2150
+F 0 "U1" H 2850 2250 30 0000 C CNN
+F 1 "PORT" H 2800 2150 30 0000 C CNN
+F 2 "" H 2800 2150 60 0000 C CNN
+F 3 "" H 2800 2150 60 0000 C CNN
+ 4 2800 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68062DAA
+P 2800 2350
+F 0 "U1" H 2850 2450 30 0000 C CNN
+F 1 "PORT" H 2800 2350 30 0000 C CNN
+F 2 "" H 2800 2350 60 0000 C CNN
+F 3 "" H 2800 2350 60 0000 C CNN
+ 5 2800 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68062EAD
+P 2800 2600
+F 0 "U1" H 2850 2700 30 0000 C CNN
+F 1 "PORT" H 2800 2600 30 0000 C CNN
+F 2 "" H 2800 2600 60 0000 C CNN
+F 3 "" H 2800 2600 60 0000 C CNN
+ 6 2800 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68062EEE
+P 2800 2800
+F 0 "U1" H 2850 2900 30 0000 C CNN
+F 1 "PORT" H 2800 2800 30 0000 C CNN
+F 2 "" H 2800 2800 60 0000 C CNN
+F 3 "" H 2800 2800 60 0000 C CNN
+ 7 2800 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68062F35
+P 2800 3050
+F 0 "U1" H 2850 3150 30 0000 C CNN
+F 1 "PORT" H 2800 3050 30 0000 C CNN
+F 2 "" H 2800 3050 60 0000 C CNN
+F 3 "" H 2800 3050 60 0000 C CNN
+ 8 2800 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68062F84
+P 2800 3250
+F 0 "U1" H 2850 3350 30 0000 C CNN
+F 1 "PORT" H 2800 3250 30 0000 C CNN
+F 2 "" H 2800 3250 60 0000 C CNN
+F 3 "" H 2800 3250 60 0000 C CNN
+ 9 2800 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68062FD3
+P 2800 3500
+F 0 "U1" H 2850 3600 30 0000 C CNN
+F 1 "PORT" H 2800 3500 30 0000 C CNN
+F 2 "" H 2800 3500 60 0000 C CNN
+F 3 "" H 2800 3500 60 0000 C CNN
+ 10 2800 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6806301E
+P 2800 3700
+F 0 "U1" H 2850 3800 30 0000 C CNN
+F 1 "PORT" H 2800 3700 30 0000 C CNN
+F 2 "" H 2800 3700 60 0000 C CNN
+F 3 "" H 2800 3700 60 0000 C CNN
+ 11 2800 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6806306D
+P 2800 3950
+F 0 "U1" H 2850 4050 30 0000 C CNN
+F 1 "PORT" H 2800 3950 30 0000 C CNN
+F 2 "" H 2800 3950 60 0000 C CNN
+F 3 "" H 2800 3950 60 0000 C CNN
+ 12 2800 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 680630BA
+P 2800 4150
+F 0 "U1" H 2850 4250 30 0000 C CNN
+F 1 "PORT" H 2800 4150 30 0000 C CNN
+F 2 "" H 2800 4150 60 0000 C CNN
+F 3 "" H 2800 4150 60 0000 C CNN
+ 13 2800 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68063113
+P 2800 4400
+F 0 "U1" H 2850 4500 30 0000 C CNN
+F 1 "PORT" H 2800 4400 30 0000 C CNN
+F 2 "" H 2800 4400 60 0000 C CNN
+F 3 "" H 2800 4400 60 0000 C CNN
+ 14 2800 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6806316E
+P 2800 4600
+F 0 "U1" H 2850 4700 30 0000 C CNN
+F 1 "PORT" H 2800 4600 30 0000 C CNN
+F 2 "" H 2800 4600 60 0000 C CNN
+F 3 "" H 2800 4600 60 0000 C CNN
+ 15 2800 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 680631C1
+P 2800 4850
+F 0 "U1" H 2850 4950 30 0000 C CNN
+F 1 "PORT" H 2800 4850 30 0000 C CNN
+F 2 "" H 2800 4850 60 0000 C CNN
+F 3 "" H 2800 4850 60 0000 C CNN
+ 16 2800 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 68063218
+P 2800 5050
+F 0 "U1" H 2850 5150 30 0000 C CNN
+F 1 "PORT" H 2800 5050 30 0000 C CNN
+F 2 "" H 2800 5050 60 0000 C CNN
+F 3 "" H 2800 5050 60 0000 C CNN
+ 17 2800 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 6806334C
+P 9550 3400
+F 0 "U1" H 9600 3500 30 0000 C CNN
+F 1 "PORT" H 9550 3400 30 0000 C CNN
+F 2 "" H 9550 3400 60 0000 C CNN
+F 3 "" H 9550 3400 60 0000 C CNN
+ 18 9550 3400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 3050 1200 3400 1200
+Wire Wire Line
+ 3050 1700 3400 1700
+Wire Wire Line
+ 3050 1900 3400 1900
+Wire Wire Line
+ 3400 1900 3400 1800
+Wire Wire Line
+ 3050 2150 3400 2150
+Wire Wire Line
+ 3050 2350 3400 2350
+Wire Wire Line
+ 3400 2350 3400 2250
+Wire Wire Line
+ 3050 2600 3400 2600
+Wire Wire Line
+ 3050 2800 3400 2800
+Wire Wire Line
+ 3400 2800 3400 2700
+Wire Wire Line
+ 3050 3050 3400 3050
+Wire Wire Line
+ 3050 3250 3400 3250
+Wire Wire Line
+ 3400 3250 3400 3150
+Wire Wire Line
+ 3050 3500 3400 3500
+Wire Wire Line
+ 3050 3700 3400 3700
+Wire Wire Line
+ 3400 3700 3400 3600
+Wire Wire Line
+ 3050 3950 3400 3950
+Wire Wire Line
+ 3050 4150 3400 4150
+Wire Wire Line
+ 3400 4150 3400 4050
+Wire Wire Line
+ 3050 4400 3400 4400
+Wire Wire Line
+ 3050 4600 3400 4600
+Wire Wire Line
+ 3400 4600 3400 4500
+Wire Wire Line
+ 3050 4850 3400 4850
+Wire Wire Line
+ 3050 5050 3400 5050
+Wire Wire Line
+ 3400 5050 3400 4950
+Wire Wire Line
+ 4300 4450 5550 4450
+Wire Wire Line
+ 5550 4450 5550 4650
+Wire Wire Line
+ 4300 4900 5550 4900
+Wire Wire Line
+ 5550 4900 5550 4750
+Wire Wire Line
+ 6450 4700 7350 4700
+Wire Wire Line
+ 7350 4700 7350 3550
+Wire Wire Line
+ 4300 3100 5500 3100
+Wire Wire Line
+ 5500 3100 5500 3300
+Wire Wire Line
+ 4300 3550 5050 3550
+Wire Wire Line
+ 5050 3550 5050 3400
+Wire Wire Line
+ 5050 3400 5500 3400
+Wire Wire Line
+ 4300 4000 5500 4000
+Wire Wire Line
+ 5500 4000 5500 3500
+Wire Wire Line
+ 6350 3400 7350 3400
+Wire Wire Line
+ 7350 3400 7350 3450
+Wire Wire Line
+ 4000 1200 7350 1200
+Wire Wire Line
+ 7350 1200 7350 3250
+Wire Wire Line
+ 4300 1750 5500 1750
+Wire Wire Line
+ 5500 1750 5500 2150
+Wire Wire Line
+ 4300 2200 5500 2200
+Wire Wire Line
+ 5500 2200 5500 2250
+Wire Wire Line
+ 4300 2650 5500 2650
+Wire Wire Line
+ 5500 2650 5500 2350
+Wire Wire Line
+ 6350 2250 7150 2250
+Wire Wire Line
+ 7150 2250 7150 3350
+Wire Wire Line
+ 7150 3350 7350 3350
+Wire Wire Line
+ 8250 3400 8400 3400
+Wire Wire Line
+ 9000 3400 9300 3400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC688/74688.sub b/library/SubcircuitLibrary/SN74HC688/74688.sub
new file mode 100644
index 00000000..d68463db
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688.sub
@@ -0,0 +1,55 @@
+* Subcircuit 74688
+.subckt 74688 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_
+* c:\fossee\esim\library\subcircuitlibrary\74688\74688.cir
+.include 3_and.sub
+.include 4_and.sub
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_xnor
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u4-pad3_ d_xnor
+* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u5-pad3_ d_xnor
+* u6 net-_u1-pad8_ net-_u1-pad9_ net-_u6-pad3_ d_xnor
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u7-pad3_ d_xnor
+* u8 net-_u1-pad12_ net-_u1-pad13_ net-_u8-pad3_ d_xnor
+* u9 net-_u1-pad14_ net-_u1-pad15_ net-_u11-pad1_ d_xnor
+* u10 net-_u1-pad16_ net-_u1-pad17_ net-_u10-pad3_ d_xnor
+x1 net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ net-_x1-pad4_ 3_and
+x2 net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_x2-pad4_ 3_and
+* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_and
+x3 net-_u2-pad2_ net-_x1-pad4_ net-_x2-pad4_ net-_u11-pad3_ net-_u12-pad1_ 4_and
+* u12 net-_u12-pad1_ net-_u1-pad18_ d_inverter
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u5-pad3_ u5
+a5 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u6-pad3_ u6
+a6 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u7-pad3_ u7
+a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u8-pad3_ u8
+a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u11-pad1_ u9
+a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11
+a11 net-_u12-pad1_ net-_u1-pad18_ u12
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74688 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml
new file mode 100644
index 00000000..b87a5652
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/74688_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_xnor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_xnor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_xnor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC688/analysis b/library/SubcircuitLibrary/SN74HC688/analysis
new file mode 100644
index 00000000..b7cf1aee
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC688/analysis
@@ -0,0 +1 @@
+.tran 10e-03 4e-00 0e-03 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-05-25 04:04:06 +0000