diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN74ALS520N')
8 files changed, 954 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib b/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib new file mode 100644 index 00000000..f840f078 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 7421 +# +DEF 7421 X 0 40 Y Y 1 F N +F0 "X" 0 250 60 H V C CNN +F1 "7421" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 150 400 -650 0 1 0 N +X IN1 1 -750 50 200 R 50 50 1 1 I +X IN2 2 -750 -100 200 R 50 50 1 1 I +X IN3 3 -750 -250 200 R 50 50 1 1 I +X IN4 4 -750 -400 200 R 50 50 1 1 I +X OUT1 5 -750 -550 200 R 50 50 1 1 O +X IN1 6 600 50 200 L 50 50 1 1 I +X IN2 7 600 -100 200 L 50 50 1 1 I +X IN3 8 600 -250 200 L 50 50 1 1 I +X IN4 9 600 -400 200 L 50 50 1 1 I +X OUT2 10 600 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CD4077 +# +DEF CD4077 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "CD4077" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 -150 450 -1050 0 1 0 N +X IN1 1 -550 -250 200 R 50 50 1 1 I +X IN2 2 -550 -350 200 R 50 50 1 1 I +X IN1 3 -550 -450 200 R 50 50 1 1 I +X IN2 4 -550 -550 200 R 50 50 1 1 I +X IN1 5 -550 -650 200 R 50 50 1 1 I +X IN2 6 -550 -750 200 R 50 50 1 1 I +X IN1 7 -550 -850 200 R 50 50 1 1 I +X IN2 8 -550 -950 200 R 50 50 1 1 I +X OUT1 9 650 -250 200 L 50 50 1 1 O +X OUT2 10 650 -500 200 L 50 50 1 1 O +X OUT3 11 650 -700 200 L 50 50 1 1 O +X OUT4 12 650 -900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.cir b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir new file mode 100644 index 00000000..1f23492e --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir @@ -0,0 +1,31 @@ +* C:\Users\pt710\eSim-Workspace\74520N\74520N.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/25 12:10:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X1-Pad9_ Net-_X1-Pad10_ Net-_X1-Pad11_ Net-_X1-Pad12_ CD4077 +X2 Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_X2-Pad9_ Net-_X2-Pad10_ Net-_X2-Pad11_ Net-_X2-Pad12_ CD4077 +X3 Net-_X1-Pad9_ Net-_X1-Pad10_ Net-_X1-Pad11_ Net-_X1-Pad12_ Net-_U3-Pad1_ Net-_X2-Pad12_ Net-_X2-Pad11_ Net-_X2-Pad10_ Net-_X2-Pad9_ Net-_U3-Pad2_ 7421 +U1 Net-_U1-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad5_ Net-_U1-Pad5_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ adc_bridge_8 +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +R1 out GND 10k +U5 out plot_v1 +v1 Net-_U1-Pad1_ GND DC +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_and +v2 Net-_U1-Pad3_ GND DC +v3 Net-_U1-Pad5_ GND DC +v4 Net-_U1-Pad8_ GND DC +v5 Net-_U2-Pad1_ GND DC +v6 Net-_U2-Pad2_ GND DC +v7 Net-_U2-Pad3_ GND DC +v8 Net-_U2-Pad4_ GND DC +v9 Net-_U2-Pad5_ GND DC +v10 Net-_U2-Pad6_ GND DC +v11 Net-_U2-Pad7_ GND DC +v12 Net-_U2-Pad8_ GND DC +U4 Net-_U3-Pad3_ out dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out new file mode 100644 index 00000000..00c8acc3 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out @@ -0,0 +1,47 @@ +* c:\users\pt710\esim-workspace\74520n\74520n.cir + +.include 7421.sub +.include CD4077.sub +x1 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ CD4077 +x2 net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_x2-pad9_ net-_x2-pad10_ net-_x2-pad11_ net-_x2-pad12_ CD4077 +x3 net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ net-_u3-pad1_ net-_x2-pad12_ net-_x2-pad11_ net-_x2-pad10_ net-_x2-pad9_ net-_u3-pad2_ 7421 +* u1 net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ adc_bridge_8 +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +r1 out gnd 10k +* u5 out plot_v1 +v1 net-_u1-pad1_ gnd dc 5 +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and +v2 net-_u1-pad3_ gnd dc 5 +v3 net-_u1-pad5_ gnd dc 5 +v4 net-_u1-pad8_ gnd dc 5 +v5 net-_u2-pad1_ gnd dc 5 +v6 net-_u2-pad2_ gnd dc 5 +v7 net-_u2-pad3_ gnd dc 5 +v8 net-_u2-pad4_ gnd dc 5 +v9 net-_u2-pad5_ gnd dc 5 +v10 net-_u2-pad6_ gnd dc 5 +v11 net-_u2-pad7_ gnd dc 5 +v12 net-_u2-pad8_ gnd dc 5 +* u4 net-_u3-pad3_ out dac_bridge_1 +a1 [net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ ] [out ] u4 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-06 10e-03 1e-06 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out) +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.pro b/library/SubcircuitLibrary/SN74ALS520N/74520N.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.proj b/library/SubcircuitLibrary/SN74ALS520N/74520N.proj new file mode 100644 index 00000000..8a55fd63 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.proj @@ -0,0 +1 @@ +schematicFile 74520N.sch diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.sch b/library/SubcircuitLibrary/SN74ALS520N/74520N.sch new file mode 100644 index 00000000..2dff2365 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N.sch @@ -0,0 +1,629 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CD4077 X1 +U 1 1 67DCFD03 +P 4900 1350 +F 0 "X1" H 4900 1350 60 0000 C CNN +F 1 "CD4077" H 4900 1450 60 0000 C CNN +F 2 "" H 4900 1350 60 0001 C CNN +F 3 "" H 4900 1350 60 0001 C CNN + 1 4900 1350 + 1 0 0 -1 +$EndComp +$Comp +L CD4077 X2 +U 1 1 67DCFE03 +P 4900 2550 +F 0 "X2" H 4900 2550 60 0000 C CNN +F 1 "CD4077" H 4900 2650 60 0000 C CNN +F 2 "" H 4900 2550 60 0001 C CNN +F 3 "" H 4900 2550 60 0001 C CNN + 1 4900 2550 + 1 0 0 -1 +$EndComp +$Comp +L 7421 X3 +U 1 1 67DCFE8E +P 7150 1700 +F 0 "X3" H 7150 1950 60 0000 C CNN +F 1 "7421" H 7150 2050 60 0000 C CNN +F 2 "" H 7150 1700 60 0001 C CNN +F 3 "" H 7150 1700 60 0001 C CNN + 1 7150 1700 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U1 +U 1 1 67DCFF30 +P 3250 1650 +F 0 "U1" H 3250 1650 60 0000 C CNN +F 1 "adc_bridge_8" H 3250 1800 60 0000 C CNN +F 2 "" H 3250 1650 60 0000 C CNN +F 3 "" H 3250 1650 60 0000 C CNN + 1 3250 1650 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U2 +U 1 1 67DCFF9B +P 3250 2850 +F 0 "U2" H 3250 2850 60 0000 C CNN +F 1 "adc_bridge_8" H 3250 3000 60 0000 C CNN +F 2 "" H 3250 2850 60 0000 C CNN +F 3 "" H 3250 2850 60 0000 C CNN + 1 3250 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 1600 4350 1600 +Wire Wire Line + 3800 1700 4350 1700 +Wire Wire Line + 3800 1800 4350 1800 +Wire Wire Line + 3800 1900 4350 1900 +Wire Wire Line + 3800 2000 4350 2000 +Wire Wire Line + 3800 2100 4350 2100 +Wire Wire Line + 3800 2200 4350 2200 +Wire Wire Line + 3800 2300 4350 2300 +Wire Wire Line + 5550 1600 6400 1600 +Wire Wire Line + 6400 1600 6400 1650 +Wire Wire Line + 5550 1850 6400 1850 +Wire Wire Line + 6400 1850 6400 1800 +Wire Wire Line + 5550 2050 6400 2050 +Wire Wire Line + 6400 2050 6400 1950 +Wire Wire Line + 5550 2250 6200 2250 +Wire Wire Line + 6200 2250 6200 2100 +Wire Wire Line + 6200 2100 6400 2100 +Wire Wire Line + 3800 2800 4350 2800 +Wire Wire Line + 3800 2900 4350 2900 +Wire Wire Line + 3800 3000 4350 3000 +Wire Wire Line + 3800 3100 4350 3100 +Wire Wire Line + 3800 3200 4350 3200 +Wire Wire Line + 3800 3300 4350 3300 +Wire Wire Line + 3800 3400 4350 3400 +Wire Wire Line + 3800 3500 4350 3500 +Wire Wire Line + 5550 2800 8200 2800 +Wire Wire Line + 8200 2800 8200 2100 +Wire Wire Line + 8200 2100 7750 2100 +Wire Wire Line + 5550 3050 8400 3050 +Wire Wire Line + 8400 3050 8400 1950 +Wire Wire Line + 8400 1950 7750 1950 +Wire Wire Line + 5550 3250 8650 3250 +Wire Wire Line + 8650 3250 8650 1800 +Wire Wire Line + 8650 1800 7750 1800 +Wire Wire Line + 5550 3450 8900 3450 +Wire Wire Line + 8900 3450 8900 1650 +Wire Wire Line + 8900 1650 7750 1650 +Wire Wire Line + 6400 2250 6400 4350 +Wire Wire Line + 6400 4350 6650 4350 +Wire Wire Line + 7750 2250 7750 4050 +Wire Wire Line + 7750 4050 5750 4050 +Wire Wire Line + 5750 4050 5750 4450 +Wire Wire Line + 5750 4450 6650 4450 +$Comp +L GND #PWR01 +U 1 1 67DD0482 +P 10250 4350 +F 0 "#PWR01" H 10250 4100 50 0001 C CNN +F 1 "GND" H 10250 4200 50 0000 C CNN +F 2 "" H 10250 4350 50 0001 C CNN +F 3 "" H 10250 4350 50 0001 C CNN + 1 10250 4350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67DD04C2 +P 9450 4400 +F 0 "R1" H 9500 4530 50 0000 C CNN +F 1 "10k" H 9500 4350 50 0000 C CNN +F 2 "" H 9500 4380 30 0000 C CNN +F 3 "" V 9500 4450 30 0000 C CNN + 1 9450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8650 4400 9350 4400 +Wire Wire Line + 9350 4400 9350 4350 +Wire Wire Line + 9650 4350 10250 4350 +$Comp +L plot_v1 U5 +U 1 1 67DD05F6 +P 8950 4600 +F 0 "U5" H 8950 5100 60 0000 C CNN +F 1 "plot_v1" H 9150 4950 60 0000 C CNN +F 2 "" H 8950 4600 60 0000 C CNN +F 3 "" H 8950 4600 60 0000 C CNN + 1 8950 4600 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 67DD074A +P 1850 1600 +F 0 "v1" H 1650 1700 60 0000 C CNN +F 1 "DC" H 1700 1450 60 0000 C CNN +F 2 "R1" H 1850 1600 60 0000 C CNN +F 3 "" H 1850 1600 60 0000 C CNN + 1 1850 1600 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 67DD07A8 +P 7100 4450 +F 0 "U3" H 7100 4450 60 0000 C CNN +F 1 "d_and" H 7150 4550 60 0000 C CNN +F 2 "" H 7100 4450 60 0000 C CNN +F 3 "" H 7100 4450 60 0000 C CNN + 1 7100 4450 + 1 0 0 -1 +$EndComp +Text GLabel 8950 4400 0 60 Input ~ 0 +out +$Comp +L DC v2 +U 1 1 67DD0928 +P 1850 1900 +F 0 "v2" H 1700 2050 60 0000 C CNN +F 1 "DC" H 1700 1750 60 0000 C CNN +F 2 "R1" H 1850 1900 60 0000 C CNN +F 3 "" H 1850 1900 60 0000 C CNN + 1 1850 1900 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 67DD0975 +P 1850 2200 +F 0 "v3" H 1700 2350 60 0000 C CNN +F 1 "DC" H 1750 2050 60 0000 C CNN +F 2 "R1" H 1850 2200 60 0000 C CNN +F 3 "" H 1850 2200 60 0000 C CNN + 1 1850 2200 + 0 1 1 0 +$EndComp +$Comp +L DC v4 +U 1 1 67DD0B88 +P 1850 2500 +F 0 "v4" H 1750 2700 60 0000 C CNN +F 1 "DC" H 1700 2350 60 0000 C CNN +F 2 "R1" H 1550 2500 60 0000 C CNN +F 3 "" H 1850 2500 60 0000 C CNN + 1 1850 2500 + 0 1 1 0 +$EndComp +$Comp +L DC v5 +U 1 1 67DD0C23 +P 1850 2800 +F 0 "v5" H 1700 2950 60 0000 C CNN +F 1 "DC" H 1700 2650 60 0000 C CNN +F 2 "R1" H 1550 2800 60 0000 C CNN +F 3 "" H 1850 2800 60 0000 C CNN + 1 1850 2800 + 0 1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 67DD0E6E +P 1850 3100 +F 0 "v6" H 1700 3250 60 0000 C CNN +F 1 "DC" H 1700 2950 60 0000 C CNN +F 2 "R1" H 1550 3100 60 0000 C CNN +F 3 "" H 1850 3100 60 0000 C CNN + 1 1850 3100 + 0 1 1 0 +$EndComp +$Comp +L DC v7 +U 1 1 67DD1147 +P 1850 3400 +F 0 "v7" H 1700 3550 60 0000 C CNN +F 1 "DC" H 1700 3250 60 0000 C CNN +F 2 "R1" H 1550 3400 60 0000 C CNN +F 3 "" H 1850 3400 60 0000 C CNN + 1 1850 3400 + 0 1 1 0 +$EndComp +$Comp +L DC v8 +U 1 1 67DD142C +P 1850 3700 +F 0 "v8" H 1700 3850 60 0000 C CNN +F 1 "DC" H 1700 3550 60 0000 C CNN +F 2 "R1" H 1550 3700 60 0000 C CNN +F 3 "" H 1850 3700 60 0000 C CNN + 1 1850 3700 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 67DD16E5 +P 1000 1600 +F 0 "#PWR02" H 1000 1350 50 0001 C CNN +F 1 "GND" H 1000 1450 50 0000 C CNN +F 2 "" H 1000 1600 50 0001 C CNN +F 3 "" H 1000 1600 50 0001 C CNN + 1 1000 1600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 67DD1719 +P 1000 1900 +F 0 "#PWR03" H 1000 1650 50 0001 C CNN +F 1 "GND" H 1000 1750 50 0000 C CNN +F 2 "" H 1000 1900 50 0001 C CNN +F 3 "" H 1000 1900 50 0001 C CNN + 1 1000 1900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 67DD174D +P 1000 2200 +F 0 "#PWR04" H 1000 1950 50 0001 C CNN +F 1 "GND" H 1000 2050 50 0000 C CNN +F 2 "" H 1000 2200 50 0001 C CNN +F 3 "" H 1000 2200 50 0001 C CNN + 1 1000 2200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 67DD1781 +P 1000 2500 +F 0 "#PWR05" H 1000 2250 50 0001 C CNN +F 1 "GND" H 1000 2350 50 0000 C CNN +F 2 "" H 1000 2500 50 0001 C CNN +F 3 "" H 1000 2500 50 0001 C CNN + 1 1000 2500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 67DD17B5 +P 1000 2800 +F 0 "#PWR06" H 1000 2550 50 0001 C CNN +F 1 "GND" H 1000 2650 50 0000 C CNN +F 2 "" H 1000 2800 50 0001 C CNN +F 3 "" H 1000 2800 50 0001 C CNN + 1 1000 2800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 67DD17E9 +P 1000 3100 +F 0 "#PWR07" H 1000 2850 50 0001 C CNN +F 1 "GND" H 1000 2950 50 0000 C CNN +F 2 "" H 1000 3100 50 0001 C CNN +F 3 "" H 1000 3100 50 0001 C CNN + 1 1000 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 67DD190D +P 1000 3400 +F 0 "#PWR08" H 1000 3150 50 0001 C CNN +F 1 "GND" H 1000 3250 50 0000 C CNN +F 2 "" H 1000 3400 50 0001 C CNN +F 3 "" H 1000 3400 50 0001 C CNN + 1 1000 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 67DD1941 +P 1000 3700 +F 0 "#PWR09" H 1000 3450 50 0001 C CNN +F 1 "GND" H 1000 3550 50 0000 C CNN +F 2 "" H 1000 3700 50 0001 C CNN +F 3 "" H 1000 3700 50 0001 C CNN + 1 1000 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1000 1600 1400 1600 +Wire Wire Line + 2300 1600 2650 1600 +Wire Wire Line + 2300 1700 2650 1700 +Wire Wire Line + 2250 1900 2500 1900 +Wire Wire Line + 2500 1900 2500 1800 +Wire Wire Line + 2500 1800 2650 1800 +Wire Wire Line + 2300 2200 2650 2200 +Wire Wire Line + 2300 2500 2300 2300 +Wire Wire Line + 2300 2300 2650 2300 +Wire Wire Line + 1000 1900 1400 1900 +Wire Wire Line + 1000 2200 1400 2200 +Wire Wire Line + 1000 2500 1400 2500 +Wire Wire Line + 2250 1950 2650 1950 +Wire Wire Line + 2650 2000 2400 2000 +Wire Wire Line + 2650 1950 2650 1900 +Wire Wire Line + 2550 2050 2650 2050 +Wire Wire Line + 2650 2050 2650 2100 +Wire Wire Line + 1000 2800 1400 2800 +Wire Wire Line + 1000 3100 1400 3100 +Wire Wire Line + 1000 3400 1400 3400 +Wire Wire Line + 1400 3700 1000 3700 +Wire Wire Line + 2300 2800 2650 2800 +Wire Wire Line + 2300 3100 2300 2900 +Wire Wire Line + 2300 2900 2650 2900 +Wire Wire Line + 2300 3400 2350 3400 +Wire Wire Line + 2350 3400 2350 3000 +Wire Wire Line + 2350 3000 2650 3000 +Wire Wire Line + 2300 3700 2400 3700 +Wire Wire Line + 2400 3700 2400 3100 +Wire Wire Line + 2400 3100 2650 3100 +$Comp +L DC v9 +U 1 1 67DD2460 +P 1850 4000 +F 0 "v9" H 1700 4150 60 0000 C CNN +F 1 "DC" H 1700 3850 60 0000 C CNN +F 2 "R1" H 1550 4000 60 0000 C CNN +F 3 "" H 1850 4000 60 0000 C CNN + 1 1850 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v10 +U 1 1 67DD24B5 +P 1850 4300 +F 0 "v10" H 1700 4450 60 0000 C CNN +F 1 "DC" H 1700 4150 60 0000 C CNN +F 2 "R1" H 1550 4300 60 0000 C CNN +F 3 "" H 1850 4300 60 0000 C CNN + 1 1850 4300 + 0 1 1 0 +$EndComp +$Comp +L DC v11 +U 1 1 67DD258A +P 1850 4600 +F 0 "v11" H 1700 4750 60 0000 C CNN +F 1 "DC" H 1700 4450 60 0000 C CNN +F 2 "R1" H 1550 4600 60 0000 C CNN +F 3 "" H 1850 4600 60 0000 C CNN + 1 1850 4600 + 0 1 1 0 +$EndComp +$Comp +L DC v12 +U 1 1 67DD25CD +P 1850 4900 +F 0 "v12" H 1700 5050 60 0000 C CNN +F 1 "DC" H 1700 4750 60 0000 C CNN +F 2 "R1" H 1550 4900 60 0000 C CNN +F 3 "" H 1850 4900 60 0000 C CNN + 1 1850 4900 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR013 +U 1 1 67DD261A +P 1000 4000 +F 0 "#PWR013" H 1000 3750 50 0001 C CNN +F 1 "GND" H 1000 3850 50 0000 C CNN +F 2 "" H 1000 4000 50 0001 C CNN +F 3 "" H 1000 4000 50 0001 C CNN + 1 1000 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR014 +U 1 1 67DD2656 +P 1000 4300 +F 0 "#PWR014" H 1000 4050 50 0001 C CNN +F 1 "GND" H 1000 4150 50 0000 C CNN +F 2 "" H 1000 4300 50 0001 C CNN +F 3 "" H 1000 4300 50 0001 C CNN + 1 1000 4300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR015 +U 1 1 67DD2692 +P 1000 4600 +F 0 "#PWR015" H 1000 4350 50 0001 C CNN +F 1 "GND" H 1000 4450 50 0000 C CNN +F 2 "" H 1000 4600 50 0001 C CNN +F 3 "" H 1000 4600 50 0001 C CNN + 1 1000 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR016 +U 1 1 67DD26CE +P 1000 4900 +F 0 "#PWR016" H 1000 4650 50 0001 C CNN +F 1 "GND" H 1000 4750 50 0000 C CNN +F 2 "" H 1000 4900 50 0001 C CNN +F 3 "" H 1000 4900 50 0001 C CNN + 1 1000 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1000 4000 1400 4000 +Wire Wire Line + 1000 4300 1400 4300 +Wire Wire Line + 1000 4600 1400 4600 +Wire Wire Line + 1000 4900 1400 4900 +Wire Wire Line + 2300 4000 2450 4000 +Wire Wire Line + 2450 4000 2450 3200 +Wire Wire Line + 2450 3200 2650 3200 +Wire Wire Line + 2300 4300 2500 4300 +Wire Wire Line + 2500 4300 2500 3300 +Wire Wire Line + 2500 3300 2650 3300 +Wire Wire Line + 2300 4600 2550 4600 +Wire Wire Line + 2550 4600 2550 3400 +Wire Wire Line + 2550 3400 2650 3400 +Wire Wire Line + 2300 4900 2650 4900 +Wire Wire Line + 2650 4900 2650 3500 +$Comp +L dac_bridge_1 U4 +U 1 1 67DD3EDA +P 8100 4450 +F 0 "U4" H 8100 4450 60 0000 C CNN +F 1 "dac_bridge_1" H 8100 4600 60 0000 C CNN +F 2 "" H 8100 4450 60 0000 C CNN +F 3 "" H 8100 4450 60 0000 C CNN + 1 8100 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 4400 7550 4400 +Wire Wire Line + 2550 2050 2550 2200 +Connection ~ 2550 2200 +Wire Wire Line + 2300 1700 2300 1600 +Wire Wire Line + 2250 1950 2250 1900 +Connection ~ 2300 1900 +Wire Wire Line + 2400 2000 2400 2200 +Wire Wire Line + 2400 2200 2350 2200 +Connection ~ 2350 2200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml new file mode 100644 index 00000000..052d2364 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/74520N_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">5</field1></v8><v9 name="Source type">dc<field1 name="Value">5</field1></v9><v10 name="Source type">dc<field1 name="Value">5</field1></v10><v11 name="Source type">dc<field1 name="Value">5</field1></v11><v12 name="Source type">dc<field1 name="Value">5</field1></v12></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u2 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">dac_bridge<field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter value for out_undef (default=0.5)" /><field15 name="Enter value for input load (default=1.0e-12)" /><field16 name="Enter the Rise Time (default=1.0e-9)" /><field17 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4077</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4077</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\7421</field></x3></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">us</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS520N/analysis b/library/SubcircuitLibrary/SN74ALS520N/analysis new file mode 100644 index 00000000..79194fd6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS520N/analysis @@ -0,0 +1 @@ +.tran 1e-06 10e-03 1e-06
\ No newline at end of file |