diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN74100/SN74100.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN74100/SN74100.cir.out | 236 |
1 files changed, 236 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74100/SN74100.cir.out b/library/SubcircuitLibrary/SN74100/SN74100.cir.out new file mode 100644 index 00000000..3bb5b968 --- /dev/null +++ b/library/SubcircuitLibrary/SN74100/SN74100.cir.out @@ -0,0 +1,236 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74100\sn74100.cir + +* u5 net-_u11-pad2_ net-_u3-pad2_ d_inverter +* u7 net-_u11-pad2_ net-_u11-pad23_ net-_u7-pad3_ d_and +* u3 net-_u11-pad23_ net-_u3-pad2_ net-_u2-pad2_ d_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u11-pad5_ d_nor +* u4 net-_u4-pad1_ net-_u2-pad1_ d_buffer +* u6 net-_u11-pad5_ net-_u6-pad2_ d_buffer +* u8 net-_u7-pad3_ net-_u6-pad2_ net-_u4-pad1_ d_nor +* u18 net-_u11-pad3_ net-_u12-pad2_ d_inverter +* u24 net-_u11-pad3_ net-_u11-pad23_ net-_u24-pad3_ d_and +* u12 net-_u11-pad23_ net-_u12-pad2_ net-_u1-pad2_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u1-pad1_ d_buffer +* u21 net-_u1-pad3_ net-_u21-pad2_ d_buffer +* u27 net-_u24-pad3_ net-_u21-pad2_ net-_u15-pad1_ d_nor +* u42 net-_u11-pad11_ net-_u34-pad2_ d_inverter +* u49 net-_u11-pad11_ net-_u11-pad12_ net-_u49-pad3_ d_and +* u34 net-_u11-pad12_ net-_u34-pad2_ net-_u30-pad2_ d_and +* u30 net-_u30-pad1_ net-_u30-pad2_ net-_u11-pad8_ d_nor +* u38 net-_u38-pad1_ net-_u30-pad1_ d_buffer +* u46 net-_u11-pad8_ net-_u46-pad2_ d_buffer +* u54 net-_u49-pad3_ net-_u46-pad2_ net-_u38-pad1_ d_nor +* u43 net-_u11-pad10_ net-_u35-pad2_ d_inverter +* u51 net-_u11-pad10_ net-_u11-pad12_ net-_u51-pad3_ d_and +* u35 net-_u11-pad12_ net-_u35-pad2_ net-_u31-pad2_ d_and +* u31 net-_u31-pad1_ net-_u31-pad2_ net-_u11-pad9_ d_nor +* u39 net-_u39-pad1_ net-_u31-pad1_ d_buffer +* u47 net-_u11-pad9_ net-_u47-pad2_ d_buffer +* u55 net-_u51-pad3_ net-_u47-pad2_ net-_u39-pad1_ d_nor +* u19 net-_u11-pad22_ net-_u13-pad2_ d_inverter +* u25 net-_u11-pad22_ net-_u11-pad23_ net-_u25-pad3_ d_and +* u13 net-_u11-pad23_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u9 net-_u16-pad2_ net-_u13-pad3_ net-_u11-pad19_ d_nor +* u16 net-_u16-pad1_ net-_u16-pad2_ d_buffer +* u22 net-_u11-pad19_ net-_u22-pad2_ d_buffer +* u28 net-_u25-pad3_ net-_u22-pad2_ net-_u16-pad1_ d_nor +* u20 net-_u11-pad21_ net-_u14-pad2_ d_inverter +* u26 net-_u11-pad21_ net-_u11-pad23_ net-_u26-pad3_ d_and +* u14 net-_u11-pad23_ net-_u14-pad2_ net-_u10-pad2_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u17 net-_u17-pad1_ net-_u10-pad1_ d_buffer +* u23 net-_u10-pad3_ net-_u23-pad2_ d_buffer +* u29 net-_u26-pad3_ net-_u23-pad2_ net-_u17-pad1_ d_nor +* u44 net-_u11-pad15_ net-_u36-pad2_ d_inverter +* u52 net-_u11-pad15_ net-_u11-pad12_ net-_u52-pad3_ d_and +* u36 net-_u11-pad12_ net-_u36-pad2_ net-_u32-pad2_ d_and +* u32 net-_u32-pad1_ net-_u32-pad2_ net-_u11-pad18_ d_nor +* u40 net-_u40-pad1_ net-_u32-pad1_ d_buffer +* u48 net-_u11-pad18_ net-_u48-pad2_ d_buffer +* u56 net-_u52-pad3_ net-_u48-pad2_ net-_u40-pad1_ d_nor +* u45 net-_u11-pad16_ net-_u37-pad2_ d_inverter +* u53 net-_u11-pad16_ net-_u11-pad12_ net-_u53-pad3_ d_and +* u37 net-_u11-pad12_ net-_u37-pad2_ net-_u33-pad2_ d_and +* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u11-pad17_ d_nor +* u41 net-_u41-pad1_ net-_u33-pad1_ d_buffer +* u50 net-_u11-pad17_ net-_u50-pad2_ d_buffer +* u57 net-_u53-pad3_ net-_u50-pad2_ net-_u41-pad1_ d_nor +* u11 ? net-_u11-pad2_ net-_u11-pad3_ net-_u1-pad3_ net-_u11-pad5_ ? ? net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ ? ? net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u10-pad3_ net-_u11-pad21_ net-_u11-pad22_ net-_u11-pad23_ ? port +a1 net-_u11-pad2_ net-_u3-pad2_ u5 +a2 [net-_u11-pad2_ net-_u11-pad23_ ] net-_u7-pad3_ u7 +a3 [net-_u11-pad23_ net-_u3-pad2_ ] net-_u2-pad2_ u3 +a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u11-pad5_ u2 +a5 net-_u4-pad1_ net-_u2-pad1_ u4 +a6 net-_u11-pad5_ net-_u6-pad2_ u6 +a7 [net-_u7-pad3_ net-_u6-pad2_ ] net-_u4-pad1_ u8 +a8 net-_u11-pad3_ net-_u12-pad2_ u18 +a9 [net-_u11-pad3_ net-_u11-pad23_ ] net-_u24-pad3_ u24 +a10 [net-_u11-pad23_ net-_u12-pad2_ ] net-_u1-pad2_ u12 +a11 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a12 net-_u15-pad1_ net-_u1-pad1_ u15 +a13 net-_u1-pad3_ net-_u21-pad2_ u21 +a14 [net-_u24-pad3_ net-_u21-pad2_ ] net-_u15-pad1_ u27 +a15 net-_u11-pad11_ net-_u34-pad2_ u42 +a16 [net-_u11-pad11_ net-_u11-pad12_ ] net-_u49-pad3_ u49 +a17 [net-_u11-pad12_ net-_u34-pad2_ ] net-_u30-pad2_ u34 +a18 [net-_u30-pad1_ net-_u30-pad2_ ] net-_u11-pad8_ u30 +a19 net-_u38-pad1_ net-_u30-pad1_ u38 +a20 net-_u11-pad8_ net-_u46-pad2_ u46 +a21 [net-_u49-pad3_ net-_u46-pad2_ ] net-_u38-pad1_ u54 +a22 net-_u11-pad10_ net-_u35-pad2_ u43 +a23 [net-_u11-pad10_ net-_u11-pad12_ ] net-_u51-pad3_ u51 +a24 [net-_u11-pad12_ net-_u35-pad2_ ] net-_u31-pad2_ u35 +a25 [net-_u31-pad1_ net-_u31-pad2_ ] net-_u11-pad9_ u31 +a26 net-_u39-pad1_ net-_u31-pad1_ u39 +a27 net-_u11-pad9_ net-_u47-pad2_ u47 +a28 [net-_u51-pad3_ net-_u47-pad2_ ] net-_u39-pad1_ u55 +a29 net-_u11-pad22_ net-_u13-pad2_ u19 +a30 [net-_u11-pad22_ net-_u11-pad23_ ] net-_u25-pad3_ u25 +a31 [net-_u11-pad23_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a32 [net-_u16-pad2_ net-_u13-pad3_ ] net-_u11-pad19_ u9 +a33 net-_u16-pad1_ net-_u16-pad2_ u16 +a34 net-_u11-pad19_ net-_u22-pad2_ u22 +a35 [net-_u25-pad3_ net-_u22-pad2_ ] net-_u16-pad1_ u28 +a36 net-_u11-pad21_ net-_u14-pad2_ u20 +a37 [net-_u11-pad21_ net-_u11-pad23_ ] net-_u26-pad3_ u26 +a38 [net-_u11-pad23_ net-_u14-pad2_ ] net-_u10-pad2_ u14 +a39 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a40 net-_u17-pad1_ net-_u10-pad1_ u17 +a41 net-_u10-pad3_ net-_u23-pad2_ u23 +a42 [net-_u26-pad3_ net-_u23-pad2_ ] net-_u17-pad1_ u29 +a43 net-_u11-pad15_ net-_u36-pad2_ u44 +a44 [net-_u11-pad15_ net-_u11-pad12_ ] net-_u52-pad3_ u52 +a45 [net-_u11-pad12_ net-_u36-pad2_ ] net-_u32-pad2_ u36 +a46 [net-_u32-pad1_ net-_u32-pad2_ ] net-_u11-pad18_ u32 +a47 net-_u40-pad1_ net-_u32-pad1_ u40 +a48 net-_u11-pad18_ net-_u48-pad2_ u48 +a49 [net-_u52-pad3_ net-_u48-pad2_ ] net-_u40-pad1_ u56 +a50 net-_u11-pad16_ net-_u37-pad2_ u45 +a51 [net-_u11-pad16_ net-_u11-pad12_ ] net-_u53-pad3_ u53 +a52 [net-_u11-pad12_ net-_u37-pad2_ ] net-_u33-pad2_ u37 +a53 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u11-pad17_ u33 +a54 net-_u41-pad1_ net-_u33-pad1_ u41 +a55 net-_u11-pad17_ net-_u50-pad2_ u50 +a56 [net-_u53-pad3_ net-_u50-pad2_ ] net-_u41-pad1_ u57 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u1 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u46 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u54 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u47 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u55 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u16 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u48 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u56 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u57 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 5e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |