diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out new file mode 100644 index 00000000..554080b1 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out @@ -0,0 +1,80 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn54lvc157a\sn54lvc157a.cir + +* u9 net-_u1-pad4_ net-_u11-pad2_ net-_u16-pad1_ d_and +* u10 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u16 net-_u16-pad1_ net-_u10-pad3_ net-_u1-pad6_ d_or +* u11 net-_u1-pad7_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad8_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u17 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad9_ d_or +* u13 net-_u1-pad10_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u18 net-_u13-pad3_ net-_u14-pad3_ net-_u1-pad12_ d_or +* u7 net-_u1-pad1_ net-_u11-pad2_ net-_u15-pad1_ d_and +* u8 net-_u1-pad2_ net-_u10-pad2_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u1-pad3_ d_or +* u5 net-_u2-pad2_ net-_u3-pad2_ net-_u11-pad2_ d_and +* u6 net-_u4-pad2_ net-_u1-pad14_ net-_u10-pad2_ d_and +* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad14_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad5_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u1-pad6_ u16 +a4 [net-_u1-pad7_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad9_ u17 +a7 [net-_u1-pad10_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u1-pad12_ u18 +a10 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u15-pad1_ u7 +a11 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u15-pad2_ u8 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u1-pad3_ u15 +a13 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u11-pad2_ u5 +a14 [net-_u4-pad2_ net-_u1-pad14_ ] net-_u10-pad2_ u6 +a15 net-_u1-pad13_ net-_u2-pad2_ u2 +a16 net-_u1-pad14_ net-_u3-pad2_ u3 +a17 net-_u1-pad13_ net-_u4-pad2_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |