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-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154-cache.lib35
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154.cir101
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154.cir.out375
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154.pro73
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154.sch1644
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154.sub277
-rw-r--r--library/SubcircuitLibrary/SN54154/SN54154_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/SN54154/analysis1
8 files changed, 2507 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54154/SN54154-cache.lib b/library/SubcircuitLibrary/SN54154/SN54154-cache.lib
new file mode 100644
index 00000000..2a9c1f16
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154-cache.lib
@@ -0,0 +1,35 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54154/SN54154.cir b/library/SubcircuitLibrary/SN54154/SN54154.cir
new file mode 100644
index 00000000..d936010b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154.cir
@@ -0,0 +1,101 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN54154\SN54154.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 4/12/2025 10:26:58 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ G d_and
+U5 G1_bar Net-_U11-Pad1_ d_inverter
+U6 G2_bar Net-_U11-Pad2_ d_inverter
+U1 A_in A_bar d_inverter
+U7 A_bar A d_inverter
+U2 B_in B_bar d_inverter
+U8 B_bar B d_inverter
+U3 C_in C_bar d_inverter
+U9 C_bar C d_inverter
+U4 D_in D_bar d_inverter
+U10 D_bar D d_inverter
+U60 G Net-_U44-Pad3_ Net-_U60-Pad3_ d_and
+U44 A_bar Net-_U28-Pad3_ Net-_U44-Pad3_ d_and
+U28 B_bar Net-_U12-Pad3_ Net-_U28-Pad3_ d_and
+U12 C_bar D_bar Net-_U12-Pad3_ d_and
+U61 G Net-_U45-Pad3_ Net-_U61-Pad3_ d_and
+U45 A Net-_U29-Pad3_ Net-_U45-Pad3_ d_and
+U29 B_bar Net-_U13-Pad3_ Net-_U29-Pad3_ d_and
+U13 C_bar D_bar Net-_U13-Pad3_ d_and
+U62 G Net-_U46-Pad3_ Net-_U62-Pad3_ d_and
+U46 A_bar Net-_U30-Pad3_ Net-_U46-Pad3_ d_and
+U30 B Net-_U14-Pad3_ Net-_U30-Pad3_ d_and
+U14 C_bar D_bar Net-_U14-Pad3_ d_and
+U15 C_bar D_bar Net-_U15-Pad3_ d_and
+U31 B Net-_U15-Pad3_ Net-_U31-Pad3_ d_and
+U47 A Net-_U31-Pad3_ Net-_U47-Pad3_ d_and
+U63 G Net-_U47-Pad3_ Net-_U63-Pad3_ d_and
+U16 C D_bar Net-_U16-Pad3_ d_and
+U32 B_bar Net-_U16-Pad3_ Net-_U32-Pad3_ d_and
+U48 A_bar Net-_U32-Pad3_ Net-_U48-Pad3_ d_and
+U64 G Net-_U48-Pad3_ Net-_U64-Pad3_ d_and
+U17 C D_bar Net-_U17-Pad3_ d_and
+U33 B_bar Net-_U17-Pad3_ Net-_U33-Pad3_ d_and
+U49 A Net-_U33-Pad3_ Net-_U49-Pad3_ d_and
+U65 G Net-_U49-Pad3_ Net-_U65-Pad3_ d_and
+U18 C D_bar Net-_U18-Pad3_ d_and
+U34 B Net-_U18-Pad3_ Net-_U34-Pad3_ d_and
+U50 A_bar Net-_U34-Pad3_ Net-_U50-Pad3_ d_and
+U66 G Net-_U50-Pad3_ Net-_U66-Pad3_ d_and
+U19 C D_bar Net-_U19-Pad3_ d_and
+U35 B Net-_U19-Pad3_ Net-_U35-Pad3_ d_and
+U51 A Net-_U35-Pad3_ Net-_U51-Pad3_ d_and
+U67 G Net-_U51-Pad3_ Net-_U67-Pad3_ d_and
+U20 C_bar D Net-_U20-Pad3_ d_and
+U36 B_bar Net-_U20-Pad3_ Net-_U36-Pad3_ d_and
+U52 A_bar Net-_U36-Pad3_ Net-_U52-Pad3_ d_and
+U68 G Net-_U52-Pad3_ Net-_U68-Pad3_ d_and
+U21 C_bar D Net-_U21-Pad3_ d_and
+U37 B_bar Net-_U21-Pad3_ Net-_U37-Pad3_ d_and
+U53 A Net-_U37-Pad3_ Net-_U53-Pad3_ d_and
+U69 G Net-_U53-Pad3_ Net-_U69-Pad3_ d_and
+U22 C_bar D Net-_U22-Pad3_ d_and
+U38 B Net-_U22-Pad3_ Net-_U38-Pad3_ d_and
+U54 A_bar Net-_U38-Pad3_ Net-_U54-Pad3_ d_and
+U70 G Net-_U54-Pad3_ Net-_U70-Pad3_ d_and
+U25 C_bar D Net-_U25-Pad3_ d_and
+U41 B Net-_U25-Pad3_ Net-_U41-Pad3_ d_and
+U57 A Net-_U41-Pad3_ Net-_U57-Pad3_ d_and
+U73 G Net-_U57-Pad3_ Net-_U73-Pad3_ d_and
+U26 C D Net-_U26-Pad3_ d_and
+U42 B_bar Net-_U26-Pad3_ Net-_U42-Pad3_ d_and
+U58 A_bar Net-_U42-Pad3_ Net-_U58-Pad3_ d_and
+U74 G Net-_U58-Pad3_ Net-_U74-Pad3_ d_and
+U23 C D Net-_U23-Pad3_ d_and
+U39 B_bar Net-_U23-Pad3_ Net-_U39-Pad3_ d_and
+U55 A Net-_U39-Pad3_ Net-_U55-Pad3_ d_and
+U71 G Net-_U55-Pad3_ Net-_U71-Pad3_ d_and
+U24 C D Net-_U24-Pad3_ d_and
+U40 B Net-_U24-Pad3_ Net-_U40-Pad3_ d_and
+U56 A_bar Net-_U40-Pad3_ Net-_U56-Pad3_ d_and
+U72 G Net-_U56-Pad3_ Net-_U72-Pad3_ d_and
+U27 C D Net-_U27-Pad3_ d_and
+U43 B Net-_U27-Pad3_ Net-_U43-Pad3_ d_and
+U59 A Net-_U43-Pad3_ Net-_U59-Pad3_ d_and
+U75 G Net-_U59-Pad3_ Net-_U75-Pad3_ d_and
+U76 Net-_U60-Pad3_ o0 d_inverter
+U77 Net-_U61-Pad3_ o1 d_inverter
+U78 Net-_U62-Pad3_ o2 d_inverter
+U79 Net-_U63-Pad3_ o3 d_inverter
+U80 Net-_U64-Pad3_ o4 d_inverter
+U81 Net-_U65-Pad3_ o5 d_inverter
+U82 Net-_U66-Pad3_ o6 d_inverter
+U83 Net-_U67-Pad3_ o7 d_inverter
+U84 Net-_U68-Pad3_ o8 d_inverter
+U85 Net-_U69-Pad3_ o9 d_inverter
+U86 Net-_U70-Pad3_ o10 d_inverter
+U89 Net-_U73-Pad3_ o11 d_inverter
+U90 Net-_U74-Pad3_ o12 d_inverter
+U87 Net-_U71-Pad3_ o13 d_inverter
+U88 Net-_U72-Pad3_ o14 d_inverter
+U91 Net-_U75-Pad3_ o15 d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/SN54154/SN54154.cir.out b/library/SubcircuitLibrary/SN54154/SN54154.cir.out
new file mode 100644
index 00000000..198f4867
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154.cir.out
@@ -0,0 +1,375 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn54154\sn54154.cir
+
+* u11 net-_u11-pad1_ net-_u11-pad2_ g d_and
+* u5 ? net-_u11-pad1_ d_inverter
+* u6 ? net-_u11-pad2_ d_inverter
+* u1 ? a_bar d_inverter
+* u7 a_bar a d_inverter
+* u2 ? b_bar d_inverter
+* u8 b_bar b d_inverter
+* u3 ? c_bar d_inverter
+* u9 c_bar c d_inverter
+* u4 ? d_bar d_inverter
+* u10 d_bar d d_inverter
+* u60 g net-_u44-pad3_ net-_u60-pad3_ d_and
+* u44 a_bar net-_u28-pad3_ net-_u44-pad3_ d_and
+* u28 b_bar net-_u12-pad3_ net-_u28-pad3_ d_and
+* u12 c_bar d_bar net-_u12-pad3_ d_and
+* u61 g net-_u45-pad3_ net-_u61-pad3_ d_and
+* u45 a net-_u29-pad3_ net-_u45-pad3_ d_and
+* u29 b_bar net-_u13-pad3_ net-_u29-pad3_ d_and
+* u13 c_bar d_bar net-_u13-pad3_ d_and
+* u62 g net-_u46-pad3_ net-_u62-pad3_ d_and
+* u46 a_bar net-_u30-pad3_ net-_u46-pad3_ d_and
+* u30 b net-_u14-pad3_ net-_u30-pad3_ d_and
+* u14 c_bar d_bar net-_u14-pad3_ d_and
+* u15 c_bar d_bar net-_u15-pad3_ d_and
+* u31 b net-_u15-pad3_ net-_u31-pad3_ d_and
+* u47 a net-_u31-pad3_ net-_u47-pad3_ d_and
+* u63 g net-_u47-pad3_ net-_u63-pad3_ d_and
+* u16 c d_bar net-_u16-pad3_ d_and
+* u32 b_bar net-_u16-pad3_ net-_u32-pad3_ d_and
+* u48 a_bar net-_u32-pad3_ net-_u48-pad3_ d_and
+* u64 g net-_u48-pad3_ net-_u64-pad3_ d_and
+* u17 c d_bar net-_u17-pad3_ d_and
+* u33 b_bar net-_u17-pad3_ net-_u33-pad3_ d_and
+* u49 a net-_u33-pad3_ net-_u49-pad3_ d_and
+* u65 g net-_u49-pad3_ net-_u65-pad3_ d_and
+* u18 c d_bar net-_u18-pad3_ d_and
+* u34 b net-_u18-pad3_ net-_u34-pad3_ d_and
+* u50 a_bar net-_u34-pad3_ net-_u50-pad3_ d_and
+* u66 g net-_u50-pad3_ net-_u66-pad3_ d_and
+* u19 c d_bar net-_u19-pad3_ d_and
+* u35 b net-_u19-pad3_ net-_u35-pad3_ d_and
+* u51 a net-_u35-pad3_ net-_u51-pad3_ d_and
+* u67 g net-_u51-pad3_ net-_u67-pad3_ d_and
+* u20 c_bar d net-_u20-pad3_ d_and
+* u36 b_bar net-_u20-pad3_ net-_u36-pad3_ d_and
+* u52 a_bar net-_u36-pad3_ net-_u52-pad3_ d_and
+* u68 g net-_u52-pad3_ net-_u68-pad3_ d_and
+* u21 c_bar d net-_u21-pad3_ d_and
+* u37 b_bar net-_u21-pad3_ net-_u37-pad3_ d_and
+* u53 a net-_u37-pad3_ net-_u53-pad3_ d_and
+* u69 g net-_u53-pad3_ net-_u69-pad3_ d_and
+* u22 c_bar d net-_u22-pad3_ d_and
+* u38 b net-_u22-pad3_ net-_u38-pad3_ d_and
+* u54 a_bar net-_u38-pad3_ net-_u54-pad3_ d_and
+* u70 g net-_u54-pad3_ net-_u70-pad3_ d_and
+* u25 c_bar d net-_u25-pad3_ d_and
+* u41 b net-_u25-pad3_ net-_u41-pad3_ d_and
+* u57 a net-_u41-pad3_ net-_u57-pad3_ d_and
+* u73 g net-_u57-pad3_ net-_u73-pad3_ d_and
+* u26 c d net-_u26-pad3_ d_and
+* u42 b_bar net-_u26-pad3_ net-_u42-pad3_ d_and
+* u58 a_bar net-_u42-pad3_ net-_u58-pad3_ d_and
+* u74 g net-_u58-pad3_ net-_u74-pad3_ d_and
+* u23 c d net-_u23-pad3_ d_and
+* u39 b_bar net-_u23-pad3_ net-_u39-pad3_ d_and
+* u55 a net-_u39-pad3_ net-_u55-pad3_ d_and
+* u71 g net-_u55-pad3_ net-_u71-pad3_ d_and
+* u24 c d net-_u24-pad3_ d_and
+* u40 b net-_u24-pad3_ net-_u40-pad3_ d_and
+* u56 a_bar net-_u40-pad3_ net-_u56-pad3_ d_and
+* u72 g net-_u56-pad3_ net-_u72-pad3_ d_and
+* u27 c d net-_u27-pad3_ d_and
+* u43 b net-_u27-pad3_ net-_u43-pad3_ d_and
+* u59 a net-_u43-pad3_ net-_u59-pad3_ d_and
+* u75 g net-_u59-pad3_ net-_u75-pad3_ d_and
+* u76 net-_u60-pad3_ ? d_inverter
+* u77 net-_u61-pad3_ ? d_inverter
+* u78 net-_u62-pad3_ ? d_inverter
+* u79 net-_u63-pad3_ ? d_inverter
+* u80 net-_u64-pad3_ ? d_inverter
+* u81 net-_u65-pad3_ ? d_inverter
+* u82 net-_u66-pad3_ ? d_inverter
+* u83 net-_u67-pad3_ ? d_inverter
+* u84 net-_u68-pad3_ ? d_inverter
+* u85 net-_u69-pad3_ ? d_inverter
+* u86 net-_u70-pad3_ ? d_inverter
+* u89 net-_u73-pad3_ ? d_inverter
+* u90 net-_u74-pad3_ ? d_inverter
+* u87 net-_u71-pad3_ ? d_inverter
+* u88 net-_u72-pad3_ ? d_inverter
+* u91 net-_u75-pad3_ ? d_inverter
+a1 [net-_u11-pad1_ net-_u11-pad2_ ] g u11
+a2 g1_bar net-_u11-pad1_ u5
+a3 g2_bar net-_u11-pad2_ u6
+a4 a_in a_bar u1
+a5 a_bar a u7
+a6 b_in b_bar u2
+a7 b_bar b u8
+a8 c_in c_bar u3
+a9 c_bar c u9
+a10 d_in d_bar u4
+a11 d_bar d u10
+a12 [g net-_u44-pad3_ ] net-_u60-pad3_ u60
+a13 [a_bar net-_u28-pad3_ ] net-_u44-pad3_ u44
+a14 [b_bar net-_u12-pad3_ ] net-_u28-pad3_ u28
+a15 [c_bar d_bar ] net-_u12-pad3_ u12
+a16 [g net-_u45-pad3_ ] net-_u61-pad3_ u61
+a17 [a net-_u29-pad3_ ] net-_u45-pad3_ u45
+a18 [b_bar net-_u13-pad3_ ] net-_u29-pad3_ u29
+a19 [c_bar d_bar ] net-_u13-pad3_ u13
+a20 [g net-_u46-pad3_ ] net-_u62-pad3_ u62
+a21 [a_bar net-_u30-pad3_ ] net-_u46-pad3_ u46
+a22 [b net-_u14-pad3_ ] net-_u30-pad3_ u30
+a23 [c_bar d_bar ] net-_u14-pad3_ u14
+a24 [c_bar d_bar ] net-_u15-pad3_ u15
+a25 [b net-_u15-pad3_ ] net-_u31-pad3_ u31
+a26 [a net-_u31-pad3_ ] net-_u47-pad3_ u47
+a27 [g net-_u47-pad3_ ] net-_u63-pad3_ u63
+a28 [c d_bar ] net-_u16-pad3_ u16
+a29 [b_bar net-_u16-pad3_ ] net-_u32-pad3_ u32
+a30 [a_bar net-_u32-pad3_ ] net-_u48-pad3_ u48
+a31 [g net-_u48-pad3_ ] net-_u64-pad3_ u64
+a32 [c d_bar ] net-_u17-pad3_ u17
+a33 [b_bar net-_u17-pad3_ ] net-_u33-pad3_ u33
+a34 [a net-_u33-pad3_ ] net-_u49-pad3_ u49
+a35 [g net-_u49-pad3_ ] net-_u65-pad3_ u65
+a36 [c d_bar ] net-_u18-pad3_ u18
+a37 [b net-_u18-pad3_ ] net-_u34-pad3_ u34
+a38 [a_bar net-_u34-pad3_ ] net-_u50-pad3_ u50
+a39 [g net-_u50-pad3_ ] net-_u66-pad3_ u66
+a40 [c d_bar ] net-_u19-pad3_ u19
+a41 [b net-_u19-pad3_ ] net-_u35-pad3_ u35
+a42 [a net-_u35-pad3_ ] net-_u51-pad3_ u51
+a43 [g net-_u51-pad3_ ] net-_u67-pad3_ u67
+a44 [c_bar d ] net-_u20-pad3_ u20
+a45 [b_bar net-_u20-pad3_ ] net-_u36-pad3_ u36
+a46 [a_bar net-_u36-pad3_ ] net-_u52-pad3_ u52
+a47 [g net-_u52-pad3_ ] net-_u68-pad3_ u68
+a48 [c_bar d ] net-_u21-pad3_ u21
+a49 [b_bar net-_u21-pad3_ ] net-_u37-pad3_ u37
+a50 [a net-_u37-pad3_ ] net-_u53-pad3_ u53
+a51 [g net-_u53-pad3_ ] net-_u69-pad3_ u69
+a52 [c_bar d ] net-_u22-pad3_ u22
+a53 [b net-_u22-pad3_ ] net-_u38-pad3_ u38
+a54 [a_bar net-_u38-pad3_ ] net-_u54-pad3_ u54
+a55 [g net-_u54-pad3_ ] net-_u70-pad3_ u70
+a56 [c_bar d ] net-_u25-pad3_ u25
+a57 [b net-_u25-pad3_ ] net-_u41-pad3_ u41
+a58 [a net-_u41-pad3_ ] net-_u57-pad3_ u57
+a59 [g net-_u57-pad3_ ] net-_u73-pad3_ u73
+a60 [c d ] net-_u26-pad3_ u26
+a61 [b_bar net-_u26-pad3_ ] net-_u42-pad3_ u42
+a62 [a_bar net-_u42-pad3_ ] net-_u58-pad3_ u58
+a63 [g net-_u58-pad3_ ] net-_u74-pad3_ u74
+a64 [c d ] net-_u23-pad3_ u23
+a65 [b_bar net-_u23-pad3_ ] net-_u39-pad3_ u39
+a66 [a net-_u39-pad3_ ] net-_u55-pad3_ u55
+a67 [g net-_u55-pad3_ ] net-_u71-pad3_ u71
+a68 [c d ] net-_u24-pad3_ u24
+a69 [b net-_u24-pad3_ ] net-_u40-pad3_ u40
+a70 [a_bar net-_u40-pad3_ ] net-_u56-pad3_ u56
+a71 [g net-_u56-pad3_ ] net-_u72-pad3_ u72
+a72 [c d ] net-_u27-pad3_ u27
+a73 [b net-_u27-pad3_ ] net-_u43-pad3_ u43
+a74 [a net-_u43-pad3_ ] net-_u59-pad3_ u59
+a75 [g net-_u59-pad3_ ] net-_u75-pad3_ u75
+a76 net-_u60-pad3_ o0 u76
+a77 net-_u61-pad3_ o1 u77
+a78 net-_u62-pad3_ o2 u78
+a79 net-_u63-pad3_ o3 u79
+a80 net-_u64-pad3_ o4 u80
+a81 net-_u65-pad3_ o5 u81
+a82 net-_u66-pad3_ o6 u82
+a83 net-_u67-pad3_ o7 u83
+a84 net-_u68-pad3_ o8 u84
+a85 net-_u69-pad3_ o9 u85
+a86 net-_u70-pad3_ o10 u86
+a87 net-_u73-pad3_ o11 u89
+a88 net-_u74-pad3_ o12 u90
+a89 net-_u71-pad3_ o13 u87
+a90 net-_u72-pad3_ o14 u88
+a91 net-_u75-pad3_ o15 u91
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u62 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u64 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u65 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u66 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u67 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u68 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u69 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u70 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u73 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u82 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u83 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u84 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u85 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u86 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u89 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u90 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u87 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u88 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u91 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54154/SN54154.pro b/library/SubcircuitLibrary/SN54154/SN54154.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54154/SN54154.sch b/library/SubcircuitLibrary/SN54154/SN54154.sch
new file mode 100644
index 00000000..72809ad1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154.sch
@@ -0,0 +1,1644 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54154-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
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+Text GLabel 7800 850 0 60 Input ~ 0
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+Text GLabel 6900 1000 0 60 Input ~ 0
+B_bar
+Text GLabel 6000 1200 0 60 Input ~ 0
+C_bar
+Text GLabel 6000 1300 0 60 Input ~ 0
+D_bar
+Text GLabel 8750 700 0 60 Input ~ 0
+G
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Text GLabel 10600 750 2 60 Input ~ 0
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+Wire Wire Line
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+A
+Text GLabel 6950 1950 0 60 Input ~ 0
+B_bar
+Text GLabel 6050 2150 0 60 Input ~ 0
+C_bar
+Text GLabel 6050 2250 0 60 Input ~ 0
+D_bar
+Text GLabel 8800 1650 0 60 Input ~ 0
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+A_bar
+Text GLabel 6950 4500 0 60 Input ~ 0
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+Text GLabel 6050 4700 0 60 Input ~ 0
+C
+Text GLabel 6050 4800 0 60 Input ~ 0
+D_bar
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diff --git a/library/SubcircuitLibrary/SN54154/SN54154.sub b/library/SubcircuitLibrary/SN54154/SN54154.sub
new file mode 100644
index 00000000..e5f7b310
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154.sub
@@ -0,0 +1,277 @@
+* Subcircuit SN54154
+* c:\fossee\esim\library\subcircuitlibrary\SN54154\SN54154.sub
+.subckt SN54154 o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 ? o11 o12 o13 o14 o15 g1_bar g2_bar d_in c_in b_in a_in ?
+a1 [net-_u11-pad1_ net-_u11-pad2_ ] g u11
+a2 g1_bar net-_u11-pad1_ u5
+a3 g2_bar net-_u11-pad2_ u6
+a4 a_in a_bar u1
+a5 a_bar a u7
+a6 b_in b_bar u2
+a7 b_bar b u8
+a8 c_in c_bar u3
+a9 c_bar c u9
+a10 d_in d_bar u4
+a11 d_bar d u10
+a12 [g net-_u44-pad3_ ] net-_u60-pad3_ u60
+a13 [a_bar net-_u28-pad3_ ] net-_u44-pad3_ u44
+a14 [b_bar net-_u12-pad3_ ] net-_u28-pad3_ u28
+a15 [c_bar d_bar ] net-_u12-pad3_ u12
+a16 [g net-_u45-pad3_ ] net-_u61-pad3_ u61
+a17 [a net-_u29-pad3_ ] net-_u45-pad3_ u45
+a18 [b_bar net-_u13-pad3_ ] net-_u29-pad3_ u29
+a19 [c_bar d_bar ] net-_u13-pad3_ u13
+a20 [g net-_u46-pad3_ ] net-_u62-pad3_ u62
+a21 [a_bar net-_u30-pad3_ ] net-_u46-pad3_ u46
+a22 [b net-_u14-pad3_ ] net-_u30-pad3_ u30
+a23 [c_bar d_bar ] net-_u14-pad3_ u14
+a24 [c_bar d_bar ] net-_u15-pad3_ u15
+a25 [b net-_u15-pad3_ ] net-_u31-pad3_ u31
+a26 [a net-_u31-pad3_ ] net-_u47-pad3_ u47
+a27 [g net-_u47-pad3_ ] net-_u63-pad3_ u63
+a28 [c d_bar ] net-_u16-pad3_ u16
+a29 [b_bar net-_u16-pad3_ ] net-_u32-pad3_ u32
+a30 [a_bar net-_u32-pad3_ ] net-_u48-pad3_ u48
+a31 [g net-_u48-pad3_ ] net-_u64-pad3_ u64
+a32 [c d_bar ] net-_u17-pad3_ u17
+a33 [b_bar net-_u17-pad3_ ] net-_u33-pad3_ u33
+a34 [a net-_u33-pad3_ ] net-_u49-pad3_ u49
+a35 [g net-_u49-pad3_ ] net-_u65-pad3_ u65
+a36 [c d_bar ] net-_u18-pad3_ u18
+a37 [b net-_u18-pad3_ ] net-_u34-pad3_ u34
+a38 [a_bar net-_u34-pad3_ ] net-_u50-pad3_ u50
+a39 [g net-_u50-pad3_ ] net-_u66-pad3_ u66
+a40 [c d_bar ] net-_u19-pad3_ u19
+a41 [b net-_u19-pad3_ ] net-_u35-pad3_ u35
+a42 [a net-_u35-pad3_ ] net-_u51-pad3_ u51
+a43 [g net-_u51-pad3_ ] net-_u67-pad3_ u67
+a44 [c_bar d ] net-_u20-pad3_ u20
+a45 [b_bar net-_u20-pad3_ ] net-_u36-pad3_ u36
+a46 [a_bar net-_u36-pad3_ ] net-_u52-pad3_ u52
+a47 [g net-_u52-pad3_ ] net-_u68-pad3_ u68
+a48 [c_bar d ] net-_u21-pad3_ u21
+a49 [b_bar net-_u21-pad3_ ] net-_u37-pad3_ u37
+a50 [a net-_u37-pad3_ ] net-_u53-pad3_ u53
+a51 [g net-_u53-pad3_ ] net-_u69-pad3_ u69
+a52 [c_bar d ] net-_u22-pad3_ u22
+a53 [b net-_u22-pad3_ ] net-_u38-pad3_ u38
+a54 [a_bar net-_u38-pad3_ ] net-_u54-pad3_ u54
+a55 [g net-_u54-pad3_ ] net-_u70-pad3_ u70
+a56 [c_bar d ] net-_u25-pad3_ u25
+a57 [b net-_u25-pad3_ ] net-_u41-pad3_ u41
+a58 [a net-_u41-pad3_ ] net-_u57-pad3_ u57
+a59 [g net-_u57-pad3_ ] net-_u73-pad3_ u73
+a60 [c d ] net-_u26-pad3_ u26
+a61 [b_bar net-_u26-pad3_ ] net-_u42-pad3_ u42
+a62 [a_bar net-_u42-pad3_ ] net-_u58-pad3_ u58
+a63 [g net-_u58-pad3_ ] net-_u74-pad3_ u74
+a64 [c d ] net-_u23-pad3_ u23
+a65 [b_bar net-_u23-pad3_ ] net-_u39-pad3_ u39
+a66 [a net-_u39-pad3_ ] net-_u55-pad3_ u55
+a67 [g net-_u55-pad3_ ] net-_u71-pad3_ u71
+a68 [c d ] net-_u24-pad3_ u24
+a69 [b net-_u24-pad3_ ] net-_u40-pad3_ u40
+a70 [a_bar net-_u40-pad3_ ] net-_u56-pad3_ u56
+a71 [g net-_u56-pad3_ ] net-_u72-pad3_ u72
+a72 [c d ] net-_u27-pad3_ u27
+a73 [b net-_u27-pad3_ ] net-_u43-pad3_ u43
+a74 [a net-_u43-pad3_ ] net-_u59-pad3_ u59
+a75 [g net-_u59-pad3_ ] net-_u75-pad3_ u75
+a76 net-_u60-pad3_ o0 u76
+a77 net-_u61-pad3_ o1 u77
+a78 net-_u62-pad3_ o2 u78
+a79 net-_u63-pad3_ o3 u79
+a80 net-_u64-pad3_ o4 u80
+a81 net-_u65-pad3_ o5 u81
+a82 net-_u66-pad3_ o6 u82
+a83 net-_u67-pad3_ o7 u83
+a84 net-_u68-pad3_ o8 u84
+a85 net-_u69-pad3_ o9 u85
+a86 net-_u70-pad3_ o10 u86
+a87 net-_u73-pad3_ o11 u89
+a88 net-_u74-pad3_ o12 u90
+a89 net-_u71-pad3_ o13 u87
+a90 net-_u72-pad3_ o14 u88
+a91 net-_u75-pad3_ o15 u91
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u62 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u64 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u65 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u66 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u67 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u68 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u69 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u70 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u73 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u82 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u83 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u84 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u85 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u86 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u89 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u90 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u87 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u88 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u91 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.ends SN54154 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54154/SN54154_Previous_Values.xml b/library/SubcircuitLibrary/SN54154/SN54154_Previous_Values.xml
new file mode 100644
index 00000000..8eab043a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/SN54154_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u60 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u60><u44 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u44><u28 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u28><u12 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u12><u61 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u61><u45 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u45><u29 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u29><u13 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u13><u62 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u62><u46 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u46><u30 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u30><u14 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u14><u63 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u63><u47 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u47><u31 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u31><u15 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u64 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u64><u48 name="type">d_nand<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u48><u32 name="type">d_nand<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u32><u16 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u16><u65 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u65><u49 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u49><u33 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u33><u17 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u17><u66 name="type">d_nand<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u66><u50 name="type">d_nand<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u50><u34 name="type">d_nand<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" 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name="type">d_inverter<field238 name="Enter Rise Delay (default=1.0e-9)" /><field239 name="Enter Fall Delay (default=1.0e-9)" /><field240 name="Enter Input Load (default=1.0e-12)" /></u80><u81 name="type">d_inverter<field241 name="Enter Rise Delay (default=1.0e-9)" /><field242 name="Enter Fall Delay (default=1.0e-9)" /><field243 name="Enter Input Load (default=1.0e-12)" /></u81><u82 name="type">d_inverter<field244 name="Enter Rise Delay (default=1.0e-9)" /><field245 name="Enter Fall Delay (default=1.0e-9)" /><field246 name="Enter Input Load (default=1.0e-12)" /></u82><u83 name="type">d_inverter<field247 name="Enter Rise Delay (default=1.0e-9)" /><field248 name="Enter Fall Delay (default=1.0e-9)" /><field249 name="Enter Input Load (default=1.0e-12)" /></u83><u84 name="type">d_inverter<field250 name="Enter Rise Delay (default=1.0e-9)" /><field251 name="Enter Fall Delay (default=1.0e-9)" /><field252 name="Enter Input Load (default=1.0e-12)" /></u84><u85 name="type">d_inverter<field253 name="Enter Rise Delay (default=1.0e-9)" /><field254 name="Enter Fall Delay (default=1.0e-9)" /><field255 name="Enter Input Load (default=1.0e-12)" /></u85><u86 name="type">d_inverter<field256 name="Enter Rise Delay (default=1.0e-9)" /><field257 name="Enter Fall Delay (default=1.0e-9)" /><field258 name="Enter Input Load (default=1.0e-12)" /></u86><u89 name="type">d_inverter<field259 name="Enter Rise Delay (default=1.0e-9)" /><field260 name="Enter Fall Delay (default=1.0e-9)" /><field261 name="Enter Input Load (default=1.0e-12)" /></u89><u90 name="type">d_inverter<field262 name="Enter Rise Delay (default=1.0e-9)" /><field263 name="Enter Fall Delay (default=1.0e-9)" /><field264 name="Enter Input Load (default=1.0e-12)" /></u90><u87 name="type">d_inverter<field265 name="Enter Rise Delay (default=1.0e-9)" /><field266 name="Enter Fall Delay (default=1.0e-9)" /><field267 name="Enter Input Load (default=1.0e-12)" /></u87><u88 name="type">d_inverter<field268 name="Enter Rise Delay (default=1.0e-9)" /><field269 name="Enter Fall Delay (default=1.0e-9)" /><field270 name="Enter Input Load (default=1.0e-12)" /></u88><u91 name="type">d_inverter<field271 name="Enter Rise Delay (default=1.0e-9)" /><field272 name="Enter Fall Delay (default=1.0e-9)" /><field273 name="Enter Input Load (default=1.0e-12)" /></u91></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54154/analysis b/library/SubcircuitLibrary/SN54154/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54154/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-07-05 01:37:16 +0000