diff options
Diffstat (limited to 'library/SubcircuitLibrary/HD74HC149')
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149.cir | 52 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149.cir.out | 148 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149.pro | 83 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149.sch | 1012 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149.sub | 142 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HD74HC149/analysis | 1 |
7 files changed, 1439 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/HD74HC149/74149.cir b/library/SubcircuitLibrary/HD74HC149/74149.cir new file mode 100644 index 00000000..c1bd662d --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.cir @@ -0,0 +1,52 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74149\74149.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/12/25 14:03:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad9_ Net-_U14-Pad1_ d_inverter +U3 Net-_U1-Pad8_ Net-_U11-Pad1_ d_inverter +U4 Net-_U1-Pad7_ Net-_U12-Pad1_ d_inverter +U5 Net-_U1-Pad6_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U15-Pad1_ d_inverter +U7 Net-_U1-Pad4_ Net-_U16-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U19-Pad1_ d_inverter +U9 Net-_U1-Pad2_ Net-_U17-Pad1_ d_inverter +U10 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U18 Net-_U10-Pad2_ Net-_U18-Pad2_ d_inverter +U20 Net-_U18-Pad2_ Net-_U20-Pad2_ d_inverter +U21 Net-_U11-Pad1_ Net-_U14-Pad2_ Net-_U21-Pad3_ d_and +U24 Net-_U14-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad18_ d_nand +U25 Net-_U21-Pad3_ Net-_U20-Pad2_ Net-_U1-Pad17_ d_nand +X1 Net-_U12-Pad1_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U26-Pad1_ 3_and +X2 Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U27-Pad1_ 4_and +X3 Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U23-Pad1_ 4_and +U26 Net-_U26-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad16_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad15_ d_nand +X7 Net-_U15-Pad1_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U29-Pad1_ 3_and +U29 Net-_U29-Pad1_ Net-_U1-Pad14_ d_inverter +U22 Net-_U16-Pad1_ Net-_U15-Pad2_ Net-_U22-Pad3_ d_and +X4 Net-_U19-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_X4-Pad4_ 3_and +X5 Net-_U17-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_X10-Pad1_ 4_and +X6 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_U17-Pad2_ Net-_U23-Pad2_ 4_and +X8 Net-_U22-Pad3_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U30-Pad1_ 3_and +X9 Net-_X4-Pad4_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U31-Pad1_ 3_and +X10 Net-_X10-Pad1_ Net-_U23-Pad1_ Net-_U20-Pad2_ Net-_U32-Pad1_ 3_and +U28 Net-_U23-Pad3_ Net-_U20-Pad2_ Net-_U1-Pad10_ d_nand +U30 Net-_U30-Pad1_ Net-_U1-Pad13_ d_inverter +U31 Net-_U31-Pad1_ Net-_U1-Pad12_ d_inverter +U32 Net-_U32-Pad1_ Net-_U1-Pad11_ d_inverter +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/HD74HC149/74149.cir.out b/library/SubcircuitLibrary/HD74HC149/74149.cir.out new file mode 100644 index 00000000..6b56ec63 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.cir.out @@ -0,0 +1,148 @@ +* c:\fossee\esim\library\subcircuitlibrary\74149\74149.cir + +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad9_ net-_u14-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u4 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u5 net-_u1-pad6_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad4_ net-_u16-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u19-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u17-pad1_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u18-pad2_ d_inverter +* u20 net-_u18-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u24 net-_u14-pad1_ net-_u20-pad2_ net-_u1-pad18_ d_nand +* u25 net-_u21-pad3_ net-_u20-pad2_ net-_u1-pad17_ d_nand +x1 net-_u12-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u26-pad1_ 3_and +x2 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u27-pad1_ 4_and +x3 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u23-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u20-pad2_ net-_u1-pad16_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u20-pad2_ net-_u1-pad15_ d_nand +x7 net-_u15-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u29-pad1_ 3_and +* u29 net-_u29-pad1_ net-_u1-pad14_ d_inverter +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +x4 net-_u19-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_x4-pad4_ 3_and +x5 net-_u17-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_x10-pad1_ 4_and +x6 net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u17-pad2_ net-_u23-pad2_ 4_and +x8 net-_u22-pad3_ net-_u23-pad1_ net-_u20-pad2_ net-_u30-pad1_ 3_and +x9 net-_x4-pad4_ net-_u23-pad1_ net-_u20-pad2_ net-_u31-pad1_ 3_and +x10 net-_x10-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u32-pad1_ 3_and +* u28 net-_u23-pad3_ net-_u20-pad2_ net-_u1-pad10_ d_nand +* u30 net-_u30-pad1_ net-_u1-pad13_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad12_ d_inverter +* u32 net-_u32-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 net-_u1-pad9_ net-_u14-pad1_ u2 +a2 net-_u1-pad8_ net-_u11-pad1_ u3 +a3 net-_u1-pad7_ net-_u12-pad1_ u4 +a4 net-_u1-pad6_ net-_u13-pad1_ u5 +a5 net-_u1-pad5_ net-_u15-pad1_ u6 +a6 net-_u1-pad4_ net-_u16-pad1_ u7 +a7 net-_u1-pad3_ net-_u19-pad1_ u8 +a8 net-_u1-pad2_ net-_u17-pad1_ u9 +a9 net-_u1-pad1_ net-_u10-pad2_ u10 +a10 net-_u14-pad1_ net-_u14-pad2_ u14 +a11 net-_u11-pad1_ net-_u11-pad2_ u11 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u19-pad1_ net-_u19-pad2_ u19 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u10-pad2_ net-_u18-pad2_ u18 +a18 net-_u18-pad2_ net-_u20-pad2_ u20 +a19 [net-_u11-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a20 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u1-pad18_ u24 +a21 [net-_u21-pad3_ net-_u20-pad2_ ] net-_u1-pad17_ u25 +a22 [net-_u26-pad1_ net-_u20-pad2_ ] net-_u1-pad16_ u26 +a23 net-_u12-pad1_ net-_u12-pad2_ u12 +a24 [net-_u27-pad1_ net-_u20-pad2_ ] net-_u1-pad15_ u27 +a25 net-_u29-pad1_ net-_u1-pad14_ u29 +a26 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a27 [net-_u23-pad3_ net-_u20-pad2_ ] net-_u1-pad10_ u28 +a28 net-_u30-pad1_ net-_u1-pad13_ u30 +a29 net-_u31-pad1_ net-_u1-pad12_ u31 +a30 net-_u32-pad1_ net-_u1-pad11_ u32 +a31 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74HC149/74149.pro b/library/SubcircuitLibrary/HD74HC149/74149.pro new file mode 100644 index 00000000..1ae53d0a --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.pro @@ -0,0 +1,83 @@ +update=05/12/25 17:39:01 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/HD74HC149/74149.sch b/library/SubcircuitLibrary/HD74HC149/74149.sch new file mode 100644 index 00000000..762be4ab --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.sch @@ -0,0 +1,1012 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74149-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68219668 +P 2100 1000 +F 0 "U2" H 2100 900 60 0000 C CNN +F 1 "d_inverter" H 2100 1150 60 0000 C CNN +F 2 "" H 2150 950 60 0000 C CNN +F 3 "" H 2150 950 60 0000 C CNN + 1 2100 1000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6821967F +P 2100 1800 +F 0 "U3" H 2100 1700 60 0000 C CNN +F 1 "d_inverter" H 2100 1950 60 0000 C CNN +F 2 "" H 2150 1750 60 0000 C CNN +F 3 "" H 2150 1750 60 0000 C CNN + 1 2100 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68219698 +P 2100 2200 +F 0 "U4" H 2100 2100 60 0000 C CNN +F 1 "d_inverter" H 2100 2350 60 0000 C CNN +F 2 "" H 2150 2150 60 0000 C CNN +F 3 "" H 2150 2150 60 0000 C CNN + 1 2100 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 682196BF +P 2100 2600 +F 0 "U5" H 2100 2500 60 0000 C CNN +F 1 "d_inverter" H 2100 2750 60 0000 C CNN +F 2 "" H 2150 2550 60 0000 C CNN +F 3 "" H 2150 2550 60 0000 C CNN + 1 2100 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 682196E6 +P 2200 3750 +F 0 "U6" H 2200 3650 60 0000 C CNN +F 1 "d_inverter" H 2200 3900 60 0000 C CNN +F 2 "" H 2250 3700 60 0000 C CNN +F 3 "" H 2250 3700 60 0000 C CNN + 1 2200 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 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"U1" H 9350 5200 30 0000 C CNN +F 1 "PORT" H 9300 5100 30 0000 C CNN +F 2 "" H 9300 5100 60 0000 C CNN +F 3 "" H 9300 5100 60 0000 C CNN + 11 9300 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 68224F0B +P 9300 4700 +F 0 "U1" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 12 9300 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6822500E +P 9300 4300 +F 0 "U1" H 9350 4400 30 0000 C CNN +F 1 "PORT" H 9300 4300 30 0000 C CNN +F 2 "" H 9300 4300 60 0000 C CNN +F 3 "" H 9300 4300 60 0000 C CNN + 13 9300 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 682250D6 +P 9300 3850 +F 0 "U1" H 9350 3950 30 0000 C CNN +F 1 "PORT" H 9300 3850 30 0000 C CNN +F 2 "" H 9300 3850 60 0000 C CNN +F 3 "" H 9300 3850 60 0000 C CNN + 14 9300 3850 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5500 9050 5500 +Wire Wire Line + 8500 5100 9050 5100 +Wire Wire Line + 8500 4700 9050 4700 +Wire Wire Line + 8500 4300 9050 4300 +Wire Wire Line + 8450 3850 9050 3850 +$Comp +L PORT U1 +U 15 1 68225CA3 +P 9300 2700 +F 0 "U1" H 9350 2800 30 0000 C CNN +F 1 "PORT" H 9300 2700 30 0000 C CNN +F 2 "" H 9300 2700 60 0000 C CNN +F 3 "" H 9300 2700 60 0000 C CNN + 15 9300 2700 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 2700 9050 2700 +$Comp +L PORT U1 +U 16 1 68225FD7 +P 9300 2050 +F 0 "U1" H 9350 2150 30 0000 C CNN +F 1 "PORT" H 9300 2050 30 0000 C CNN +F 2 "" H 9300 2050 60 0000 C CNN +F 3 "" H 9300 2050 60 0000 C CNN + 16 9300 2050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 2050 9050 2050 +$Comp +L PORT U1 +U 17 1 68226BC9 +P 9300 1350 +F 0 "U1" H 9350 1450 30 0000 C CNN +F 1 "PORT" H 9300 1350 30 0000 C CNN +F 2 "" H 9300 1350 60 0000 C CNN +F 3 "" H 9300 1350 60 0000 C CNN + 17 9300 1350 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 1350 9050 1350 +$Comp +L PORT U1 +U 18 1 68226F4F +P 9300 900 +F 0 "U1" H 9350 1000 30 0000 C CNN +F 1 "PORT" H 9300 900 30 0000 C CNN +F 2 "" H 9300 900 60 0000 C CNN +F 3 "" H 9300 900 60 0000 C CNN + 18 9300 900 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 950 9050 950 +Wire Wire Line + 9050 950 9050 900 +Wire Wire Line + 1750 5650 1900 5650 +Wire Wire Line + 5650 4050 6800 4050 +Wire Wire Line + 6800 4050 6800 4200 +Wire Wire Line + 5600 4650 6800 4650 +Wire Wire Line + 6800 4650 6800 4600 +Wire Wire Line + 5650 5250 5650 5000 +Wire Wire Line + 5650 5000 6800 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74HC149/74149.sub b/library/SubcircuitLibrary/HD74HC149/74149.sub new file mode 100644 index 00000000..8de8694c --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149.sub @@ -0,0 +1,142 @@ +* Subcircuit 74149 +.subckt 74149 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\fossee\esim\library\subcircuitlibrary\74149\74149.cir +.include 3_and.sub +.include 4_and.sub +* u2 net-_u1-pad9_ net-_u14-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u4 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u5 net-_u1-pad6_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad4_ net-_u16-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u19-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u17-pad1_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u18-pad2_ d_inverter +* u20 net-_u18-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u24 net-_u14-pad1_ net-_u20-pad2_ net-_u1-pad18_ d_nand +* u25 net-_u21-pad3_ net-_u20-pad2_ net-_u1-pad17_ d_nand +x1 net-_u12-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u26-pad1_ 3_and +x2 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u27-pad1_ 4_and +x3 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u23-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u20-pad2_ net-_u1-pad16_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u20-pad2_ net-_u1-pad15_ d_nand +x7 net-_u15-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u29-pad1_ 3_and +* u29 net-_u29-pad1_ net-_u1-pad14_ d_inverter +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +x4 net-_u19-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_x4-pad4_ 3_and +x5 net-_u17-pad1_ net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_x10-pad1_ 4_and +x6 net-_u15-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u17-pad2_ net-_u23-pad2_ 4_and +x8 net-_u22-pad3_ net-_u23-pad1_ net-_u20-pad2_ net-_u30-pad1_ 3_and +x9 net-_x4-pad4_ net-_u23-pad1_ net-_u20-pad2_ net-_u31-pad1_ 3_and +x10 net-_x10-pad1_ net-_u23-pad1_ net-_u20-pad2_ net-_u32-pad1_ 3_and +* u28 net-_u23-pad3_ net-_u20-pad2_ net-_u1-pad10_ d_nand +* u30 net-_u30-pad1_ net-_u1-pad13_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad12_ d_inverter +* u32 net-_u32-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nand +a1 net-_u1-pad9_ net-_u14-pad1_ u2 +a2 net-_u1-pad8_ net-_u11-pad1_ u3 +a3 net-_u1-pad7_ net-_u12-pad1_ u4 +a4 net-_u1-pad6_ net-_u13-pad1_ u5 +a5 net-_u1-pad5_ net-_u15-pad1_ u6 +a6 net-_u1-pad4_ net-_u16-pad1_ u7 +a7 net-_u1-pad3_ net-_u19-pad1_ u8 +a8 net-_u1-pad2_ net-_u17-pad1_ u9 +a9 net-_u1-pad1_ net-_u10-pad2_ u10 +a10 net-_u14-pad1_ net-_u14-pad2_ u14 +a11 net-_u11-pad1_ net-_u11-pad2_ u11 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u19-pad1_ net-_u19-pad2_ u19 +a16 net-_u17-pad1_ net-_u17-pad2_ u17 +a17 net-_u10-pad2_ net-_u18-pad2_ u18 +a18 net-_u18-pad2_ net-_u20-pad2_ u20 +a19 [net-_u11-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a20 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u1-pad18_ u24 +a21 [net-_u21-pad3_ net-_u20-pad2_ ] net-_u1-pad17_ u25 +a22 [net-_u26-pad1_ net-_u20-pad2_ ] net-_u1-pad16_ u26 +a23 net-_u12-pad1_ net-_u12-pad2_ u12 +a24 [net-_u27-pad1_ net-_u20-pad2_ ] net-_u1-pad15_ u27 +a25 net-_u29-pad1_ net-_u1-pad14_ u29 +a26 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a27 [net-_u23-pad3_ net-_u20-pad2_ ] net-_u1-pad10_ u28 +a28 net-_u30-pad1_ net-_u1-pad13_ u30 +a29 net-_u31-pad1_ net-_u1-pad12_ u31 +a30 net-_u32-pad1_ net-_u1-pad11_ u32 +a31 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74149
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml b/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml new file mode 100644 index 00000000..1279b07e --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/74149_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u16><u19 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u19><u17 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u12 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u12><u27 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u27><u29 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u22 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u22><u28 name="type">d_nand<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u30 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u32><u23 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74HC149/analysis b/library/SubcircuitLibrary/HD74HC149/analysis new file mode 100644 index 00000000..5c9b0b46 --- /dev/null +++ b/library/SubcircuitLibrary/HD74HC149/analysis @@ -0,0 +1 @@ +.tran 10e-03 20e-00 0e-03
\ No newline at end of file |