diff options
Diffstat (limited to 'library/SubcircuitLibrary/HCC4076B')
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B-cache.lib | 144 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B.cir | 36 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B.cir.out | 112 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B.pro | 73 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B.sch | 781 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B.sub | 106 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/HCC4076B_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/HCC4076B/analysis | 1 |
8 files changed, 1254 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B-cache.lib b/library/SubcircuitLibrary/HCC4076B/HCC4076B-cache.lib new file mode 100644 index 00000000..3710734e --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B-cache.lib @@ -0,0 +1,144 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir b/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir new file mode 100644 index 00000000..e056745b --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\HCC4076B\HCC4076B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/09/25 15:34:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U29-Pad2_ d_nand +U6 Net-_U10-Pad2_ Net-_U11-Pad2_ d_inverter +U7 Net-_U21-Pad5_ Net-_U11-Pad2_ Net-_U17-Pad1_ d_and +U8 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U17-Pad2_ d_and +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_or +U21 Net-_U17-Pad3_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad4_ Net-_U21-Pad5_ Net-_U21-Pad6_ d_dff +U29 Net-_U21-Pad6_ Net-_U29-Pad2_ Net-_U1-Pad12_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT +U9 Net-_U22-Pad5_ Net-_U11-Pad2_ Net-_U18-Pad1_ d_and +U10 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U18 Net-_U18-Pad1_ Net-_U10-Pad3_ Net-_U18-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad4_ Net-_U22-Pad5_ Net-_U22-Pad6_ d_dff +U30 Net-_U22-Pad6_ Net-_U29-Pad2_ Net-_U1-Pad13_ d_tristate +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U10-Pad2_ d_nand +U2 Net-_U1-Pad7_ Net-_U2-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U19 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_or +U23 Net-_U19-Pad3_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad4_ Net-_U11-Pad1_ Net-_U23-Pad6_ d_dff +U31 Net-_U23-Pad6_ Net-_U29-Pad2_ Net-_U1-Pad14_ d_tristate +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U15 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U15-Pad3_ d_and +U20 Net-_U13-Pad3_ Net-_U15-Pad3_ Net-_U20-Pad3_ d_or +U24 Net-_U20-Pad3_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad4_ Net-_U13-Pad1_ Net-_U24-Pad6_ d_dff +U32 Net-_U24-Pad6_ Net-_U29-Pad2_ Net-_U1-Pad15_ d_tristate +U5 Net-_U1-Pad5_ Net-_U21-Pad4_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir.out b/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir.out new file mode 100644 index 00000000..4e45fd2e --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B.cir.out @@ -0,0 +1,112 @@ +* c:\fossee\esim\library\subcircuitlibrary\hcc4076b\hcc4076b.cir + +* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u29-pad2_ d_nand +* u6 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u7 net-_u21-pad5_ net-_u11-pad2_ net-_u17-pad1_ d_and +* u8 net-_u1-pad8_ net-_u10-pad2_ net-_u17-pad2_ d_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ d_dff +* u29 net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port +* u9 net-_u22-pad5_ net-_u11-pad2_ net-_u18-pad1_ d_and +* u10 net-_u1-pad9_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u18 net-_u18-pad1_ net-_u10-pad3_ net-_u18-pad3_ d_or +* u22 net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ d_dff +* u30 net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ d_tristate +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_nand +* u2 net-_u1-pad7_ net-_u2-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or +* u23 net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ d_dff +* u31 net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ d_tristate +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u15 net-_u1-pad11_ net-_u10-pad2_ net-_u15-pad3_ d_and +* u20 net-_u13-pad3_ net-_u15-pad3_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ d_dff +* u32 net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ d_tristate +* u5 net-_u1-pad5_ net-_u21-pad4_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u29-pad2_ u4 +a2 net-_u10-pad2_ net-_u11-pad2_ u6 +a3 [net-_u21-pad5_ net-_u11-pad2_ ] net-_u17-pad1_ u7 +a4 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u17-pad2_ u8 +a5 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a6 net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ u21 +a7 net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ u29 +a8 [net-_u22-pad5_ net-_u11-pad2_ ] net-_u18-pad1_ u9 +a9 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a10 [net-_u18-pad1_ net-_u10-pad3_ ] net-_u18-pad3_ u18 +a11 net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ u22 +a12 net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ u30 +a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u3 +a14 net-_u1-pad7_ net-_u2-pad2_ u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19 +a18 net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ u23 +a19 net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ u31 +a20 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u13-pad3_ net-_u15-pad3_ ] net-_u20-pad3_ u20 +a23 net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ u24 +a24 net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ u32 +a25 net-_u1-pad5_ net-_u21-pad4_ u5 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u29 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u30 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u31 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u32 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B.pro b/library/SubcircuitLibrary/HCC4076B/HCC4076B.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B.sch b/library/SubcircuitLibrary/HCC4076B/HCC4076B.sch new file mode 100644 index 00000000..84b1e993 --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B.sch @@ -0,0 +1,781 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:HCC4076B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U4 +U 1 1 6846796A +P 18900 -250 +F 0 "U4" H 18900 -250 60 0000 C CNN +F 1 "d_nand" H 18950 -150 60 0000 C CNN +F 2 "" H 18900 -250 60 0000 C CNN +F 3 "" H 18900 -250 60 0000 C CNN + 1 18900 -250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6846796B +P 19600 500 +F 0 "U6" H 19600 400 60 0000 C CNN +F 1 "d_inverter" H 19600 650 60 0000 C CNN +F 2 "" H 19650 450 60 0000 C CNN +F 3 "" H 19650 450 60 0000 C CNN + 1 19600 500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 6846796C +P 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+Wire Wire Line + 24350 3350 24500 3350 +Wire Wire Line + 24500 2750 24350 2750 +Wire Wire Line + 24350 2750 24350 2550 +Wire Wire Line + 24500 5800 24500 6300 +Wire Wire Line + 24500 6300 24650 6300 +Wire Wire Line + 24650 5700 24500 5700 +Wire Wire Line + 24500 5700 24500 5400 +Wire Wire Line + 24450 7850 24500 7850 +Wire Wire Line + 24500 7250 24600 7250 +Wire Wire Line + 24600 7250 24600 7450 +Wire Wire Line + 24500 7850 24500 7250 +Wire Wire Line + 24650 6300 24650 5700 +Wire Wire Line + 24500 3350 24500 2750 +Wire Wire Line + 24550 950 24550 1550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B.sub b/library/SubcircuitLibrary/HCC4076B/HCC4076B.sub new file mode 100644 index 00000000..095324e0 --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B.sub @@ -0,0 +1,106 @@ +* Subcircuit HCC4076B +.subckt HCC4076B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ +* c:\fossee\esim\library\subcircuitlibrary\hcc4076b\hcc4076b.cir +* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u29-pad2_ d_nand +* u6 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u7 net-_u21-pad5_ net-_u11-pad2_ net-_u17-pad1_ d_and +* u8 net-_u1-pad8_ net-_u10-pad2_ net-_u17-pad2_ d_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ d_dff +* u29 net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ d_tristate +* u9 net-_u22-pad5_ net-_u11-pad2_ net-_u18-pad1_ d_and +* u10 net-_u1-pad9_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u18 net-_u18-pad1_ net-_u10-pad3_ net-_u18-pad3_ d_or +* u22 net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ d_dff +* u30 net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ d_tristate +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_nand +* u2 net-_u1-pad7_ net-_u2-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or +* u23 net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ d_dff +* u31 net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ d_tristate +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u15 net-_u1-pad11_ net-_u10-pad2_ net-_u15-pad3_ d_and +* u20 net-_u13-pad3_ net-_u15-pad3_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ d_dff +* u32 net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ d_tristate +* u5 net-_u1-pad5_ net-_u21-pad4_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u29-pad2_ u4 +a2 net-_u10-pad2_ net-_u11-pad2_ u6 +a3 [net-_u21-pad5_ net-_u11-pad2_ ] net-_u17-pad1_ u7 +a4 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u17-pad2_ u8 +a5 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a6 net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ u21 +a7 net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ u29 +a8 [net-_u22-pad5_ net-_u11-pad2_ ] net-_u18-pad1_ u9 +a9 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a10 [net-_u18-pad1_ net-_u10-pad3_ ] net-_u18-pad3_ u18 +a11 net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ u22 +a12 net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ u30 +a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u3 +a14 net-_u1-pad7_ net-_u2-pad2_ u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19 +a18 net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ u23 +a19 net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ u31 +a20 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u13-pad3_ net-_u15-pad3_ ] net-_u20-pad3_ u20 +a23 net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ u24 +a24 net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ u32 +a25 net-_u1-pad5_ net-_u21-pad4_ u5 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u29 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u30 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u31 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u32 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HCC4076B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HCC4076B/HCC4076B_Previous_Values.xml b/library/SubcircuitLibrary/HCC4076B/HCC4076B_Previous_Values.xml new file mode 100644 index 00000000..67e76ec4 --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/HCC4076B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u8><u17 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_dff<field16 name="Enter Clk Delay (default=1.0e-9)" /><field17 name="Enter Set Delay (default=1.0e-9)" /><field18 name="Enter Reset Delay (default=1.0)" /><field19 name="Enter IC (default=0)" /><field20 name="Enter value for Data Load (default=1.0e-12)" /><field21 name="Enter value for Clk Load (default=1.0e-12)" /><field22 name="Enter value for Set Load (default=1.0e-12)" /><field23 name="Enter value for Reset Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter Fall Delay (default=1.0e-9)" /></u21><u29 name="type">d_tristate<field26 name="Enter Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /><field28 name="Enter Enable Load (default=1.0e-12)" /></u29><u9 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /><field34 name="Enter Input Load (default=1.0e-12)" /></u10><u18 name="type">d_or<field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /><field37 name="Enter Input Load (default=1.0e-12)" /></u18><u22 name="type">d_dff<field38 name="Enter Clk Delay (default=1.0e-9)" /><field39 name="Enter Set Delay (default=1.0e-9)" /><field40 name="Enter Reset Delay (default=1.0)" /><field41 name="Enter IC (default=0)" /><field42 name="Enter value for Data Load (default=1.0e-12)" /><field43 name="Enter value for Clk Load (default=1.0e-12)" /><field44 name="Enter value for Set Load (default=1.0e-12)" /><field45 name="Enter value for Reset Load (default=1.0e-12)" /><field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /></u22><u30 name="type">d_tristate<field48 name="Enter Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /><field50 name="Enter Enable Load (default=1.0e-12)" /></u30><u3 name="type">d_nand<field51 name="Enter Rise Delay (default=1.0e-9)" /><field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field54 name="Enter Rise Delay (default=1.0e-9)" /><field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /></u2><u11 name="type">d_and<field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /></u12><u19 name="type">d_or<field63 name="Enter Rise Delay (default=1.0e-9)" /><field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_dff<field66 name="Enter Clk Delay (default=1.0e-9)" /><field67 name="Enter Set Delay (default=1.0e-9)" /><field68 name="Enter Reset Delay (default=1.0)" /><field69 name="Enter IC (default=0)" /><field70 name="Enter value for Data Load (default=1.0e-12)" /><field71 name="Enter value for Clk Load (default=1.0e-12)" /><field72 name="Enter value for Set Load (default=1.0e-12)" /><field73 name="Enter value for Reset Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u23><u31 name="type">d_tristate<field76 name="Enter Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Enable Load (default=1.0e-12)" /></u31><u13 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_and<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u15><u20 name="type">d_or<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u20><u24 name="type">d_dff<field88 name="Enter Clk Delay (default=1.0e-9)" /><field89 name="Enter Set Delay (default=1.0e-9)" /><field90 name="Enter Reset Delay (default=1.0)" /><field91 name="Enter IC (default=0)" /><field92 name="Enter value for Data Load (default=1.0e-12)" /><field93 name="Enter value for Clk Load (default=1.0e-12)" /><field94 name="Enter value for Set Load (default=1.0e-12)" /><field95 name="Enter value for Reset Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /></u24><u32 name="type">d_tristate<field98 name="Enter Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Enable Load (default=1.0e-12)" /></u32><u5 name="type">d_inverter<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u5><u14 name="type">d_inverter<field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /><field106 name="Enter Input Load (default=1.0e-12)" /></u14><u16 name="type">d_inverter<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u16><u27 name="type">d_inverter<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u27><u25 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u25><u28 name="type">d_inverter<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u28><u26 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u26></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HCC4076B/analysis b/library/SubcircuitLibrary/HCC4076B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/HCC4076B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |