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-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib114
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.cir32
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.cir.out96
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.pro83
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.sch698
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.sub90
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/analysis1
8 files changed, 1115 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib b/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib
new file mode 100644
index 00000000..58420ef7
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480-cache.lib
@@ -0,0 +1,114 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.cir b/library/SubcircuitLibrary/CY74FCT480T/74480.cir
new file mode 100644
index 00000000..41b94a89
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.cir
@@ -0,0 +1,32 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74480\74480.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/20/25 19:44:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad1_ d_xor
+U5 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U10-Pad2_ d_xor
+U6 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U11-Pad1_ d_xor
+U7 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U11-Pad2_ d_xor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_xor
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_xor
+U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U14-Pad3_ d_xor
+U8 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U12-Pad1_ d_xor
+U9 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U12-Pad2_ d_xor
+U2 Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U13-Pad1_ d_xor
+U3 Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U13-Pad2_ d_xor
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_xor
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_xor
+U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U15-Pad3_ d_xor
+U20 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U1-Pad20_ d_xor
+U21 Net-_U15-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad22_ d_xor
+U22 Net-_U1-Pad20_ Net-_U1-Pad22_ Net-_U1-Pad21_ d_nor
+U18 Net-_U16-Pad3_ Net-_U18-Pad2_ d_inverter
+U16 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U16-Pad3_ d_and
+U17 Net-_U1-Pad10_ Net-_U1-Pad19_ Net-_U17-Pad3_ d_and
+U19 Net-_U17-Pad3_ Net-_U19-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out b/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out
new file mode 100644
index 00000000..59fd5704
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.cir.out
@@ -0,0 +1,96 @@
+* c:\fossee\esim\library\subcircuitlibrary\74480\74480.cir
+
+* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad1_ d_xor
+* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_xor
+* u6 net-_u1-pad5_ net-_u1-pad6_ net-_u11-pad1_ d_xor
+* u7 net-_u1-pad7_ net-_u1-pad8_ net-_u11-pad2_ d_xor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_xor
+* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_xor
+* u8 net-_u1-pad11_ net-_u1-pad12_ net-_u12-pad1_ d_xor
+* u9 net-_u1-pad13_ net-_u1-pad14_ net-_u12-pad2_ d_xor
+* u2 net-_u1-pad15_ net-_u1-pad16_ net-_u13-pad1_ d_xor
+* u3 net-_u1-pad17_ net-_u1-pad18_ net-_u13-pad2_ d_xor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_xor
+* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_xor
+* u20 net-_u14-pad3_ net-_u18-pad2_ net-_u1-pad20_ d_xor
+* u21 net-_u15-pad3_ net-_u19-pad2_ net-_u1-pad22_ d_xor
+* u22 net-_u1-pad20_ net-_u1-pad22_ net-_u1-pad21_ d_nor
+* u18 net-_u16-pad3_ net-_u18-pad2_ d_inverter
+* u16 net-_u1-pad9_ net-_u1-pad10_ net-_u16-pad3_ d_and
+* u17 net-_u1-pad10_ net-_u1-pad19_ net-_u17-pad3_ d_and
+* u19 net-_u17-pad3_ net-_u19-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad1_ u4
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u5
+a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u11-pad1_ u6
+a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u11-pad2_ u7
+a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14
+a8 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u12-pad1_ u8
+a9 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u12-pad2_ u9
+a10 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u13-pad1_ u2
+a11 [net-_u1-pad17_ net-_u1-pad18_ ] net-_u13-pad2_ u3
+a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u1-pad20_ u20
+a16 [net-_u15-pad3_ net-_u19-pad2_ ] net-_u1-pad22_ u21
+a17 [net-_u1-pad20_ net-_u1-pad22_ ] net-_u1-pad21_ u22
+a18 net-_u16-pad3_ net-_u18-pad2_ u18
+a19 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u16-pad3_ u16
+a20 [net-_u1-pad10_ net-_u1-pad19_ ] net-_u17-pad3_ u17
+a21 net-_u17-pad3_ net-_u19-pad2_ u19
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u15 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.pro b/library/SubcircuitLibrary/CY74FCT480T/74480.pro
new file mode 100644
index 00000000..52048d93
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.pro
@@ -0,0 +1,83 @@
+update=05/06/25 21:00:50
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.sch b/library/SubcircuitLibrary/CY74FCT480T/74480.sch
new file mode 100644
index 00000000..12144421
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.sch
@@ -0,0 +1,698 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U4
+U 1 1 6804FCB9
+P 2950 1100
+F 0 "U4" H 2950 1100 60 0000 C CNN
+F 1 "d_xor" H 3000 1200 47 0000 C CNN
+F 2 "" H 2950 1100 60 0000 C CNN
+F 3 "" H 2950 1100 60 0000 C CNN
+ 1 2950 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U5
+U 1 1 6804FCEE
+P 2950 1550
+F 0 "U5" H 2950 1550 60 0000 C CNN
+F 1 "d_xor" H 3000 1650 47 0000 C CNN
+F 2 "" H 2950 1550 60 0000 C CNN
+F 3 "" H 2950 1550 60 0000 C CNN
+ 1 2950 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U6
+U 1 1 6804FD11
+P 2950 2050
+F 0 "U6" H 2950 2050 60 0000 C CNN
+F 1 "d_xor" H 3000 2150 47 0000 C CNN
+F 2 "" H 2950 2050 60 0000 C CNN
+F 3 "" H 2950 2050 60 0000 C CNN
+ 1 2950 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U7
+U 1 1 6804FD38
+P 2950 2550
+F 0 "U7" H 2950 2550 60 0000 C CNN
+F 1 "d_xor" H 3000 2650 47 0000 C CNN
+F 2 "" H 2950 2550 60 0000 C CNN
+F 3 "" H 2950 2550 60 0000 C CNN
+ 1 2950 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U10
+U 1 1 6804FD5D
+P 4250 1300
+F 0 "U10" H 4250 1300 60 0000 C CNN
+F 1 "d_xor" H 4300 1400 47 0000 C CNN
+F 2 "" H 4250 1300 60 0000 C CNN
+F 3 "" H 4250 1300 60 0000 C CNN
+ 1 4250 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U11
+U 1 1 6804FD84
+P 4250 2300
+F 0 "U11" H 4250 2300 60 0000 C CNN
+F 1 "d_xor" H 4300 2400 47 0000 C CNN
+F 2 "" H 4250 2300 60 0000 C CNN
+F 3 "" H 4250 2300 60 0000 C CNN
+ 1 4250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U14
+U 1 1 6804FDB9
+P 5350 1750
+F 0 "U14" H 5350 1750 60 0000 C CNN
+F 1 "d_xor" H 5400 1850 47 0000 C CNN
+F 2 "" H 5350 1750 60 0000 C CNN
+F 3 "" H 5350 1750 60 0000 C CNN
+ 1 5350 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U8
+U 1 1 6804FDE2
+P 2950 3650
+F 0 "U8" H 2950 3650 60 0000 C CNN
+F 1 "d_xor" H 3000 3750 47 0000 C CNN
+F 2 "" H 2950 3650 60 0000 C CNN
+F 3 "" H 2950 3650 60 0000 C CNN
+ 1 2950 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U9
+U 1 1 6804FE11
+P 2950 4150
+F 0 "U9" H 2950 4150 60 0000 C CNN
+F 1 "d_xor" H 3000 4250 47 0000 C CNN
+F 2 "" H 2950 4150 60 0000 C CNN
+F 3 "" H 2950 4150 60 0000 C CNN
+ 1 2950 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U2
+U 1 1 6804FE42
+P 2900 4650
+F 0 "U2" H 2900 4650 60 0000 C CNN
+F 1 "d_xor" H 2950 4750 47 0000 C CNN
+F 2 "" H 2900 4650 60 0000 C CNN
+F 3 "" H 2900 4650 60 0000 C CNN
+ 1 2900 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 6804FE73
+P 2900 5100
+F 0 "U3" H 2900 5100 60 0000 C CNN
+F 1 "d_xor" H 2950 5200 47 0000 C CNN
+F 2 "" H 2900 5100 60 0000 C CNN
+F 3 "" H 2900 5100 60 0000 C CNN
+ 1 2900 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U12
+U 1 1 6804FEA4
+P 4300 3850
+F 0 "U12" H 4300 3850 60 0000 C CNN
+F 1 "d_xor" H 4350 3950 47 0000 C CNN
+F 2 "" H 4300 3850 60 0000 C CNN
+F 3 "" H 4300 3850 60 0000 C CNN
+ 1 4300 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U13
+U 1 1 6804FED3
+P 4350 4850
+F 0 "U13" H 4350 4850 60 0000 C CNN
+F 1 "d_xor" H 4400 4950 47 0000 C CNN
+F 2 "" H 4350 4850 60 0000 C CNN
+F 3 "" H 4350 4850 60 0000 C CNN
+ 1 4350 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U15
+U 1 1 6804FF0C
+P 5600 4350
+F 0 "U15" H 5600 4350 60 0000 C CNN
+F 1 "d_xor" H 5650 4450 47 0000 C CNN
+F 2 "" H 5600 4350 60 0000 C CNN
+F 3 "" H 5600 4350 60 0000 C CNN
+ 1 5600 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U20
+U 1 1 6804FF43
+P 7800 1700
+F 0 "U20" H 7800 1700 60 0000 C CNN
+F 1 "d_xor" H 7850 1800 47 0000 C CNN
+F 2 "" H 7800 1700 60 0000 C CNN
+F 3 "" H 7800 1700 60 0000 C CNN
+ 1 7800 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U21
+U 1 1 6804FF8C
+P 7850 4400
+F 0 "U21" H 7850 4400 60 0000 C CNN
+F 1 "d_xor" H 7900 4500 47 0000 C CNN
+F 2 "" H 7850 4400 60 0000 C CNN
+F 3 "" H 7850 4400 60 0000 C CNN
+ 1 7850 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U22
+U 1 1 6804FFCD
+P 9550 3050
+F 0 "U22" H 9550 3050 60 0000 C CNN
+F 1 "d_nor" H 9600 3150 60 0000 C CNN
+F 2 "" H 9550 3050 60 0000 C CNN
+F 3 "" H 9550 3050 60 0000 C CNN
+ 1 9550 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 68050016
+P 7200 2300
+F 0 "U18" H 7200 2200 60 0000 C CNN
+F 1 "d_inverter" H 7200 2450 60 0000 C CNN
+F 2 "" H 7250 2250 60 0000 C CNN
+F 3 "" H 7250 2250 60 0000 C CNN
+ 1 7200 2300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_and U16
+U 1 1 6805005D
+P 6700 2950
+F 0 "U16" H 6700 2950 60 0000 C CNN
+F 1 "d_and" H 6750 3050 60 0000 C CNN
+F 2 "" H 6700 2950 60 0000 C CNN
+F 3 "" H 6700 2950 60 0000 C CNN
+ 1 6700 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 680500A4
+P 6800 5450
+F 0 "U17" H 6800 5450 60 0000 C CNN
+F 1 "d_and" H 6850 5550 60 0000 C CNN
+F 2 "" H 6800 5450 60 0000 C CNN
+F 3 "" H 6800 5450 60 0000 C CNN
+ 1 6800 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 680500E7
+P 7350 4900
+F 0 "U19" H 7350 4800 60 0000 C CNN
+F 1 "d_inverter" H 7350 5050 60 0000 C CNN
+F 2 "" H 7400 4850 60 0000 C CNN
+F 3 "" H 7400 4850 60 0000 C CNN
+ 1 7350 4900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6805012C
+P 1550 900
+F 0 "U1" H 1600 1000 30 0000 C CNN
+F 1 "PORT" H 1550 900 30 0000 C CNN
+F 2 "" H 1550 900 60 0000 C CNN
+F 3 "" H 1550 900 60 0000 C CNN
+ 1 1550 900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6805029B
+P 1550 1100
+F 0 "U1" H 1600 1200 30 0000 C CNN
+F 1 "PORT" H 1550 1100 30 0000 C CNN
+F 2 "" H 1550 1100 60 0000 C CNN
+F 3 "" H 1550 1100 60 0000 C CNN
+ 2 1550 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 680502E2
+P 1550 1350
+F 0 "U1" H 1600 1450 30 0000 C CNN
+F 1 "PORT" H 1550 1350 30 0000 C CNN
+F 2 "" H 1550 1350 60 0000 C CNN
+F 3 "" H 1550 1350 60 0000 C CNN
+ 3 1550 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6805032D
+P 1550 1550
+F 0 "U1" H 1600 1650 30 0000 C CNN
+F 1 "PORT" H 1550 1550 30 0000 C CNN
+F 2 "" H 1550 1550 60 0000 C CNN
+F 3 "" H 1550 1550 60 0000 C CNN
+ 4 1550 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 680503C1
+P 1550 1800
+F 0 "U1" H 1600 1900 30 0000 C CNN
+F 1 "PORT" H 1550 1800 30 0000 C CNN
+F 2 "" H 1550 1800 60 0000 C CNN
+F 3 "" H 1550 1800 60 0000 C CNN
+ 5 1550 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68050412
+P 1550 2000
+F 0 "U1" H 1600 2100 30 0000 C CNN
+F 1 "PORT" H 1550 2000 30 0000 C CNN
+F 2 "" H 1550 2000 60 0000 C CNN
+F 3 "" H 1550 2000 60 0000 C CNN
+ 6 1550 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68050465
+P 1550 2300
+F 0 "U1" H 1600 2400 30 0000 C CNN
+F 1 "PORT" H 1550 2300 30 0000 C CNN
+F 2 "" H 1550 2300 60 0000 C CNN
+F 3 "" H 1550 2300 60 0000 C CNN
+ 7 1550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 680504B8
+P 1550 2500
+F 0 "U1" H 1600 2600 30 0000 C CNN
+F 1 "PORT" H 1550 2500 30 0000 C CNN
+F 2 "" H 1550 2500 60 0000 C CNN
+F 3 "" H 1550 2500 60 0000 C CNN
+ 8 1550 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68050543
+P 1550 2750
+F 0 "U1" H 1600 2850 30 0000 C CNN
+F 1 "PORT" H 1550 2750 30 0000 C CNN
+F 2 "" H 1550 2750 60 0000 C CNN
+F 3 "" H 1550 2750 60 0000 C CNN
+ 9 1550 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6805059A
+P 1550 3050
+F 0 "U1" H 1600 3150 30 0000 C CNN
+F 1 "PORT" H 1550 3050 30 0000 C CNN
+F 2 "" H 1550 3050 60 0000 C CNN
+F 3 "" H 1550 3050 60 0000 C CNN
+ 10 1550 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 680505EF
+P 1550 3450
+F 0 "U1" H 1600 3550 30 0000 C CNN
+F 1 "PORT" H 1550 3450 30 0000 C CNN
+F 2 "" H 1550 3450 60 0000 C CNN
+F 3 "" H 1550 3450 60 0000 C CNN
+ 11 1550 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6805064C
+P 1550 3700
+F 0 "U1" H 1600 3800 30 0000 C CNN
+F 1 "PORT" H 1550 3700 30 0000 C CNN
+F 2 "" H 1550 3700 60 0000 C CNN
+F 3 "" H 1550 3700 60 0000 C CNN
+ 12 1550 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 680506A9
+P 1550 4000
+F 0 "U1" H 1600 4100 30 0000 C CNN
+F 1 "PORT" H 1550 4000 30 0000 C CNN
+F 2 "" H 1550 4000 60 0000 C CNN
+F 3 "" H 1550 4000 60 0000 C CNN
+ 13 1550 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68050702
+P 1550 4200
+F 0 "U1" H 1600 4300 30 0000 C CNN
+F 1 "PORT" H 1550 4200 30 0000 C CNN
+F 2 "" H 1550 4200 60 0000 C CNN
+F 3 "" H 1550 4200 60 0000 C CNN
+ 14 1550 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6805075F
+P 1550 4450
+F 0 "U1" H 1600 4550 30 0000 C CNN
+F 1 "PORT" H 1550 4450 30 0000 C CNN
+F 2 "" H 1550 4450 60 0000 C CNN
+F 3 "" H 1550 4450 60 0000 C CNN
+ 15 1550 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 680507CC
+P 1550 4650
+F 0 "U1" H 1600 4750 30 0000 C CNN
+F 1 "PORT" H 1550 4650 30 0000 C CNN
+F 2 "" H 1550 4650 60 0000 C CNN
+F 3 "" H 1550 4650 60 0000 C CNN
+ 16 1550 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 68050831
+P 1550 4900
+F 0 "U1" H 1600 5000 30 0000 C CNN
+F 1 "PORT" H 1550 4900 30 0000 C CNN
+F 2 "" H 1550 4900 60 0000 C CNN
+F 3 "" H 1550 4900 60 0000 C CNN
+ 17 1550 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 68050896
+P 1550 5100
+F 0 "U1" H 1600 5200 30 0000 C CNN
+F 1 "PORT" H 1550 5100 30 0000 C CNN
+F 2 "" H 1550 5100 60 0000 C CNN
+F 3 "" H 1550 5100 60 0000 C CNN
+ 18 1550 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 680509C6
+P 1550 5350
+F 0 "U1" H 1600 5450 30 0000 C CNN
+F 1 "PORT" H 1550 5350 30 0000 C CNN
+F 2 "" H 1550 5350 60 0000 C CNN
+F 3 "" H 1550 5350 60 0000 C CNN
+ 19 1550 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 21 1 68050B25
+P 10750 3000
+F 0 "U1" H 10800 3100 30 0000 C CNN
+F 1 "PORT" H 10750 3000 30 0000 C CNN
+F 2 "" H 10750 3000 60 0000 C CNN
+F 3 "" H 10750 3000 60 0000 C CNN
+ 21 10750 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 68050B96
+P 10700 1300
+F 0 "U1" H 10750 1400 30 0000 C CNN
+F 1 "PORT" H 10700 1300 30 0000 C CNN
+F 2 "" H 10700 1300 60 0000 C CNN
+F 3 "" H 10700 1300 60 0000 C CNN
+ 20 10700 1300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 68050C07
+P 10700 4300
+F 0 "U1" H 10750 4400 30 0000 C CNN
+F 1 "PORT" H 10700 4300 30 0000 C CNN
+F 2 "" H 10700 4300 60 0000 C CNN
+F 3 "" H 10700 4300 60 0000 C CNN
+ 22 10700 4300
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 1800 900 2500 900
+Wire Wire Line
+ 2500 900 2500 1000
+Wire Wire Line
+ 1800 1100 2500 1100
+Wire Wire Line
+ 1800 1350 2500 1350
+Wire Wire Line
+ 2500 1350 2500 1450
+Wire Wire Line
+ 1800 1550 2500 1550
+Wire Wire Line
+ 3400 1050 3800 1050
+Wire Wire Line
+ 3800 1050 3800 1200
+Wire Wire Line
+ 3400 1500 3800 1500
+Wire Wire Line
+ 3800 1500 3800 1300
+Wire Wire Line
+ 1800 1800 2500 1800
+Wire Wire Line
+ 2500 1800 2500 1950
+Wire Wire Line
+ 1800 2000 1800 2050
+Wire Wire Line
+ 1800 2050 2500 2050
+Wire Wire Line
+ 3400 2000 3800 2000
+Wire Wire Line
+ 3800 2000 3800 2200
+Wire Wire Line
+ 1800 2300 2500 2300
+Wire Wire Line
+ 2500 2300 2500 2450
+Wire Wire Line
+ 1800 2500 2500 2500
+Wire Wire Line
+ 2500 2500 2500 2550
+Wire Wire Line
+ 3400 2500 3800 2500
+Wire Wire Line
+ 3800 2500 3800 2300
+Wire Wire Line
+ 1800 2750 6250 2750
+Wire Wire Line
+ 6250 2750 6250 2850
+Wire Wire Line
+ 4700 1250 4900 1250
+Wire Wire Line
+ 4900 1250 4900 1650
+Wire Wire Line
+ 4700 2250 4900 2250
+Wire Wire Line
+ 4900 2250 4900 1750
+Wire Wire Line
+ 7150 2900 7200 2900
+Wire Wire Line
+ 7200 2900 7200 2600
+Wire Wire Line
+ 5800 1700 6650 1700
+Wire Wire Line
+ 6650 1700 6650 1600
+Wire Wire Line
+ 6650 1600 7350 1600
+Wire Wire Line
+ 7200 2000 7200 1700
+Wire Wire Line
+ 7200 1700 7350 1700
+Wire Wire Line
+ 1800 3050 6150 3050
+Wire Wire Line
+ 6350 5350 6150 5350
+Wire Wire Line
+ 6150 5350 6150 2950
+Wire Wire Line
+ 6150 2950 6250 2950
+Connection ~ 6150 3050
+Wire Wire Line
+ 6050 4300 7400 4300
+Wire Wire Line
+ 7400 4400 7350 4400
+Wire Wire Line
+ 7350 4400 7350 4600
+Wire Wire Line
+ 7250 5400 7350 5400
+Wire Wire Line
+ 7350 5400 7350 5200
+Wire Wire Line
+ 1800 5350 5700 5350
+Wire Wire Line
+ 5700 5350 5700 5450
+Wire Wire Line
+ 5700 5450 6350 5450
+Wire Wire Line
+ 1800 3450 2500 3450
+Wire Wire Line
+ 2500 3450 2500 3550
+Wire Wire Line
+ 1800 3700 2500 3700
+Wire Wire Line
+ 2500 3700 2500 3650
+Wire Wire Line
+ 1800 4000 2500 4000
+Wire Wire Line
+ 2500 4000 2500 4050
+Wire Wire Line
+ 1800 4200 2500 4200
+Wire Wire Line
+ 2500 4200 2500 4150
+Wire Wire Line
+ 1800 4450 2400 4450
+Wire Wire Line
+ 2400 4450 2400 4550
+Wire Wire Line
+ 2400 4550 2450 4550
+Wire Wire Line
+ 1800 4650 2450 4650
+Wire Wire Line
+ 1800 4900 2450 4900
+Wire Wire Line
+ 2450 4900 2450 5000
+Wire Wire Line
+ 1800 5100 2450 5100
+Wire Wire Line
+ 3400 3600 3850 3600
+Wire Wire Line
+ 3850 3600 3850 3750
+Wire Wire Line
+ 3400 4100 3850 4100
+Wire Wire Line
+ 3850 4100 3850 3850
+Wire Wire Line
+ 3350 4600 3900 4600
+Wire Wire Line
+ 3900 4600 3900 4750
+Wire Wire Line
+ 3350 5050 3900 5050
+Wire Wire Line
+ 3900 5050 3900 4850
+Wire Wire Line
+ 4750 3800 5150 3800
+Wire Wire Line
+ 5150 3800 5150 4250
+Wire Wire Line
+ 4800 4800 5150 4800
+Wire Wire Line
+ 5150 4800 5150 4350
+Wire Wire Line
+ 8250 1650 10450 1650
+Wire Wire Line
+ 10450 1650 10450 1300
+Wire Wire Line
+ 8500 1650 8500 2950
+Wire Wire Line
+ 8500 2950 9100 2950
+Connection ~ 8500 1650
+Wire Wire Line
+ 8300 4350 10450 4350
+Wire Wire Line
+ 10450 4350 10450 4300
+Wire Wire Line
+ 9100 3050 8700 3050
+Wire Wire Line
+ 8700 3050 8700 4350
+Connection ~ 8700 4350
+Wire Wire Line
+ 10000 3000 10500 3000
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.sub b/library/SubcircuitLibrary/CY74FCT480T/74480.sub
new file mode 100644
index 00000000..d91baa60
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.sub
@@ -0,0 +1,90 @@
+* Subcircuit 74480
+.subckt 74480 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_
+* c:\fossee\esim\library\subcircuitlibrary\74480\74480.cir
+* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad1_ d_xor
+* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_xor
+* u6 net-_u1-pad5_ net-_u1-pad6_ net-_u11-pad1_ d_xor
+* u7 net-_u1-pad7_ net-_u1-pad8_ net-_u11-pad2_ d_xor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_xor
+* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_xor
+* u8 net-_u1-pad11_ net-_u1-pad12_ net-_u12-pad1_ d_xor
+* u9 net-_u1-pad13_ net-_u1-pad14_ net-_u12-pad2_ d_xor
+* u2 net-_u1-pad15_ net-_u1-pad16_ net-_u13-pad1_ d_xor
+* u3 net-_u1-pad17_ net-_u1-pad18_ net-_u13-pad2_ d_xor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_xor
+* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_xor
+* u20 net-_u14-pad3_ net-_u18-pad2_ net-_u1-pad20_ d_xor
+* u21 net-_u15-pad3_ net-_u19-pad2_ net-_u1-pad22_ d_xor
+* u22 net-_u1-pad20_ net-_u1-pad22_ net-_u1-pad21_ d_nor
+* u18 net-_u16-pad3_ net-_u18-pad2_ d_inverter
+* u16 net-_u1-pad9_ net-_u1-pad10_ net-_u16-pad3_ d_and
+* u17 net-_u1-pad10_ net-_u1-pad19_ net-_u17-pad3_ d_and
+* u19 net-_u17-pad3_ net-_u19-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad1_ u4
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u5
+a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u11-pad1_ u6
+a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u11-pad2_ u7
+a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14
+a8 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u12-pad1_ u8
+a9 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u12-pad2_ u9
+a10 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u13-pad1_ u2
+a11 [net-_u1-pad17_ net-_u1-pad18_ ] net-_u13-pad2_ u3
+a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u1-pad20_ u20
+a16 [net-_u15-pad3_ net-_u19-pad2_ ] net-_u1-pad22_ u21
+a17 [net-_u1-pad20_ net-_u1-pad22_ ] net-_u1-pad21_ u22
+a18 net-_u16-pad3_ net-_u18-pad2_ u18
+a19 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u16-pad3_ u16
+a20 [net-_u1-pad10_ net-_u1-pad19_ ] net-_u17-pad3_ u17
+a21 net-_u17-pad3_ net-_u19-pad2_ u19
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u15 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74480 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml b/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml
new file mode 100644
index 00000000..cca77fc4
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/74480_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_xor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_xor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_xor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u11><u14 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_xor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_xor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u2 name="type">d_xor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xor<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_xor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_xor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_xor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u20 name="type">d_xor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u22><u18 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u19></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/CY74FCT480T/analysis b/library/SubcircuitLibrary/CY74FCT480T/analysis
new file mode 100644
index 00000000..5c9b0b46
--- /dev/null
+++ b/library/SubcircuitLibrary/CY74FCT480T/analysis
@@ -0,0 +1 @@
+.tran 10e-03 20e-00 0e-03 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-05-24 00:20:19 +0000