diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4529BM')
17 files changed, 2424 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4529BM/3_and-cache.lib b/library/SubcircuitLibrary/CD4529BM/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4529BM/3_and.cir b/library/SubcircuitLibrary/CD4529BM/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4529BM/3_and.cir.out b/library/SubcircuitLibrary/CD4529BM/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4529BM/3_and.pro b/library/SubcircuitLibrary/CD4529BM/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4529BM/3_and.sch b/library/SubcircuitLibrary/CD4529BM/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4529BM/3_and.sub b/library/SubcircuitLibrary/CD4529BM/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4529BM/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4529BM/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM-cache.lib b/library/SubcircuitLibrary/CD4529BM/CD4529BM-cache.lib new file mode 100644 index 00000000..e473a8e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM-cache.lib @@ -0,0 +1,148 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir b/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir new file mode 100644 index 00000000..9f1de602 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir @@ -0,0 +1,67 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4529BM\CD4529BM.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/16/25 15:55:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad1_ Net-_U4-Pad2_ d_inverter +U6 Net-_U1-Pad3_ Net-_U6-Pad2_ d_inverter +U8 Net-_U1-Pad4_ Net-_U8-Pad2_ d_inverter +U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter +U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter +U7 Net-_U6-Pad2_ Net-_U7-Pad2_ d_inverter +U9 Net-_U8-Pad2_ Net-_U9-Pad2_ d_inverter +U25 Net-_U14-Pad2_ Net-_U25-Pad2_ d_inverter +M16 Net-_M1-Pad3_ Net-_M16-Pad2_ Net-_M12-Pad1_ VDD mosfet_p +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_M13-Pad3_ Net-_M14-Pad3_ Net-_M11-Pad3_ Net-_M10-Pad3_ Net-_M15-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad1_ Net-_M12-Pad1_ Net-_M1-Pad3_ Net-_M10-Pad1_ VDD GND PORT +U18 Net-_U11-Pad2_ Net-_U18-Pad2_ d_inverter +M6 Net-_M1-Pad3_ Net-_M6-Pad2_ Net-_M1-Pad1_ VDD mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U19 Net-_U15-Pad2_ Net-_U19-Pad2_ d_inverter +M8 Net-_M1-Pad3_ Net-_M8-Pad2_ Net-_M2-Pad1_ VDD mosfet_p +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U24 Net-_U16-Pad2_ Net-_U24-Pad2_ d_inverter +M15 Net-_M1-Pad3_ Net-_M15-Pad2_ Net-_M15-Pad3_ VDD mosfet_p +M9 Net-_M15-Pad3_ Net-_M9-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U20 Net-_U12-Pad2_ Net-_U20-Pad2_ d_inverter +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ VDD mosfet_p +M3 Net-_M10-Pad3_ Net-_M3-Pad2_ Net-_M10-Pad1_ GND mosfet_n +U21 Net-_U13-Pad2_ Net-_U21-Pad2_ d_inverter +M11 Net-_M10-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ VDD mosfet_p +M4 Net-_M11-Pad3_ Net-_M4-Pad2_ Net-_M10-Pad1_ GND mosfet_n +U23 Net-_U17-Pad2_ Net-_U23-Pad2_ d_inverter +M14 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M14-Pad3_ VDD mosfet_p +M7 Net-_M14-Pad3_ Net-_M7-Pad2_ Net-_M10-Pad1_ GND mosfet_n +U22 Net-_U10-Pad2_ Net-_U22-Pad2_ d_inverter +M13 Net-_M10-Pad1_ Net-_M13-Pad2_ Net-_M13-Pad3_ VDD mosfet_p +M5 Net-_M13-Pad3_ Net-_M5-Pad2_ Net-_M10-Pad1_ GND mosfet_n +X1 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U10-Pad1_ 3_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +X8 Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U17-Pad1_ 3_and +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +X4 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U13-Pad1_ 3_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +X3 Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U12-Pad1_ 3_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +X7 Net-_U9-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U16-Pad1_ 3_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +X6 Net-_U9-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U15-Pad1_ 3_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +X2 Net-_U9-Pad2_ Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U11-Pad1_ 3_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +X5 Net-_U9-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U14-Pad1_ 3_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U30 Net-_U10-Pad2_ Net-_U22-Pad2_ Net-_M13-Pad2_ Net-_M5-Pad2_ dac_bridge_2 +U31 Net-_U17-Pad2_ Net-_U23-Pad2_ Net-_M14-Pad2_ Net-_M7-Pad2_ dac_bridge_2 +U29 Net-_U13-Pad2_ Net-_U21-Pad2_ Net-_M11-Pad2_ Net-_M4-Pad2_ dac_bridge_2 +U28 Net-_U12-Pad2_ Net-_U20-Pad2_ Net-_M10-Pad2_ Net-_M3-Pad2_ dac_bridge_2 +U32 Net-_U16-Pad2_ Net-_U24-Pad2_ Net-_M15-Pad2_ Net-_M9-Pad2_ dac_bridge_2 +U27 Net-_U15-Pad2_ Net-_U19-Pad2_ Net-_M8-Pad2_ Net-_M2-Pad2_ dac_bridge_2 +U26 Net-_U11-Pad2_ Net-_U18-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad2_ dac_bridge_2 +U33 Net-_U14-Pad2_ Net-_U25-Pad2_ Net-_M16-Pad2_ Net-_M12-Pad2_ dac_bridge_2 + +.end diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir.out b/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir.out new file mode 100644 index 00000000..49ca170c --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM.cir.out @@ -0,0 +1,167 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4529bm\cd4529bm.cir + +.include 3_and.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u6-pad2_ d_inverter +* u8 net-_u1-pad4_ net-_u8-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u7-pad2_ d_inverter +* u9 net-_u8-pad2_ net-_u9-pad2_ d_inverter +* u25 net-_u14-pad2_ net-_u25-pad2_ d_inverter +m16 net-_m1-pad3_ net-_m16-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_m13-pad3_ net-_m14-pad3_ net-_m11-pad3_ net-_m10-pad3_ net-_m15-pad3_ net-_m2-pad1_ net-_m1-pad1_ net-_m12-pad1_ net-_m1-pad3_ net-_m10-pad1_ vdd gnd port +* u18 net-_u11-pad2_ net-_u18-pad2_ d_inverter +m6 net-_m1-pad3_ net-_m6-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u19 net-_u15-pad2_ net-_u19-pad2_ d_inverter +m8 net-_m1-pad3_ net-_m8-pad2_ net-_m2-pad1_ vdd CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u24 net-_u16-pad2_ net-_u24-pad2_ d_inverter +m15 net-_m1-pad3_ net-_m15-pad2_ net-_m15-pad3_ vdd CMOSP W=100u L=100u M=1 +m9 net-_m15-pad3_ net-_m9-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u20 net-_u12-pad2_ net-_u20-pad2_ d_inverter +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1 +m3 net-_m10-pad3_ net-_m3-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u21 net-_u13-pad2_ net-_u21-pad2_ d_inverter +m11 net-_m10-pad1_ net-_m11-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1 +m4 net-_m11-pad3_ net-_m4-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u23 net-_u17-pad2_ net-_u23-pad2_ d_inverter +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m14-pad3_ vdd CMOSP W=100u L=100u M=1 +m7 net-_m14-pad3_ net-_m7-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u22 net-_u10-pad2_ net-_u22-pad2_ d_inverter +m13 net-_m10-pad1_ net-_m13-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m13-pad3_ net-_m5-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +x1 net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u10-pad1_ 3_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x8 net-_u7-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u17-pad1_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +x4 net-_u7-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x3 net-_u7-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +x7 net-_u9-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u16-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x6 net-_u9-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u15-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +x2 net-_u9-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u11-pad1_ 3_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x5 net-_u9-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u14-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u30 net-_u10-pad2_ net-_u22-pad2_ net-_m13-pad2_ net-_m5-pad2_ dac_bridge_2 +* u31 net-_u17-pad2_ net-_u23-pad2_ net-_m14-pad2_ net-_m7-pad2_ dac_bridge_2 +* u29 net-_u13-pad2_ net-_u21-pad2_ net-_m11-pad2_ net-_m4-pad2_ dac_bridge_2 +* u28 net-_u12-pad2_ net-_u20-pad2_ net-_m10-pad2_ net-_m3-pad2_ dac_bridge_2 +* u32 net-_u16-pad2_ net-_u24-pad2_ net-_m15-pad2_ net-_m9-pad2_ dac_bridge_2 +* u27 net-_u15-pad2_ net-_u19-pad2_ net-_m8-pad2_ net-_m2-pad2_ dac_bridge_2 +* u26 net-_u11-pad2_ net-_u18-pad2_ net-_m6-pad2_ net-_m1-pad2_ dac_bridge_2 +* u33 net-_u14-pad2_ net-_u25-pad2_ net-_m16-pad2_ net-_m12-pad2_ dac_bridge_2 +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 net-_u1-pad1_ net-_u4-pad2_ u4 +a3 net-_u1-pad3_ net-_u6-pad2_ u6 +a4 net-_u1-pad4_ net-_u8-pad2_ u8 +a5 net-_u2-pad2_ net-_u3-pad2_ u3 +a6 net-_u4-pad2_ net-_u5-pad2_ u5 +a7 net-_u6-pad2_ net-_u7-pad2_ u7 +a8 net-_u8-pad2_ net-_u9-pad2_ u9 +a9 net-_u14-pad2_ net-_u25-pad2_ u25 +a10 net-_u11-pad2_ net-_u18-pad2_ u18 +a11 net-_u15-pad2_ net-_u19-pad2_ u19 +a12 net-_u16-pad2_ net-_u24-pad2_ u24 +a13 net-_u12-pad2_ net-_u20-pad2_ u20 +a14 net-_u13-pad2_ net-_u21-pad2_ u21 +a15 net-_u17-pad2_ net-_u23-pad2_ u23 +a16 net-_u10-pad2_ net-_u22-pad2_ u22 +a17 net-_u10-pad1_ net-_u10-pad2_ u10 +a18 net-_u17-pad1_ net-_u17-pad2_ u17 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 net-_u12-pad1_ net-_u12-pad2_ u12 +a21 net-_u16-pad1_ net-_u16-pad2_ u16 +a22 net-_u15-pad1_ net-_u15-pad2_ u15 +a23 net-_u11-pad1_ net-_u11-pad2_ u11 +a24 net-_u14-pad1_ net-_u14-pad2_ u14 +a25 [net-_u10-pad2_ net-_u22-pad2_ ] [net-_m13-pad2_ net-_m5-pad2_ ] u30 +a26 [net-_u17-pad2_ net-_u23-pad2_ ] [net-_m14-pad2_ net-_m7-pad2_ ] u31 +a27 [net-_u13-pad2_ net-_u21-pad2_ ] [net-_m11-pad2_ net-_m4-pad2_ ] u29 +a28 [net-_u12-pad2_ net-_u20-pad2_ ] [net-_m10-pad2_ net-_m3-pad2_ ] u28 +a29 [net-_u16-pad2_ net-_u24-pad2_ ] [net-_m15-pad2_ net-_m9-pad2_ ] u32 +a30 [net-_u15-pad2_ net-_u19-pad2_ ] [net-_m8-pad2_ net-_m2-pad2_ ] u27 +a31 [net-_u11-pad2_ net-_u18-pad2_ ] [net-_m6-pad2_ net-_m1-pad2_ ] u26 +a32 [net-_u14-pad2_ net-_u25-pad2_ ] [net-_m16-pad2_ net-_m12-pad2_ ] u33 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM.pro b/library/SubcircuitLibrary/CD4529BM/CD4529BM.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM.sch b/library/SubcircuitLibrary/CD4529BM/CD4529BM.sch new file mode 100644 index 00000000..a767effa --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM.sch @@ -0,0 +1,1500 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 684FD71E +P 20450 -850 +F 0 "U2" H 20450 -950 60 0000 C CNN +F 1 "d_inverter" H 20450 -700 60 0000 C CNN +F 2 "" H 20500 -900 60 0000 C CNN +F 3 "" H 20500 -900 60 0000 C CNN + 1 20450 -850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 684FD754 +P 21400 -900 +F 0 "U4" H 21400 -1000 60 0000 C CNN +F 1 "d_inverter" H 21400 -750 60 0000 C CNN +F 2 "" H 21450 -950 60 0000 C CNN +F 3 "" H 21450 -950 60 0000 C CNN + 1 21400 -900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 684FD78E +P 22500 -950 +F 0 "U6" H 22500 -1050 60 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60 0000 C CNN +F 2 "" H 25600 8750 60 0000 C CNN +F 3 "" H 25600 8750 60 0000 C CNN + 1 25550 8800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24900 8800 25250 8800 +$Comp +L 3_and X3 +U 1 1 68506EA2 +P 24400 7400 +F 0 "X3" H 24500 7350 60 0000 C CNN +F 1 "3_and" H 24550 7550 60 0000 C CNN +F 2 "" H 24400 7400 60 0000 C CNN +F 3 "" H 24400 7400 60 0000 C CNN + 1 24400 7400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68506EA8 +P 25550 7350 +F 0 "U12" H 25550 7250 60 0000 C CNN +F 1 "d_inverter" H 25550 7500 60 0000 C CNN +F 2 "" H 25600 7300 60 0000 C CNN +F 3 "" H 25600 7300 60 0000 C CNN + 1 25550 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24900 7350 25250 7350 +$Comp +L 3_and X7 +U 1 1 685070F5 +P 24500 5050 +F 0 "X7" H 24600 5000 60 0000 C CNN +F 1 "3_and" H 24650 5200 60 0000 C CNN +F 2 "" H 24500 5050 60 0000 C CNN +F 3 "" H 24500 5050 60 0000 C CNN + 1 24500 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 685070FB +P 25650 5000 +F 0 "U16" H 25650 4900 60 0000 C CNN +F 1 "d_inverter" H 25650 5150 60 0000 C CNN +F 2 "" H 25700 4950 60 0000 C CNN +F 3 "" H 25700 4950 60 0000 C CNN + 1 25650 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 25000 5000 25350 5000 +$Comp +L 3_and X6 +U 1 1 68507244 +P 24500 3750 +F 0 "X6" H 24600 3700 60 0000 C CNN +F 1 "3_and" H 24650 3900 60 0000 C CNN +F 2 "" H 24500 3750 60 0000 C CNN +F 3 "" H 24500 3750 60 0000 C CNN + 1 24500 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6850724A +P 25650 3700 +F 0 "U15" H 25650 3600 60 0000 C CNN +F 1 "d_inverter" H 25650 3850 60 0000 C CNN +F 2 "" H 25700 3650 60 0000 C CNN +F 3 "" H 25700 3650 60 0000 C CNN + 1 25650 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 25000 3700 25350 3700 +$Comp +L 3_and X2 +U 1 1 6850741F +P 24300 2400 +F 0 "X2" H 24400 2350 60 0000 C CNN +F 1 "3_and" H 24450 2550 60 0000 C CNN +F 2 "" H 24300 2400 60 0000 C CNN +F 3 "" H 24300 2400 60 0000 C CNN + 1 24300 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68507425 +P 25450 2350 +F 0 "U11" H 25450 2250 60 0000 C CNN +F 1 "d_inverter" H 25450 2500 60 0000 C CNN +F 2 "" H 25500 2300 60 0000 C CNN +F 3 "" H 25500 2300 60 0000 C CNN + 1 25450 2350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24800 2350 25150 2350 +$Comp +L 3_and X5 +U 1 1 6850758D +P 24500 850 +F 0 "X5" H 24600 800 60 0000 C CNN +F 1 "3_and" H 24650 1000 60 0000 C CNN +F 2 "" H 24500 850 60 0000 C CNN +F 3 "" H 24500 850 60 0000 C CNN + 1 24500 850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 68507593 +P 25650 800 +F 0 "U14" H 25650 700 60 0000 C CNN +F 1 "d_inverter" H 25650 950 60 0000 C CNN +F 2 "" H 25700 750 60 0000 C CNN +F 3 "" H 25700 750 60 0000 C CNN + 1 25650 800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 25000 800 25350 800 +Wire Wire Line + 30300 750 30850 750 +Wire Wire Line + 30850 750 30850 4950 +Wire Wire Line + 30850 2300 29950 2300 +Connection ~ 29950 2300 +Connection ~ 30300 750 +Wire Wire Line + 30850 3650 30000 3650 +Connection ~ 30000 3650 +Connection ~ 30850 2300 +Wire Wire Line + 30850 4950 30200 4950 +Connection ~ 30200 4950 +Connection ~ 30850 3650 +Wire Wire Line + 30000 7300 30900 7300 +Wire Wire Line + 30900 7300 30900 12050 +Wire Wire Line + 30900 8750 30000 8750 +Connection ~ 30000 8750 +Connection ~ 30000 7300 +Wire Wire Line + 30900 10350 30150 10350 +Connection ~ 30150 10350 +Connection ~ 30900 8750 +Wire Wire Line + 30900 12050 30100 12050 +Connection ~ 30100 12050 +Connection ~ 30900 10350 +Wire Wire Line + 20450 400 20450 12200 +Wire Wire Line + 20450 12200 23900 12200 +Wire Wire Line + 24150 10500 20450 10500 +Connection ~ 20450 10500 +Wire Wire Line + 24150 5100 20450 5100 +Connection ~ 20450 5100 +Wire Wire Line + 24150 3800 20450 3800 +Connection ~ 20450 3800 +Wire Wire Line + 20450 -300 20950 -300 +Wire Wire Line + 20950 -300 20950 8900 +Wire Wire Line + 20950 8900 24050 8900 +Connection ~ 20450 -300 +Wire Wire Line + 24050 7450 20950 7450 +Connection ~ 20950 7450 +Wire Wire Line + 23950 2450 20950 2450 +Connection ~ 20950 2450 +Wire Wire Line + 24150 900 20950 900 +Connection ~ 20950 900 +Wire Wire Line + 21400 450 21400 12100 +Wire Wire Line + 21400 12100 23900 12100 +Wire Wire Line + 24050 8800 21400 8800 +Connection ~ 21400 8800 +Wire Wire Line + 24150 5000 21400 5000 +Connection ~ 21400 5000 +Wire Wire Line + 23950 2350 21400 2350 +Connection ~ 21400 2350 +Wire Wire Line + 21400 -350 22000 -350 +Wire Wire Line + 22000 -350 22000 10400 +Wire Wire Line + 22000 10400 24150 10400 +Connection ~ 21400 -350 +Wire Wire Line + 24050 7350 22000 7350 +Connection ~ 22000 7350 +Wire Wire Line + 24150 3700 22000 3700 +Connection ~ 22000 3700 +Wire Wire Line + 24150 800 22000 800 +Connection ~ 22000 800 +Wire Wire Line + 22500 400 22500 12000 +Wire Wire Line + 22500 12000 23900 12000 +Wire Wire Line + 24150 10300 22500 10300 +Connection ~ 22500 10300 +Wire Wire Line + 24050 8700 22500 8700 +Connection ~ 22500 8700 +Wire Wire Line + 24050 7250 22500 7250 +Connection ~ 22500 7250 +Wire Wire Line + 23050 400 23050 4900 +Wire Wire Line + 23050 4900 24150 4900 +Wire Wire Line + 24150 3600 23050 3600 +Connection ~ 23050 3600 +Wire Wire Line + 23950 2250 23050 2250 +Connection ~ 23050 2250 +Wire Wire Line + 24150 700 23050 700 +Connection ~ 23050 700 +$Comp +L dac_bridge_2 U30 +U 1 1 6851ACA1 +P 28550 11700 +F 0 "U30" H 28550 11700 60 0000 C CNN +F 1 "dac_bridge_2" H 28600 11850 60 0000 C CNN +F 2 "" H 28550 11700 60 0000 C CNN +F 3 "" H 28550 11700 60 0000 C CNN + 1 28550 11700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29100 11750 29250 11750 +$Comp +L dac_bridge_2 U31 +U 1 1 6851B274 +P 28600 10000 +F 0 "U31" H 28600 10000 60 0000 C CNN +F 1 "dac_bridge_2" H 28650 10150 60 0000 C CNN +F 2 "" H 28600 10000 60 0000 C CNN +F 3 "" H 28600 10000 60 0000 C CNN + 1 28600 10000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29150 10050 29300 10050 +$Comp +L dac_bridge_2 U29 +U 1 1 6851B66A +P 28450 8400 +F 0 "U29" H 28450 8400 60 0000 C CNN +F 1 "dac_bridge_2" H 28500 8550 60 0000 C CNN +F 2 "" H 28450 8400 60 0000 C CNN +F 3 "" H 28450 8400 60 0000 C CNN + 1 28450 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29000 8450 29150 8450 +$Comp +L dac_bridge_2 U28 +U 1 1 6851BCF5 +P 28450 6950 +F 0 "U28" H 28450 6950 60 0000 C CNN +F 1 "dac_bridge_2" H 28500 7100 60 0000 C CNN +F 2 "" H 28450 6950 60 0000 C CNN +F 3 "" H 28450 6950 60 0000 C CNN + 1 28450 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29150 7000 29000 7000 +$Comp +L dac_bridge_2 U32 +U 1 1 6851C393 +P 28650 4600 +F 0 "U32" H 28650 4600 60 0000 C CNN +F 1 "dac_bridge_2" H 28700 4750 60 0000 C CNN +F 2 "" H 28650 4600 60 0000 C CNN +F 3 "" H 28650 4600 60 0000 C CNN + 1 28650 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29200 4650 29350 4650 +$Comp +L dac_bridge_2 U27 +U 1 1 6851C86D +P 28450 3300 +F 0 "U27" H 28450 3300 60 0000 C CNN +F 1 "dac_bridge_2" H 28500 3450 60 0000 C CNN +F 2 "" H 28450 3300 60 0000 C CNN +F 3 "" H 28450 3300 60 0000 C CNN + 1 28450 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29000 3350 29150 3350 +$Comp +L dac_bridge_2 U26 +U 1 1 6851D159 +P 28400 1950 +F 0 "U26" H 28400 1950 60 0000 C CNN +F 1 "dac_bridge_2" H 28450 2100 60 0000 C CNN +F 2 "" H 28400 1950 60 0000 C CNN +F 3 "" H 28400 1950 60 0000 C CNN + 1 28400 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 28950 2000 29100 2000 +$Comp +L dac_bridge_2 U33 +U 1 1 6851D736 +P 28750 400 +F 0 "U33" H 28750 400 60 0000 C CNN +F 1 "dac_bridge_2" H 28800 550 60 0000 C CNN +F 2 "" H 28750 400 60 0000 C CNN +F 3 "" H 28750 400 60 0000 C CNN + 1 28750 400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29300 450 29450 450 +$Comp +L PORT U1 +U 1 1 6851DED0 +P 21400 -1800 +F 0 "U1" H 21450 -1700 30 0000 C CNN +F 1 "PORT" H 21400 -1800 30 0000 C CNN +F 2 "" H 21400 -1800 60 0000 C CNN +F 3 "" H 21400 -1800 60 0000 C CNN + 1 21400 -1800 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6851E4D5 +P 20450 -1750 +F 0 "U1" H 20500 -1650 30 0000 C CNN +F 1 "PORT" H 20450 -1750 30 0000 C CNN +F 2 "" H 20450 -1750 60 0000 C CNN +F 3 "" H 20450 -1750 60 0000 C CNN + 2 20450 -1750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 6851E578 +P 22500 -1800 +F 0 "U1" H 22550 -1700 30 0000 C CNN +F 1 "PORT" H 22500 -1800 30 0000 C CNN +F 2 "" H 22500 -1800 60 0000 C CNN +F 3 "" H 22500 -1800 60 0000 C CNN + 3 22500 -1800 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6851E789 +P 23050 -1850 +F 0 "U1" H 23100 -1750 30 0000 C CNN +F 1 "PORT" H 23050 -1850 30 0000 C CNN +F 2 "" H 23050 -1850 60 0000 C CNN +F 3 "" H 23050 -1850 60 0000 C CNN + 4 23050 -1850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 6851ECFE +P 30050 -1100 +F 0 "U1" H 30100 -1000 30 0000 C CNN +F 1 "PORT" H 30050 -1100 30 0000 C CNN +F 2 "" H 30050 -1100 60 0000 C CNN +F 3 "" H 30050 -1100 60 0000 C CNN + 15 30050 -1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6851F331 +P 30000 -800 +F 0 "U1" H 30050 -700 30 0000 C CNN +F 1 "PORT" H 30000 -800 30 0000 C CNN +F 2 "" H 30000 -800 60 0000 C CNN +F 3 "" H 30000 -800 60 0000 C CNN + 16 30000 -800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20450 -1500 20450 -1150 +Wire Wire Line + 21400 -1550 21400 -1200 +Wire Wire Line + 22500 -1550 22500 -1250 +Wire Wire Line + 23050 -1600 23050 -1200 +Wire Wire Line + 32750 3100 30850 3100 +Connection ~ 30850 3100 +Wire Wire Line + 33200 9600 30900 9600 +Connection ~ 30900 9600 +$Comp +L PORT U1 +U 12 1 68521E1C +P 29050 1250 +F 0 "U1" H 29100 1350 30 0000 C CNN +F 1 "PORT" H 29050 1250 30 0000 C CNN +F 2 "" H 29050 1250 60 0000 C CNN +F 3 "" H 29050 1250 60 0000 C CNN + 12 29050 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68522662 +P 28800 7800 +F 0 "U1" H 28850 7900 30 0000 C CNN +F 1 "PORT" H 28800 7800 30 0000 C CNN +F 2 "" H 28800 7800 60 0000 C CNN +F 3 "" H 28800 7800 60 0000 C CNN + 8 28800 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685227B6 +P 28900 4050 +F 0 "U1" H 28950 4150 30 0000 C CNN +F 1 "PORT" H 28900 4050 30 0000 C CNN +F 2 "" H 28900 4050 60 0000 C CNN +F 3 "" H 28900 4050 60 0000 C CNN + 10 28900 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6852287D +P 28800 2700 +F 0 "U1" H 28850 2800 30 0000 C CNN +F 1 "PORT" H 28800 2700 30 0000 C CNN +F 2 "" H 28800 2700 60 0000 C CNN +F 3 "" H 28800 2700 60 0000 C CNN + 11 28800 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68522A94 +P 29000 5550 +F 0 "U1" H 29050 5650 30 0000 C CNN +F 1 "PORT" H 29000 5550 30 0000 C CNN +F 2 "" H 29000 5550 60 0000 C CNN +F 3 "" H 29000 5550 60 0000 C CNN + 9 29000 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68522B57 +P 28650 9300 +F 0 "U1" H 28700 9400 30 0000 C CNN +F 1 "PORT" H 28650 9300 30 0000 C CNN +F 2 "" H 28650 9300 60 0000 C CNN +F 3 "" H 28650 9300 60 0000 C CNN + 7 28650 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68522C2C +P 28450 10900 +F 0 "U1" H 28500 11000 30 0000 C CNN +F 1 "PORT" H 28450 10900 30 0000 C CNN +F 2 "" H 28450 10900 60 0000 C CNN +F 3 "" H 28450 10900 60 0000 C CNN + 6 28450 10900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68522CD5 +P 28250 12600 +F 0 "U1" H 28300 12700 30 0000 C CNN +F 1 "PORT" H 28250 12600 30 0000 C CNN +F 2 "" H 28250 12600 60 0000 C CNN +F 3 "" H 28250 12600 60 0000 C CNN + 5 28250 12600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 29500 12050 28650 12050 +Wire Wire Line + 28650 12050 28650 12600 +Wire Wire Line + 28650 12600 28500 12600 +Connection ~ 29500 12050 +Wire Wire Line + 29550 10350 28850 10350 +Wire Wire Line + 28850 10350 28850 10900 +Wire Wire Line + 28850 10900 28700 10900 +Connection ~ 29550 10350 +Wire Wire Line + 29400 8800 29050 8800 +Wire Wire Line + 29050 8800 29050 9300 +Wire Wire Line + 29050 9300 28900 9300 +Connection ~ 29400 8800 +Wire Wire Line + 29400 7300 29150 7300 +Wire Wire Line + 29150 7300 29150 7800 +Wire Wire Line + 29150 7800 29050 7800 +Connection ~ 29400 7300 +Wire Wire Line + 29600 4950 29350 4950 +Wire Wire Line + 29350 4950 29350 5550 +Wire Wire Line + 29350 5550 29250 5550 +Connection ~ 29600 4950 +Wire Wire Line + 29150 4050 29150 3700 +Wire Wire Line + 29150 3700 29400 3700 +Connection ~ 29400 3700 +Wire Wire Line + 29050 2700 29050 2300 +Wire Wire Line + 29050 2300 29350 2300 +Connection ~ 29350 2300 +Wire Wire Line + 29300 1250 29300 800 +Wire Wire Line + 29300 800 29700 800 +Connection ~ 29700 800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM.sub b/library/SubcircuitLibrary/CD4529BM/CD4529BM.sub new file mode 100644 index 00000000..4e519712 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM.sub @@ -0,0 +1,161 @@ +* Subcircuit CD4529BM +.subckt CD4529BM net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_m13-pad3_ net-_m14-pad3_ net-_m11-pad3_ net-_m10-pad3_ net-_m15-pad3_ net-_m2-pad1_ net-_m1-pad1_ net-_m12-pad1_ net-_m1-pad3_ net-_m10-pad1_ vdd gnd +* c:\fossee\esim\library\subcircuitlibrary\cd4529bm\cd4529bm.cir +.include 3_and.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u6-pad2_ d_inverter +* u8 net-_u1-pad4_ net-_u8-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u7-pad2_ d_inverter +* u9 net-_u8-pad2_ net-_u9-pad2_ d_inverter +* u25 net-_u14-pad2_ net-_u25-pad2_ d_inverter +m16 net-_m1-pad3_ net-_m16-pad2_ net-_m12-pad1_ vdd CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u18 net-_u11-pad2_ net-_u18-pad2_ d_inverter +m6 net-_m1-pad3_ net-_m6-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u19 net-_u15-pad2_ net-_u19-pad2_ d_inverter +m8 net-_m1-pad3_ net-_m8-pad2_ net-_m2-pad1_ vdd CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u24 net-_u16-pad2_ net-_u24-pad2_ d_inverter +m15 net-_m1-pad3_ net-_m15-pad2_ net-_m15-pad3_ vdd CMOSP W=100u L=100u M=1 +m9 net-_m15-pad3_ net-_m9-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u20 net-_u12-pad2_ net-_u20-pad2_ d_inverter +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1 +m3 net-_m10-pad3_ net-_m3-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u21 net-_u13-pad2_ net-_u21-pad2_ d_inverter +m11 net-_m10-pad1_ net-_m11-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1 +m4 net-_m11-pad3_ net-_m4-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u23 net-_u17-pad2_ net-_u23-pad2_ d_inverter +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m14-pad3_ vdd CMOSP W=100u L=100u M=1 +m7 net-_m14-pad3_ net-_m7-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +* u22 net-_u10-pad2_ net-_u22-pad2_ d_inverter +m13 net-_m10-pad1_ net-_m13-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m13-pad3_ net-_m5-pad2_ net-_m10-pad1_ gnd CMOSN W=100u L=100u M=1 +x1 net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u10-pad1_ 3_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x8 net-_u7-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u17-pad1_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +x4 net-_u7-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x3 net-_u7-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +x7 net-_u9-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u16-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x6 net-_u9-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u15-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +x2 net-_u9-pad2_ net-_u5-pad2_ net-_u2-pad2_ net-_u11-pad1_ 3_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x5 net-_u9-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u14-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u30 net-_u10-pad2_ net-_u22-pad2_ net-_m13-pad2_ net-_m5-pad2_ dac_bridge_2 +* u31 net-_u17-pad2_ net-_u23-pad2_ net-_m14-pad2_ net-_m7-pad2_ dac_bridge_2 +* u29 net-_u13-pad2_ net-_u21-pad2_ net-_m11-pad2_ net-_m4-pad2_ dac_bridge_2 +* u28 net-_u12-pad2_ net-_u20-pad2_ net-_m10-pad2_ net-_m3-pad2_ dac_bridge_2 +* u32 net-_u16-pad2_ net-_u24-pad2_ net-_m15-pad2_ net-_m9-pad2_ dac_bridge_2 +* u27 net-_u15-pad2_ net-_u19-pad2_ net-_m8-pad2_ net-_m2-pad2_ dac_bridge_2 +* u26 net-_u11-pad2_ net-_u18-pad2_ net-_m6-pad2_ net-_m1-pad2_ dac_bridge_2 +* u33 net-_u14-pad2_ net-_u25-pad2_ net-_m16-pad2_ net-_m12-pad2_ dac_bridge_2 +a1 net-_u1-pad2_ net-_u2-pad2_ u2 +a2 net-_u1-pad1_ net-_u4-pad2_ u4 +a3 net-_u1-pad3_ net-_u6-pad2_ u6 +a4 net-_u1-pad4_ net-_u8-pad2_ u8 +a5 net-_u2-pad2_ net-_u3-pad2_ u3 +a6 net-_u4-pad2_ net-_u5-pad2_ u5 +a7 net-_u6-pad2_ net-_u7-pad2_ u7 +a8 net-_u8-pad2_ net-_u9-pad2_ u9 +a9 net-_u14-pad2_ net-_u25-pad2_ u25 +a10 net-_u11-pad2_ net-_u18-pad2_ u18 +a11 net-_u15-pad2_ net-_u19-pad2_ u19 +a12 net-_u16-pad2_ net-_u24-pad2_ u24 +a13 net-_u12-pad2_ net-_u20-pad2_ u20 +a14 net-_u13-pad2_ net-_u21-pad2_ u21 +a15 net-_u17-pad2_ net-_u23-pad2_ u23 +a16 net-_u10-pad2_ net-_u22-pad2_ u22 +a17 net-_u10-pad1_ net-_u10-pad2_ u10 +a18 net-_u17-pad1_ net-_u17-pad2_ u17 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 net-_u12-pad1_ net-_u12-pad2_ u12 +a21 net-_u16-pad1_ net-_u16-pad2_ u16 +a22 net-_u15-pad1_ net-_u15-pad2_ u15 +a23 net-_u11-pad1_ net-_u11-pad2_ u11 +a24 net-_u14-pad1_ net-_u14-pad2_ u14 +a25 [net-_u10-pad2_ net-_u22-pad2_ ] [net-_m13-pad2_ net-_m5-pad2_ ] u30 +a26 [net-_u17-pad2_ net-_u23-pad2_ ] [net-_m14-pad2_ net-_m7-pad2_ ] u31 +a27 [net-_u13-pad2_ net-_u21-pad2_ ] [net-_m11-pad2_ net-_m4-pad2_ ] u29 +a28 [net-_u12-pad2_ net-_u20-pad2_ ] [net-_m10-pad2_ net-_m3-pad2_ ] u28 +a29 [net-_u16-pad2_ net-_u24-pad2_ ] [net-_m15-pad2_ net-_m9-pad2_ ] u32 +a30 [net-_u15-pad2_ net-_u19-pad2_ ] [net-_m8-pad2_ net-_m2-pad2_ ] u27 +a31 [net-_u11-pad2_ net-_u18-pad2_ ] [net-_m6-pad2_ net-_m1-pad2_ ] u26 +a32 [net-_u14-pad2_ net-_u25-pad2_ ] [net-_m16-pad2_ net-_m12-pad2_ ] u33 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4529BM
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4529BM/CD4529BM_Previous_Values.xml b/library/SubcircuitLibrary/CD4529BM/CD4529BM_Previous_Values.xml new file mode 100644 index 00000000..b06f4a75 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/CD4529BM_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u8><u3 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u7><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u25 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u25><u18 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u19><u24 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u24><u20 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u21><u23 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u23><u22 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u22><u10 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u10><u17 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u12><u16 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u15><u11 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u11><u14 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u14><u30 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u30><u31 name="type">dac_bridge<field79 name="Enter value for out_low (default=0.0)" /><field80 name="Enter value for out_high (default=5.0)" /><field81 name="Enter value for out_undef (default=0.5)" /><field82 name="Enter value for input load (default=1.0e-12)" /><field83 name="Enter the Rise Time (default=1.0e-9)" /><field84 name="Enter the Fall Time (default=1.0e-9)" /></u31><u29 name="type">dac_bridge<field85 name="Enter value for out_low (default=0.0)" /><field86 name="Enter value for out_high (default=5.0)" /><field87 name="Enter value for out_undef (default=0.5)" /><field88 name="Enter value for input load (default=1.0e-12)" /><field89 name="Enter the Rise Time (default=1.0e-9)" /><field90 name="Enter the Fall Time (default=1.0e-9)" /></u29><u28 name="type">dac_bridge<field91 name="Enter value for out_low (default=0.0)" /><field92 name="Enter value for out_high (default=5.0)" /><field93 name="Enter value for out_undef (default=0.5)" /><field94 name="Enter value for input load (default=1.0e-12)" /><field95 name="Enter the Rise Time (default=1.0e-9)" /><field96 name="Enter the Fall Time (default=1.0e-9)" /></u28><u32 name="type">dac_bridge<field97 name="Enter value for out_low (default=0.0)" /><field98 name="Enter value for out_high (default=5.0)" /><field99 name="Enter value for out_undef (default=0.5)" /><field100 name="Enter value for input load (default=1.0e-12)" /><field101 name="Enter the Rise Time (default=1.0e-9)" /><field102 name="Enter the Fall Time (default=1.0e-9)" /></u32><u27 name="type">dac_bridge<field103 name="Enter value for out_low (default=0.0)" /><field104 name="Enter value for out_high (default=5.0)" /><field105 name="Enter value for out_undef (default=0.5)" /><field106 name="Enter value for input load (default=1.0e-12)" /><field107 name="Enter the Rise Time (default=1.0e-9)" /><field108 name="Enter the Fall Time (default=1.0e-9)" /></u27><u26 name="type">dac_bridge<field109 name="Enter value for out_low (default=0.0)" /><field110 name="Enter value for out_high (default=5.0)" /><field111 name="Enter value for out_undef (default=0.5)" /><field112 name="Enter value for input load (default=1.0e-12)" /><field113 name="Enter the Rise Time (default=1.0e-9)" /><field114 name="Enter the Fall Time (default=1.0e-9)" /></u26><u33 name="type">dac_bridge<field115 name="Enter value for out_low (default=0.0)" /><field116 name="Enter value for out_high (default=5.0)" /><field117 name="Enter value for out_undef (default=0.5)" /><field118 name="Enter value for input load (default=1.0e-12)" /><field119 name="Enter the Rise Time (default=1.0e-9)" /><field120 name="Enter the Fall Time (default=1.0e-9)" /></u33></model><devicemodel><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5></devicemodel><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4529BM/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4529BM/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4529BM/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4529BM/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4529BM/analysis b/library/SubcircuitLibrary/CD4529BM/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4529BM/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |