diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4048BMS')
28 files changed, 3249 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and-cache.lib b/library/SubcircuitLibrary/CD4048BMS/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and.cir b/library/SubcircuitLibrary/CD4048BMS/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and.cir.out b/library/SubcircuitLibrary/CD4048BMS/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and.pro b/library/SubcircuitLibrary/CD4048BMS/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and.sch b/library/SubcircuitLibrary/CD4048BMS/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and.sub b/library/SubcircuitLibrary/CD4048BMS/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4048BMS/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and-cache.lib b/library/SubcircuitLibrary/CD4048BMS/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and-rescue.lib b/library/SubcircuitLibrary/CD4048BMS/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and.cir b/library/SubcircuitLibrary/CD4048BMS/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and.cir.out b/library/SubcircuitLibrary/CD4048BMS/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and.pro b/library/SubcircuitLibrary/CD4048BMS/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and.sch b/library/SubcircuitLibrary/CD4048BMS/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and.sub b/library/SubcircuitLibrary/CD4048BMS/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4048BMS/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS-cache.lib b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS-cache.lib new file mode 100644 index 00000000..b4fb2785 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS-cache.lib @@ -0,0 +1,223 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.bck b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.bck new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.bck @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir new file mode 100644 index 00000000..7bfb8261 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir @@ -0,0 +1,50 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4048BMS\CD4048BMS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 11:26:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad14_ Net-_U17-Pad2_ d_inverter +U3 Net-_U1-Pad13_ Net-_U18-Pad2_ d_inverter +U4 Net-_U1-Pad12_ Net-_U19-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U20-Pad2_ d_inverter +U6 Net-_U1-Pad15_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U21-Pad2_ d_inverter +U8 Net-_U1-Pad5_ Net-_U22-Pad2_ d_inverter +U9 Net-_U1-Pad4_ Net-_U23-Pad2_ d_inverter +U10 Net-_U1-Pad3_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad7_ Net-_U12-Pad2_ d_inverter +U13 Net-_U1-Pad9_ Net-_U13-Pad2_ d_inverter +U14 Net-_U1-Pad2_ Net-_U14-Pad2_ d_inverter +U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U16 Net-_U14-Pad2_ Net-_U16-Pad2_ d_inverter +U17 Net-_U15-Pad2_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_xor +U18 Net-_U15-Pad2_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_xor +U19 Net-_U15-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_xor +U20 Net-_U15-Pad2_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xor +U21 Net-_U15-Pad2_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_xor +U22 Net-_U15-Pad2_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_xor +U23 Net-_U15-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_xor +U24 Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_xor +X2 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad1_ 4_and +X3 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U26-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U29 Net-_U12-Pad2_ Net-_U25-Pad2_ Net-_U29-Pad3_ d_xor +U28 Net-_U26-Pad2_ Net-_U12-Pad2_ Net-_U28-Pad3_ d_xor +X1 Net-_U29-Pad3_ Net-_U6-Pad2_ Net-_U28-Pad3_ Net-_U27-Pad1_ 3_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U30 Net-_U27-Pad2_ Net-_U13-Pad2_ Net-_U30-Pad3_ d_xor +U31 Net-_U16-Pad2_ Net-_U30-Pad3_ Net-_U31-Pad3_ d_and +U32 Net-_U30-Pad3_ Net-_U14-Pad2_ Net-_U32-Pad3_ d_or +U33 Net-_U31-Pad3_ Net-_U33-Pad2_ d_inverter +U34 Net-_U32-Pad3_ Net-_U34-Pad2_ d_inverter +M2 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_n +U1 Net-_M1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_M2-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_M1-Pad3_ PORT +U35 Net-_U33-Pad2_ Net-_U34-Pad2_ Net-_M1-Pad2_ Net-_M2-Pad2_ dac_bridge_2 +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p + +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir.out b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir.out new file mode 100644 index 00000000..0ce2eef1 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.cir.out @@ -0,0 +1,157 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4048bms\cd4048bms.cir + +.include 3_and.sub +.include 4_and.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u1-pad14_ net-_u17-pad2_ d_inverter +* u3 net-_u1-pad13_ net-_u18-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u19-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u20-pad2_ d_inverter +* u6 net-_u1-pad15_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u21-pad2_ d_inverter +* u8 net-_u1-pad5_ net-_u22-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u23-pad2_ d_inverter +* u10 net-_u1-pad3_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad7_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad9_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u14-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u15-pad2_ net-_u17-pad2_ net-_u17-pad3_ d_xor +* u18 net-_u15-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xor +* u19 net-_u15-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_xor +* u20 net-_u15-pad2_ net-_u20-pad2_ net-_u20-pad3_ d_xor +* u21 net-_u15-pad2_ net-_u21-pad2_ net-_u21-pad3_ d_xor +* u22 net-_u15-pad2_ net-_u22-pad2_ net-_u22-pad3_ d_xor +* u23 net-_u15-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_xor +* u24 net-_u15-pad2_ net-_u10-pad2_ net-_u24-pad3_ d_xor +x2 net-_u17-pad3_ net-_u18-pad3_ net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad1_ 4_and +x3 net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u12-pad2_ net-_u25-pad2_ net-_u29-pad3_ d_xor +* u28 net-_u26-pad2_ net-_u12-pad2_ net-_u28-pad3_ d_xor +x1 net-_u29-pad3_ net-_u6-pad2_ net-_u28-pad3_ net-_u27-pad1_ 3_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u13-pad2_ net-_u30-pad3_ d_xor +* u31 net-_u16-pad2_ net-_u30-pad3_ net-_u31-pad3_ d_and +* u32 net-_u30-pad3_ net-_u14-pad2_ net-_u32-pad3_ d_or +* u33 net-_u31-pad3_ net-_u33-pad2_ d_inverter +* u34 net-_u32-pad3_ net-_u34-pad2_ d_inverter +m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m2-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_m1-pad3_ port +* u35 net-_u33-pad2_ net-_u34-pad2_ net-_m1-pad2_ net-_m2-pad2_ dac_bridge_2 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +a1 net-_u1-pad14_ net-_u17-pad2_ u2 +a2 net-_u1-pad13_ net-_u18-pad2_ u3 +a3 net-_u1-pad12_ net-_u19-pad2_ u4 +a4 net-_u1-pad11_ net-_u20-pad2_ u5 +a5 net-_u1-pad15_ net-_u6-pad2_ u6 +a6 net-_u1-pad6_ net-_u21-pad2_ u7 +a7 net-_u1-pad5_ net-_u22-pad2_ u8 +a8 net-_u1-pad4_ net-_u23-pad2_ u9 +a9 net-_u1-pad3_ net-_u10-pad2_ u10 +a10 net-_u1-pad10_ net-_u11-pad2_ u11 +a11 net-_u1-pad7_ net-_u12-pad2_ u12 +a12 net-_u1-pad9_ net-_u13-pad2_ u13 +a13 net-_u1-pad2_ net-_u14-pad2_ u14 +a14 net-_u11-pad2_ net-_u15-pad2_ u15 +a15 net-_u14-pad2_ net-_u16-pad2_ u16 +a16 [net-_u15-pad2_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u15-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u15-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a19 [net-_u15-pad2_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a20 [net-_u15-pad2_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a21 [net-_u15-pad2_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a22 [net-_u15-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a23 [net-_u15-pad2_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a24 net-_u25-pad1_ net-_u25-pad2_ u25 +a25 net-_u26-pad1_ net-_u26-pad2_ u26 +a26 [net-_u12-pad2_ net-_u25-pad2_ ] net-_u29-pad3_ u29 +a27 [net-_u26-pad2_ net-_u12-pad2_ ] net-_u28-pad3_ u28 +a28 net-_u27-pad1_ net-_u27-pad2_ u27 +a29 [net-_u27-pad2_ net-_u13-pad2_ ] net-_u30-pad3_ u30 +a30 [net-_u16-pad2_ net-_u30-pad3_ ] net-_u31-pad3_ u31 +a31 [net-_u30-pad3_ net-_u14-pad2_ ] net-_u32-pad3_ u32 +a32 net-_u31-pad3_ net-_u33-pad2_ u33 +a33 net-_u32-pad3_ net-_u34-pad2_ u34 +a34 [net-_u33-pad2_ net-_u34-pad2_ ] [net-_m1-pad2_ net-_m2-pad2_ ] u35 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u17 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u18 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u22 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u23 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u30 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.dcm b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.lib b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.lib new file mode 100644 index 00000000..9181ef13 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.lib @@ -0,0 +1,1021 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74HC194 +# +DEF 74HC194 X 0 40 Y Y 1 F N +F0 "X" 50 300 60 H V C CNN +F1 "74HC194" 50 550 60 H V C CNN +F2 "" 50 300 60 H I C CNN +F3 "" 50 300 60 H I C CNN +DRAW +A 0 1350 100 -1799 -1 0 1 0 N -100 1350 100 1350 +S -400 1350 450 -750 0 1 0 N +X MR_bar 1 -600 1200 200 R 50 50 1 1 I +X DSR 2 -600 950 200 R 50 50 1 1 I +X D0 3 -600 700 200 R 50 50 1 1 I +X D1 4 -600 450 200 R 50 50 1 1 I +X D2 5 -600 200 200 R 50 50 1 1 I +X D3 6 -600 -50 200 R 50 50 1 1 I +X DSL 7 -600 -300 200 R 50 50 1 1 I +X GND 8 -600 -550 200 R 50 50 1 1 I +X S0 9 650 -550 200 L 50 50 1 1 I +X S1 10 650 -300 200 L 50 50 1 1 I +X CP 11 650 -50 200 L 50 50 1 1 I +X Q3 12 650 200 200 L 50 50 1 1 O +X Q2 13 650 450 200 L 50 50 1 1 O +X Q1 14 650 700 200 L 50 50 1 1 O +X Q0 15 650 950 200 L 50 50 1 1 O +X VCC 16 650 1200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CD4048BMS +# +DEF CD4048BMS X 0 40 Y Y 1 F N +F0 "X" 0 300 60 H V C CNN +F1 "CD4048BMS" -50 950 60 H V C CNN +F2 "" -50 950 60 H I C CNN +F3 "" -50 950 60 H I C CNN +DRAW +S -450 900 400 -300 0 1 0 N +X J(O/P) 1 -650 800 200 R 50 50 1 1 O +X Kd 2 -650 650 200 R 50 50 1 1 I +X H 3 -650 500 200 R 50 50 1 1 I +X G 4 -650 350 200 R 50 50 1 1 I +X F 5 -650 200 200 R 50 50 1 1 I +X E 6 -650 50 200 R 50 50 1 1 I +X Kb 7 -650 -100 200 R 50 50 1 1 I +X VSS 8 -650 -250 200 R 50 50 1 1 I +X Kc 9 600 -250 200 L 50 50 1 1 I +X Ka 10 600 -100 200 L 50 50 1 1 I +X D 11 600 50 200 L 50 50 1 1 I +X C 12 600 200 200 L 50 50 1 1 I +X B 13 600 350 200 L 50 50 1 1 I +X A 14 600 500 200 L 50 50 1 1 I +X Expand 15 600 650 200 L 50 50 1 1 I +X VDD 16 600 800 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DFF +# +DEF DFF X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "DFF" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 750 550 -500 0 1 0 N +X D 1 -750 550 200 R 50 50 1 1 I +X CLK 2 -750 -250 200 R 50 50 1 1 I +X SET 3 0 950 200 D 50 50 1 1 I +X RESET 4 0 -700 200 U 50 50 1 1 I +X Q 5 750 550 200 L 50 50 1 1 O +X Q_bar 6 750 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC-LM3900 +# +DEF IC-LM3900 X 0 40 Y Y 1 F N +F0 "X" 0 -300 60 H V C CNN +F1 "IC-LM3900" 0 -200 60 H V C CNN +F2 "" 0 -200 60 H I C CNN +F3 "" 0 -200 60 H I C CNN +DRAW +A -1200 -100 150 -899 899 0 0 0 N -1200 -250 -1200 50 +T 0 -550 -500 60 0 0 0 + Normal 0 C C +T 0 -550 50 60 0 0 0 + Normal 0 C C +T 0 750 -300 60 0 0 0 + Normal 0 C C +T 0 750 250 60 0 0 0 + Normal 0 C C +T 0 -550 -250 60 0 0 0 - Normal 0 C C +T 0 -550 300 60 0 0 0 - Normal 0 C C +T 0 750 -500 60 0 0 0 - Normal 0 C C +T 0 750 50 60 0 0 0 - Normal 0 C C +T 0 650 -400 60 0 0 0 1 Normal 0 C C +T 0 -450 -400 60 0 0 0 2 Normal 0 C C +T 0 650 150 60 0 0 0 3 Normal 0 C C +T 0 -450 150 60 0 0 0 4 Normal 0 C C +S -1200 750 1150 -1050 0 0 0 N +P 3 0 0 0 -600 -550 -650 -550 -650 -800 N +P 3 0 0 0 -200 -400 50 -400 50 -800 N +P 3 0 0 0 400 -400 350 -400 350 -800 N +P 3 0 0 0 800 0 950 0 950 500 N +P 5 0 0 0 -600 -250 -800 -250 -800 -700 -300 -700 -300 -800 N +P 5 0 0 0 -600 0 -800 0 -800 400 -300 400 -300 500 N +P 5 0 0 0 -600 300 -700 300 -700 450 50 450 50 500 N +P 5 0 0 0 -200 150 150 150 150 450 350 450 350 500 N +P 5 0 0 0 400 150 250 150 250 400 650 400 650 500 N +P 5 0 0 0 800 -550 900 -550 900 -750 650 -750 650 -800 N +P 5 0 0 0 800 -250 950 -250 950 -650 -950 -650 -950 -800 N +P 6 0 0 0 800 300 1000 300 1000 -100 -1000 -100 -1000 500 -650 500 N +C -600 -400 71 0 1 0 N +C -600 150 71 0 1 0 N +C 800 -400 71 0 1 0 N +C 800 150 71 0 1 0 N +P 4 0 1 0 -650 -350 -600 -450 -550 -350 -650 -350 N +P 4 0 1 0 -650 200 -600 100 -550 200 -650 200 N +P 4 0 1 0 -600 -200 -600 -600 -200 -400 -600 -200 N +P 4 0 1 0 -600 350 -600 -50 -200 150 -600 350 N +P 4 0 1 0 800 -600 800 -200 400 -400 800 -600 N +P 4 0 1 0 800 -50 800 350 400 150 800 -50 N +P 4 0 1 0 850 -450 800 -350 750 -450 850 -450 N +P 4 0 1 0 850 100 800 200 750 100 850 100 N +X IN1+ 1 -950 -1250 200 U 50 50 1 1 I +X IN2+ 2 -650 -1250 200 U 50 50 1 1 I +X IN2- 3 -300 -1250 200 U 50 50 1 1 I +X OUT2 4 50 -1250 200 U 50 50 1 1 O +X OUT1 5 350 -1250 200 U 50 50 1 1 O +X IN1- 6 650 -1250 200 U 50 50 1 1 I +X GND 7 950 -1250 200 U 50 50 1 1 I +X IN3- 8 950 950 200 D 50 50 1 1 I +X OUT3 9 650 950 200 D 50 50 1 1 O +X OUT4 10 350 950 200 D 50 50 1 1 O +X IN4- 11 50 950 200 D 50 50 1 1 I +X IN4+ 12 -300 950 200 D 50 50 1 1 I +X IN3+ 13 -650 950 200 D 50 50 1 1 I +X VCC 14 -950 950 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_LM3900 +# +DEF IC_LM3900 X 0 40 Y Y 1 F N +F0 "X" 4050 -2350 60 H V C CNN +F1 "IC_LM3900" 4050 -2350 60 H V C CNN +F2 "" 4050 -2350 60 H I C CNN +F3 "" 4050 -2350 60 H I C CNN +DRAW +C 3650 -2350 112 0 1 0 N +P 4 0 1 0 3550 -2300 3650 -2450 3750 -2300 3550 -2300 N +P 5 0 1 0 3650 -2000 3650 -2700 4650 -2350 3650 -2000 3650 -2350 N +X IN- 1 3450 -2100 200 R 50 50 1 1 I +X IN+ 2 3450 -2600 200 R 50 50 1 1 I +X OUT 3 4850 -2350 200 L 50 50 1 1 O +X VCC 4 3950 -1900 200 D 50 50 1 1 I +X GND 5 3950 -2800 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM3900 +# +DEF LM3900 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "LM3900" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -750 550 -750 550 0 1 0 N +S -750 800 750 -1150 0 1 0 N +X VCC 1 -950 550 200 R 50 50 1 1 I +X GND 2 -950 -800 200 R 50 50 1 1 I +X IN+ 3 -950 150 200 R 50 50 1 1 I +X IN- 4 -950 -350 200 R 50 50 1 1 I +X OUT 5 950 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# SN54LS385 +# +DEF SN54LS385 X 0 40 Y Y 1 F N +F0 "X" -150 -200 60 H V C CNN +F1 "SN54LS385" -200 0 60 H V C CNN +F2 "" -200 0 60 H I C CNN +F3 "" -200 0 60 H I C CNN +DRAW +S -900 1100 450 -1700 0 1 0 N +X A 1 -1100 700 200 R 50 50 1 1 I +X B 2 -1100 150 200 R 50 50 1 1 I +X A_S 3 -1100 -400 200 R 50 50 1 1 I +X CLK 4 -1100 -900 200 R 50 50 1 1 I +X CLR 5 -1100 -1450 200 R 50 50 1 1 I +X Sum 6 650 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# SN74100 +# +DEF SN74100 X 0 40 Y Y 1 F N +F0 "X" 2450 50 60 H V C CNN +F1 "SN74100" 2450 300 60 H V C CNN +F2 "" 2450 300 60 H I C CNN +F3 "" 2450 300 60 H I C CNN +DRAW +S 3150 -550 1750 850 0 1 0 N +X OUT 1 3350 200 200 L 50 50 1 1 O +X Enable_C 2 1550 -200 200 R 50 50 1 1 I +X Data 3 1550 500 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SN74120 +# +DEF SN74120 X 0 40 Y Y 1 F N +F0 "X" 0 800 60 H V C CNN +F1 "SN74120" 0 1000 60 H V C CNN +F2 "" 0 800 60 H I C CNN +F3 "" 0 800 60 H I C CNN +DRAW +S -500 1100 500 -950 0 1 0 N +X M_1 1 -700 950 200 R 50 50 1 1 I +X S1_bar_1 2 -700 700 200 R 50 50 1 1 I +X S2_bar_1 3 -700 450 200 R 50 50 1 1 I +X R_bar_1 4 -700 200 200 R 50 50 1 1 I +X C_1 5 -700 -50 200 R 50 50 1 1 I +X Y_1 6 -700 -300 200 R 50 50 1 1 O +X Y_bar_1 7 -700 -550 200 R 50 50 1 1 O +X GND 8 -700 -800 200 R 50 50 1 1 I +X Y_bar_2 9 700 -800 200 L 50 50 1 1 O +X Y_2 10 700 -550 200 L 50 50 1 1 O +X C_2 11 700 -300 200 L 50 50 1 1 I +X R_bar_2 12 700 -50 200 L 50 50 1 1 I +X S1_bar_2 13 700 200 200 L 50 50 1 1 I +X S2_bar_2 14 700 450 200 L 50 50 1 1 I +X M_2 15 700 700 200 L 50 50 1 1 I +X VCC 16 700 950 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SN74LVC4245A +# +DEF SN74LVC4245A X 0 40 Y Y 1 F N +F0 "X" -50 -1200 60 H V C CNN +F1 "SN74LVC4245A" -50 1400 60 H V C CNN +F2 "" -50 1400 60 H I C CNN +F3 "" -50 1400 60 H I C CNN +DRAW +S -300 1350 200 -1150 0 1 0 N +X VccA(5V) 1 -500 1200 200 R 50 31 1 1 I +X DIR 2 -500 1000 200 R 50 50 1 1 I +X A1 3 -500 800 200 R 50 50 1 1 B +X A2 4 -500 600 200 R 50 50 1 1 B +X A3 5 -500 400 200 R 50 50 1 1 B +X A4 6 -500 200 200 R 50 50 1 1 B +X A5 7 -500 0 200 R 50 50 1 1 B +X A6 8 -500 -200 200 R 50 50 1 1 B +X A7 9 -500 -400 200 R 50 50 1 1 B +X A8 10 -500 -600 200 R 50 50 1 1 B +X B2 20 400 400 200 L 50 50 1 1 B +X GND 11 -500 -800 200 R 50 50 1 1 I +X B1 21 400 600 200 L 50 50 1 1 B +X GND 12 -500 -1000 200 R 50 50 1 1 I +X OE_bar 22 400 800 200 L 50 50 1 1 B +X GND 13 400 -1000 200 L 50 50 1 1 I +X VccB(3.3V) 23 400 1000 200 L 50 31 1 1 B +X B8 14 400 -800 200 L 50 50 1 1 B +X Vcc 24 400 1200 200 L 50 50 1 1 B +X B7 15 400 -600 200 L 50 50 1 1 B +X B6 16 400 -400 200 L 50 50 1 1 B +X B5 17 400 -200 200 L 50 50 1 1 B +X B4 18 400 0 200 L 50 50 1 1 B +X B3 19 400 200 200 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# SN74S64 +# +DEF SN74S64 X 0 40 Y Y 1 F N +F0 "X" 50 -850 60 H V C CNN +F1 "SN74S64" 50 350 60 H V C CNN +F2 "" 50 350 60 H I C CNN +F3 "" 50 350 60 H I C CNN +DRAW +S -200 300 250 -800 0 1 0 N +X A 1 -300 200 121 R 34 50 1 1 I +X E 2 -300 50 121 R 34 50 1 1 I +X F 3 -300 -100 121 R 34 50 1 1 I +X G 4 -300 -250 121 R 34 50 1 1 I +X H 5 -300 -400 121 R 34 50 1 1 I +X I 6 -300 -550 121 R 34 50 1 1 I +X GND 7 -300 -700 121 R 34 50 1 1 I +X Y 8 350 -700 121 L 34 50 1 1 O +X J 9 350 -550 121 L 34 50 1 1 I +X K 10 350 -400 121 L 34 50 1 1 I +X B 11 350 -250 121 L 34 50 1 1 I +X C 12 350 -100 121 L 34 50 1 1 I +X D 13 350 50 121 L 34 50 1 1 I +X VCC 14 350 200 121 L 34 50 1 1 I +ENDDRAW +ENDDEF +# +# Tri_Buffer +# +DEF Tri_Buffer X 0 40 Y Y 1 F N +F0 "X" 100 -150 31 H V C CNN +F1 "Tri_Buffer" 150 150 31 H V C CNN +F2 "" 150 150 60 H I C CNN +F3 "" 150 150 60 H I C CNN +DRAW +P 4 0 1 0 -150 200 -150 -200 200 0 -150 200 N +X In 1 -350 0 200 R 31 31 1 1 I +X En 2 -50 -350 200 U 31 31 1 1 I +X Vcc 3 -50 350 200 D 31 31 1 1 I +X Gnd 4 0 300 200 D 31 31 1 1 I +X Out 5 400 0 200 L 31 31 1 1 O +ENDDRAW +ENDDEF +# +# UAF42 +# +DEF UAF42 X 0 40 Y Y 1 F N +F0 "X" 100 -100 60 H V C CNN +F1 "UAF42" 100 0 60 H V C CNN +F2 "" 100 0 60 H I C CNN +F3 "" 100 0 60 H I C CNN +DRAW +S -550 800 750 -1250 0 1 0 N +S 100 0 100 0 0 1 0 N +X Low_Pass_O/P 1 -750 650 200 R 50 50 1 1 O +X VIN3 2 -750 400 200 R 50 50 1 1 I +X VIN2 3 -750 100 200 R 50 50 1 1 I +X Auxiliary_In+ 4 -750 -200 200 R 50 50 1 1 I +X Auxiliary_In- 5 -750 -550 200 R 50 50 1 1 I +X Auxiliary_O/P 6 -750 -850 200 R 50 50 1 1 O +X Band_Pass_O/P 7 -750 -1150 200 R 50 50 1 1 O +X Freq_Adjust_1 8 950 -1150 200 L 50 50 1 1 I +X V- 9 950 -850 200 L 50 50 1 1 I +X V+ 10 950 -550 200 L 50 50 1 1 I +X GND 11 950 -200 200 L 50 50 1 1 I +X VIN1 12 950 100 200 L 50 50 1 1 I +X High_Pass_O/P 13 950 400 200 L 50 50 1 1 O +X Freq_Adjust_2 14 950 650 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.pro b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sch b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sch new file mode 100644 index 00000000..c67426e2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sch @@ -0,0 +1,899 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4048BMS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68393EB7 +P 2150 1450 +F 0 "U2" H 2150 1350 60 0000 C CNN +F 1 "d_inverter" H 2150 1600 60 0000 C CNN +F 2 "" H 2200 1400 60 0000 C CNN +F 3 "" H 2200 1400 60 0000 C CNN + 1 2150 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68393EFC +P 2150 1900 +F 0 "U3" H 2150 1800 60 0000 C CNN +F 1 "d_inverter" H 2150 2050 60 0000 C CNN +F 2 "" H 2200 1850 60 0000 C CNN +F 3 "" H 2200 1850 60 0000 C CNN + 1 2150 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68393F17 +P 2150 2350 +F 0 "U4" H 2150 2250 60 0000 C CNN +F 1 "d_inverter" H 2150 2500 60 0000 C CNN +F 2 "" H 2200 2300 60 0000 C CNN +F 3 "" H 2200 2300 60 0000 C CNN + 1 2150 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68393F3A +P 2150 2750 +F 0 "U5" H 2150 2650 60 0000 C CNN +F 1 "d_inverter" H 2150 2900 60 0000 C CNN +F 2 "" H 2200 2700 60 0000 C CNN +F 3 "" H 2200 2700 60 0000 C CNN + 1 2150 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68393F57 +P 2150 3250 +F 0 "U6" H 2150 3150 60 0000 C CNN +F 1 "d_inverter" H 2150 3400 60 0000 C CNN +F 2 "" H 2200 3200 60 0000 C CNN +F 3 "" H 2200 3200 60 0000 C CNN + 1 2150 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68393F92 +P 2150 3700 +F 0 "U7" H 2150 3600 60 0000 C CNN +F 1 "d_inverter" H 2150 3850 60 0000 C CNN +F 2 "" H 2200 3650 60 0000 C CNN +F 3 "" H 2200 3650 60 0000 C CNN + 1 2150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68393FB5 +P 2200 4100 +F 0 "U8" H 2200 4000 60 0000 C CNN +F 1 "d_inverter" H 2200 4250 60 0000 C CNN +F 2 "" H 2250 4050 60 0000 C CNN +F 3 "" H 2250 4050 60 0000 C CNN + 1 2200 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 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6 1 683970E7 +P 1600 3700 +F 0 "U1" H 1650 3800 30 0000 C CNN +F 1 "PORT" H 1600 3700 30 0000 C CNN +F 2 "" H 1600 3700 60 0000 C CNN +F 3 "" H 1600 3700 60 0000 C CNN + 6 1600 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 683971B4 +P 1650 5850 +F 0 "U1" H 1700 5950 30 0000 C CNN +F 1 "PORT" H 1650 5850 30 0000 C CNN +F 2 "" H 1650 5850 60 0000 C CNN +F 3 "" H 1650 5850 60 0000 C CNN + 7 1650 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6839721D +P 9750 6000 +F 0 "U1" H 9800 6100 30 0000 C CNN +F 1 "PORT" H 9750 6000 30 0000 C CNN +F 2 "" H 9750 6000 60 0000 C CNN +F 3 "" H 9750 6000 60 0000 C CNN + 8 9750 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68397284 +P 1650 5350 +F 0 "U1" H 1700 5450 30 0000 C CNN +F 1 "PORT" H 1650 5350 30 0000 C CNN +F 2 "" H 1650 5350 60 0000 C CNN +F 3 "" H 1650 5350 60 0000 C CNN + 10 1650 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 683972ED +P 1600 2750 +F 0 "U1" H 1650 2850 30 0000 C CNN +F 1 "PORT" H 1600 2750 30 0000 C CNN +F 2 "" H 1600 2750 60 0000 C CNN +F 3 "" H 1600 2750 60 0000 C CNN + 11 1600 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68397368 +P 1600 2350 +F 0 "U1" H 1650 2450 30 0000 C CNN +F 1 "PORT" H 1600 2350 30 0000 C CNN +F 2 "" H 1600 2350 60 0000 C CNN +F 3 "" H 1600 2350 60 0000 C CNN + 12 1600 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 683973D9 +P 9900 4000 +F 0 "U1" H 9950 4100 30 0000 C CNN +F 1 "PORT" H 9900 4000 30 0000 C CNN +F 2 "" H 9900 4000 60 0000 C CNN +F 3 "" H 9900 4000 60 0000 C CNN + 16 9900 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6839744C +P 1600 1900 +F 0 "U1" H 1650 2000 30 0000 C CNN +F 1 "PORT" H 1600 1900 30 0000 C CNN +F 2 "" H 1600 1900 60 0000 C CNN +F 3 "" H 1600 1900 60 0000 C CNN + 13 1600 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 683974C1 +P 1600 1450 +F 0 "U1" H 1650 1550 30 0000 C CNN +F 1 "PORT" H 1600 1450 30 0000 C CNN +F 2 "" H 1600 1450 60 0000 C CNN +F 3 "" H 1600 1450 60 0000 C CNN + 14 1600 1450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 68397548 +P 1600 3250 +F 0 "U1" H 1650 3350 30 0000 C CNN +F 1 "PORT" H 1600 3250 30 0000 C CNN +F 2 "" H 1600 3250 60 0000 C CNN +F 3 "" H 1600 3250 60 0000 C CNN + 15 1600 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 683975D1 +P 10900 5000 +F 0 "U1" H 10950 5100 30 0000 C CNN +F 1 "PORT" H 10900 5000 30 0000 C CNN +F 2 "" H 10900 5000 60 0000 C CNN +F 3 "" H 10900 5000 60 0000 C CNN + 1 10900 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68397660 +P 1650 6400 +F 0 "U1" H 1700 6500 30 0000 C CNN +F 1 "PORT" H 1650 6400 30 0000 C CNN +F 2 "" H 1650 6400 60 0000 C CNN +F 3 "" H 1650 6400 60 0000 C CNN + 9 1650 6400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 683976EF +P 1650 6950 +F 0 "U1" H 1700 7050 30 0000 C CNN +F 1 "PORT" H 1650 6950 30 0000 C CNN +F 2 "" H 1650 6950 60 0000 C CNN +F 3 "" H 1650 6950 60 0000 C CNN + 2 1650 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6839777E +P 1650 4850 +F 0 "U1" H 1700 4950 30 0000 C CNN +F 1 "PORT" H 1650 4850 30 0000 C CNN +F 2 "" H 1650 4850 60 0000 C CNN +F 3 "" H 1650 4850 60 0000 C CNN + 3 1650 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6839780D +P 1650 4500 +F 0 "U1" H 1700 4600 30 0000 C CNN +F 1 "PORT" H 1650 4500 30 0000 C CNN +F 2 "" H 1650 4500 60 0000 C CNN +F 3 "" H 1650 4500 60 0000 C CNN + 4 1650 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 683978A0 +P 1650 4100 +F 0 "U1" H 1700 4200 30 0000 C CNN +F 1 "PORT" H 1650 4100 30 0000 C CNN +F 2 "" H 1650 4100 60 0000 C CNN +F 3 "" H 1650 4100 60 0000 C CNN + 5 1650 4100 + 1 0 0 -1 +$EndComp +NoConn ~ 1850 1100 +NoConn ~ 1850 800 +Wire Wire Line + 10150 6000 10000 6000 +Connection ~ 10150 5800 +Connection ~ 10150 4200 +Wire Wire Line + 9600 2600 9800 2600 +Wire Wire Line + 9800 2600 9800 2950 +Wire Wire Line + 9600 3550 9800 3550 +Wire Wire Line + 9800 3550 9800 3050 +Wire Wire Line + 10900 2950 10900 3750 +Wire Wire Line + 10900 3750 9600 3750 +Wire Wire Line + 9600 3750 9600 4550 +Wire Wire Line + 10800 3050 10800 3650 +Wire Wire Line + 10800 3650 9500 3650 +Wire Wire Line + 9500 3650 9500 5500 +$Comp +L dac_bridge_2 U35 +U 1 1 683D7E19 +P 10250 3000 +F 0 "U35" H 10250 3000 60 0000 C CNN +F 1 "dac_bridge_2" H 10300 3150 60 0000 C CNN +F 2 "" H 10250 3000 60 0000 C CNN +F 3 "" H 10250 3000 60 0000 C CNN + 1 10250 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10900 2950 10800 2950 +$Comp +L mosfet_p M1 +U 1 1 683E90F0 +P 10000 4550 +F 0 "M1" H 9950 4600 50 0000 R CNN +F 1 "mosfet_p" H 10050 4700 50 0000 R CNN +F 2 "" H 10250 4650 29 0000 C CNN +F 3 "" H 10050 4550 60 0000 C CNN + 1 10000 4550 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sub b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sub new file mode 100644 index 00000000..b8cef0e9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS.sub @@ -0,0 +1,151 @@ +* Subcircuit CD4048BMS +.subckt CD4048BMS net-_m1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m2-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4048bms\cd4048bms.cir +.include 3_and.sub +.include 4_and.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u2 net-_u1-pad14_ net-_u17-pad2_ d_inverter +* u3 net-_u1-pad13_ net-_u18-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u19-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u20-pad2_ d_inverter +* u6 net-_u1-pad15_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u21-pad2_ d_inverter +* u8 net-_u1-pad5_ net-_u22-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u23-pad2_ d_inverter +* u10 net-_u1-pad3_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad7_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad9_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u14-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u15-pad2_ net-_u17-pad2_ net-_u17-pad3_ d_xor +* u18 net-_u15-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xor +* u19 net-_u15-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_xor +* u20 net-_u15-pad2_ net-_u20-pad2_ net-_u20-pad3_ d_xor +* u21 net-_u15-pad2_ net-_u21-pad2_ net-_u21-pad3_ d_xor +* u22 net-_u15-pad2_ net-_u22-pad2_ net-_u22-pad3_ d_xor +* u23 net-_u15-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_xor +* u24 net-_u15-pad2_ net-_u10-pad2_ net-_u24-pad3_ d_xor +x2 net-_u17-pad3_ net-_u18-pad3_ net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad1_ 4_and +x3 net-_u21-pad3_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u12-pad2_ net-_u25-pad2_ net-_u29-pad3_ d_xor +* u28 net-_u26-pad2_ net-_u12-pad2_ net-_u28-pad3_ d_xor +x1 net-_u29-pad3_ net-_u6-pad2_ net-_u28-pad3_ net-_u27-pad1_ 3_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u13-pad2_ net-_u30-pad3_ d_xor +* u31 net-_u16-pad2_ net-_u30-pad3_ net-_u31-pad3_ d_and +* u32 net-_u30-pad3_ net-_u14-pad2_ net-_u32-pad3_ d_or +* u33 net-_u31-pad3_ net-_u33-pad2_ d_inverter +* u34 net-_u32-pad3_ net-_u34-pad2_ d_inverter +m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +* u35 net-_u33-pad2_ net-_u34-pad2_ net-_m1-pad2_ net-_m2-pad2_ dac_bridge_2 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +a1 net-_u1-pad14_ net-_u17-pad2_ u2 +a2 net-_u1-pad13_ net-_u18-pad2_ u3 +a3 net-_u1-pad12_ net-_u19-pad2_ u4 +a4 net-_u1-pad11_ net-_u20-pad2_ u5 +a5 net-_u1-pad15_ net-_u6-pad2_ u6 +a6 net-_u1-pad6_ net-_u21-pad2_ u7 +a7 net-_u1-pad5_ net-_u22-pad2_ u8 +a8 net-_u1-pad4_ net-_u23-pad2_ u9 +a9 net-_u1-pad3_ net-_u10-pad2_ u10 +a10 net-_u1-pad10_ net-_u11-pad2_ u11 +a11 net-_u1-pad7_ net-_u12-pad2_ u12 +a12 net-_u1-pad9_ net-_u13-pad2_ u13 +a13 net-_u1-pad2_ net-_u14-pad2_ u14 +a14 net-_u11-pad2_ net-_u15-pad2_ u15 +a15 net-_u14-pad2_ net-_u16-pad2_ u16 +a16 [net-_u15-pad2_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u15-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u15-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a19 [net-_u15-pad2_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a20 [net-_u15-pad2_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a21 [net-_u15-pad2_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a22 [net-_u15-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a23 [net-_u15-pad2_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a24 net-_u25-pad1_ net-_u25-pad2_ u25 +a25 net-_u26-pad1_ net-_u26-pad2_ u26 +a26 [net-_u12-pad2_ net-_u25-pad2_ ] net-_u29-pad3_ u29 +a27 [net-_u26-pad2_ net-_u12-pad2_ ] net-_u28-pad3_ u28 +a28 net-_u27-pad1_ net-_u27-pad2_ u27 +a29 [net-_u27-pad2_ net-_u13-pad2_ ] net-_u30-pad3_ u30 +a30 [net-_u16-pad2_ net-_u30-pad3_ ] net-_u31-pad3_ u31 +a31 [net-_u30-pad3_ net-_u14-pad2_ ] net-_u32-pad3_ u32 +a32 net-_u31-pad3_ net-_u33-pad2_ u33 +a33 net-_u32-pad3_ net-_u34-pad2_ u34 +a34 [net-_u33-pad2_ net-_u34-pad2_ ] [net-_m1-pad2_ net-_m2-pad2_ ] u35 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u17 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u18 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u22 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u23 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u30 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4048BMS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/CD4048BMS_Previous_Values.xml b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS_Previous_Values.xml new file mode 100644 index 00000000..378abc3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/CD4048BMS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_xor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_xor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_xor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_xor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_xor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_xor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_xor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_xor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u29><u28 name="type">d_xor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u27 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u27><u30 name="type">d_xor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_or<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u34><u35 name="type">dac_bridge<field100 name="Enter value for out_low (default=0.0)" /><field101 name="Enter value for out_high (default=5.0)" /><field102 name="Enter value for out_undef (default=0.5)" /><field103 name="Enter value for input load (default=1.0e-12)" /><field104 name="Enter the Rise Time (default=1.0e-9)" /><field105 name="Enter the Fall Time (default=1.0e-9)" /></u35></model><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m1></devicemodel><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4048BMS/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4048BMS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4048BMS/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4048BMS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4048BMS/analysis b/library/SubcircuitLibrary/CD4048BMS/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4048BMS/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |