diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4038B')
17 files changed, 2972 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4038B/3_nor-cache.lib b/library/SubcircuitLibrary/CD4038B/3_nor-cache.lib new file mode 100644 index 00000000..4ba918af --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4038B/3_nor.cir b/library/SubcircuitLibrary/CD4038B/3_nor.cir new file mode 100644 index 00000000..b8881701 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor.cir @@ -0,0 +1,20 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor\3_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/25 12:25:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M5 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M6 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad1_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M2-Pad1_ eSim_MOS_P +M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +U4 Net-_U3-Pad2_ Net-_U1-Pad6_ d_buffer +U3 Net-_M1-Pad1_ Net-_U3-Pad2_ adc_bridge_1 +U2 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M4-Pad2_ dac_bridge_3 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad3_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4038B/3_nor.cir.out b/library/SubcircuitLibrary/CD4038B/3_nor.cir.out new file mode 100644 index 00000000..551422c5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer +* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 +* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ port +a1 net-_u3-pad2_ net-_u1-pad6_ u4 +a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 +a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4038B/3_nor.pro b/library/SubcircuitLibrary/CD4038B/3_nor.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4038B/3_nor.sch b/library/SubcircuitLibrary/CD4038B/3_nor.sch new file mode 100644 index 00000000..fe1cae25 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor.sch @@ -0,0 +1,332 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:3_nor-cache +LIBS:3_norgate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3300 4650 3300 4450 +Wire Wire Line + 3300 1300 3300 4300 +$Comp +L mosfet_n M1 +U 1 1 684BC8E7 +P 4700 3600 +F 0 "M1" H 4700 3450 50 0000 R CNN +F 1 "mosfet_n" H 4800 3550 50 0000 R CNN +F 2 "" H 5000 3300 29 0000 C CNN +F 3 "" H 4800 3400 60 0000 C CNN + 1 4700 3600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 684BC8E8 +P 6050 3600 +F 0 "M5" H 6050 3450 50 0000 R CNN +F 1 "mosfet_n" H 6150 3550 50 0000 R CNN +F 2 "" H 6350 3300 29 0000 C CNN +F 3 "" H 6150 3400 60 0000 C CNN + 1 6050 3600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 684BC8E9 +P 7200 3650 +F 0 "M6" H 7200 3500 50 0000 R CNN +F 1 "mosfet_n" H 7300 3600 50 0000 R CNN +F 2 "" H 7500 3350 29 0000 C CNN +F 3 "" H 7300 3450 60 0000 C CNN + 1 7200 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 684BC8EA +P 5400 1300 +F 0 "M2" H 5350 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 1450 50 0000 R CNN +F 2 "" H 5650 1400 29 0000 C CNN +F 3 "" H 5450 1300 60 0000 C CNN + 1 5400 1300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 684BC8EB +P 5400 1950 +F 0 "M3" H 5350 2000 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 2100 50 0000 R CNN +F 2 "" H 5650 2050 29 0000 C CNN +F 3 "" H 5450 1950 60 0000 C CNN + 1 5400 1950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 684BC8EC +P 5400 2600 +F 0 "M4" H 5350 2650 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 2750 50 0000 R CNN +F 2 "" H 5650 2700 29 0000 C CNN +F 3 "" H 5450 2600 60 0000 C CNN + 1 5400 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 3600 7400 3600 +Wire Wire Line + 7400 3600 7400 3650 +Connection ~ 6250 3600 +Wire Wire Line + 4900 4000 4900 4250 +Wire Wire Line + 4900 4250 7500 4250 +Wire Wire Line + 7400 4250 7400 4050 +Wire Wire Line + 6250 4000 6250 4250 +Connection ~ 6250 4250 +Wire Wire Line + 5000 3950 5000 4250 +Connection ~ 5000 4250 +Wire Wire Line + 6350 3950 6350 4500 +Connection ~ 6350 4250 +Wire Wire Line + 7500 4250 7500 4000 +Connection ~ 7400 4250 +Wire Wire Line + 5550 1500 5550 1750 +Wire Wire Line + 5550 2150 5550 2400 +Wire Wire Line + 5550 1100 5550 850 +Wire Wire Line + 5550 850 6500 850 +Wire Wire Line + 5650 1450 5950 1450 +Wire Wire Line + 5950 850 5950 2750 +Connection ~ 5950 850 +Wire Wire Line + 5950 2100 5650 2100 +Connection ~ 5950 1450 +Wire Wire Line + 5950 2750 5650 2750 +Connection ~ 5950 2100 +Wire Wire Line + 5550 2800 5550 3600 +Connection ~ 5550 3600 +Wire Wire Line + 3300 3800 4600 3800 +Wire Wire Line + 3300 1300 5250 1300 +Connection ~ 3300 3800 +Wire Wire Line + 3300 4450 5950 4450 +Wire Wire Line + 5950 4450 5950 3800 +Wire Wire Line + 3650 5050 7100 5050 +Wire Wire Line + 7100 5050 7100 3850 +Wire Wire Line + 4200 4450 4200 1950 +Wire Wire Line + 4200 1950 5250 1950 +Connection ~ 4200 4450 +Wire Wire Line + 5350 5050 5350 2800 +Wire Wire Line + 5350 2800 5100 2800 +Wire Wire Line + 5100 2800 5100 2600 +Wire Wire Line + 5100 2600 5250 2600 +Connection ~ 5350 5050 +Connection ~ 5550 3200 +$Comp +L d_buffer U4 +U 1 1 684BC8F1 +P 7800 3100 +F 0 "U4" H 7800 3050 60 0000 C CNN +F 1 "d_buffer" H 7800 3150 60 0000 C CNN +F 2 "" H 7800 3100 60 0000 C CNN +F 3 "" H 7800 3100 60 0000 C CNN + 1 7800 3100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 684BC8F2 +P 6400 3250 +F 0 "U3" H 6400 3250 60 0000 C CNN +F 1 "adc_bridge_1" H 6400 3400 60 0000 C CNN +F 2 "" H 6400 3250 60 0000 C CNN +F 3 "" H 6400 3250 60 0000 C CNN + 1 6400 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 3200 5800 3200 +Wire Wire Line + 6950 3200 6950 3100 +Wire Wire Line + 6950 3100 7300 3100 +Wire Wire Line + 8450 3100 8450 3550 +Wire Wire Line + 8450 3550 8550 3550 +$Comp +L dac_bridge_3 U2 +U 1 1 684BCCBA +P 2350 4600 +F 0 "U2" H 2350 4600 60 0000 C CNN +F 1 "dac_bridge_3" H 2350 4750 60 0000 C CNN +F 2 "" H 2350 4600 60 0000 C CNN +F 3 "" H 2350 4600 60 0000 C CNN + 1 2350 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4550 3100 4550 +Wire Wire Line + 3100 4550 3100 4300 +Wire Wire Line + 3100 4300 3300 4300 +Wire Wire Line + 2900 4650 3300 4650 +Wire Wire Line + 2900 4750 3650 4750 +Wire Wire Line + 3650 4750 3650 5050 +$Comp +L PORT U1 +U 3 1 684BCFDE +P 1050 4500 +F 0 "U1" H 1100 4600 30 0000 C CNN +F 1 "PORT" H 1050 4500 30 0000 C CNN +F 2 "" H 1050 4500 60 0000 C CNN +F 3 "" H 1050 4500 60 0000 C CNN + 3 1050 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 684BD073 +P 950 4650 +F 0 "U1" H 1000 4750 30 0000 C CNN +F 1 "PORT" H 950 4650 30 0000 C CNN +F 2 "" H 950 4650 60 0000 C CNN +F 3 "" H 950 4650 60 0000 C CNN + 1 950 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684BD0CA +P 950 4850 +F 0 "U1" H 1000 4950 30 0000 C CNN +F 1 "PORT" H 950 4850 30 0000 C CNN +F 2 "" H 950 4850 60 0000 C CNN +F 3 "" H 950 4850 60 0000 C CNN + 2 950 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 4500 1750 4500 +Wire Wire Line + 1750 4500 1750 4550 +Wire Wire Line + 1200 4650 1750 4650 +Wire Wire Line + 1200 4850 1200 4750 +Wire Wire Line + 1200 4750 1750 4750 +$Comp +L PORT U1 +U 4 1 684BD531 +P 6500 1100 +F 0 "U1" H 6550 1200 30 0000 C CNN +F 1 "PORT" H 6500 1100 30 0000 C CNN +F 2 "" H 6500 1100 60 0000 C CNN +F 3 "" H 6500 1100 60 0000 C CNN + 4 6500 1100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 684BD700 +P 6600 4500 +F 0 "U1" H 6650 4600 30 0000 C CNN +F 1 "PORT" H 6600 4500 30 0000 C CNN +F 2 "" H 6600 4500 60 0000 C CNN +F 3 "" H 6600 4500 60 0000 C CNN + 5 6600 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 684BDA88 +P 8800 3550 +F 0 "U1" H 8850 3650 30 0000 C CNN +F 1 "PORT" H 8800 3550 30 0000 C CNN +F 2 "" H 8800 3550 60 0000 C CNN +F 3 "" H 8800 3550 60 0000 C CNN + 6 8800 3550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4038B/3_nor.sub b/library/SubcircuitLibrary/CD4038B/3_nor.sub new file mode 100644 index 00000000..9bbbe57a --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor.sub @@ -0,0 +1,26 @@ +* Subcircuit 3_nor +.subckt 3_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ +* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer +* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 +* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 +a1 net-_u3-pad2_ net-_u1-pad6_ u4 +a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 +a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 3_nor
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4038B/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/CD4038B/3_nor_Previous_Values.xml new file mode 100644 index 00000000..2c30c1aa --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/3_nor_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_buffer<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">adc_bridge<field4 name="Enter value for in_low (default=1.0)" /><field5 name="Enter value for in_high (default=2.0)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /><field7 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">dac_bridge<field8 name="Enter value for out_low (default=0.0)" /><field9 name="Enter value for out_high (default=5.0)" /><field10 name="Enter value for out_undef (default=0.5)" /><field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /></u2></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B-cache.lib b/library/SubcircuitLibrary/CD4038B/CD4038B-cache.lib new file mode 100644 index 00000000..aa4b4529 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B-cache.lib @@ -0,0 +1,195 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_nor_gate +# +DEF 3_nor_gate X 0 40 Y Y 1 F N +F0 "X" 500 -400 60 H V C CNN +F1 "3_nor_gate" 50 -150 60 H V C CNN +F2 "" 50 -150 60 H I C CNN +F3 "" 50 -150 60 H I C CNN +DRAW +S 450 -300 -350 200 0 1 0 N +X A 1 -550 100 200 R 50 50 1 1 I +X B 2 -550 0 200 R 50 50 1 1 I +X C 3 -550 -150 200 R 50 50 1 1 I +X VDD 4 150 400 200 D 50 50 1 1 I +X VSS 5 350 -500 200 U 50 50 1 1 I +X OUT 6 650 -50 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# qb_dff +# +DEF qb_dff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "qb_dff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X D0 1 2150 1900 200 R 50 50 1 1 I +X cl0 2 2150 1800 200 R 50 50 1 1 I +X Q_bar0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# r_dff +# +DEF r_dff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "r_dff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X D0 1 2150 1900 200 R 50 50 1 1 I +X CL0 2 2150 1800 200 R 50 50 1 1 I +X R0 3 2150 1700 200 R 50 50 1 1 I +X Q_B0 4 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B.cir b/library/SubcircuitLibrary/CD4038B/CD4038B.cir new file mode 100644 index 00000000..5418e4df --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B.cir @@ -0,0 +1,79 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4038B\CD4038B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 13:19:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad1_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U5 Net-_U1-Pad2_ Net-_U16-Pad1_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U26 Net-_U14-Pad2_ Net-_U16-Pad2_ Net-_U26-Pad3_ d_xor +U42 Net-_U26-Pad3_ Net-_U42-Pad2_ Net-_U42-Pad3_ d_xnor +U48 Net-_U42-Pad3_ Net-_U48-Pad2_ d_inverter +U52 Net-_U48-Pad2_ Net-_U52-Pad2_ d_buffer +U55 Net-_U52-Pad2_ Net-_U55-Pad2_ d_inverter +U58 Net-_U55-Pad2_ Net-_U58-Pad2_ d_inverter +U63 Net-_U58-Pad2_ Net-_U1-Pad4_ d_buffer +U29 Net-_U29-Pad1_ Net-_U14-Pad2_ Net-_U29-Pad3_ d_and +U30 Net-_U14-Pad2_ Net-_U16-Pad2_ Net-_U30-Pad3_ d_and +U31 Net-_U16-Pad2_ Net-_U29-Pad1_ Net-_U31-Pad3_ d_and +X1 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U31-Pad3_ VDD VSS Net-_U45-Pad1_ 3_nor_gate +U61 Net-_U29-Pad1_ Net-_U35-Pad2_ Net-_U42-Pad2_ d_xor +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ d_inverter +U21 Net-_U12-Pad2_ Net-_U21-Pad2_ d_inverter +U35 Net-_U21-Pad2_ Net-_U35-Pad2_ d_buffer +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ VDD VSS PORT +U6 Net-_U1-Pad5_ Net-_U17-Pad1_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U18-Pad1_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U27 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U27-Pad3_ d_xor +U43 Net-_U27-Pad3_ Net-_U43-Pad2_ Net-_U43-Pad3_ d_xnor +U49 Net-_U43-Pad3_ Net-_U49-Pad2_ d_inverter +U53 Net-_U49-Pad2_ Net-_U53-Pad2_ d_buffer +U56 Net-_U53-Pad2_ Net-_U56-Pad2_ d_inverter +U59 Net-_U56-Pad2_ Net-_U59-Pad2_ d_inverter +U65 Net-_U59-Pad2_ Net-_U1-Pad8_ d_buffer +U32 Net-_U32-Pad1_ Net-_U17-Pad2_ Net-_U32-Pad3_ d_and +U33 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U33-Pad3_ d_and +U34 Net-_U18-Pad2_ Net-_U32-Pad1_ Net-_U34-Pad3_ d_and +X2 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U34-Pad3_ VDD VSS Net-_U47-Pad1_ 3_nor_gate +U62 Net-_U32-Pad1_ Net-_U40-Pad2_ Net-_U43-Pad2_ d_xor +U13 Net-_U1-Pad7_ Net-_U13-Pad2_ d_inverter +U23 Net-_U13-Pad2_ Net-_U23-Pad2_ d_inverter +U40 Net-_U23-Pad2_ Net-_U40-Pad2_ d_buffer +U8 Net-_U1-Pad9_ Net-_U19-Pad1_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U9 Net-_U1-Pad10_ Net-_U20-Pad1_ d_inverter +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U28 Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U28-Pad3_ d_xor +U44 Net-_U28-Pad3_ Net-_U44-Pad2_ Net-_U44-Pad3_ d_xnor +U50 Net-_U44-Pad3_ Net-_U50-Pad2_ d_inverter +U54 Net-_U50-Pad2_ Net-_U54-Pad2_ d_buffer +U57 Net-_U54-Pad2_ Net-_U57-Pad2_ d_inverter +U60 Net-_U57-Pad2_ Net-_U60-Pad2_ d_inverter +U66 Net-_U60-Pad2_ Net-_U1-Pad12_ d_buffer +U36 Net-_U36-Pad1_ Net-_U19-Pad2_ Net-_U36-Pad3_ d_and +U37 Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U37-Pad3_ d_and +U38 Net-_U20-Pad2_ Net-_U36-Pad1_ Net-_U38-Pad3_ d_and +X3 Net-_U36-Pad3_ Net-_U37-Pad3_ Net-_U38-Pad3_ VDD VSS Net-_U46-Pad1_ 3_nor_gate +U64 Net-_U36-Pad1_ Net-_U41-Pad2_ Net-_U44-Pad2_ d_xor +U15 Net-_U1-Pad11_ Net-_U15-Pad2_ d_inverter +U25 Net-_U15-Pad2_ Net-_U25-Pad2_ d_inverter +U41 Net-_U25-Pad2_ Net-_U41-Pad2_ d_buffer +U2 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U22 Net-_U10-Pad2_ Net-_U22-Pad2_ d_buffer +U51 Net-_U3-Pad3_ Net-_U24-Pad2_ Net-_U45-Pad3_ d_nand +U11 Net-_U1-Pad14_ Net-_U11-Pad2_ d_inverter +U24 Net-_U11-Pad2_ Net-_U24-Pad2_ d_inverter +U39 Net-_U24-Pad2_ Net-_U39-Pad2_ d_buffer +U3 Net-_U22-Pad2_ Net-_U24-Pad2_ Net-_U3-Pad3_ qb_dff +U45 Net-_U45-Pad1_ Net-_U39-Pad2_ Net-_U45-Pad3_ Net-_U29-Pad1_ r_dff +U47 Net-_U47-Pad1_ Net-_U39-Pad2_ Net-_U45-Pad3_ Net-_U32-Pad1_ r_dff +U46 Net-_U46-Pad1_ Net-_U39-Pad2_ Net-_U45-Pad3_ Net-_U36-Pad1_ r_dff + +.end diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B.cir.out b/library/SubcircuitLibrary/CD4038B/CD4038B.cir.out new file mode 100644 index 00000000..27197ec7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B.cir.out @@ -0,0 +1,276 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4038b\cd4038b.cir + +.include 3_nor.sub +* u4 net-_u1-pad1_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u16-pad1_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u26 net-_u14-pad2_ net-_u16-pad2_ net-_u26-pad3_ d_xor +* u42 net-_u26-pad3_ net-_u42-pad2_ net-_u42-pad3_ d_xnor +* u48 net-_u42-pad3_ net-_u48-pad2_ d_inverter +* u52 net-_u48-pad2_ net-_u52-pad2_ d_buffer +* u55 net-_u52-pad2_ net-_u55-pad2_ d_inverter +* u58 net-_u55-pad2_ net-_u58-pad2_ d_inverter +* u63 net-_u58-pad2_ net-_u1-pad4_ d_buffer +* u29 net-_u29-pad1_ net-_u14-pad2_ net-_u29-pad3_ d_and +* u30 net-_u14-pad2_ net-_u16-pad2_ net-_u30-pad3_ d_and +* u31 net-_u16-pad2_ net-_u29-pad1_ net-_u31-pad3_ d_and +x1 net-_u29-pad3_ net-_u30-pad3_ net-_u31-pad3_ vdd vss net-_u45-pad1_ 3_nor +* u61 net-_u29-pad1_ net-_u35-pad2_ net-_u42-pad2_ d_xor +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u21 net-_u12-pad2_ net-_u21-pad2_ d_inverter +* u35 net-_u21-pad2_ net-_u35-pad2_ d_buffer +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ vdd vss port +* u6 net-_u1-pad5_ net-_u17-pad1_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u18-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u27 net-_u17-pad2_ net-_u18-pad2_ net-_u27-pad3_ d_xor +* u43 net-_u27-pad3_ net-_u43-pad2_ net-_u43-pad3_ d_xnor +* u49 net-_u43-pad3_ net-_u49-pad2_ d_inverter +* u53 net-_u49-pad2_ net-_u53-pad2_ d_buffer +* u56 net-_u53-pad2_ net-_u56-pad2_ d_inverter +* u59 net-_u56-pad2_ net-_u59-pad2_ d_inverter +* u65 net-_u59-pad2_ net-_u1-pad8_ d_buffer +* u32 net-_u32-pad1_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u33 net-_u17-pad2_ net-_u18-pad2_ net-_u33-pad3_ d_and +* u34 net-_u18-pad2_ net-_u32-pad1_ net-_u34-pad3_ d_and +x2 net-_u32-pad3_ net-_u33-pad3_ net-_u34-pad3_ vdd vss net-_u47-pad1_ 3_nor +* u62 net-_u32-pad1_ net-_u40-pad2_ net-_u43-pad2_ d_xor +* u13 net-_u1-pad7_ net-_u13-pad2_ d_inverter +* u23 net-_u13-pad2_ net-_u23-pad2_ d_inverter +* u40 net-_u23-pad2_ net-_u40-pad2_ d_buffer +* u8 net-_u1-pad9_ net-_u19-pad1_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u9 net-_u1-pad10_ net-_u20-pad1_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u28 net-_u19-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_xor +* u44 net-_u28-pad3_ net-_u44-pad2_ net-_u44-pad3_ d_xnor +* u50 net-_u44-pad3_ net-_u50-pad2_ d_inverter +* u54 net-_u50-pad2_ net-_u54-pad2_ d_buffer +* u57 net-_u54-pad2_ net-_u57-pad2_ d_inverter +* u60 net-_u57-pad2_ net-_u60-pad2_ d_inverter +* u66 net-_u60-pad2_ net-_u1-pad12_ d_buffer +* u36 net-_u36-pad1_ net-_u19-pad2_ net-_u36-pad3_ d_and +* u37 net-_u19-pad2_ net-_u20-pad2_ net-_u37-pad3_ d_and +* u38 net-_u20-pad2_ net-_u36-pad1_ net-_u38-pad3_ d_and +x3 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ vdd vss net-_u46-pad1_ 3_nor +* u64 net-_u36-pad1_ net-_u41-pad2_ net-_u44-pad2_ d_xor +* u15 net-_u1-pad11_ net-_u15-pad2_ d_inverter +* u25 net-_u15-pad2_ net-_u25-pad2_ d_inverter +* u41 net-_u25-pad2_ net-_u41-pad2_ d_buffer +* u2 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u22 net-_u10-pad2_ net-_u22-pad2_ d_buffer +* u51 net-_u3-pad3_ net-_u24-pad2_ net-_u45-pad3_ d_nand +* u11 net-_u1-pad14_ net-_u11-pad2_ d_inverter +* u24 net-_u11-pad2_ net-_u24-pad2_ d_inverter +* u39 net-_u24-pad2_ net-_u39-pad2_ d_buffer +* u3 net-_u22-pad2_ net-_u24-pad2_ net-_u3-pad3_ qb_dff +* u45 net-_u45-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u29-pad1_ r_dff +* u47 net-_u47-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u32-pad1_ r_dff +* u46 net-_u46-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u36-pad1_ r_dff +a1 net-_u1-pad1_ net-_u14-pad1_ u4 +a2 net-_u14-pad1_ net-_u14-pad2_ u14 +a3 net-_u1-pad2_ net-_u16-pad1_ u5 +a4 net-_u16-pad1_ net-_u16-pad2_ u16 +a5 [net-_u14-pad2_ net-_u16-pad2_ ] net-_u26-pad3_ u26 +a6 [net-_u26-pad3_ net-_u42-pad2_ ] net-_u42-pad3_ u42 +a7 net-_u42-pad3_ net-_u48-pad2_ u48 +a8 net-_u48-pad2_ net-_u52-pad2_ u52 +a9 net-_u52-pad2_ net-_u55-pad2_ u55 +a10 net-_u55-pad2_ net-_u58-pad2_ u58 +a11 net-_u58-pad2_ net-_u1-pad4_ u63 +a12 [net-_u29-pad1_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a13 [net-_u14-pad2_ net-_u16-pad2_ ] net-_u30-pad3_ u30 +a14 [net-_u16-pad2_ net-_u29-pad1_ ] net-_u31-pad3_ u31 +a15 [net-_u29-pad1_ net-_u35-pad2_ ] net-_u42-pad2_ u61 +a16 net-_u1-pad3_ net-_u12-pad2_ u12 +a17 net-_u12-pad2_ net-_u21-pad2_ u21 +a18 net-_u21-pad2_ net-_u35-pad2_ u35 +a19 net-_u1-pad5_ net-_u17-pad1_ u6 +a20 net-_u17-pad1_ net-_u17-pad2_ u17 +a21 net-_u1-pad6_ net-_u18-pad1_ u7 +a22 net-_u18-pad1_ net-_u18-pad2_ u18 +a23 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u27-pad3_ u27 +a24 [net-_u27-pad3_ net-_u43-pad2_ ] net-_u43-pad3_ u43 +a25 net-_u43-pad3_ net-_u49-pad2_ u49 +a26 net-_u49-pad2_ net-_u53-pad2_ u53 +a27 net-_u53-pad2_ net-_u56-pad2_ u56 +a28 net-_u56-pad2_ net-_u59-pad2_ u59 +a29 net-_u59-pad2_ net-_u1-pad8_ u65 +a30 [net-_u32-pad1_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a31 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u33-pad3_ u33 +a32 [net-_u18-pad2_ net-_u32-pad1_ ] net-_u34-pad3_ u34 +a33 [net-_u32-pad1_ net-_u40-pad2_ ] net-_u43-pad2_ u62 +a34 net-_u1-pad7_ net-_u13-pad2_ u13 +a35 net-_u13-pad2_ net-_u23-pad2_ u23 +a36 net-_u23-pad2_ net-_u40-pad2_ u40 +a37 net-_u1-pad9_ net-_u19-pad1_ u8 +a38 net-_u19-pad1_ net-_u19-pad2_ u19 +a39 net-_u1-pad10_ net-_u20-pad1_ u9 +a40 net-_u20-pad1_ net-_u20-pad2_ u20 +a41 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28 +a42 [net-_u28-pad3_ net-_u44-pad2_ ] net-_u44-pad3_ u44 +a43 net-_u44-pad3_ net-_u50-pad2_ u50 +a44 net-_u50-pad2_ net-_u54-pad2_ u54 +a45 net-_u54-pad2_ net-_u57-pad2_ u57 +a46 net-_u57-pad2_ net-_u60-pad2_ u60 +a47 net-_u60-pad2_ net-_u1-pad12_ u66 +a48 [net-_u36-pad1_ net-_u19-pad2_ ] net-_u36-pad3_ u36 +a49 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u37-pad3_ u37 +a50 [net-_u20-pad2_ net-_u36-pad1_ ] net-_u38-pad3_ u38 +a51 [net-_u36-pad1_ net-_u41-pad2_ ] net-_u44-pad2_ u64 +a52 net-_u1-pad11_ net-_u15-pad2_ u15 +a53 net-_u15-pad2_ net-_u25-pad2_ u25 +a54 net-_u25-pad2_ net-_u41-pad2_ u41 +a55 net-_u1-pad13_ net-_u10-pad1_ u2 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u10-pad2_ net-_u22-pad2_ u22 +a58 [net-_u3-pad3_ net-_u24-pad2_ ] net-_u45-pad3_ u51 +a59 net-_u1-pad14_ net-_u11-pad2_ u11 +a60 net-_u11-pad2_ net-_u24-pad2_ u24 +a61 net-_u24-pad2_ net-_u39-pad2_ u39 +a62 [net-_u22-pad2_ ] [net-_u24-pad2_ ] [net-_u3-pad3_ ] u3 +a63 [net-_u45-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u29-pad1_ ] u45 +a64 [net-_u47-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u32-pad1_ ] u47 +a65 [net-_u46-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u36-pad1_ ] u46 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u26 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u42 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u52 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u63 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u61 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u43 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u65 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u62 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u44 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u66 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u64 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: qb_dff, NgSpice Name: qb_dff +.model u3 qb_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u45 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u47 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u46 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B.pro b/library/SubcircuitLibrary/CD4038B/CD4038B.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B.sch b/library/SubcircuitLibrary/CD4038B/CD4038B.sch new file mode 100644 index 00000000..b0f70962 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B.sch @@ -0,0 +1,1423 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4032B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U4 +U 1 1 6853C07E +P 1500 1650 +F 0 "U4" H 1500 1550 60 0000 C CNN +F 1 "d_inverter" H 1500 1800 60 0000 C CNN +F 2 "" H 1550 1600 60 0000 C CNN +F 3 "" H 1550 1600 60 0000 C CNN + 1 1500 1650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6853C07F +P 2250 1650 +F 0 "U14" H 2250 1550 60 0000 C CNN +F 1 "d_inverter" H 2250 1800 60 0000 C CNN +F 2 "" H 2300 1600 60 0000 C CNN +F 3 "" H 2300 1600 60 0000 C CNN + 1 2250 1650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6853C080 +P 1500 2100 +F 0 "U5" H 1500 2000 60 0000 C CNN +F 1 "d_inverter" H 1500 2250 60 0000 C CNN +F 2 "" H 1550 2050 60 0000 C CNN +F 3 "" H 1550 2050 60 0000 C CNN + 1 1500 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6853C081 +P 2300 2100 +F 0 "U16" H 2300 2000 60 0000 C CNN +F 1 "d_inverter" H 2300 2250 60 0000 C CNN +F 2 "" H 2350 2050 60 0000 C CNN +F 3 "" H 2350 2050 60 0000 C CNN + 1 2300 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U26 +U 1 1 6853C082 +P 3800 1900 +F 0 "U26" H 3800 1900 60 0000 C CNN +F 1 "d_xor" H 3850 2000 47 0000 C CNN +F 2 "" H 3800 1900 60 0000 C CNN +F 3 "" H 3800 1900 60 0000 C CNN + 1 3800 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U42 +U 1 1 6853C083 +P 4900 1950 +F 0 "U42" H 4900 1950 60 0000 C CNN +F 1 "d_xnor" H 4950 2050 47 0000 C CNN +F 2 "" H 4900 1950 60 0000 C CNN +F 3 "" H 4900 1950 60 0000 C CNN + 1 4900 1950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U48 +U 1 1 6853C084 +P 5800 1900 +F 0 "U48" H 5800 1800 60 0000 C CNN +F 1 "d_inverter" H 5800 2050 60 0000 C CNN +F 2 "" H 5850 1850 60 0000 C CNN +F 3 "" H 5850 1850 60 0000 C CNN + 1 5800 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U52 +U 1 1 6853C085 +P 6750 1900 +F 0 "U52" H 6750 1850 60 0000 C CNN +F 1 "d_buffer" H 6750 1950 60 0000 C CNN +F 2 "" H 6750 1900 60 0000 C CNN +F 3 "" H 6750 1900 60 0000 C CNN + 1 6750 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U55 +U 1 1 6853C086 +P 7850 1900 +F 0 "U55" H 7850 1800 60 0000 C CNN +F 1 "d_inverter" H 7850 2050 60 0000 C CNN +F 2 "" H 7900 1850 60 0000 C CNN +F 3 "" H 7900 1850 60 0000 C CNN + 1 7850 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U58 +U 1 1 6853C087 +P 8650 1900 +F 0 "U58" H 8650 1800 60 0000 C CNN +F 1 "d_inverter" H 8650 2050 60 0000 C CNN +F 2 "" H 8700 1850 60 0000 C CNN +F 3 "" H 8700 1850 60 0000 C CNN + 1 8650 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U63 +U 1 1 6853C088 +P 9600 1900 +F 0 "U63" H 9600 1850 60 0000 C CNN +F 1 "d_buffer" H 9600 1950 60 0000 C CNN +F 2 "" H 9600 1900 60 0000 C CNN +F 3 "" H 9600 1900 60 0000 C CNN + 1 9600 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 6853C089 +P 4000 2700 +F 0 "U29" H 4000 2700 60 0000 C CNN +F 1 "d_and" H 4050 2800 60 0000 C CNN +F 2 "" H 4000 2700 60 0000 C CNN +F 3 "" H 4000 2700 60 0000 C CNN + 1 4000 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 6853C08A +P 4000 3250 +F 0 "U30" H 4000 3250 60 0000 C CNN +F 1 "d_and" H 4050 3350 60 0000 C CNN +F 2 "" H 4000 3250 60 0000 C CNN +F 3 "" H 4000 3250 60 0000 C CNN + 1 4000 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 6853C08B +P 4000 3900 +F 0 "U31" H 4000 3900 60 0000 C CNN +F 1 "d_and" H 4050 4000 60 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 1 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor_gate X1 +U 1 1 6853C08C +P 6100 3100 +F 0 "X1" H 6600 2700 60 0000 C CNN +F 1 "3_nor_gate" H 6150 2950 60 0000 C CNN +F 2 "" H 6150 2950 60 0001 C CNN +F 3 "" H 6150 2950 60 0001 C CNN + 1 6100 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U61 +U 1 1 6853C08D +P 9450 3850 +F 0 "U61" H 9450 3850 60 0000 C CNN +F 1 "d_xor" H 9500 3950 47 0000 C CNN +F 2 "" H 9450 3850 60 0000 C CNN +F 3 "" H 9450 3850 60 0000 C CNN + 1 9450 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6853C08E +P 2100 4650 +F 0 "U12" H 2100 4550 60 0000 C CNN +F 1 "d_inverter" H 2100 4800 60 0000 C CNN +F 2 "" H 2150 4600 60 0000 C CNN +F 3 "" H 2150 4600 60 0000 C CNN + 1 2100 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6853C08F +P 2900 4650 +F 0 "U21" H 2900 4550 60 0000 C CNN +F 1 "d_inverter" H 2900 4800 60 0000 C CNN +F 2 "" H 2950 4600 60 0000 C CNN +F 3 "" H 2950 4600 60 0000 C CNN + 1 2900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U35 +U 1 1 6853C090 +P 4150 4600 +F 0 "U35" H 4150 4550 60 0000 C CNN +F 1 "d_buffer" H 4150 4650 60 0000 C CNN +F 2 "" H 4150 4600 60 0000 C CNN +F 3 "" H 4150 4600 60 0000 C CNN + 1 4150 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6853C091 +P 5850 1150 +F 0 "U1" H 5900 1250 30 0000 C CNN +F 1 "PORT" H 5850 1150 30 0000 C CNN +F 2 "" H 5850 1150 60 0000 C CNN +F 3 "" H 5850 1150 60 0000 C CNN + 16 5850 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6853C092 +P 900 9400 +F 0 "U1" H 950 9500 30 0000 C CNN +F 1 "PORT" H 900 9400 30 0000 C CNN +F 2 "" H 900 9400 60 0000 C CNN +F 3 "" H 900 9400 60 0000 C CNN + 9 900 9400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6853C093 +P 11050 5650 +F 0 "U1" H 11100 5750 30 0000 C CNN +F 1 "PORT" H 11050 5650 30 0000 C CNN +F 2 "" H 11050 5650 60 0000 C CNN +F 3 "" H 11050 5650 60 0000 C CNN + 8 11050 5650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6853C094 +P 650 2100 +F 0 "U1" H 700 2200 30 0000 C CNN +F 1 "PORT" H 650 2100 30 0000 C CNN +F 2 "" H 650 2100 60 0000 C CNN +F 3 "" H 650 2100 60 0000 C CNN + 2 650 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6853C095 +P 1600 5400 +F 0 "U6" H 1600 5300 60 0000 C CNN +F 1 "d_inverter" H 1600 5550 60 0000 C CNN +F 2 "" H 1650 5350 60 0000 C CNN +F 3 "" H 1650 5350 60 0000 C CNN + 1 1600 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6853C096 +P 2350 5400 +F 0 "U17" H 2350 5300 60 0000 C CNN +F 1 "d_inverter" H 2350 5550 60 0000 C CNN +F 2 "" H 2400 5350 60 0000 C CNN +F 3 "" H 2400 5350 60 0000 C CNN + 1 2350 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6853C097 +P 1600 5850 +F 0 "U7" H 1600 5750 60 0000 C CNN +F 1 "d_inverter" H 1600 6000 60 0000 C CNN +F 2 "" H 1650 5800 60 0000 C CNN +F 3 "" H 1650 5800 60 0000 C CNN + 1 1600 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6853C098 +P 2400 5850 +F 0 "U18" H 2400 5750 60 0000 C CNN +F 1 "d_inverter" H 2400 6000 60 0000 C CNN +F 2 "" H 2450 5800 60 0000 C CNN +F 3 "" H 2450 5800 60 0000 C CNN + 1 2400 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U27 +U 1 1 6853C099 +P 3900 5650 +F 0 "U27" H 3900 5650 60 0000 C CNN +F 1 "d_xor" H 3950 5750 47 0000 C CNN +F 2 "" H 3900 5650 60 0000 C CNN +F 3 "" H 3900 5650 60 0000 C CNN + 1 3900 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U43 +U 1 1 6853C09A +P 5000 5700 +F 0 "U43" H 5000 5700 60 0000 C CNN +F 1 "d_xnor" H 5050 5800 47 0000 C CNN +F 2 "" H 5000 5700 60 0000 C CNN +F 3 "" H 5000 5700 60 0000 C CNN + 1 5000 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U49 +U 1 1 6853C09B +P 5900 5650 +F 0 "U49" H 5900 5550 60 0000 C CNN +F 1 "d_inverter" H 5900 5800 60 0000 C CNN +F 2 "" H 5950 5600 60 0000 C CNN +F 3 "" H 5950 5600 60 0000 C CNN + 1 5900 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U53 +U 1 1 6853C09C +P 6850 5650 +F 0 "U53" H 6850 5600 60 0000 C CNN +F 1 "d_buffer" H 6850 5700 60 0000 C CNN +F 2 "" H 6850 5650 60 0000 C CNN +F 3 "" H 6850 5650 60 0000 C CNN + 1 6850 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U56 +U 1 1 6853C09D +P 7950 5650 +F 0 "U56" H 7950 5550 60 0000 C CNN +F 1 "d_inverter" H 7950 5800 60 0000 C CNN +F 2 "" H 8000 5600 60 0000 C CNN +F 3 "" H 8000 5600 60 0000 C CNN + 1 7950 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U59 +U 1 1 6853C09E +P 8750 5650 +F 0 "U59" H 8750 5550 60 0000 C CNN +F 1 "d_inverter" H 8750 5800 60 0000 C CNN +F 2 "" H 8800 5600 60 0000 C CNN +F 3 "" H 8800 5600 60 0000 C CNN + 1 8750 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U65 +U 1 1 6853C09F +P 9700 5650 +F 0 "U65" H 9700 5600 60 0000 C CNN +F 1 "d_buffer" H 9700 5700 60 0000 C CNN +F 2 "" H 9700 5650 60 0000 C CNN +F 3 "" H 9700 5650 60 0000 C CNN + 1 9700 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U32 +U 1 1 6853C0A0 +P 4100 6450 +F 0 "U32" H 4100 6450 60 0000 C CNN +F 1 "d_and" H 4150 6550 60 0000 C CNN +F 2 "" H 4100 6450 60 0000 C CNN +F 3 "" H 4100 6450 60 0000 C CNN + 1 4100 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U33 +U 1 1 6853C0A1 +P 4100 7000 +F 0 "U33" H 4100 7000 60 0000 C CNN +F 1 "d_and" H 4150 7100 60 0000 C CNN +F 2 "" H 4100 7000 60 0000 C CNN +F 3 "" H 4100 7000 60 0000 C CNN + 1 4100 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U34 +U 1 1 6853C0A2 +P 4100 7650 +F 0 "U34" H 4100 7650 60 0000 C CNN +F 1 "d_and" H 4150 7750 60 0000 C CNN +F 2 "" H 4100 7650 60 0000 C CNN +F 3 "" H 4100 7650 60 0000 C CNN + 1 4100 7650 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor_gate X2 +U 1 1 6853C0A3 +P 6200 6850 +F 0 "X2" H 6700 6450 60 0000 C CNN +F 1 "3_nor_gate" H 6250 6700 60 0000 C CNN +F 2 "" H 6250 6700 60 0001 C CNN +F 3 "" H 6250 6700 60 0001 C CNN + 1 6200 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U62 +U 1 1 6853C0A4 +P 9550 7600 +F 0 "U62" H 9550 7600 60 0000 C CNN +F 1 "d_xor" H 9600 7700 47 0000 C CNN +F 2 "" H 9550 7600 60 0000 C CNN +F 3 "" H 9550 7600 60 0000 C CNN + 1 9550 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 6853C0A5 +P 2200 8400 +F 0 "U13" H 2200 8300 60 0000 C CNN +F 1 "d_inverter" H 2200 8550 60 0000 C CNN +F 2 "" H 2250 8350 60 0000 C CNN +F 3 "" H 2250 8350 60 0000 C CNN + 1 2200 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6853C0A6 +P 3000 8400 +F 0 "U23" H 3000 8300 60 0000 C CNN +F 1 "d_inverter" H 3000 8550 60 0000 C CNN +F 2 "" H 3050 8350 60 0000 C CNN +F 3 "" H 3050 8350 60 0000 C CNN + 1 3000 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U40 +U 1 1 6853C0A7 +P 4250 8350 +F 0 "U40" H 4250 8300 60 0000 C CNN +F 1 "d_buffer" H 4250 8400 60 0000 C CNN +F 2 "" H 4250 8350 60 0000 C CNN +F 3 "" H 4250 8350 60 0000 C CNN + 1 4250 8350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6853C0A8 +P 800 9850 +F 0 "U1" H 850 9950 30 0000 C CNN +F 1 "PORT" H 800 9850 30 0000 C CNN +F 2 "" H 800 9850 60 0000 C CNN +F 3 "" H 800 9850 60 0000 C CNN + 10 800 9850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6853C0A9 +P 1150 8400 +F 0 "U1" H 1200 8500 30 0000 C CNN +F 1 "PORT" H 1150 8400 30 0000 C CNN +F 2 "" H 1150 8400 60 0000 C CNN +F 3 "" H 1150 8400 60 0000 C CNN + 7 1150 8400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6853C0AA +P 750 5850 +F 0 "U1" H 800 5950 30 0000 C CNN +F 1 "PORT" H 750 5850 30 0000 C CNN +F 2 "" H 750 5850 60 0000 C CNN +F 3 "" H 750 5850 60 0000 C CNN + 6 750 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6853C0AB +P 11100 9650 +F 0 "U1" H 11150 9750 30 0000 C CNN +F 1 "PORT" H 11100 9650 30 0000 C CNN +F 2 "" H 11100 9650 60 0000 C CNN +F 3 "" H 11100 9650 60 0000 C CNN + 12 11100 9650 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6853C0AC +P 1650 9400 +F 0 "U8" H 1650 9300 60 0000 C CNN +F 1 "d_inverter" H 1650 9550 60 0000 C CNN +F 2 "" H 1700 9350 60 0000 C CNN +F 3 "" H 1700 9350 60 0000 C CNN + 1 1650 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6853C0AD +P 2400 9400 +F 0 "U19" H 2400 9300 60 0000 C CNN +F 1 "d_inverter" H 2400 9550 60 0000 C CNN +F 2 "" H 2450 9350 60 0000 C CNN +F 3 "" H 2450 9350 60 0000 C CNN + 1 2400 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6853C0AE +P 1650 9850 +F 0 "U9" H 1650 9750 60 0000 C CNN +F 1 "d_inverter" H 1650 10000 60 0000 C CNN +F 2 "" H 1700 9800 60 0000 C CNN +F 3 "" H 1700 9800 60 0000 C CNN + 1 1650 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6853C0AF +P 2450 9850 +F 0 "U20" H 2450 9750 60 0000 C CNN +F 1 "d_inverter" H 2450 10000 60 0000 C CNN +F 2 "" H 2500 9800 60 0000 C CNN +F 3 "" H 2500 9800 60 0000 C CNN + 1 2450 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U28 +U 1 1 6853C0B0 +P 3950 9650 +F 0 "U28" H 3950 9650 60 0000 C CNN +F 1 "d_xor" H 4000 9750 47 0000 C CNN +F 2 "" H 3950 9650 60 0000 C CNN +F 3 "" H 3950 9650 60 0000 C CNN + 1 3950 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U44 +U 1 1 6853C0B1 +P 5050 9700 +F 0 "U44" H 5050 9700 60 0000 C CNN +F 1 "d_xnor" H 5100 9800 47 0000 C CNN +F 2 "" H 5050 9700 60 0000 C CNN +F 3 "" H 5050 9700 60 0000 C CNN + 1 5050 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U50 +U 1 1 6853C0B2 +P 5950 9650 +F 0 "U50" H 5950 9550 60 0000 C CNN +F 1 "d_inverter" H 5950 9800 60 0000 C CNN +F 2 "" H 6000 9600 60 0000 C CNN +F 3 "" H 6000 9600 60 0000 C CNN + 1 5950 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U54 +U 1 1 6853C0B3 +P 6900 9650 +F 0 "U54" H 6900 9600 60 0000 C CNN +F 1 "d_buffer" H 6900 9700 60 0000 C CNN +F 2 "" H 6900 9650 60 0000 C CNN +F 3 "" H 6900 9650 60 0000 C CNN + 1 6900 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U57 +U 1 1 6853C0B4 +P 8000 9650 +F 0 "U57" H 8000 9550 60 0000 C CNN +F 1 "d_inverter" H 8000 9800 60 0000 C CNN +F 2 "" H 8050 9600 60 0000 C CNN +F 3 "" H 8050 9600 60 0000 C CNN + 1 8000 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U60 +U 1 1 6853C0B5 +P 8800 9650 +F 0 "U60" H 8800 9550 60 0000 C CNN +F 1 "d_inverter" H 8800 9800 60 0000 C CNN +F 2 "" H 8850 9600 60 0000 C CNN +F 3 "" H 8850 9600 60 0000 C CNN + 1 8800 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U66 +U 1 1 6853C0B6 +P 9750 9650 +F 0 "U66" H 9750 9600 60 0000 C CNN +F 1 "d_buffer" H 9750 9700 60 0000 C CNN +F 2 "" H 9750 9650 60 0000 C CNN +F 3 "" H 9750 9650 60 0000 C CNN + 1 9750 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U36 +U 1 1 6853C0B7 +P 4150 10450 +F 0 "U36" H 4150 10450 60 0000 C CNN +F 1 "d_and" H 4200 10550 60 0000 C CNN +F 2 "" H 4150 10450 60 0000 C CNN +F 3 "" H 4150 10450 60 0000 C CNN + 1 4150 10450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U37 +U 1 1 6853C0B8 +P 4150 11000 +F 0 "U37" H 4150 11000 60 0000 C CNN +F 1 "d_and" H 4200 11100 60 0000 C CNN +F 2 "" H 4150 11000 60 0000 C CNN +F 3 "" H 4150 11000 60 0000 C CNN + 1 4150 11000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U38 +U 1 1 6853C0B9 +P 4150 11650 +F 0 "U38" H 4150 11650 60 0000 C CNN +F 1 "d_and" H 4200 11750 60 0000 C CNN +F 2 "" H 4150 11650 60 0000 C CNN +F 3 "" H 4150 11650 60 0000 C CNN + 1 4150 11650 + 1 0 0 -1 +$EndComp +$Comp +L 3_nor_gate X3 +U 1 1 6853C0BA +P 6250 10850 +F 0 "X3" H 6750 10450 60 0000 C CNN +F 1 "3_nor_gate" H 6300 10700 60 0000 C CNN +F 2 "" H 6300 10700 60 0001 C CNN +F 3 "" H 6300 10700 60 0001 C CNN + 1 6250 10850 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U64 +U 1 1 6853C0BB +P 9600 11600 +F 0 "U64" H 9600 11600 60 0000 C CNN +F 1 "d_xor" H 9650 11700 47 0000 C CNN +F 2 "" H 9600 11600 60 0000 C CNN +F 3 "" H 9600 11600 60 0000 C CNN + 1 9600 11600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6853C0BC +P 2250 12400 +F 0 "U15" H 2250 12300 60 0000 C CNN +F 1 "d_inverter" H 2250 12550 60 0000 C CNN +F 2 "" H 2300 12350 60 0000 C CNN +F 3 "" H 2300 12350 60 0000 C CNN + 1 2250 12400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 6853C0BD +P 3050 12400 +F 0 "U25" H 3050 12300 60 0000 C CNN +F 1 "d_inverter" H 3050 12550 60 0000 C CNN +F 2 "" H 3100 12350 60 0000 C CNN +F 3 "" H 3100 12350 60 0000 C CNN + 1 3050 12400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U41 +U 1 1 6853C0BE +P 4300 12350 +F 0 "U41" H 4300 12300 60 0000 C CNN +F 1 "d_buffer" H 4300 12400 60 0000 C CNN +F 2 "" H 4300 12350 60 0000 C CNN +F 3 "" H 4300 12350 60 0000 C CNN + 1 4300 12350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6853C0BF +P 800 15150 +F 0 "U1" H 850 15250 30 0000 C CNN +F 1 "PORT" H 800 15150 30 0000 C CNN +F 2 "" H 800 15150 60 0000 C CNN +F 3 "" H 800 15150 60 0000 C CNN + 14 800 15150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6853C0C0 +P 850 5400 +F 0 "U1" H 900 5500 30 0000 C CNN +F 1 "PORT" H 850 5400 30 0000 C CNN +F 2 "" H 850 5400 60 0000 C CNN +F 3 "" H 850 5400 60 0000 C CNN + 5 850 5400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6853C0C1 +P 1200 12400 +F 0 "U1" H 1250 12500 30 0000 C CNN +F 1 "PORT" H 1200 12400 30 0000 C CNN +F 2 "" H 1200 12400 60 0000 C CNN +F 3 "" H 1200 12400 60 0000 C CNN + 11 1200 12400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6853C0C2 +P 100 13300 +F 0 "U1" H 150 13400 30 0000 C CNN +F 1 "PORT" H 100 13300 30 0000 C CNN +F 2 "" H 100 13300 60 0000 C CNN +F 3 "" H 100 13300 60 0000 C CNN + 13 100 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6853C0C3 +P 900 13300 +F 0 "U2" H 900 13200 60 0000 C CNN +F 1 "d_inverter" H 900 13450 60 0000 C CNN +F 2 "" H 950 13250 60 0000 C CNN +F 3 "" H 950 13250 60 0000 C CNN + 1 900 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6853C0C4 +P 1850 13300 +F 0 "U10" H 1850 13200 60 0000 C CNN +F 1 "d_inverter" H 1850 13450 60 0000 C CNN +F 2 "" H 1900 13250 60 0000 C CNN +F 3 "" H 1900 13250 60 0000 C CNN + 1 1850 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U22 +U 1 1 6853C0C5 +P 2900 13300 +F 0 "U22" H 2900 13250 60 0000 C CNN +F 1 "d_buffer" H 2900 13350 60 0000 C CNN +F 2 "" H 2900 13300 60 0000 C CNN +F 3 "" H 2900 13300 60 0000 C CNN + 1 2900 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U51 +U 1 1 6853C0C6 +P 6700 14050 +F 0 "U51" H 6700 14050 60 0000 C CNN +F 1 "d_nand" H 6750 14150 60 0000 C CNN +F 2 "" H 6700 14050 60 0000 C CNN +F 3 "" H 6700 14050 60 0000 C CNN + 1 6700 14050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6853C0C7 +P 1950 14900 +F 0 "U11" H 1950 14800 60 0000 C CNN +F 1 "d_inverter" H 1950 15050 60 0000 C CNN +F 2 "" H 2000 14850 60 0000 C CNN +F 3 "" H 2000 14850 60 0000 C CNN + 1 1950 14900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6853C0C8 +P 3000 14900 +F 0 "U24" H 3000 14800 60 0000 C CNN +F 1 "d_inverter" H 3000 15050 60 0000 C CNN +F 2 "" H 3050 14850 60 0000 C CNN +F 3 "" H 3050 14850 60 0000 C CNN + 1 3000 14900 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U39 +U 1 1 6853C0C9 +P 4150 14900 +F 0 "U39" H 4150 14850 60 0000 C CNN +F 1 "d_buffer" H 4150 14950 60 0000 C CNN +F 2 "" H 4150 14900 60 0000 C CNN +F 3 "" H 4150 14900 60 0000 C CNN + 1 4150 14900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6853C0CA +P 10950 1900 +F 0 "U1" H 11000 2000 30 0000 C CNN +F 1 "PORT" H 10950 1900 30 0000 C CNN +F 2 "" H 10950 1900 60 0000 C CNN +F 3 "" H 10950 1900 60 0000 C CNN + 4 10950 1900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6853C0CB +P 1050 4650 +F 0 "U1" H 1100 4750 30 0000 C CNN +F 1 "PORT" H 1050 4650 30 0000 C CNN +F 2 "" H 1050 4650 60 0000 C CNN +F 3 "" H 1050 4650 60 0000 C CNN + 3 1050 4650 + 1 0 0 -1 +$EndComp +Text GLabel 6750 950 2 60 Input ~ 0 +VDD +Text GLabel 6800 1150 2 60 Input ~ 0 +VSS +$Comp +L PORT U1 +U 1 1 6853C0CC +P 750 1650 +F 0 "U1" H 800 1750 30 0000 C CNN +F 1 "PORT" H 750 1650 30 0000 C CNN +F 2 "" H 750 1650 60 0000 C CNN +F 3 "" H 750 1650 60 0000 C CNN + 1 750 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6853C0CD +P 5900 900 +F 0 "U1" H 5950 1000 30 0000 C CNN +F 1 "PORT" H 5900 900 30 0000 C CNN +F 2 "" H 5900 900 60 0000 C CNN +F 3 "" H 5900 900 60 0000 C CNN + 15 5900 900 + 1 0 0 -1 +$EndComp +Text GLabel 5850 2700 0 60 Input ~ 0 +VDD +Text GLabel 6000 6450 0 60 Input ~ 0 +VDD +Text GLabel 6150 10450 0 60 Input ~ 0 +VDD +Text GLabel 6550 3750 2 60 Input ~ 0 +VSS +Text GLabel 6300 7500 0 60 Input ~ 0 +VSS +Text GLabel 6200 11500 0 60 Input ~ 0 +VSS +$Comp +L qb_dff U3 +U 1 1 6853C0CE +P 1300 15750 +F 0 "U3" H 4150 17550 60 0000 C CNN +F 1 "qb_dff" H 4150 17750 60 0000 C CNN +F 2 "" H 4150 17700 60 0000 C CNN +F 3 "" H 4150 17700 60 0000 C CNN + 1 1300 15750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1800 1650 1950 1650 +Wire Wire Line + 1800 2100 2000 2100 +Wire Wire Line + 2550 1650 3100 1650 +Wire Wire Line + 3100 1650 3100 1800 +Wire Wire Line + 3100 1800 3350 1800 +Wire Wire Line + 2600 2100 2600 1900 +Wire Wire Line + 2600 1900 3350 1900 +Wire Wire Line + 4250 1850 4450 1850 +Wire Wire Line + 5350 1900 5500 1900 +Wire Wire Line + 6100 1900 6250 1900 +Wire Wire Line + 7400 1900 7550 1900 +Wire Wire Line + 8150 1900 8350 1900 +Wire Wire Line + 8950 1900 9100 1900 +Wire Wire Line + 4450 2650 5400 2650 +Wire Wire Line + 5400 2650 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 4450 3200 5250 3200 +Wire Wire Line + 5250 3200 5250 3100 +Wire Wire Line + 5250 3100 5550 3100 +Wire Wire Line + 4450 3850 4450 3250 +Wire Wire Line + 4450 3250 5550 3250 +Wire Wire Line + 9000 3700 9000 3750 +Wire Wire Line + 4450 1950 4450 2300 +Wire Wire Line + 4450 2300 10150 2300 +Wire Wire Line + 10150 2300 10150 3800 +Wire Wire Line + 10150 3800 9900 3800 +Wire Wire Line + 3550 3900 3550 4300 +Wire Wire Line + 3550 4300 8700 4300 +Wire Wire Line + 8700 4300 8700 2450 +Connection ~ 8700 3700 +Wire Wire Line + 2950 3250 3550 3250 +Wire Wire Line + 2950 3800 3550 3800 +Wire Wire Line + 3550 2600 3550 2450 +Wire Wire Line + 3550 2450 8700 2450 +Connection ~ 3200 1800 +Connection ~ 2950 1900 +Wire Wire Line + 3200 1800 3200 3150 +Wire Wire Line + 3200 2700 3550 2700 +Wire Wire Line + 3200 3150 3550 3150 +Connection ~ 3200 2700 +Wire Wire Line + 2950 1900 2950 3800 +Connection ~ 2950 3250 +Wire Wire Line + 2400 4650 2600 4650 +Wire Wire Line + 3200 4650 3450 4650 +Wire Wire Line + 3450 4650 3450 4600 +Wire Wire Line + 3450 4600 3650 4600 +Wire Wire Line + 4800 4600 9000 4600 +Wire Wire Line + 9000 4600 9000 3850 +Wire Wire Line + 1000 1650 1200 1650 +Wire Wire Line + 900 2100 1200 2100 +Wire Wire Line + 1300 4650 1800 4650 +Wire Wire Line + 10250 1900 10700 1900 +Wire Wire Line + 1900 5400 2050 5400 +Wire Wire Line + 1900 5850 2100 5850 +Wire Wire Line + 2650 5400 3200 5400 +Wire Wire Line + 3200 5400 3200 5550 +Wire Wire Line + 3200 5550 3450 5550 +Wire Wire Line + 2700 5850 2700 5650 +Wire Wire Line + 2700 5650 3450 5650 +Wire Wire Line + 4350 5600 4550 5600 +Wire Wire Line + 5450 5650 5600 5650 +Wire Wire Line + 6200 5650 6350 5650 +Wire Wire Line + 7500 5650 7650 5650 +Wire Wire Line + 8250 5650 8450 5650 +Wire Wire Line + 9050 5650 9200 5650 +Wire Wire Line + 4550 6400 5500 6400 +Wire Wire Line + 5500 6400 5500 6750 +Wire Wire Line + 5500 6750 5650 6750 +Wire Wire Line + 4550 6950 5350 6950 +Wire Wire Line + 5350 6950 5350 6850 +Wire Wire Line + 5350 6850 5650 6850 +Wire Wire Line + 4550 7600 4550 7000 +Wire Wire Line + 4550 7000 5650 7000 +Wire Wire Line + 8550 7550 8550 7450 +Wire Wire Line + 8550 7450 9100 7450 +Wire Wire Line + 9100 7450 9100 7500 +Wire Wire Line + 4550 5700 4550 6050 +Wire Wire Line + 4550 6050 10250 6050 +Wire Wire Line + 10250 6050 10250 7550 +Wire Wire Line + 10250 7550 10000 7550 +Wire Wire Line + 3650 7650 3650 8050 +Wire Wire Line + 3650 8050 8800 8050 +Wire Wire Line + 8800 8050 8800 6200 +Connection ~ 8800 7450 +Wire Wire Line + 3050 7000 3650 7000 +Wire Wire Line + 3050 7550 3650 7550 +Wire Wire Line + 3650 6350 3650 6200 +Wire Wire Line + 3650 6200 8800 6200 +Connection ~ 3300 5550 +Connection ~ 3050 5650 +Wire Wire Line + 3300 5550 3300 6900 +Wire Wire Line + 3300 6450 3650 6450 +Wire Wire Line + 3300 6900 3650 6900 +Connection ~ 3300 6450 +Wire Wire Line + 3050 5650 3050 7550 +Connection ~ 3050 7000 +Wire Wire Line + 2500 8400 2700 8400 +Wire Wire Line + 3300 8400 3550 8400 +Wire Wire Line + 3550 8400 3550 8350 +Wire Wire Line + 3550 8350 3750 8350 +Wire Wire Line + 4900 8350 9100 8350 +Wire Wire Line + 9100 8350 9100 7600 +Wire Wire Line + 1100 5400 1300 5400 +Wire Wire Line + 1000 5850 1300 5850 +Wire Wire Line + 1400 8400 1900 8400 +Wire Wire Line + 10350 5650 10800 5650 +Wire Wire Line + 1950 9400 2100 9400 +Wire Wire Line + 1950 9850 2150 9850 +Wire Wire Line + 2700 9400 3250 9400 +Wire Wire Line + 3250 9400 3250 9550 +Wire Wire Line + 3250 9550 3500 9550 +Wire Wire Line + 2750 9850 2750 9650 +Wire Wire Line + 2750 9650 3500 9650 +Wire Wire Line + 4400 9600 4600 9600 +Wire Wire Line + 5500 9650 5650 9650 +Wire Wire Line + 6250 9650 6400 9650 +Wire Wire Line + 7550 9650 7700 9650 +Wire Wire Line + 8300 9650 8500 9650 +Wire Wire Line + 9100 9650 9250 9650 +Wire Wire Line + 4600 10400 5550 10400 +Wire Wire Line + 5550 10400 5550 10750 +Wire Wire Line + 5550 10750 5700 10750 +Wire Wire Line + 4600 10950 5400 10950 +Wire Wire Line + 5400 10950 5400 10850 +Wire Wire Line + 5400 10850 5700 10850 +Wire Wire Line + 4600 11600 4600 11000 +Wire Wire Line + 4600 11000 5700 11000 +Wire Wire Line + 9150 11450 9150 11500 +Wire Wire Line + 4600 9700 4600 10050 +Wire Wire Line + 4600 10050 10300 10050 +Wire Wire Line + 10300 10050 10300 11550 +Wire Wire Line + 10300 11550 10050 11550 +Wire Wire Line + 3700 11650 3700 12050 +Wire Wire Line + 3700 12050 8850 12050 +Wire Wire Line + 8850 12050 8850 10200 +Connection ~ 8850 11450 +Wire Wire Line + 3100 11000 3700 11000 +Wire Wire Line + 3100 11550 3700 11550 +Wire Wire Line + 3700 10350 3700 10200 +Wire Wire Line + 3700 10200 8850 10200 +Connection ~ 3350 9550 +Connection ~ 3100 9650 +Wire Wire Line + 3350 9550 3350 10900 +Wire Wire Line + 3350 10450 3700 10450 +Wire Wire Line + 3350 10900 3700 10900 +Connection ~ 3350 10450 +Wire Wire Line + 3100 9650 3100 11550 +Connection ~ 3100 11000 +Wire Wire Line + 2550 12400 2750 12400 +Wire Wire Line + 3350 12400 3600 12400 +Wire Wire Line + 3600 12400 3600 12350 +Wire Wire Line + 3600 12350 3800 12350 +Wire Wire Line + 4950 12350 9150 12350 +Wire Wire Line + 9150 12350 9150 11600 +Wire Wire Line + 1150 9400 1350 9400 +Wire Wire Line + 1050 9850 1350 9850 +Wire Wire Line + 1450 12400 1950 12400 +Wire Wire Line + 10400 9650 10850 9650 +Wire Wire Line + 1200 13300 1550 13300 +Wire Wire Line + 2150 13300 2400 13300 +Wire Wire Line + 2250 14900 2700 14900 +Wire Wire Line + 3300 14900 3650 14900 +Wire Wire Line + 4850 13950 6250 13950 +Wire Wire Line + 3450 13950 3450 14900 +Connection ~ 3450 14900 +Wire Wire Line + 3450 14500 6250 14500 +Wire Wire Line + 6250 14500 6250 14050 +Connection ~ 3450 14500 +Wire Wire Line + 7150 2850 7150 14000 +Wire Wire Line + 7400 14900 4800 14900 +Wire Wire Line + 7400 3850 7400 14900 +Wire Wire Line + 7350 3850 7400 3850 +Wire Wire Line + 7350 3700 7350 3850 +Wire Wire Line + 350 13300 600 13300 +Wire Wire Line + 800 14900 1650 14900 +Wire Wire Line + 6150 900 6700 900 +Wire Wire Line + 6700 900 6700 950 +Wire Wire Line + 6700 950 6750 950 +Wire Wire Line + 6100 1150 6800 1150 +Wire Wire Line + 5850 2700 6250 2700 +Wire Wire Line + 6000 6450 6350 6450 +Wire Wire Line + 6150 10450 6400 10450 +Wire Wire Line + 6450 3600 6450 3750 +Wire Wire Line + 6450 3750 6550 3750 +Wire Wire Line + 6300 7500 6550 7500 +Wire Wire Line + 6550 7500 6550 7350 +Wire Wire Line + 6200 11500 6600 11500 +Wire Wire Line + 6600 11500 6600 11350 +Wire Wire Line + 3550 13300 3550 13700 +Wire Wire Line + 3550 13700 3450 13700 +Wire Wire Line + 3450 13700 3450 13850 +Wire Wire Line + 4850 13850 4850 13950 +Wire Wire Line + 6900 11000 7550 11000 +Wire Wire Line + 7150 11200 7550 11200 +Connection ~ 7150 11200 +Wire Wire Line + 7400 11100 7550 11100 +Connection ~ 7400 11100 +Wire Wire Line + 9150 11450 8850 11450 +Wire Wire Line + 8950 11000 8950 11450 +Connection ~ 8950 11450 +Wire Wire Line + 7150 7000 7900 7000 +Connection ~ 7150 7000 +Wire Wire Line + 7400 6950 7900 6950 +Wire Wire Line + 7900 6950 7900 6900 +Connection ~ 7400 6950 +Wire Wire Line + 9300 6800 9400 6800 +Wire Wire Line + 9400 6800 9400 7300 +Wire Wire Line + 9400 7300 8400 7300 +Wire Wire Line + 8400 7300 8400 7550 +Wire Wire Line + 8400 7550 8550 7550 +Wire Wire Line + 7150 2850 6950 2850 +Wire Wire Line + 6950 2850 6950 3550 +Wire Wire Line + 6950 3550 7250 3550 +Wire Wire Line + 7350 3700 7200 3700 +Wire Wire Line + 7200 3700 7200 3450 +Wire Wire Line + 7200 3450 7250 3450 +Wire Wire Line + 8650 3350 8650 3700 +Wire Wire Line + 8650 3700 9000 3700 +Wire Wire Line + 6850 6900 7700 6900 +Wire Wire Line + 7700 6900 7700 6800 +Wire Wire Line + 7700 6800 7900 6800 +Wire Wire Line + 6750 3150 6750 3350 +Wire Wire Line + 6750 3350 7250 3350 +Wire Wire Line + 6900 10900 6900 11000 +$Comp +L r_dff U45 +U 1 1 6853D681 +P 5100 5250 +F 0 "U45" H 7950 7050 60 0000 C CNN +F 1 "r_dff" H 7950 7250 60 0000 C CNN +F 2 "" H 7950 7200 60 0000 C CNN +F 3 "" H 7950 7200 60 0000 C CNN + 1 5100 5250 + 1 0 0 -1 +$EndComp +$Comp +L r_dff U47 +U 1 1 6853E23F +P 5750 8700 +F 0 "U47" H 8600 10500 60 0000 C CNN +F 1 "r_dff" H 8600 10700 60 0000 C CNN +F 2 "" H 8600 10650 60 0000 C CNN +F 3 "" H 8600 10650 60 0000 C CNN + 1 5750 8700 + 1 0 0 -1 +$EndComp +$Comp +L r_dff U46 +U 1 1 6853E694 +P 5400 12900 +F 0 "U46" H 8250 14700 60 0000 C CNN +F 1 "r_dff" H 8250 14900 60 0000 C CNN +F 2 "" H 8250 14850 60 0000 C CNN +F 3 "" H 8250 14850 60 0000 C CNN + 1 5400 12900 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B.sub b/library/SubcircuitLibrary/CD4038B/CD4038B.sub new file mode 100644 index 00000000..2f6df05f --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B.sub @@ -0,0 +1,270 @@ +* Subcircuit CD4038B +.subckt CD4038B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ vdd vss +* c:\fossee\esim\library\subcircuitlibrary\cd4038b\cd4038b.cir +.include 3_nor.sub +* u4 net-_u1-pad1_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u16-pad1_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u26 net-_u14-pad2_ net-_u16-pad2_ net-_u26-pad3_ d_xor +* u42 net-_u26-pad3_ net-_u42-pad2_ net-_u42-pad3_ d_xnor +* u48 net-_u42-pad3_ net-_u48-pad2_ d_inverter +* u52 net-_u48-pad2_ net-_u52-pad2_ d_buffer +* u55 net-_u52-pad2_ net-_u55-pad2_ d_inverter +* u58 net-_u55-pad2_ net-_u58-pad2_ d_inverter +* u63 net-_u58-pad2_ net-_u1-pad4_ d_buffer +* u29 net-_u29-pad1_ net-_u14-pad2_ net-_u29-pad3_ d_and +* u30 net-_u14-pad2_ net-_u16-pad2_ net-_u30-pad3_ d_and +* u31 net-_u16-pad2_ net-_u29-pad1_ net-_u31-pad3_ d_and +x1 net-_u29-pad3_ net-_u30-pad3_ net-_u31-pad3_ vdd vss net-_u45-pad1_ 3_nor +* u61 net-_u29-pad1_ net-_u35-pad2_ net-_u42-pad2_ d_xor +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u21 net-_u12-pad2_ net-_u21-pad2_ d_inverter +* u35 net-_u21-pad2_ net-_u35-pad2_ d_buffer +* u6 net-_u1-pad5_ net-_u17-pad1_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u18-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u27 net-_u17-pad2_ net-_u18-pad2_ net-_u27-pad3_ d_xor +* u43 net-_u27-pad3_ net-_u43-pad2_ net-_u43-pad3_ d_xnor +* u49 net-_u43-pad3_ net-_u49-pad2_ d_inverter +* u53 net-_u49-pad2_ net-_u53-pad2_ d_buffer +* u56 net-_u53-pad2_ net-_u56-pad2_ d_inverter +* u59 net-_u56-pad2_ net-_u59-pad2_ d_inverter +* u65 net-_u59-pad2_ net-_u1-pad8_ d_buffer +* u32 net-_u32-pad1_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u33 net-_u17-pad2_ net-_u18-pad2_ net-_u33-pad3_ d_and +* u34 net-_u18-pad2_ net-_u32-pad1_ net-_u34-pad3_ d_and +x2 net-_u32-pad3_ net-_u33-pad3_ net-_u34-pad3_ vdd vss net-_u47-pad1_ 3_nor +* u62 net-_u32-pad1_ net-_u40-pad2_ net-_u43-pad2_ d_xor +* u13 net-_u1-pad7_ net-_u13-pad2_ d_inverter +* u23 net-_u13-pad2_ net-_u23-pad2_ d_inverter +* u40 net-_u23-pad2_ net-_u40-pad2_ d_buffer +* u8 net-_u1-pad9_ net-_u19-pad1_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u9 net-_u1-pad10_ net-_u20-pad1_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u28 net-_u19-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_xor +* u44 net-_u28-pad3_ net-_u44-pad2_ net-_u44-pad3_ d_xnor +* u50 net-_u44-pad3_ net-_u50-pad2_ d_inverter +* u54 net-_u50-pad2_ net-_u54-pad2_ d_buffer +* u57 net-_u54-pad2_ net-_u57-pad2_ d_inverter +* u60 net-_u57-pad2_ net-_u60-pad2_ d_inverter +* u66 net-_u60-pad2_ net-_u1-pad12_ d_buffer +* u36 net-_u36-pad1_ net-_u19-pad2_ net-_u36-pad3_ d_and +* u37 net-_u19-pad2_ net-_u20-pad2_ net-_u37-pad3_ d_and +* u38 net-_u20-pad2_ net-_u36-pad1_ net-_u38-pad3_ d_and +x3 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ vdd vss net-_u46-pad1_ 3_nor +* u64 net-_u36-pad1_ net-_u41-pad2_ net-_u44-pad2_ d_xor +* u15 net-_u1-pad11_ net-_u15-pad2_ d_inverter +* u25 net-_u15-pad2_ net-_u25-pad2_ d_inverter +* u41 net-_u25-pad2_ net-_u41-pad2_ d_buffer +* u2 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u22 net-_u10-pad2_ net-_u22-pad2_ d_buffer +* u51 net-_u3-pad3_ net-_u24-pad2_ net-_u45-pad3_ d_nand +* u11 net-_u1-pad14_ net-_u11-pad2_ d_inverter +* u24 net-_u11-pad2_ net-_u24-pad2_ d_inverter +* u39 net-_u24-pad2_ net-_u39-pad2_ d_buffer +* u3 net-_u22-pad2_ net-_u24-pad2_ net-_u3-pad3_ qb_dff +* u45 net-_u45-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u29-pad1_ r_dff +* u47 net-_u47-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u32-pad1_ r_dff +* u46 net-_u46-pad1_ net-_u39-pad2_ net-_u45-pad3_ net-_u36-pad1_ r_dff +a1 net-_u1-pad1_ net-_u14-pad1_ u4 +a2 net-_u14-pad1_ net-_u14-pad2_ u14 +a3 net-_u1-pad2_ net-_u16-pad1_ u5 +a4 net-_u16-pad1_ net-_u16-pad2_ u16 +a5 [net-_u14-pad2_ net-_u16-pad2_ ] net-_u26-pad3_ u26 +a6 [net-_u26-pad3_ net-_u42-pad2_ ] net-_u42-pad3_ u42 +a7 net-_u42-pad3_ net-_u48-pad2_ u48 +a8 net-_u48-pad2_ net-_u52-pad2_ u52 +a9 net-_u52-pad2_ net-_u55-pad2_ u55 +a10 net-_u55-pad2_ net-_u58-pad2_ u58 +a11 net-_u58-pad2_ net-_u1-pad4_ u63 +a12 [net-_u29-pad1_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a13 [net-_u14-pad2_ net-_u16-pad2_ ] net-_u30-pad3_ u30 +a14 [net-_u16-pad2_ net-_u29-pad1_ ] net-_u31-pad3_ u31 +a15 [net-_u29-pad1_ net-_u35-pad2_ ] net-_u42-pad2_ u61 +a16 net-_u1-pad3_ net-_u12-pad2_ u12 +a17 net-_u12-pad2_ net-_u21-pad2_ u21 +a18 net-_u21-pad2_ net-_u35-pad2_ u35 +a19 net-_u1-pad5_ net-_u17-pad1_ u6 +a20 net-_u17-pad1_ net-_u17-pad2_ u17 +a21 net-_u1-pad6_ net-_u18-pad1_ u7 +a22 net-_u18-pad1_ net-_u18-pad2_ u18 +a23 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u27-pad3_ u27 +a24 [net-_u27-pad3_ net-_u43-pad2_ ] net-_u43-pad3_ u43 +a25 net-_u43-pad3_ net-_u49-pad2_ u49 +a26 net-_u49-pad2_ net-_u53-pad2_ u53 +a27 net-_u53-pad2_ net-_u56-pad2_ u56 +a28 net-_u56-pad2_ net-_u59-pad2_ u59 +a29 net-_u59-pad2_ net-_u1-pad8_ u65 +a30 [net-_u32-pad1_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a31 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u33-pad3_ u33 +a32 [net-_u18-pad2_ net-_u32-pad1_ ] net-_u34-pad3_ u34 +a33 [net-_u32-pad1_ net-_u40-pad2_ ] net-_u43-pad2_ u62 +a34 net-_u1-pad7_ net-_u13-pad2_ u13 +a35 net-_u13-pad2_ net-_u23-pad2_ u23 +a36 net-_u23-pad2_ net-_u40-pad2_ u40 +a37 net-_u1-pad9_ net-_u19-pad1_ u8 +a38 net-_u19-pad1_ net-_u19-pad2_ u19 +a39 net-_u1-pad10_ net-_u20-pad1_ u9 +a40 net-_u20-pad1_ net-_u20-pad2_ u20 +a41 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28 +a42 [net-_u28-pad3_ net-_u44-pad2_ ] net-_u44-pad3_ u44 +a43 net-_u44-pad3_ net-_u50-pad2_ u50 +a44 net-_u50-pad2_ net-_u54-pad2_ u54 +a45 net-_u54-pad2_ net-_u57-pad2_ u57 +a46 net-_u57-pad2_ net-_u60-pad2_ u60 +a47 net-_u60-pad2_ net-_u1-pad12_ u66 +a48 [net-_u36-pad1_ net-_u19-pad2_ ] net-_u36-pad3_ u36 +a49 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u37-pad3_ u37 +a50 [net-_u20-pad2_ net-_u36-pad1_ ] net-_u38-pad3_ u38 +a51 [net-_u36-pad1_ net-_u41-pad2_ ] net-_u44-pad2_ u64 +a52 net-_u1-pad11_ net-_u15-pad2_ u15 +a53 net-_u15-pad2_ net-_u25-pad2_ u25 +a54 net-_u25-pad2_ net-_u41-pad2_ u41 +a55 net-_u1-pad13_ net-_u10-pad1_ u2 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u10-pad2_ net-_u22-pad2_ u22 +a58 [net-_u3-pad3_ net-_u24-pad2_ ] net-_u45-pad3_ u51 +a59 net-_u1-pad14_ net-_u11-pad2_ u11 +a60 net-_u11-pad2_ net-_u24-pad2_ u24 +a61 net-_u24-pad2_ net-_u39-pad2_ u39 +a62 [net-_u22-pad2_ ] [net-_u24-pad2_ ] [net-_u3-pad3_ ] u3 +a63 [net-_u45-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u29-pad1_ ] u45 +a64 [net-_u47-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u32-pad1_ ] u47 +a65 [net-_u46-pad1_ ] [net-_u39-pad2_ ] [net-_u45-pad3_ ] [net-_u36-pad1_ ] u46 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u26 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u42 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u52 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u63 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u61 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u43 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u65 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u62 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u40 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u44 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u66 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u64 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u39 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: qb_dff, NgSpice Name: qb_dff +.model u3 qb_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u45 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u47 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: r_dff, NgSpice Name: r_dff +.model u46 r_dff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends CD4038B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4038B/CD4038B_Previous_Values.xml b/library/SubcircuitLibrary/CD4038B/CD4038B_Previous_Values.xml new file mode 100644 index 00000000..ecd5aa0c --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/CD4038B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u14 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u14><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u16 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u16><u26 name="type">d_xor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u26><u42 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u42><u48 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u48><u52 name="type">d_buffer<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u52><u55 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u55><u58 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u58><u63 name="type">d_buffer<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u63><u29 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u31><u61 name="type">d_xor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u61><u12 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u12><u21 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u21><u35 name="type">d_buffer<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u35><u6 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u6><u17 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u17><u7 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u7><u18 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u18><u27 name="type">d_xor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u27><u43 name="type">d_xnor<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u43><u49 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u49><u53 name="type">d_buffer<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u53><u56 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u56><u59 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u59><u65 name="type">d_buffer<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u65><u32 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u34><u62 name="type">d_xor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u62><u13 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u13><u23 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u23><u40 name="type">d_buffer<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u40><u8 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u8><u19 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u19><u9 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u9><u20 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u20><u28 name="type">d_xor<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u28><u44 name="type">d_xnor<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u44><u50 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u50><u54 name="type">d_buffer<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u54><u57 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u57><u60 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u60><u66 name="type">d_buffer<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u66><u36 name="type">d_and<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u36><u37 name="type">d_and<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_and<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u38><u64 name="type">d_xor<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u64><u15 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u15><u25 name="type">d_inverter<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u25><u41 name="type">d_buffer<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u41><u2 name="type">d_inverter<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u2><u10 name="type">d_inverter<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u10><u22 name="type">d_buffer<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u22><u51 name="type">d_nand<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u51><u11 name="type">d_inverter<field175 name="Enter Rise Delay (default=1.0e-9)" /><field176 name="Enter Fall Delay (default=1.0e-9)" /><field177 name="Enter Input Load (default=1.0e-12)" /></u11><u24 name="type">d_inverter<field178 name="Enter Rise Delay (default=1.0e-9)" /><field179 name="Enter Fall Delay (default=1.0e-9)" /><field180 name="Enter Input Load (default=1.0e-12)" /></u24><u39 name="type">d_buffer<field181 name="Enter Rise Delay (default=1.0e-9)" /><field182 name="Enter Fall Delay (default=1.0e-9)" /><field183 name="Enter Input Load (default=1.0e-12)" /></u39><u3 name="type">qb_dff<field184 name="Enter Rise Delay (default=1.0e-9)" /><field185 name="Enter Fall Delay (default=1.0e-9)" /><field186 name="Enter Input Load (default=1.0e-12)" /><field187 name="Enter Instance ID (Between 0-99)" /></u3><u45 name="type">r_dff<field188 name="Enter Rise Delay (default=1.0e-9)" /><field189 name="Enter Fall Delay (default=1.0e-9)" /><field190 name="Enter Input Load (default=1.0e-12)" /><field191 name="Enter Instance ID (Between 0-99)" /></u45><u47 name="type">r_dff<field192 name="Enter Rise Delay (default=1.0e-9)" /><field193 name="Enter Fall Delay (default=1.0e-9)" /><field194 name="Enter Input Load (default=1.0e-12)" /><field195 name="Enter Instance ID (Between 0-99)" /></u47><u46 name="type">r_dff<field196 name="Enter Rise Delay (default=1.0e-9)" /><field197 name="Enter Fall Delay (default=1.0e-9)" /><field198 name="Enter Input Load (default=1.0e-12)" /><field199 name="Enter Instance ID (Between 0-99)" /></u46></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor</field></x3></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4038B/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4038B/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4038B/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4038B/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4038B/analysis b/library/SubcircuitLibrary/CD4038B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4038B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |