diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4035BM')
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM-cache.lib | 247 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM.cir | 65 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM.cir.out | 182 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM.pro | 73 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM.sch | 1464 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM.sub | 176 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/CD4035BM_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/NMOS-180nm.lib | 13 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/PMOS-180nm.lib | 11 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/CD4035BM/analysis | 1 |
10 files changed, 2233 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM-cache.lib b/library/SubcircuitLibrary/CD4035BM/CD4035BM-cache.lib new file mode 100644 index 00000000..5eb870c2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM-cache.lib @@ -0,0 +1,247 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir b/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir new file mode 100644 index 00000000..2c3e3c06 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir @@ -0,0 +1,65 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4035BM\CD4035BM.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/11/25 13:18:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad3_ Net-_U15-Pad1_ d_inverter +M3 Net-_M1-Pad3_ Net-_M10-Pad2_ Net-_M1-Pad1_ VDD mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ VSS mosfet_n +U9 Net-_U15-Pad1_ Net-_M10-Pad2_ dac_bridge_1 +U15 Net-_U15-Pad1_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_M1-Pad2_ dac_bridge_1 +M4 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad1_ VDD mosfet_p +M2 Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ VSS mosfet_n +U4 Net-_U16-Pad5_ Net-_U1-Pad4_ Net-_U10-Pad1_ d_nand +U5 Net-_U16-Pad5_ Net-_U2-Pad2_ Net-_U10-Pad2_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U2 Net-_U1-Pad5_ Net-_U2-Pad2_ d_inverter +U16 Net-_U13-Pad2_ Net-_U16-Pad2_ Net-_U1-Pad17_ Net-_U12-Pad2_ Net-_U16-Pad5_ Net-_U16-Pad6_ d_dff +M7 Net-_M5-Pad3_ Net-_M10-Pad2_ Net-_M5-Pad1_ VDD mosfet_p +M5 Net-_M5-Pad1_ Net-_M5-Pad2_ Net-_M5-Pad3_ VSS mosfet_n +U22 Net-_U15-Pad1_ Net-_U21-Pad1_ d_inverter +U21 Net-_U21-Pad1_ Net-_M5-Pad2_ dac_bridge_1 +M8 Net-_M5-Pad3_ Net-_M5-Pad2_ Net-_M6-Pad1_ VDD mosfet_p +M6 Net-_M6-Pad1_ Net-_M10-Pad2_ Net-_M5-Pad3_ VSS mosfet_n +U23 Net-_U20-Pad2_ Net-_U16-Pad2_ Net-_U1-Pad17_ Net-_U12-Pad2_ ? Net-_U23-Pad6_ d_dff +U24 Net-_U23-Pad6_ Net-_U24-Pad2_ d_buffer +U17 Net-_U16-Pad6_ Net-_U17-Pad2_ d_buffer +M11 Net-_M10-Pad3_ Net-_M10-Pad2_ Net-_M11-Pad3_ VDD mosfet_p +M9 Net-_M11-Pad3_ Net-_M12-Pad2_ Net-_M10-Pad3_ VSS mosfet_n +U29 Net-_U15-Pad1_ Net-_U28-Pad1_ d_inverter +U28 Net-_U28-Pad1_ Net-_M12-Pad2_ dac_bridge_1 +M12 Net-_M10-Pad3_ Net-_M12-Pad2_ Net-_M10-Pad1_ VDD mosfet_p +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ VSS mosfet_n +U30 Net-_U27-Pad2_ Net-_U16-Pad2_ Net-_U1-Pad17_ Net-_U12-Pad2_ ? Net-_U30-Pad6_ d_dff +U31 Net-_U30-Pad6_ Net-_U31-Pad2_ d_buffer +M15 Net-_M13-Pad3_ Net-_M10-Pad2_ Net-_M13-Pad1_ VDD mosfet_p +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M13-Pad3_ VSS mosfet_n +U36 Net-_U15-Pad1_ Net-_U35-Pad1_ d_inverter +U35 Net-_U35-Pad1_ Net-_M13-Pad2_ dac_bridge_1 +M16 Net-_M13-Pad3_ Net-_M13-Pad2_ Net-_M14-Pad1_ VDD mosfet_p +M14 Net-_M14-Pad1_ Net-_M10-Pad2_ Net-_M13-Pad3_ VSS mosfet_n +U37 Net-_U34-Pad2_ Net-_U16-Pad2_ Net-_U1-Pad17_ Net-_U12-Pad2_ ? Net-_U37-Pad6_ d_dff +U38 Net-_U37-Pad6_ Net-_U38-Pad2_ d_buffer +U6 Net-_U1-Pad6_ Net-_U16-Pad2_ d_inverter +U7 Net-_U1-Pad7_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer +U8 Net-_U1-Pad8_ Net-_U18-Pad2_ d_inverter +U1 VDD VSS Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_M1-Pad1_ Net-_M5-Pad1_ Net-_M11-Pad3_ Net-_M13-Pad1_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ PORT +U18 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U1-Pad13_ d_xor +U25 Net-_U24-Pad2_ Net-_U18-Pad2_ Net-_U1-Pad14_ d_xor +U32 Net-_U31-Pad2_ Net-_U18-Pad2_ Net-_U1-Pad15_ d_xor +U39 Net-_U38-Pad2_ Net-_U18-Pad2_ Net-_U1-Pad16_ d_xor +U34 Net-_M13-Pad3_ Net-_U34-Pad2_ adc_bridge_1 +U27 Net-_M10-Pad3_ Net-_U27-Pad2_ adc_bridge_1 +U20 Net-_M5-Pad3_ Net-_U20-Pad2_ adc_bridge_1 +U13 Net-_M1-Pad3_ Net-_U13-Pad2_ adc_bridge_1 +U19 Net-_U17-Pad2_ Net-_M6-Pad1_ dac_bridge_1 +U26 Net-_U24-Pad2_ Net-_M10-Pad1_ dac_bridge_1 +U33 Net-_U31-Pad2_ Net-_M14-Pad1_ dac_bridge_1 +U11 Net-_U10-Pad3_ Net-_M2-Pad1_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir.out b/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir.out new file mode 100644 index 00000000..a8da4fd0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM.cir.out @@ -0,0 +1,182 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4035bm\cd4035bm.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u3 net-_u1-pad3_ net-_u15-pad1_ d_inverter +m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 +* u9 net-_u15-pad1_ net-_m10-pad2_ dac_bridge_1 +* u15 net-_u15-pad1_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_m1-pad2_ dac_bridge_1 +m4 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad1_ vdd CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 +* u4 net-_u16-pad5_ net-_u1-pad4_ net-_u10-pad1_ d_nand +* u5 net-_u16-pad5_ net-_u2-pad2_ net-_u10-pad2_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u2 net-_u1-pad5_ net-_u2-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ d_dff +m7 net-_m5-pad3_ net-_m10-pad2_ net-_m5-pad1_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 +* u22 net-_u15-pad1_ net-_u21-pad1_ d_inverter +* u21 net-_u21-pad1_ net-_m5-pad2_ dac_bridge_1 +m8 net-_m5-pad3_ net-_m5-pad2_ net-_m6-pad1_ vdd CMOSP W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_m10-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 +* u23 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ d_dff +* u24 net-_u23-pad6_ net-_u24-pad2_ d_buffer +* u17 net-_u16-pad6_ net-_u17-pad2_ d_buffer +m11 net-_m10-pad3_ net-_m10-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1 +m9 net-_m11-pad3_ net-_m12-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 +* u29 net-_u15-pad1_ net-_u28-pad1_ d_inverter +* u28 net-_u28-pad1_ net-_m12-pad2_ dac_bridge_1 +m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 +* u30 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ d_dff +* u31 net-_u30-pad6_ net-_u31-pad2_ d_buffer +m15 net-_m13-pad3_ net-_m10-pad2_ net-_m13-pad1_ vdd CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 +* u36 net-_u15-pad1_ net-_u35-pad1_ d_inverter +* u35 net-_u35-pad1_ net-_m13-pad2_ dac_bridge_1 +m16 net-_m13-pad3_ net-_m13-pad2_ net-_m14-pad1_ vdd CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m10-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 +* u37 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ d_dff +* u38 net-_u37-pad6_ net-_u38-pad2_ d_buffer +* u6 net-_u1-pad6_ net-_u16-pad2_ d_inverter +* u7 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u8 net-_u1-pad8_ net-_u18-pad2_ d_inverter +* u1 vdd vss net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_m1-pad1_ net-_m5-pad1_ net-_m11-pad3_ net-_m13-pad1_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ port +* u18 net-_u17-pad2_ net-_u18-pad2_ net-_u1-pad13_ d_xor +* u25 net-_u24-pad2_ net-_u18-pad2_ net-_u1-pad14_ d_xor +* u32 net-_u31-pad2_ net-_u18-pad2_ net-_u1-pad15_ d_xor +* u39 net-_u38-pad2_ net-_u18-pad2_ net-_u1-pad16_ d_xor +* u34 net-_m13-pad3_ net-_u34-pad2_ adc_bridge_1 +* u27 net-_m10-pad3_ net-_u27-pad2_ adc_bridge_1 +* u20 net-_m5-pad3_ net-_u20-pad2_ adc_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u19 net-_u17-pad2_ net-_m6-pad1_ dac_bridge_1 +* u26 net-_u24-pad2_ net-_m10-pad1_ dac_bridge_1 +* u33 net-_u31-pad2_ net-_m14-pad1_ dac_bridge_1 +* u11 net-_u10-pad3_ net-_m2-pad1_ dac_bridge_1 +a1 net-_u1-pad3_ net-_u15-pad1_ u3 +a2 [net-_u15-pad1_ ] [net-_m10-pad2_ ] u9 +a3 net-_u15-pad1_ net-_u14-pad1_ u15 +a4 [net-_u14-pad1_ ] [net-_m1-pad2_ ] u14 +a5 [net-_u16-pad5_ net-_u1-pad4_ ] net-_u10-pad1_ u4 +a6 [net-_u16-pad5_ net-_u2-pad2_ ] net-_u10-pad2_ u5 +a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a8 net-_u1-pad5_ net-_u2-pad2_ u2 +a9 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ u16 +a10 net-_u15-pad1_ net-_u21-pad1_ u22 +a11 [net-_u21-pad1_ ] [net-_m5-pad2_ ] u21 +a12 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ u23 +a13 net-_u23-pad6_ net-_u24-pad2_ u24 +a14 net-_u16-pad6_ net-_u17-pad2_ u17 +a15 net-_u15-pad1_ net-_u28-pad1_ u29 +a16 [net-_u28-pad1_ ] [net-_m12-pad2_ ] u28 +a17 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ u30 +a18 net-_u30-pad6_ net-_u31-pad2_ u31 +a19 net-_u15-pad1_ net-_u35-pad1_ u36 +a20 [net-_u35-pad1_ ] [net-_m13-pad2_ ] u35 +a21 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ u37 +a22 net-_u37-pad6_ net-_u38-pad2_ u38 +a23 net-_u1-pad6_ net-_u16-pad2_ u6 +a24 net-_u1-pad7_ net-_u12-pad1_ u7 +a25 net-_u12-pad1_ net-_u12-pad2_ u12 +a26 net-_u1-pad8_ net-_u18-pad2_ u8 +a27 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u1-pad13_ u18 +a28 [net-_u24-pad2_ net-_u18-pad2_ ] net-_u1-pad14_ u25 +a29 [net-_u31-pad2_ net-_u18-pad2_ ] net-_u1-pad15_ u32 +a30 [net-_u38-pad2_ net-_u18-pad2_ ] net-_u1-pad16_ u39 +a31 [net-_m13-pad3_ ] [net-_u34-pad2_ ] u34 +a32 [net-_m10-pad3_ ] [net-_u27-pad2_ ] u27 +a33 [net-_m5-pad3_ ] [net-_u20-pad2_ ] u20 +a34 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a35 [net-_u17-pad2_ ] [net-_m6-pad1_ ] u19 +a36 [net-_u24-pad2_ ] [net-_m10-pad1_ ] u26 +a37 [net-_u31-pad2_ ] [net-_m14-pad1_ ] u33 +a38 [net-_u10-pad3_ ] [net-_m2-pad1_ ] u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u37 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u18 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u25 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u34 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM.pro b/library/SubcircuitLibrary/CD4035BM/CD4035BM.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM.sch b/library/SubcircuitLibrary/CD4035BM/CD4035BM.sch new file mode 100644 index 00000000..84128cb9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM.sch @@ -0,0 +1,1464 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 6849104D +P 1150 1400 +F 0 "U3" H 1150 1300 60 0000 C CNN +F 1 "d_inverter" H 1150 1550 60 0000 C CNN +F 2 "" H 1200 1350 60 0000 C CNN +F 3 "" H 1200 1350 60 0000 C CNN + 1 1150 1400 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 684910F8 +P 3850 1550 +F 0 "M3" H 3800 1600 50 0000 R CNN +F 1 "mosfet_p" H 3900 1700 50 0000 R CNN +F 2 "" H 4100 1650 29 0000 C CNN +F 3 "" H 3900 1550 60 0000 C CNN + 1 3850 1550 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 6849113D +P 3700 2650 +F 0 "M1" H 3700 2500 50 0000 R CNN +F 1 "mosfet_n" H 3800 2600 50 0000 R CNN +F 2 "" H 4000 2350 29 0000 C CNN +F 3 "" H 3800 2450 60 0000 C CNN + 1 3700 2650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3650 1700 3650 2450 +Wire Wire Line + 3650 2450 3700 2450 +Wire Wire Line + 4050 1700 4150 1700 +Wire Wire Line + 4150 1700 4150 2450 +Wire Wire Line + 4150 2450 4100 2450 +Text GLabel 3750 2000 3 60 Input ~ 0 +VDD +Wire Wire Line + 3700 1800 3700 2000 +Wire Wire Line + 3700 2000 3750 2000 +Text GLabel 4250 2500 3 60 Input ~ 0 +VSS +Wire Wire Line + 4250 2500 4250 2350 +$Comp +L dac_bridge_1 U9 +U 1 1 684919A6 +P 2450 1450 +F 0 "U9" H 2450 1450 60 0000 C CNN +F 1 "dac_bridge_1" H 2450 1600 60 0000 C CNN +F 2 "" H 2450 1450 60 0000 C CNN +F 3 "" H 2450 1450 60 0000 C CNN + 1 2450 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1450 1400 1850 1400 +Wire Wire Line + 3000 1400 8450 1400 +$Comp +L d_inverter U15 +U 1 1 68491D96 +P 5250 1650 +F 0 "U15" H 5250 1550 60 0000 C CNN +F 1 "d_inverter" H 5250 1800 60 0000 C CNN +F 2 "" H 5300 1600 60 0000 C CNN +F 3 "" H 5300 1600 60 0000 C CNN + 1 5250 1650 + 0 1 1 0 +$EndComp +Wire Wire Line + 1700 1400 1700 900 +Wire Wire Line + 1700 900 10650 900 +Wire Wire Line + 5250 900 5250 1350 +Connection ~ 1700 1400 +$Comp +L dac_bridge_1 U14 +U 1 1 684922E7 +P 5200 2700 +F 0 "U14" H 5200 2700 60 0000 C CNN +F 1 "dac_bridge_1" H 5200 2850 60 0000 C CNN +F 2 "" H 5200 2700 60 0000 C CNN +F 3 "" H 5200 2700 60 0000 C CNN + 1 5200 2700 + 0 1 1 0 +$EndComp +Connection ~ 4150 2050 +Wire Wire Line + 4250 2350 4050 2350 +$Comp +L mosfet_p M4 +U 1 1 68492EEA +P 3900 3300 +F 0 "M4" H 3850 3350 50 0000 R CNN +F 1 "mosfet_p" H 3950 3450 50 0000 R CNN +F 2 "" H 4150 3400 29 0000 C CNN +F 3 "" H 3950 3300 60 0000 C CNN + 1 3900 3300 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 68492EF0 +P 3750 4400 +F 0 "M2" H 3750 4250 50 0000 R CNN +F 1 "mosfet_n" H 3850 4350 50 0000 R CNN +F 2 "" H 4050 4100 29 0000 C CNN +F 3 "" H 3850 4200 60 0000 C CNN + 1 3750 4400 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3700 3450 3700 4200 +Wire Wire Line + 3700 4200 3750 4200 +Wire Wire Line + 4100 3450 4200 3450 +Wire Wire Line + 4200 3450 4200 4200 +Wire Wire Line + 4200 4200 4150 4200 +Text GLabel 3800 3750 3 60 Input ~ 0 +VDD +Wire Wire Line + 3750 3550 3750 3750 +Wire Wire Line + 3750 3750 3800 3750 +Text GLabel 4300 4250 3 60 Input ~ 0 +VSS +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4100 4100 +Wire Wire Line + 3900 2750 3900 3150 +Wire Wire Line + 3300 1400 3300 4700 +Wire Wire Line + 3300 4700 3950 4700 +Wire Wire Line + 3950 4700 3950 4500 +Connection ~ 3300 1400 +Wire Wire Line + 5250 1950 5250 2100 +Wire Wire Line + 3900 2950 4700 2950 +Wire Wire Line + 4700 2950 4700 3250 +Wire Wire Line + 4700 3250 5250 3250 +Connection ~ 3900 2950 +$Comp +L d_nand U4 +U 1 1 684935ED +P 1800 3700 +F 0 "U4" H 1800 3700 60 0000 C CNN +F 1 "d_nand" H 1850 3800 60 0000 C CNN +F 2 "" H 1800 3700 60 0000 C CNN +F 3 "" H 1800 3700 60 0000 C CNN + 1 1800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68493789 +P 1850 4400 +F 0 "U5" H 1850 4400 60 0000 C CNN +F 1 "d_and" H 1900 4500 60 0000 C CNN +F 2 "" H 1850 4400 60 0000 C CNN +F 3 "" H 1850 4400 60 0000 C CNN + 1 1850 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 684937F4 +P 2750 4000 +F 0 "U10" H 2750 4000 60 0000 C CNN +F 1 "d_nor" H 2800 4100 60 0000 C CNN +F 2 "" H 2750 4000 60 0000 C CNN +F 3 "" H 2750 4000 60 0000 C CNN + 1 2750 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 684938C9 +P 950 4400 +F 0 "U2" H 950 4300 60 0000 C CNN +F 1 "d_inverter" H 950 4550 60 0000 C CNN +F 2 "" H 1000 4350 60 0000 C CNN +F 3 "" H 1000 4350 60 0000 C CNN + 1 950 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2250 3650 2250 3900 +Wire Wire Line + 2250 3900 2300 3900 +Wire Wire Line + 2300 4000 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3350 550 +F 0 "U1" H 3400 650 30 0000 C CNN +F 1 "PORT" H 3350 550 30 0000 C CNN +F 2 "" H 3350 550 60 0000 C CNN +F 3 "" H 3350 550 60 0000 C CNN + 9 3350 550 + 0 1 1 0 +$EndComp +Wire Wire Line + 3350 800 3350 2000 +Wire Wire Line + 3350 2000 3650 2000 +Connection ~ 3650 2000 +$Comp +L PORT U1 +U 12 1 684AC1A9 +P 20550 -50 +F 0 "U1" H 20600 50 30 0000 C CNN +F 1 "PORT" H 20550 -50 30 0000 C CNN +F 2 "" H 20550 -50 60 0000 C CNN +F 3 "" H 20550 -50 60 0000 C CNN + 12 20550 -50 + 0 1 1 0 +$EndComp +Wire Wire Line + 9050 800 9050 1750 +Wire Wire Line + 9050 1750 9250 1750 +Connection ~ 9250 1750 +$Comp +L PORT U1 +U 14 1 684AC791 +P 14250 8150 +F 0 "U1" H 14300 8250 30 0000 C CNN +F 1 "PORT" H 14250 8150 30 0000 C CNN +F 2 "" H 14250 8150 60 0000 C CNN +F 3 "" H 14250 8150 60 0000 C CNN + 14 14250 8150 + -1 0 0 1 +$EndComp +Wire Wire Line + 14950 400 14950 1700 +Wire Wire Line + 14950 1700 15250 1700 +Connection ~ 15250 1700 +$Comp +L PORT U1 +U 16 1 684ACF15 +P 24700 8400 +F 0 "U1" H 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+$EndComp +Wire Wire Line + 500 4400 650 4400 +$Comp +L PORT U1 +U 11 1 684AFA02 +P 15200 400 +F 0 "U1" H 15250 500 30 0000 C CNN +F 1 "PORT" H 15200 400 30 0000 C CNN +F 2 "" H 15200 400 60 0000 C CNN +F 3 "" H 15200 400 60 0000 C CNN + 11 15200 400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 684AFC79 +P 8050 8700 +F 0 "U1" H 8100 8800 30 0000 C CNN +F 1 "PORT" H 8050 8700 30 0000 C CNN +F 2 "" H 8050 8700 60 0000 C CNN +F 3 "" H 8050 8700 60 0000 C CNN + 13 8050 8700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 684AFF57 +P 19800 8400 +F 0 "U1" H 19850 8500 30 0000 C CNN +F 1 "PORT" H 19800 8400 30 0000 C CNN +F 2 "" H 19800 8400 60 0000 C CNN +F 3 "" H 19800 8400 60 0000 C CNN + 15 19800 8400 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 17 1 684B032A +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 17 6950 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24700 7450 24700 8150 +Wire Wire Line + 19800 7550 19800 8150 +Wire Wire Line + 14000 7650 14000 8150 +Wire Wire Line + 8050 7500 8050 8450 +$Comp +L dac_bridge_1 U11 +U 1 1 684B305C +P 3400 5150 +F 0 "U11" H 3400 5150 60 0000 C CNN +F 1 "dac_bridge_1" H 3400 5300 60 0000 C CNN +F 2 "" H 3400 5150 60 0000 C CNN +F 3 "" H 3400 5150 60 0000 C CNN + 1 3400 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3200 3950 3200 4600 +Wire Wire Line + 3200 4600 2800 4600 +Wire Wire Line + 2800 4600 2800 5100 +Wire Wire Line + 3700 3950 3550 3950 +Wire Wire Line + 3550 3950 3550 4600 +Wire Wire Line + 3550 4600 4100 4600 +Wire Wire Line + 4100 4600 4100 5100 +Wire Wire Line + 4100 5100 3950 5100 +Wire Wire Line + 2650 5500 22900 5500 +Wire Wire Line + 5700 5500 5700 4450 +Wire Wire Line + 5700 4450 5250 4450 +Wire Wire Line + 5250 4450 5250 4300 +Wire Wire Line + 11200 5500 11200 4500 +Wire Wire Line + 11200 4500 10800 4500 +Wire Wire Line + 10800 4500 10800 4100 +Wire Wire Line + 10800 4100 10850 4100 +Connection ~ 5700 5500 +Wire Wire Line + 17200 5500 17200 4350 +Wire Wire Line + 17200 4350 16800 4350 +Wire Wire Line + 16800 4350 16800 4100 +Wire Wire Line + 16800 4100 16850 4100 +Connection ~ 11200 5500 +Wire Wire Line + 22900 5500 22900 4200 +Wire Wire Line + 22900 4200 22450 4200 +Wire Wire Line + 22450 4200 22450 4050 +Connection ~ 17200 5500 +Text GLabel 900 700 0 60 Input ~ 0 +VDD +Text GLabel 900 900 0 60 Input ~ 0 +VSS +$Comp +L PORT U1 +U 4 1 684BB6F7 +P 900 3950 +F 0 "U1" H 950 4050 30 0000 C CNN +F 1 "PORT" H 900 3950 30 0000 C CNN +F 2 "" H 900 3950 60 0000 C CNN +F 3 "" H 900 3950 60 0000 C CNN + 4 900 3950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 900 700 1100 700 +$Comp +L PORT U1 +U 7 1 684BBA9B +P 1400 6150 +F 0 "U1" H 1450 6250 30 0000 C CNN +F 1 "PORT" H 1400 6150 30 0000 C CNN +F 2 "" H 1400 6150 60 0000 C CNN +F 3 "" H 1400 6150 60 0000 C CNN + 7 1400 6150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 900 900 1150 900 +Wire Wire Line + 5800 3350 5800 3250 +Wire Wire Line + 5800 3250 8850 3250 +Wire Wire Line + 8850 3250 8850 3000 +Wire Wire Line + 8850 3000 10150 3000 +Wire Wire Line + 10150 3000 10150 3150 +Wire Wire Line + 10150 3150 14700 3150 +Wire Wire Line + 14700 3150 14700 3000 +Wire Wire Line + 14700 3000 16150 3000 +Wire Wire Line + 16150 3000 16150 3150 +Wire Wire Line + 16150 3150 20850 3150 +Connection ~ 11400 3150 +Wire Wire Line + 20850 3150 20850 2850 +Wire Wire Line + 20850 2850 21750 2850 +Wire Wire Line + 21750 2850 21750 3100 +Wire Wire Line + 21750 3100 23000 3100 +Connection ~ 17400 3150 +$Comp +L PORT U1 +U 10 1 684BF363 +P 9050 550 +F 0 "U1" H 9100 650 30 0000 C CNN +F 1 "PORT" H 9050 550 30 0000 C CNN +F 2 "" H 9050 550 60 0000 C CNN +F 3 "" H 9050 550 60 0000 C CNN + 10 9050 550 + 0 1 1 0 +$EndComp +Wire Wire Line + 7200 3050 7200 3250 +Connection ~ 7200 3250 +NoConn ~ 12100 3450 +NoConn ~ 18100 3450 +NoConn ~ 23700 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM.sub b/library/SubcircuitLibrary/CD4035BM/CD4035BM.sub new file mode 100644 index 00000000..df3476e3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM.sub @@ -0,0 +1,176 @@ +* Subcircuit CD4035BM +.subckt CD4035BM vdd vss net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_m1-pad1_ net-_m5-pad1_ net-_m11-pad3_ net-_m13-pad1_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ +* c:\fossee\esim\library\subcircuitlibrary\cd4035bm\cd4035bm.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u3 net-_u1-pad3_ net-_u15-pad1_ d_inverter +m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 +* u9 net-_u15-pad1_ net-_m10-pad2_ dac_bridge_1 +* u15 net-_u15-pad1_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_m1-pad2_ dac_bridge_1 +m4 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad1_ vdd CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 +* u4 net-_u16-pad5_ net-_u1-pad4_ net-_u10-pad1_ d_nand +* u5 net-_u16-pad5_ net-_u2-pad2_ net-_u10-pad2_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u2 net-_u1-pad5_ net-_u2-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ d_dff +m7 net-_m5-pad3_ net-_m10-pad2_ net-_m5-pad1_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 +* u22 net-_u15-pad1_ net-_u21-pad1_ d_inverter +* u21 net-_u21-pad1_ net-_m5-pad2_ dac_bridge_1 +m8 net-_m5-pad3_ net-_m5-pad2_ net-_m6-pad1_ vdd CMOSP W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_m10-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 +* u23 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ d_dff +* u24 net-_u23-pad6_ net-_u24-pad2_ d_buffer +* u17 net-_u16-pad6_ net-_u17-pad2_ d_buffer +m11 net-_m10-pad3_ net-_m10-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1 +m9 net-_m11-pad3_ net-_m12-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 +* u29 net-_u15-pad1_ net-_u28-pad1_ d_inverter +* u28 net-_u28-pad1_ net-_m12-pad2_ dac_bridge_1 +m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 +* u30 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ d_dff +* u31 net-_u30-pad6_ net-_u31-pad2_ d_buffer +m15 net-_m13-pad3_ net-_m10-pad2_ net-_m13-pad1_ vdd CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 +* u36 net-_u15-pad1_ net-_u35-pad1_ d_inverter +* u35 net-_u35-pad1_ net-_m13-pad2_ dac_bridge_1 +m16 net-_m13-pad3_ net-_m13-pad2_ net-_m14-pad1_ vdd CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m10-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 +* u37 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ d_dff +* u38 net-_u37-pad6_ net-_u38-pad2_ d_buffer +* u6 net-_u1-pad6_ net-_u16-pad2_ d_inverter +* u7 net-_u1-pad7_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u8 net-_u1-pad8_ net-_u18-pad2_ d_inverter +* u18 net-_u17-pad2_ net-_u18-pad2_ net-_u1-pad13_ d_xor +* u25 net-_u24-pad2_ net-_u18-pad2_ net-_u1-pad14_ d_xor +* u32 net-_u31-pad2_ net-_u18-pad2_ net-_u1-pad15_ d_xor +* u39 net-_u38-pad2_ net-_u18-pad2_ net-_u1-pad16_ d_xor +* u34 net-_m13-pad3_ net-_u34-pad2_ adc_bridge_1 +* u27 net-_m10-pad3_ net-_u27-pad2_ adc_bridge_1 +* u20 net-_m5-pad3_ net-_u20-pad2_ adc_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u19 net-_u17-pad2_ net-_m6-pad1_ dac_bridge_1 +* u26 net-_u24-pad2_ net-_m10-pad1_ dac_bridge_1 +* u33 net-_u31-pad2_ net-_m14-pad1_ dac_bridge_1 +* u11 net-_u10-pad3_ net-_m2-pad1_ dac_bridge_1 +a1 net-_u1-pad3_ net-_u15-pad1_ u3 +a2 [net-_u15-pad1_ ] [net-_m10-pad2_ ] u9 +a3 net-_u15-pad1_ net-_u14-pad1_ u15 +a4 [net-_u14-pad1_ ] [net-_m1-pad2_ ] u14 +a5 [net-_u16-pad5_ net-_u1-pad4_ ] net-_u10-pad1_ u4 +a6 [net-_u16-pad5_ net-_u2-pad2_ ] net-_u10-pad2_ u5 +a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a8 net-_u1-pad5_ net-_u2-pad2_ u2 +a9 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ u16 +a10 net-_u15-pad1_ net-_u21-pad1_ u22 +a11 [net-_u21-pad1_ ] [net-_m5-pad2_ ] u21 +a12 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ u23 +a13 net-_u23-pad6_ net-_u24-pad2_ u24 +a14 net-_u16-pad6_ net-_u17-pad2_ u17 +a15 net-_u15-pad1_ net-_u28-pad1_ u29 +a16 [net-_u28-pad1_ ] [net-_m12-pad2_ ] u28 +a17 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ u30 +a18 net-_u30-pad6_ net-_u31-pad2_ u31 +a19 net-_u15-pad1_ net-_u35-pad1_ u36 +a20 [net-_u35-pad1_ ] [net-_m13-pad2_ ] u35 +a21 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ u37 +a22 net-_u37-pad6_ net-_u38-pad2_ u38 +a23 net-_u1-pad6_ net-_u16-pad2_ u6 +a24 net-_u1-pad7_ net-_u12-pad1_ u7 +a25 net-_u12-pad1_ net-_u12-pad2_ u12 +a26 net-_u1-pad8_ net-_u18-pad2_ u8 +a27 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u1-pad13_ u18 +a28 [net-_u24-pad2_ net-_u18-pad2_ ] net-_u1-pad14_ u25 +a29 [net-_u31-pad2_ net-_u18-pad2_ ] net-_u1-pad15_ u32 +a30 [net-_u38-pad2_ net-_u18-pad2_ ] net-_u1-pad16_ u39 +a31 [net-_m13-pad3_ ] [net-_u34-pad2_ ] u34 +a32 [net-_m10-pad3_ ] [net-_u27-pad2_ ] u27 +a33 [net-_m5-pad3_ ] [net-_u20-pad2_ ] u20 +a34 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a35 [net-_u17-pad2_ ] [net-_m6-pad1_ ] u19 +a36 [net-_u24-pad2_ ] [net-_m10-pad1_ ] u26 +a37 [net-_u31-pad2_ ] [net-_m14-pad1_ ] u33 +a38 [net-_u10-pad3_ ] [net-_m2-pad1_ ] u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u37 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u18 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u25 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u34 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4035BM
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4035BM/CD4035BM_Previous_Values.xml b/library/SubcircuitLibrary/CD4035BM/CD4035BM_Previous_Values.xml new file mode 100644 index 00000000..3a5c32fd --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/CD4035BM_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u9 name="type">dac_bridge<field4 name="Enter value for out_low (default=0.0)" /><field5 name="Enter value for out_high (default=5.0)" /><field6 name="Enter value for out_undef (default=0.5)" /><field7 name="Enter value for input load (default=1.0e-12)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /></u9><u15 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u14><u4 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u10 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u2 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u2><u16 name="type">d_dff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for Data Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u16><u22 name="type">d_inverter<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u22><u21 name="type">dac_bridge<field44 name="Enter value for out_low (default=0.0)" /><field45 name="Enter value for out_high (default=5.0)" /><field46 name="Enter value for out_undef (default=0.5)" /><field47 name="Enter value for input load (default=1.0e-12)" /><field48 name="Enter the Rise Time (default=1.0e-9)" /><field49 name="Enter the Fall Time (default=1.0e-9)" /></u21><u23 name="type">d_dff<field50 name="Enter Clk Delay (default=1.0e-9)" /><field51 name="Enter Set Delay (default=1.0e-9)" /><field52 name="Enter Reset Delay (default=1.0)" /><field53 name="Enter IC (default=0)" /><field54 name="Enter value for Data Load (default=1.0e-12)" /><field55 name="Enter value for Clk Load (default=1.0e-12)" /><field56 name="Enter value for Set Load (default=1.0e-12)" /><field57 name="Enter value for Reset Load (default=1.0e-12)" /><field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /></u24><u17 name="type">d_buffer<field63 name="Enter Rise Delay (default=1.0e-9)" /><field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /></u17><u29 name="type">d_inverter<field66 name="Enter Rise Delay (default=1.0e-9)" /><field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /></u29><u28 name="type">dac_bridge<field69 name="Enter value for out_low (default=0.0)" /><field70 name="Enter value for out_high (default=5.0)" /><field71 name="Enter value for out_undef (default=0.5)" /><field72 name="Enter value for input load (default=1.0e-12)" /><field73 name="Enter the Rise Time (default=1.0e-9)" /><field74 name="Enter the Fall Time (default=1.0e-9)" /></u28><u30 name="type">d_dff<field75 name="Enter Clk Delay (default=1.0e-9)" /><field76 name="Enter Set Delay (default=1.0e-9)" /><field77 name="Enter Reset Delay (default=1.0)" /><field78 name="Enter IC (default=0)" /><field79 name="Enter value for Data Load (default=1.0e-12)" /><field80 name="Enter value for Clk Load (default=1.0e-12)" /><field81 name="Enter value for Set Load (default=1.0e-12)" /><field82 name="Enter value for Reset Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u30><u31 name="type">d_buffer<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u31><u36 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u36><u35 name="type">dac_bridge<field91 name="Enter value for out_low (default=0.0)" /><field92 name="Enter value for out_high (default=5.0)" /><field93 name="Enter value for out_undef (default=0.5)" /><field94 name="Enter value for input load (default=1.0e-12)" /><field95 name="Enter the Rise Time (default=1.0e-9)" /><field96 name="Enter the Fall Time (default=1.0e-9)" /></u35><u37 name="type">d_dff<field97 name="Enter Clk Delay (default=1.0e-9)" /><field98 name="Enter Set Delay (default=1.0e-9)" /><field99 name="Enter Reset Delay (default=1.0)" /><field100 name="Enter IC (default=0)" /><field101 name="Enter value for Data Load (default=1.0e-12)" /><field102 name="Enter value for Clk Load (default=1.0e-12)" /><field103 name="Enter value for Set Load (default=1.0e-12)" /><field104 name="Enter value for Reset Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /><field106 name="Enter Fall Delay (default=1.0e-9)" /></u37><u38 name="type">d_buffer<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u38><u6 name="type">d_inverter<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u7><u12 name="type">d_buffer<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u12><u8 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u8><u18 name="type">d_xor<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u18><u25 name="type">d_xor<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u25><u32 name="type">d_xor<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u32><u39 name="type">d_xor<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u39><u34 name="type">adc_bridge<field134 name="Enter value for in_low (default=1.0)" /><field135 name="Enter value for in_high (default=2.0)" /><field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /></u34><u27 name="type">adc_bridge<field138 name="Enter value for in_low (default=1.0)" /><field139 name="Enter value for in_high (default=2.0)" /><field140 name="Enter Rise Delay (default=1.0e-9)" /><field141 name="Enter Fall Delay (default=1.0e-9)" /></u27><u20 name="type">adc_bridge<field142 name="Enter value for in_low (default=1.0)" /><field143 name="Enter value for in_high (default=2.0)" /><field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /></u20><u13 name="type">adc_bridge<field146 name="Enter value for in_low (default=1.0)" /><field147 name="Enter value for in_high (default=2.0)" /><field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /></u13><u19 name="type">dac_bridge<field150 name="Enter value for out_low (default=0.0)" /><field151 name="Enter value for out_high (default=5.0)" /><field152 name="Enter value for out_undef (default=0.5)" /><field153 name="Enter value for input load (default=1.0e-12)" /><field154 name="Enter the Rise Time (default=1.0e-9)" /><field155 name="Enter the Fall Time (default=1.0e-9)" /></u19><u26 name="type">dac_bridge<field156 name="Enter value for out_low (default=0.0)" /><field157 name="Enter value for out_high (default=5.0)" /><field158 name="Enter value for out_undef (default=0.5)" /><field159 name="Enter value for input load (default=1.0e-12)" /><field160 name="Enter the Rise Time (default=1.0e-9)" /><field161 name="Enter the Fall Time (default=1.0e-9)" /></u26><u33 name="type">dac_bridge<field162 name="Enter value for out_low (default=0.0)" /><field163 name="Enter value for out_high (default=5.0)" /><field164 name="Enter value for out_undef (default=0.5)" /><field165 name="Enter value for input load (default=1.0e-12)" /><field166 name="Enter the Rise Time (default=1.0e-9)" /><field167 name="Enter the Fall Time (default=1.0e-9)" /></u33><u11 name="type">dac_bridge<field168 name="Enter value for out_low (default=0.0)" /><field169 name="Enter value for out_high (default=5.0)" /><field170 name="Enter value for out_undef (default=0.5)" /><field171 name="Enter value for input load (default=1.0e-12)" /><field172 name="Enter the Rise Time (default=1.0e-9)" /><field173 name="Enter the Fall Time (default=1.0e-9)" /></u11></model><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m12><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m13><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m14></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4035BM/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4035BM/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4035BM/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4035BM/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4035BM/analysis b/library/SubcircuitLibrary/CD4035BM/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4035BM/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |