diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4015BC_edge')
16 files changed, 953 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-cache.lib b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-cache.lib new file mode 100644 index 00000000..a6a60bb4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-cache.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# dff_edge +# +DEF dff_edge X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "dff_edge" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 450 350 -350 0 1 0 N +X D 1 -550 300 200 R 50 50 1 1 I +X clk 2 -550 0 200 R 50 50 1 1 I C +X Q 3 550 300 200 L 50 50 1 1 O +X reset 4 0 -550 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-rescue.lib b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-rescue.lib new file mode 100644 index 00000000..54585a8f --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# dff_edge-RESCUE-CD4015BC_edge +# +DEF dff_edge-RESCUE-CD4015BC_edge X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "dff_edge-RESCUE-CD4015BC_edge" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 450 350 -350 0 1 0 N +X D 1 -550 300 200 R 50 50 1 1 I +X clk 2 -550 0 200 R 50 50 1 1 I C +X Q 3 550 300 200 L 50 50 1 1 O +X reset 5 0 -550 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir new file mode 100644 index 00000000..11bfae9c --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir @@ -0,0 +1,18 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4015BC_edge\CD4015BC_edge.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 4/21/2025 9:52:10 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 da clka qa1 ra dff_edge +X3 qa1 clka qa2 ra dff_edge +X5 qa2 clka qa3 ra dff_edge +X7 qa3 clka qa4 ra dff_edge +X2 db clkb qb1 rb dff_edge +X4 qb1 clkb qb2 rb dff_edge +X6 qb2 clkb qb3 rb dff_edge +X8 qb3 clkb qb4 rb dff_edge + +.end diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir.out b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir.out new file mode 100644 index 00000000..b1ccc884 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4015bc_edge\cd4015bc_edge.cir + +.include dff_edge.sub +x1 da clka qa1 ra dff_edge +x3 qa1 clka qa2 ra dff_edge +x5 qa2 clka qa3 ra dff_edge +x7 qa3 clka qa4 ra dff_edge +x2 db clkb qb1 rb dff_edge +x4 qb1 clkb qb2 rb dff_edge +x6 qb2 clkb qb3 rb dff_edge +x8 qb3 clkb qb4 rb dff_edge +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.pro b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.pro new file mode 100644 index 00000000..d1f4cb60 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.pro @@ -0,0 +1,74 @@ +update=4/21/2025 8:31:02 PM +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=CD4015BC_edge-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sch b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sch new file mode 100644 index 00000000..6b5a8f92 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sch @@ -0,0 +1,234 @@ +EESchema Schematic File Version 2 +LIBS:CD4015BC_edge-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4015BC_edge-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text GLabel 2250 1850 0 60 Input ~ 0 +da +Text GLabel 2250 2150 0 60 Input ~ 0 +clka +Text GLabel 2250 2700 0 60 Input ~ 0 +ra +Wire Wire Line + 2250 1850 2400 1850 +Wire Wire Line + 2250 2150 2400 2150 +Wire Wire Line + 2250 2700 7900 2700 +Connection ~ 2950 2700 +Connection ~ 4650 2700 +Connection ~ 6250 2700 +Wire Wire Line + 3500 1850 4100 1850 +Wire Wire Line + 5200 1850 5700 1850 +Wire Wire Line + 6800 1850 7350 1850 +Connection ~ 2350 2150 +Text GLabel 2250 3650 0 60 Input ~ 0 +db +Text GLabel 2250 3950 0 60 Input ~ 0 +clkb +Text GLabel 2250 4500 0 60 Input ~ 0 +rb +Wire Wire Line + 2250 3650 2400 3650 +Wire Wire Line + 2250 3950 2400 3950 +Wire Wire Line + 2250 4500 7900 4500 +Connection ~ 2950 4500 +Connection ~ 4650 4500 +Connection ~ 6250 4500 +Wire Wire Line + 3500 3650 4100 3650 +Wire Wire Line + 5200 3650 5700 3650 +Wire Wire Line + 6800 3650 7350 3650 +Wire Wire Line + 2350 3950 2350 4600 +Wire Wire Line + 2350 4600 7350 4600 +Wire Wire Line + 4100 4600 4100 3950 +Connection ~ 2350 3950 +Wire Wire Line + 5700 4600 5700 3950 +Connection ~ 4100 4600 +Wire Wire Line + 7350 4600 7350 3950 +Connection ~ 5700 4600 +Text GLabel 3600 1850 1 60 Input ~ 0 +qa1 +Text GLabel 5300 1850 1 60 Input ~ 0 +qa2 +Text GLabel 6900 1850 1 60 Input ~ 0 +qa3 +Text GLabel 8550 1850 2 60 Input ~ 0 +qa4 +Wire Wire Line + 8450 1850 8550 1850 +Text GLabel 3600 3650 1 60 Input ~ 0 +qb1 +Text GLabel 5300 3650 1 60 Input ~ 0 +qb2 +Text GLabel 6900 3650 1 60 Input ~ 0 +qb3 +Text GLabel 8550 3650 2 60 Input ~ 0 +qb4 +Wire Wire Line + 8450 3650 8550 3650 +Wire Wire Line + 2350 2150 2350 2800 +Wire Wire Line + 2350 2800 7350 2800 +Wire Wire Line + 4100 2800 4100 2150 +Wire Wire Line + 5700 2800 5700 2150 +Connection ~ 4100 2800 +Wire Wire Line + 7350 2800 7350 2150 +Connection ~ 5700 2800 +$Comp +L dff_edge X1 +U 1 1 68066A43 +P 2950 2150 +F 0 "X1" H 2950 2150 60 0000 C CNN +F 1 "dff_edge" H 2950 2250 60 0000 C CNN +F 2 "" H 2950 2150 60 0001 C CNN +F 3 "" H 2950 2150 60 0001 C CNN + 1 2950 2150 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X3 +U 1 1 68066A7D +P 4650 2150 +F 0 "X3" H 4650 2150 60 0000 C CNN +F 1 "dff_edge" H 4650 2250 60 0000 C CNN +F 2 "" H 4650 2150 60 0001 C CNN +F 3 "" H 4650 2150 60 0001 C CNN + 1 4650 2150 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X5 +U 1 1 68066A9A +P 6250 2150 +F 0 "X5" H 6250 2150 60 0000 C CNN +F 1 "dff_edge" H 6250 2250 60 0000 C CNN +F 2 "" H 6250 2150 60 0001 C CNN +F 3 "" H 6250 2150 60 0001 C CNN + 1 6250 2150 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X7 +U 1 1 68066AFF +P 7900 2150 +F 0 "X7" H 7900 2150 60 0000 C CNN +F 1 "dff_edge" H 7900 2250 60 0000 C CNN +F 2 "" H 7900 2150 60 0001 C CNN +F 3 "" H 7900 2150 60 0001 C CNN + 1 7900 2150 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X2 +U 1 1 68066B8E +P 2950 3950 +F 0 "X2" H 2950 3950 60 0000 C CNN +F 1 "dff_edge" H 2950 4050 60 0000 C CNN +F 2 "" H 2950 3950 60 0001 C CNN +F 3 "" H 2950 3950 60 0001 C CNN + 1 2950 3950 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X4 +U 1 1 68066BF3 +P 4650 3950 +F 0 "X4" H 4650 3950 60 0000 C CNN +F 1 "dff_edge" H 4650 4050 60 0000 C CNN +F 2 "" H 4650 3950 60 0001 C CNN +F 3 "" H 4650 3950 60 0001 C CNN + 1 4650 3950 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X6 +U 1 1 68066C6E +P 6250 3950 +F 0 "X6" H 6250 3950 60 0000 C CNN +F 1 "dff_edge" H 6250 4050 60 0000 C CNN +F 2 "" H 6250 3950 60 0001 C CNN +F 3 "" H 6250 3950 60 0001 C CNN + 1 6250 3950 + 1 0 0 -1 +$EndComp +$Comp +L dff_edge X8 +U 1 1 68066CA3 +P 7900 3950 +F 0 "X8" H 7900 3950 60 0000 C CNN +F 1 "dff_edge" H 7900 4050 60 0000 C CNN +F 2 "" H 7900 3950 60 0001 C CNN +F 3 "" H 7900 3950 60 0001 C CNN + 1 7900 3950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sub b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sub new file mode 100644 index 00000000..2dba4638 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge.sub @@ -0,0 +1,11 @@ +.subckt CD4015BC_edge clkb qb4 qa3 qa2 qa1 ra da ? clka qa4 qb3 qb2 qb1 rb db ? +.include dff_edge.sub +x1 da clka qa1 ra dff_edge +x3 qa1 clka qa2 ra dff_edge +x5 qa2 clka qa3 ra dff_edge +x7 qa3 clka qa4 ra dff_edge +x2 db clkb qb1 rb dff_edge +x4 qb1 clkb qb2 rb dff_edge +x6 qb2 clkb qb3 rb dff_edge +x8 qb3 clkb qb4 rb dff_edge +.ends CD4015BC_edge
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge_Previous_Values.xml b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge_Previous_Values.xml new file mode 100644 index 00000000..0cfccd65 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/CD4015BC_edge_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x3><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x5><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x7><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x4><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x6><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge</field></x8></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4015BC_edge/analysis b/library/SubcircuitLibrary/CD4015BC_edge/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge-cache.lib b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge-cache.lib new file mode 100644 index 00000000..2a9c1f16 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge-cache.lib @@ -0,0 +1,35 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir new file mode 100644 index 00000000..295cbfc9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\dff_edge\dff_edge.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 4/21/2025 9:48:20 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 o4 o2 Net-_U1-Pad3_ d_and +U6 Net-_U1-Pad3_ o1 d_inverter +U2 o1 clk Net-_U2-Pad3_ d_and +U8 Net-_U2-Pad3_ reset Net-_U10-Pad1_ d_and +U10 Net-_U10-Pad1_ o2 d_inverter +U3 o2 clk Net-_U3-Pad3_ d_and +U9 Net-_U3-Pad3_ o4 Net-_U11-Pad1_ d_and +U11 Net-_U11-Pad1_ o3 d_inverter +U4 o3 d Net-_U4-Pad3_ d_and +U7 Net-_U4-Pad3_ o4 d_inverter +U12 o2 qbar Net-_U12-Pad3_ d_and +U14 Net-_U12-Pad3_ q d_inverter +U13 o3 q Net-_U13-Pad3_ d_and +U15 Net-_U13-Pad3_ reset Net-_U15-Pad3_ d_and +U17 Net-_U15-Pad3_ qbar d_inverter + +.end diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out new file mode 100644 index 00000000..ebb6f5ae --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out @@ -0,0 +1,71 @@ +* c:\fossee\esim\library\subcircuitlibrary\dff_edge\dff_edge.cir + +* u1 o4 o2 net-_u1-pad3_ d_and +* u6 net-_u1-pad3_ o1 d_inverter +* u2 o1 clk net-_u2-pad3_ d_and +* u8 net-_u2-pad3_ reset net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ o2 d_inverter +* u3 o2 clk net-_u3-pad3_ d_and +* u9 net-_u3-pad3_ o4 net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ o3 d_inverter +* u4 o3 d net-_u4-pad3_ d_and +* u7 net-_u4-pad3_ o4 d_inverter +* u12 o2 qbar net-_u12-pad3_ d_and +* u14 net-_u12-pad3_ q d_inverter +* u13 o3 q net-_u13-pad3_ d_and +* u15 net-_u13-pad3_ reset net-_u15-pad3_ d_and +* u17 net-_u15-pad3_ qbar d_inverter +a1 [o4 o2 ] net-_u1-pad3_ u1 +a2 net-_u1-pad3_ o1 u6 +a3 [o1 clk ] net-_u2-pad3_ u2 +a4 [net-_u2-pad3_ reset ] net-_u10-pad1_ u8 +a5 net-_u10-pad1_ o2 u10 +a6 [o2 clk ] net-_u3-pad3_ u3 +a7 [net-_u3-pad3_ o4 ] net-_u11-pad1_ u9 +a8 net-_u11-pad1_ o3 u11 +a9 [o3 d ] net-_u4-pad3_ u4 +a10 net-_u4-pad3_ o4 u7 +a11 [o2 qbar ] net-_u12-pad3_ u12 +a12 net-_u12-pad3_ q u14 +a13 [o3 q ] net-_u13-pad3_ u13 +a14 [net-_u13-pad3_ reset ] net-_u15-pad3_ u15 +a15 net-_u15-pad3_ qbar u17 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-06 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.pro b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sch b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sch new file mode 100644 index 00000000..273b40f2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sch @@ -0,0 +1,302 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:dff_edge-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U1 +U 1 1 68049319 +P 2850 2050 +F 0 "U1" H 2850 2050 60 0000 C CNN +F 1 "d_and" H 2900 2150 60 0000 C CNN +F 2 "" H 2850 2050 60 0000 C CNN +F 3 "" H 2850 2050 60 0000 C CNN + 1 2850 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6804931A +P 3600 2000 +F 0 "U6" H 3600 1900 60 0000 C CNN +F 1 "d_inverter" H 3600 2150 60 0000 C CNN +F 2 "" H 3650 1950 60 0000 C CNN +F 3 "" H 3650 1950 60 0000 C CNN + 1 3600 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 6804931B +P 2850 2650 +F 0 "U2" H 2850 2650 60 0000 C CNN +F 1 "d_and" H 2900 2750 60 0000 C CNN +F 2 "" H 2850 2650 60 0000 C CNN +F 3 "" H 2850 2650 60 0000 C CNN + 1 2850 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 6804931C +P 3750 2700 +F 0 "U8" H 3750 2700 60 0000 C CNN +F 1 "d_and" H 3800 2800 60 0000 C CNN +F 2 "" H 3750 2700 60 0000 C CNN +F 3 "" H 3750 2700 60 0000 C CNN + 1 3750 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6804931D +P 4500 2650 +F 0 "U10" H 4500 2550 60 0000 C CNN +F 1 "d_inverter" H 4500 2800 60 0000 C CNN +F 2 "" H 4550 2600 60 0000 C CNN +F 3 "" H 4550 2600 60 0000 C CNN + 1 4500 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 6804931E +P 2850 3350 +F 0 "U3" H 2850 3350 60 0000 C CNN +F 1 "d_and" H 2900 3450 60 0000 C CNN +F 2 "" H 2850 3350 60 0000 C CNN +F 3 "" H 2850 3350 60 0000 C CNN + 1 2850 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 6804931F +P 3750 3400 +F 0 "U9" H 3750 3400 60 0000 C CNN +F 1 "d_and" H 3800 3500 60 0000 C CNN +F 2 "" H 3750 3400 60 0000 C CNN +F 3 "" H 3750 3400 60 0000 C CNN + 1 3750 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68049320 +P 4500 3350 +F 0 "U11" H 4500 3250 60 0000 C CNN +F 1 "d_inverter" H 4500 3500 60 0000 C CNN +F 2 "" H 4550 3300 60 0000 C CNN +F 3 "" H 4550 3300 60 0000 C CNN + 1 4500 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 68049321 +P 2850 3950 +F 0 "U4" H 2850 3950 60 0000 C CNN +F 1 "d_and" H 2900 4050 60 0000 C CNN +F 2 "" H 2850 3950 60 0000 C CNN +F 3 "" H 2850 3950 60 0000 C CNN + 1 2850 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68049322 +P 3600 3900 +F 0 "U7" H 3600 3800 60 0000 C CNN +F 1 "d_inverter" H 3600 4050 60 0000 C CNN +F 2 "" H 3650 3850 60 0000 C CNN +F 3 "" H 3650 3850 60 0000 C CNN + 1 3600 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 68049323 +P 6500 2750 +F 0 "U12" H 6500 2750 60 0000 C CNN +F 1 "d_and" H 6550 2850 60 0000 C CNN +F 2 "" H 6500 2750 60 0000 C CNN +F 3 "" H 6500 2750 60 0000 C CNN + 1 6500 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 68049324 +P 7250 2700 +F 0 "U14" H 7250 2600 60 0000 C CNN +F 1 "d_inverter" H 7250 2850 60 0000 C CNN +F 2 "" H 7300 2650 60 0000 C CNN +F 3 "" H 7300 2650 60 0000 C CNN + 1 7250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 68049325 +P 6500 3450 +F 0 "U13" H 6500 3450 60 0000 C CNN +F 1 "d_and" H 6550 3550 60 0000 C CNN +F 2 "" H 6500 3450 60 0000 C CNN +F 3 "" H 6500 3450 60 0000 C CNN + 1 6500 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 68049326 +P 7400 3500 +F 0 "U15" H 7400 3500 60 0000 C CNN +F 1 "d_and" H 7450 3600 60 0000 C CNN +F 2 "" H 7400 3500 60 0000 C CNN +F 3 "" H 7400 3500 60 0000 C CNN + 1 7400 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 68049327 +P 8150 3450 +F 0 "U17" H 8150 3350 60 0000 C CNN +F 1 "d_inverter" H 8150 3600 60 0000 C CNN +F 2 "" H 8200 3400 60 0000 C CNN +F 3 "" H 8200 3400 60 0000 C CNN + 1 8150 3450 + 1 0 0 -1 +$EndComp +Text GLabel 2300 1950 0 60 Input ~ 0 +o4 +Text GLabel 2300 2050 0 60 Input ~ 0 +o2 +Text GLabel 2300 2550 0 60 Input ~ 0 +o1 +Text GLabel 2300 2650 0 60 Input ~ 0 +clk +Text GLabel 3200 2700 0 60 Input ~ 0 +reset +Text GLabel 2300 3250 0 60 Input ~ 0 +o2 +Text GLabel 2300 3350 0 60 Input ~ 0 +clk +Text GLabel 3200 3400 0 60 Input ~ 0 +o4 +Text GLabel 2300 3850 0 60 Input ~ 0 +o3 +Text GLabel 2300 3950 0 60 Input ~ 0 +d +Text GLabel 4000 2000 2 60 Input ~ 0 +o1 +Text GLabel 4900 2650 2 60 Input ~ 0 +o2 +Text GLabel 4900 3350 2 60 Input ~ 0 +o3 +Text GLabel 4000 3900 2 60 Input ~ 0 +o4 +Text GLabel 5950 2650 0 60 Input ~ 0 +o2 +Text GLabel 5950 2750 0 60 Input ~ 0 +qbar +Text GLabel 6850 3500 0 60 Input ~ 0 +reset +Text GLabel 5950 3350 0 60 Input ~ 0 +o3 +Text GLabel 5950 3450 0 60 Input ~ 0 +q +Text GLabel 7550 2700 1 60 Input ~ 0 +q +Text GLabel 8450 3450 1 60 Input ~ 0 +qbar +Wire Wire Line + 2300 1950 2400 1950 +Wire Wire Line + 2300 2050 2400 2050 +Wire Wire Line + 2300 2550 2400 2550 +Wire Wire Line + 2300 2650 2400 2650 +Wire Wire Line + 3200 2700 3300 2700 +Wire Wire Line + 2300 3250 2400 3250 +Wire Wire Line + 2300 3350 2400 3350 +Wire Wire Line + 3200 3400 3300 3400 +Wire Wire Line + 2300 3850 2400 3850 +Wire Wire Line + 2300 3950 2400 3950 +Wire Wire Line + 3900 2000 4000 2000 +Wire Wire Line + 4800 2650 4900 2650 +Wire Wire Line + 4800 3350 4900 3350 +Wire Wire Line + 3900 3900 4000 3900 +Wire Wire Line + 5950 2650 6050 2650 +Wire Wire Line + 5950 2750 6050 2750 +Wire Wire Line + 5950 3350 6050 3350 +Wire Wire Line + 5950 3450 6050 3450 +Wire Wire Line + 6850 3500 6950 3500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sub b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sub new file mode 100644 index 00000000..de822248 --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.sub @@ -0,0 +1,47 @@ +.subckt dff_edge clk d q reset +a1 [o4 o2 ] net-_u1-pad3_ u1 +a2 net-_u1-pad3_ o1 u6 +a3 [o1 clk ] net-_u2-pad3_ u2 +a4 [net-_u2-pad3_ reset ] net-_u10-pad1_ u8 +a5 net-_u10-pad1_ o2 u10 +a6 [o2 clk ] net-_u3-pad3_ u3 +a7 [net-_u3-pad3_ o4 ] net-_u11-pad1_ u9 +a8 net-_u11-pad1_ o3 u11 +a9 [o3 d ] net-_u4-pad3_ u4 +a10 net-_u4-pad3_ o4 u7 +a11 [o2 qbar ] net-_u12-pad3_ u12 +a12 net-_u12-pad3_ q u14 +a13 [o3 q ] net-_u13-pad3_ u13 +a14 [net-_u13-pad3_ reset ] net-_u15-pad3_ u15 +a15 net-_u15-pad3_ qbar u17 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.ends dff_edge
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge_Previous_Values.xml b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge_Previous_Values.xml new file mode 100644 index 00000000..20e1309c --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u1><u5 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u7 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u9 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u10><u4 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u6><u11 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">adc_bridge<field46 name="Enter value for in_low (default=1.0)" /><field47 name="Enter value for in_high (default=2.0)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /><field49 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">dac_bridge<field50 name="Enter value for out_low (default=0.0)">0</field50><field51 name="Enter value for out_high (default=5.0)">5</field51><field52 name="Enter value for out_undef (default=0.5)">5</field52><field53 name="Enter value for input load (default=1.0e-12)" /><field54 name="Enter the Rise Time (default=1.0e-9)" /><field55 name="Enter the Fall Time (default=1.0e-9)" /></u17><u18 name="type">dac_bridge<field56 name="Enter value for out_low (default=0.0)">0</field56><field57 name="Enter value for out_high (default=5.0)">5</field57><field58 name="Enter value for out_undef (default=0.5)">0</field58><field59 name="Enter value for input load (default=1.0e-12)" /><field60 name="Enter the Rise Time (default=1.0e-9)" /><field61 name="Enter the Fall Time (default=1.0e-9)" /></u18><u9 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u11 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u11><u7 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u14 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u14><u13 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u17><u5 name="type">adc_bridge<field46 name="Enter value for in_low (default=1.0)" /><field47 name="Enter value for in_high (default=2.0)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /><field49 name="Enter Fall Delay (default=1.0e-9)" /></u5><u16 name="type">dac_bridge<field50 name="Enter value for out_low (default=0.0)" /><field51 name="Enter value for out_high (default=5.0)" /><field52 name="Enter value for out_undef (default=0.5)" /><field53 name="Enter value for input load (default=1.0e-12)" /><field54 name="Enter the Rise Time (default=1.0e-9)" /><field55 name="Enter the Fall Time (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |