diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out new file mode 100644 index 00000000..ebb6f5ae --- /dev/null +++ b/library/SubcircuitLibrary/CD4015BC_edge/dff_edge.cir.out @@ -0,0 +1,71 @@ +* c:\fossee\esim\library\subcircuitlibrary\dff_edge\dff_edge.cir + +* u1 o4 o2 net-_u1-pad3_ d_and +* u6 net-_u1-pad3_ o1 d_inverter +* u2 o1 clk net-_u2-pad3_ d_and +* u8 net-_u2-pad3_ reset net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ o2 d_inverter +* u3 o2 clk net-_u3-pad3_ d_and +* u9 net-_u3-pad3_ o4 net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ o3 d_inverter +* u4 o3 d net-_u4-pad3_ d_and +* u7 net-_u4-pad3_ o4 d_inverter +* u12 o2 qbar net-_u12-pad3_ d_and +* u14 net-_u12-pad3_ q d_inverter +* u13 o3 q net-_u13-pad3_ d_and +* u15 net-_u13-pad3_ reset net-_u15-pad3_ d_and +* u17 net-_u15-pad3_ qbar d_inverter +a1 [o4 o2 ] net-_u1-pad3_ u1 +a2 net-_u1-pad3_ o1 u6 +a3 [o1 clk ] net-_u2-pad3_ u2 +a4 [net-_u2-pad3_ reset ] net-_u10-pad1_ u8 +a5 net-_u10-pad1_ o2 u10 +a6 [o2 clk ] net-_u3-pad3_ u3 +a7 [net-_u3-pad3_ o4 ] net-_u11-pad1_ u9 +a8 net-_u11-pad1_ o3 u11 +a9 [o3 d ] net-_u4-pad3_ u4 +a10 net-_u4-pad3_ o4 u7 +a11 [o2 qbar ] net-_u12-pad3_ u12 +a12 net-_u12-pad3_ q u14 +a13 [o3 q ] net-_u13-pad3_ u13 +a14 [net-_u13-pad3_ reset ] net-_u15-pad3_ u15 +a15 net-_u15-pad3_ qbar u17 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-06 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |