diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4010BQ1')
17 files changed, 1104 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1-cache.lib b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1-cache.lib new file mode 100644 index 00000000..26e0cb76 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 1_CD4010B +# +DEF 1_CD4010B X 0 40 Y Y 1 F N +F0 "X" 400 -200 60 H V C CNN +F1 "1_CD4010B" 150 0 48 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +P 4 0 1 0 -200 300 -200 -350 550 0 -200 300 N +X A 1 -400 0 200 R 50 50 1 1 I +X B 2 750 0 200 L 46 46 1 1 I +X VCC 3 50 400 200 D 39 39 1 1 I +X VDD 4 250 -350 200 U 20 20 1 1 I +X GND 5 -100 -500 200 U 39 39 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir new file mode 100644 index 00000000..4c98ca1d --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010BQ1\CD4010BQ1.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 10:33:51 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad7_ VCC VDD GND 1_CD4010B +X2 Net-_U1-Pad2_ Net-_U1-Pad8_ VCC VDD GND 1_CD4010B +X3 Net-_U1-Pad3_ Net-_U1-Pad9_ VCC VDD GND 1_CD4010B +X4 Net-_U1-Pad4_ Net-_U1-Pad10_ VCC VDD GND 1_CD4010B +X5 Net-_U1-Pad5_ Net-_U1-Pad11_ VCC VDD GND 1_CD4010B +X6 Net-_U1-Pad6_ Net-_U1-Pad12_ VCC VDD GND 1_CD4010B +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ VCC VDD GND PORT + +.end diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir.out b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir.out new file mode 100644 index 00000000..e8b91001 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.cir.out @@ -0,0 +1,19 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4010bq1\cd4010bq1.cir + +.include CD4010B_Q1.sub +x1 net-_u1-pad1_ net-_u1-pad7_ vcc vdd gnd CD4010B_Q1 +x2 net-_u1-pad2_ net-_u1-pad8_ vcc vdd gnd CD4010B_Q1 +x3 net-_u1-pad3_ net-_u1-pad9_ vcc vdd gnd CD4010B_Q1 +x4 net-_u1-pad4_ net-_u1-pad10_ vcc vdd gnd CD4010B_Q1 +x5 net-_u1-pad5_ net-_u1-pad11_ vcc vdd gnd CD4010B_Q1 +x6 net-_u1-pad6_ net-_u1-pad12_ vcc vdd gnd CD4010B_Q1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ vcc vdd gnd port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.pro b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sch b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sch new file mode 100644 index 00000000..ed7c7c9b --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sch @@ -0,0 +1,427 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 1_CD4010B X1 +U 1 1 6852BC74 +P 5150 1300 +F 0 "X1" H 5550 1100 60 0000 C CNN +F 1 "1_CD4010B" H 5300 1300 48 0000 C CNN +F 2 "" H 5200 1300 60 0001 C CNN +F 3 "" H 5200 1300 60 0001 C CNN + 1 5150 1300 + 1 0 0 -1 +$EndComp +$Comp +L 1_CD4010B X2 +U 1 1 6852BCDB +P 5150 2450 +F 0 "X2" H 5550 2250 60 0000 C CNN +F 1 "1_CD4010B" H 5300 2450 48 0000 C CNN +F 2 "" H 5200 2450 60 0001 C CNN +F 3 "" H 5200 2450 60 0001 C CNN + 1 5150 2450 + 1 0 0 -1 +$EndComp +$Comp +L 1_CD4010B X3 +U 1 1 6852BD00 +P 5200 3450 +F 0 "X3" H 5600 3250 60 0000 C CNN +F 1 "1_CD4010B" H 5350 3450 48 0000 C CNN +F 2 "" H 5250 3450 60 0001 C CNN +F 3 "" H 5250 3450 60 0001 C CNN + 1 5200 3450 + 1 0 0 -1 +$EndComp +$Comp +L 1_CD4010B X4 +U 1 1 6852BD29 +P 5300 4550 +F 0 "X4" H 5700 4350 60 0000 C CNN +F 1 "1_CD4010B" H 5450 4550 48 0000 C CNN +F 2 "" H 5350 4550 60 0001 C CNN +F 3 "" H 5350 4550 60 0001 C CNN + 1 5300 4550 + 1 0 0 -1 +$EndComp +$Comp +L 1_CD4010B X5 +U 1 1 6852BD4E +P 5400 5650 +F 0 "X5" H 5800 5450 60 0000 C CNN +F 1 "1_CD4010B" H 5550 5650 48 0000 C CNN +F 2 "" H 5450 5650 60 0001 C CNN +F 3 "" H 5450 5650 60 0001 C CNN + 1 5400 5650 + 1 0 0 -1 +$EndComp +$Comp +L 1_CD4010B X6 +U 1 1 6852BD7F +P 5450 6750 +F 0 "X6" H 5850 6550 60 0000 C CNN +F 1 "1_CD4010B" H 5600 6750 48 0000 C CNN +F 2 "" H 5500 6750 60 0001 C CNN +F 3 "" H 5500 6750 60 0001 C CNN + 1 5450 6750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6852BE34 +P 4300 1300 +F 0 "U1" H 4350 1400 30 0000 C CNN +F 1 "PORT" H 4300 1300 30 0000 C CNN +F 2 "" H 4300 1300 60 0000 C CNN +F 3 "" H 4300 1300 60 0000 C CNN + 1 4300 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6852BE83 +P 4300 2450 +F 0 "U1" H 4350 2550 30 0000 C CNN +F 1 "PORT" H 4300 2450 30 0000 C CNN +F 2 "" H 4300 2450 60 0000 C CNN +F 3 "" H 4300 2450 60 0000 C CNN + 2 4300 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6852BF08 +P 4300 3450 +F 0 "U1" H 4350 3550 30 0000 C CNN +F 1 "PORT" H 4300 3450 30 0000 C CNN +F 2 "" H 4300 3450 60 0000 C CNN +F 3 "" H 4300 3450 60 0000 C CNN + 3 4300 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6852BF87 +P 4350 4550 +F 0 "U1" H 4400 4650 30 0000 C CNN +F 1 "PORT" H 4350 4550 30 0000 C CNN +F 2 "" H 4350 4550 60 0000 C CNN +F 3 "" H 4350 4550 60 0000 C CNN + 4 4350 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6852BFCE +P 4450 5650 +F 0 "U1" H 4500 5750 30 0000 C CNN +F 1 "PORT" H 4450 5650 30 0000 C CNN +F 2 "" H 4450 5650 60 0000 C CNN +F 3 "" H 4450 5650 60 0000 C CNN + 5 4450 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6852C053 +P 4600 6750 +F 0 "U1" H 4650 6850 30 0000 C CNN +F 1 "PORT" H 4600 6750 30 0000 C CNN +F 2 "" H 4600 6750 60 0000 C CNN +F 3 "" H 4600 6750 60 0000 C CNN + 6 4600 6750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6852C0EE +P 6500 1300 +F 0 "U1" H 6550 1400 30 0000 C CNN +F 1 "PORT" H 6500 1300 30 0000 C CNN +F 2 "" H 6500 1300 60 0000 C CNN +F 3 "" H 6500 1300 60 0000 C CNN + 7 6500 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6852C12D +P 6500 2450 +F 0 "U1" H 6550 2550 30 0000 C CNN +F 1 "PORT" H 6500 2450 30 0000 C CNN +F 2 "" H 6500 2450 60 0000 C CNN +F 3 "" H 6500 2450 60 0000 C CNN + 8 6500 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6852C1CC +P 6600 3400 +F 0 "U1" H 6650 3500 30 0000 C CNN +F 1 "PORT" H 6600 3400 30 0000 C CNN +F 2 "" H 6600 3400 60 0000 C CNN +F 3 "" H 6600 3400 60 0000 C CNN + 9 6600 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6852C229 +P 6600 4550 +F 0 "U1" H 6650 4650 30 0000 C CNN +F 1 "PORT" H 6600 4550 30 0000 C CNN +F 2 "" H 6600 4550 60 0000 C CNN +F 3 "" H 6600 4550 60 0000 C CNN + 10 6600 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6852C320 +P 6600 5650 +F 0 "U1" H 6650 5750 30 0000 C CNN +F 1 "PORT" H 6600 5650 30 0000 C CNN +F 2 "" H 6600 5650 60 0000 C CNN +F 3 "" H 6600 5650 60 0000 C CNN + 11 6600 5650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6852C3CF +P 6650 6750 +F 0 "U1" H 6700 6850 30 0000 C CNN +F 1 "PORT" H 6650 6750 30 0000 C CNN +F 2 "" H 6650 6750 60 0000 C CNN +F 3 "" H 6650 6750 60 0000 C CNN + 12 6650 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6852C612 +P 8100 800 +F 0 "U1" H 8150 900 30 0000 C CNN +F 1 "PORT" H 8100 800 30 0000 C CNN +F 2 "" H 8100 800 60 0000 C CNN +F 3 "" H 8100 800 60 0000 C CNN + 13 8100 800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6852C69B +P 8100 1150 +F 0 "U1" H 8150 1250 30 0000 C CNN +F 1 "PORT" H 8100 1150 30 0000 C CNN +F 2 "" H 8100 1150 60 0000 C CNN +F 3 "" H 8100 1150 60 0000 C CNN + 14 8100 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6852C6DE +P 8100 1500 +F 0 "U1" H 8150 1600 30 0000 C CNN +F 1 "PORT" H 8100 1500 30 0000 C CNN +F 2 "" H 8100 1500 60 0000 C CNN +F 3 "" H 8100 1500 60 0000 C CNN + 15 8100 1500 + 1 0 0 -1 +$EndComp +Text GLabel 8800 750 2 60 Input ~ 0 +VCC +Text GLabel 8850 1100 2 60 Input ~ 0 +VDD +Text GLabel 8900 1500 2 60 Input ~ 0 +GND +Wire Wire Line + 8350 800 8550 800 +Wire Wire Line + 8550 800 8550 750 +Wire Wire Line + 8550 750 8800 750 +Wire Wire Line + 8350 1150 8750 1150 +Wire Wire Line + 8750 1150 8750 1100 +Wire Wire Line + 8750 1100 8850 1100 +Wire Wire Line + 8350 1500 8900 1500 +Wire Wire Line + 4550 1300 4750 1300 +Wire Wire Line + 5900 1300 6250 1300 +Wire Wire Line + 4550 2450 4750 2450 +Wire Wire Line + 5900 2450 6250 2450 +Wire Wire Line + 4550 3450 4800 3450 +Wire Wire Line + 5950 3450 6200 3450 +Wire Wire Line + 6200 3450 6200 3400 +Wire Wire Line + 6200 3400 6350 3400 +Wire Wire Line + 4600 4550 4900 4550 +Wire Wire Line + 6050 4550 6350 4550 +Wire Wire Line + 4700 5650 5000 5650 +Wire Wire Line + 6150 5650 6350 5650 +Wire Wire Line + 4850 6750 5050 6750 +Wire Wire Line + 6200 6750 6400 6750 +Text GLabel 5350 850 2 60 Input ~ 0 +VCC +Text GLabel 5350 2000 2 60 Input ~ 0 +VCC +Text GLabel 5450 3050 2 60 Input ~ 0 +VCC +Text GLabel 5550 4150 2 60 Input ~ 0 +VCC +Text GLabel 5650 5200 2 60 Input ~ 0 +VCC +Text GLabel 5700 6350 2 60 Input ~ 0 +VCC +Wire Wire Line + 5500 6350 5700 6350 +Wire Wire Line + 5450 5250 5450 5200 +Wire Wire Line + 5450 5200 5650 5200 +Wire Wire Line + 5350 4150 5550 4150 +Wire Wire Line + 5250 3050 5450 3050 +Wire Wire Line + 5200 2050 5200 2000 +Wire Wire Line + 5200 2000 5350 2000 +Wire Wire Line + 5200 900 5200 850 +Wire Wire Line + 5200 850 5350 850 +Text GLabel 5550 1750 2 60 Input ~ 0 +VDD +Text GLabel 5550 2800 2 60 Input ~ 0 +VDD +Text GLabel 5600 3850 2 60 Input ~ 0 +VDD +Text GLabel 5700 4900 2 60 Input ~ 0 +VDD +Text GLabel 5850 6050 2 60 Input ~ 0 +VDD +Text GLabel 5900 7200 2 60 Input ~ 0 +VDD +Wire Wire Line + 5700 7100 5700 7200 +Wire Wire Line + 5700 7200 5900 7200 +Wire Wire Line + 5650 6000 5650 6050 +Wire Wire Line + 5650 6050 5850 6050 +Wire Wire Line + 5550 4900 5700 4900 +Wire Wire Line + 5450 3800 5450 3850 +Wire Wire Line + 5450 3850 5600 3850 +Wire Wire Line + 5400 2800 5550 2800 +Wire Wire Line + 5400 1650 5400 1750 +Wire Wire Line + 5400 1750 5550 1750 +Text GLabel 4900 1850 0 60 Input ~ 0 +GND +Wire Wire Line + 4900 1850 5050 1850 +Wire Wire Line + 5050 1850 5050 1800 +Text GLabel 4950 3000 0 60 Input ~ 0 +GND +Text GLabel 5100 4050 0 60 Input ~ 0 +GND +Text GLabel 4950 5100 0 60 Input ~ 0 +GND +Text GLabel 5100 6150 0 60 Input ~ 0 +GND +Text GLabel 5150 7250 0 60 Input ~ 0 +GND +Wire Wire Line + 5150 7250 5350 7250 +Wire Wire Line + 5100 6150 5300 6150 +Wire Wire Line + 4950 5100 5200 5100 +Wire Wire Line + 5200 5100 5200 5050 +Wire Wire Line + 5100 4050 5100 3950 +Wire Wire Line + 4950 3000 5050 3000 +Wire Wire Line + 5050 3000 5050 2950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sub b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sub new file mode 100644 index 00000000..8aad537a --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1.sub @@ -0,0 +1,13 @@ +* Subcircuit CD4010BQ1 +.subckt CD4010BQ1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ vcc vdd gnd +* c:\fossee\esim\library\subcircuitlibrary\cd4010bq1\cd4010bq1.cir +.include CD4010B_Q1.sub +x1 net-_u1-pad1_ net-_u1-pad7_ vcc vdd gnd CD4010B_Q1 +x2 net-_u1-pad2_ net-_u1-pad8_ vcc vdd gnd CD4010B_Q1 +x3 net-_u1-pad3_ net-_u1-pad9_ vcc vdd gnd CD4010B_Q1 +x4 net-_u1-pad4_ net-_u1-pad10_ vcc vdd gnd CD4010B_Q1 +x5 net-_u1-pad5_ net-_u1-pad11_ vcc vdd gnd CD4010B_Q1 +x6 net-_u1-pad6_ net-_u1-pad12_ vcc vdd gnd CD4010B_Q1 +* Control Statements + +.ends CD4010BQ1
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1_Previous_Values.xml b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1_Previous_Values.xml new file mode 100644 index 00000000..009f4069 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010BQ1_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1-cache.lib b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir new file mode 100644 index 00000000..72dc492e --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4010B_Q1\CD4010B_Q1.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/25 18:34:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M5 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_M3-Pad3_ Net-_M2-Pad1_ mosfet_p +M4 Net-_M3-Pad3_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir.out b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir.out new file mode 100644 index 00000000..08d2abd0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.cir.out @@ -0,0 +1,19 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4010b_q1\cd4010b_q1.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=220u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m3-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=220u L=100u M=1 +m4 net-_m3-pad3_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad1_ net-_m2-pad1_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.pro b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sch b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sch new file mode 100644 index 00000000..54ae32c8 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4010B_Q1-cache +LIBS:CD4010B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 6852B46F +P 4000 2750 +F 0 "M2" H 3950 2800 50 0000 R CNN +F 1 "mosfet_p" H 4050 2900 50 0000 R CNN +F 2 "" H 4250 2850 29 0000 C CNN +F 3 "" H 4050 2750 60 0000 C CNN + 1 4000 2750 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 6852B470 +P 3950 3450 +F 0 "M1" H 3950 3300 50 0000 R CNN +F 1 "mosfet_n" H 4050 3400 50 0000 R CNN +F 2 "" H 4250 3150 29 0000 C CNN +F 3 "" H 4050 3250 60 0000 C CNN + 1 3950 3450 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 6852B471 +P 5750 2700 +F 0 "M5" H 5700 2750 50 0000 R CNN +F 1 "mosfet_p" H 5800 2850 50 0000 R CNN +F 2 "" H 6000 2800 29 0000 C CNN +F 3 "" H 5800 2700 60 0000 C CNN + 1 5750 2700 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M4 +U 1 1 6852B472 +P 4850 3500 +F 0 "M4" H 4850 3350 50 0000 R CNN +F 1 "mosfet_n" H 4950 3450 50 0000 R CNN +F 2 "" H 5150 3200 29 0000 C CNN +F 3 "" H 4950 3300 60 0000 C CNN + 1 4850 3500 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 6852B473 +P 4850 2550 +F 0 "M3" H 4850 2400 50 0000 R CNN +F 1 "mosfet_n" H 4950 2500 50 0000 R CNN +F 2 "" H 5150 2250 29 0000 C CNN +F 3 "" H 4950 2350 60 0000 C CNN + 1 4850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6852B69C +P 2400 3300 +F 0 "U1" H 2450 3400 30 0000 C CNN +F 1 "PORT" H 2400 3300 30 0000 C CNN +F 2 "" H 2400 3300 60 0000 C CNN +F 3 "" H 2400 3300 60 0000 C CNN + 1 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6852B759 +P 4850 4200 +F 0 "U1" H 4900 4300 30 0000 C CNN +F 1 "PORT" H 4850 4200 30 0000 C CNN +F 2 "" H 4850 4200 60 0000 C CNN +F 3 "" H 4850 4200 60 0000 C CNN + 5 4850 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6852B7E3 +P 3300 1800 +F 0 "U1" H 3350 1900 30 0000 C CNN +F 1 "PORT" H 3300 1800 30 0000 C CNN +F 2 "" H 3300 1800 60 0000 C CNN +F 3 "" H 3300 1800 60 0000 C CNN + 4 3300 1800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6852B9FE +P 7100 3050 +F 0 "U1" H 7150 3150 30 0000 C CNN +F 1 "PORT" H 7100 3050 30 0000 C CNN +F 2 "" H 7100 3050 60 0000 C CNN +F 3 "" H 7100 3050 60 0000 C CNN + 2 7100 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6852BB2C +P 5500 1300 +F 0 "U1" H 5550 1400 30 0000 C CNN +F 1 "PORT" H 5500 1300 30 0000 C CNN +F 2 "" H 5500 1300 60 0000 C CNN +F 3 "" H 5500 1300 60 0000 C CNN + 3 5500 1300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4150 2950 4150 3450 +Wire Wire Line + 4250 2900 4350 2900 +Wire Wire Line + 4350 2900 4350 2550 +Wire Wire Line + 4350 2550 4150 2550 +Wire Wire Line + 5050 2950 5050 3500 +Wire Wire Line + 5150 4050 5150 3850 +Wire Wire Line + 4150 4050 5150 4050 +Wire Wire Line + 5050 4050 5050 3900 +Wire Wire Line + 6000 2850 6200 2850 +Wire Wire Line + 6200 2850 6200 2300 +Wire Wire Line + 6200 2300 4150 2300 +Wire Wire Line + 4150 2550 4150 1550 +Wire Wire Line + 4150 3850 4150 4050 +Wire Wire Line + 4250 4050 4250 3800 +Connection ~ 5050 4050 +Connection ~ 4250 4050 +Wire Wire Line + 3850 2750 3500 2750 +Wire Wire Line + 3500 2750 3500 3650 +Wire Wire Line + 3500 3650 3850 3650 +Wire Wire Line + 4150 1550 3300 1550 +Connection ~ 4150 2300 +Wire Wire Line + 5900 2500 5900 1050 +Wire Wire Line + 5900 1050 5500 1050 +Wire Wire Line + 4150 3250 5600 3250 +Wire Wire Line + 4700 3250 4700 3700 +Wire Wire Line + 4700 3700 4750 3700 +Connection ~ 4150 3250 +Wire Wire Line + 5600 3250 5600 2700 +Connection ~ 4700 3250 +Wire Wire Line + 4750 2750 4750 3150 +Wire Wire Line + 4750 3150 3500 3150 +Connection ~ 3500 3150 +Wire Wire Line + 5050 2550 5050 2150 +Wire Wire Line + 5050 2150 5900 2150 +Connection ~ 5900 2150 +Wire Wire Line + 5150 2900 5150 3050 +Wire Wire Line + 5050 3050 6850 3050 +Connection ~ 5050 3050 +Wire Wire Line + 5900 3050 5900 2900 +Connection ~ 5150 3050 +Wire Wire Line + 2650 3300 3500 3300 +Connection ~ 3500 3300 +Connection ~ 5900 3050 +Connection ~ 4600 4050 +Wire Wire Line + 4600 4200 4600 4050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sub b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sub new file mode 100644 index 00000000..fdd49d69 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1.sub @@ -0,0 +1,13 @@ +* Subcircuit CD4010B_Q1 +.subckt CD4010B_Q1 net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad1_ net-_m2-pad1_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4010b_q1\cd4010b_q1.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=220u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m3-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=220u L=100u M=1 +m4 net-_m3-pad3_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD4010B_Q1
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1_Previous_Values.xml b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1_Previous_Values.xml new file mode 100644 index 00000000..d5e3ed2e --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/CD4010B_Q1_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>200u</field><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>200u</field><field /><field /></m5><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4010BQ1/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4010BQ1/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4010BQ1/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4010BQ1/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4010BQ1/analysis b/library/SubcircuitLibrary/CD4010BQ1/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4010BQ1/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |