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-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib118
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir37
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out116
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro73
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch719
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub110
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74VHC373-D/analysis1
8 files changed, 1175 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib
new file mode 100644
index 00000000..e73e9677
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D-cache.lib
@@ -0,0 +1,118 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 P
+X ~ 2 250 0 100 L 30 30 2 1 P
+X ~ 3 250 0 100 L 30 30 3 1 P
+X ~ 4 250 0 100 L 30 30 4 1 P
+X ~ 5 250 0 100 L 30 30 5 1 P
+X ~ 6 250 0 100 L 30 30 6 1 P
+X ~ 7 250 0 100 L 30 30 7 1 P
+X ~ 8 250 0 100 L 30 30 8 1 P
+X ~ 9 250 0 100 L 30 30 9 1 P
+X ~ 10 250 0 100 L 30 30 10 1 P
+X ~ 11 250 0 100 L 30 30 11 1 P
+X ~ 12 250 0 100 L 30 30 12 1 P
+X ~ 13 250 0 100 L 30 30 13 1 P
+X ~ 14 250 0 100 L 30 30 14 1 P
+X ~ 15 250 0 100 L 30 30 15 1 P
+X ~ 16 250 0 100 L 30 30 16 1 P
+X ~ 17 250 0 100 L 30 30 17 1 P
+X ~ 18 250 0 100 L 30 30 18 1 P
+X ~ 19 250 0 100 L 30 30 19 1 P
+X ~ 20 250 0 100 L 30 30 20 1 P
+X ~ 21 250 0 100 L 30 30 21 1 P
+X ~ 22 250 0 100 L 30 30 22 1 P
+X ~ 23 250 0 100 L 30 30 23 1 P
+X ~ 24 250 0 100 L 30 30 24 1 P
+X ~ 25 250 0 100 L 30 30 25 1 P
+X ~ 26 250 0 100 L 30 30 26 1 P
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dlatch
+#
+DEF d_dlatch U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dlatch" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X EN 2 -550 -300 200 R 50 50 1 1 I
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir
new file mode 100644
index 00000000..bdb59d4c
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir
@@ -0,0 +1,37 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74VHC373-D\74VHC373-D.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/19/25 15:22:23
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U4 Net-_U1-Pad2_ Net-_U10-Pad2_ ? ? ? Net-_U4-Pad6_ d_dlatch
+U13 Net-_U1-Pad9_ Net-_U10-Pad2_ ? ? ? Net-_U13-Pad6_ d_dlatch
+U10 Net-_U1-Pad7_ Net-_U10-Pad2_ ? ? ? Net-_U10-Pad6_ d_dlatch
+U16 Net-_U1-Pad11_ Net-_U10-Pad2_ ? ? ? Net-_U16-Pad6_ d_dlatch
+U19 Net-_U1-Pad13_ Net-_U10-Pad2_ ? ? ? Net-_U19-Pad6_ d_dlatch
+U22 Net-_U1-Pad15_ Net-_U10-Pad2_ ? ? ? Net-_U22-Pad6_ d_dlatch
+U25 Net-_U1-Pad17_ Net-_U10-Pad2_ ? ? ? Net-_U25-Pad6_ d_dlatch
+U7 Net-_U1-Pad5_ Net-_U10-Pad2_ ? ? ? Net-_U7-Pad6_ d_dlatch
+U5 Net-_U4-Pad6_ Net-_U11-Pad2_ Net-_U5-Pad3_ d_tristate
+U8 Net-_U7-Pad6_ Net-_U11-Pad2_ Net-_U8-Pad3_ d_tristate
+U11 Net-_U10-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_tristate
+U14 Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate
+U17 Net-_U16-Pad6_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_tristate
+U20 Net-_U19-Pad6_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_tristate
+U23 Net-_U22-Pad6_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_tristate
+U26 Net-_U25-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_tristate
+U6 Net-_U5-Pad3_ Net-_U1-Pad4_ d_inverter
+U9 Net-_U8-Pad3_ Net-_U1-Pad6_ d_inverter
+U12 Net-_U11-Pad3_ Net-_U1-Pad8_ d_inverter
+U15 Net-_U14-Pad3_ Net-_U1-Pad10_ d_inverter
+U18 Net-_U17-Pad3_ Net-_U1-Pad12_ d_inverter
+U21 Net-_U20-Pad3_ Net-_U1-Pad14_ d_inverter
+U24 Net-_U23-Pad3_ Net-_U1-Pad16_ d_inverter
+U27 Net-_U26-Pad3_ Net-_U1-Pad18_ d_inverter
+U3 Net-_U1-Pad3_ Net-_U11-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U10-Pad2_ d_buffer
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ GND GND PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out
new file mode 100644
index 00000000..0c1dfc21
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.cir.out
@@ -0,0 +1,116 @@
+* c:\fossee\esim\library\subcircuitlibrary\74vhc373-d\74vhc373-d.cir
+
+* u4 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ d_dlatch
+* u13 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ d_dlatch
+* u10 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ d_dlatch
+* u16 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ d_dlatch
+* u19 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ d_dlatch
+* u22 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ d_dlatch
+* u25 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ d_dlatch
+* u7 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ d_dlatch
+* u5 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ d_tristate
+* u8 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ d_tristate
+* u11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ d_tristate
+* u14 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ d_tristate
+* u17 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ d_tristate
+* u20 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ d_tristate
+* u23 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ d_tristate
+* u26 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ d_tristate
+* u6 net-_u5-pad3_ net-_u1-pad4_ d_inverter
+* u9 net-_u8-pad3_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+* u15 net-_u14-pad3_ net-_u1-pad10_ d_inverter
+* u18 net-_u17-pad3_ net-_u1-pad12_ d_inverter
+* u21 net-_u20-pad3_ net-_u1-pad14_ d_inverter
+* u24 net-_u23-pad3_ net-_u1-pad16_ d_inverter
+* u27 net-_u26-pad3_ net-_u1-pad18_ d_inverter
+* u3 net-_u1-pad3_ net-_u11-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad2_ d_buffer
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd port
+a1 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ u4
+a2 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ u13
+a3 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ u10
+a4 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ u16
+a5 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ u19
+a6 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ u22
+a7 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ u25
+a8 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ u7
+a9 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ u5
+a10 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ u8
+a11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ u11
+a12 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ u14
+a13 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ u17
+a14 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ u20
+a15 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ u23
+a16 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ u26
+a17 net-_u5-pad3_ net-_u1-pad4_ u6
+a18 net-_u8-pad3_ net-_u1-pad6_ u9
+a19 net-_u11-pad3_ net-_u1-pad8_ u12
+a20 net-_u14-pad3_ net-_u1-pad10_ u15
+a21 net-_u17-pad3_ net-_u1-pad12_ u18
+a22 net-_u20-pad3_ net-_u1-pad14_ u21
+a23 net-_u23-pad3_ net-_u1-pad16_ u24
+a24 net-_u26-pad3_ net-_u1-pad18_ u27
+a25 net-_u1-pad3_ net-_u11-pad2_ u3
+a26 net-_u1-pad1_ net-_u10-pad2_ u2
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u10 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u22 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch
new file mode 100644
index 00000000..73904330
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sch
@@ -0,0 +1,719 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74VHC373-D-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
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diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub
new file mode 100644
index 00000000..e78fc2ff
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D.sub
@@ -0,0 +1,110 @@
+* Subcircuit 74VHC373-D
+.subckt 74VHC373-D net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd
+* c:\fossee\esim\library\subcircuitlibrary\74vhc373-d\74vhc373-d.cir
+* u4 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ d_dlatch
+* u13 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ d_dlatch
+* u10 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ d_dlatch
+* u16 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ d_dlatch
+* u19 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ d_dlatch
+* u22 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ d_dlatch
+* u25 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ d_dlatch
+* u7 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ d_dlatch
+* u5 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ d_tristate
+* u8 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ d_tristate
+* u11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ d_tristate
+* u14 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ d_tristate
+* u17 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ d_tristate
+* u20 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ d_tristate
+* u23 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ d_tristate
+* u26 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ d_tristate
+* u6 net-_u5-pad3_ net-_u1-pad4_ d_inverter
+* u9 net-_u8-pad3_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+* u15 net-_u14-pad3_ net-_u1-pad10_ d_inverter
+* u18 net-_u17-pad3_ net-_u1-pad12_ d_inverter
+* u21 net-_u20-pad3_ net-_u1-pad14_ d_inverter
+* u24 net-_u23-pad3_ net-_u1-pad16_ d_inverter
+* u27 net-_u26-pad3_ net-_u1-pad18_ d_inverter
+* u3 net-_u1-pad3_ net-_u11-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad2_ d_buffer
+a1 net-_u1-pad2_ net-_u10-pad2_ ? ? ? net-_u4-pad6_ u4
+a2 net-_u1-pad9_ net-_u10-pad2_ ? ? ? net-_u13-pad6_ u13
+a3 net-_u1-pad7_ net-_u10-pad2_ ? ? ? net-_u10-pad6_ u10
+a4 net-_u1-pad11_ net-_u10-pad2_ ? ? ? net-_u16-pad6_ u16
+a5 net-_u1-pad13_ net-_u10-pad2_ ? ? ? net-_u19-pad6_ u19
+a6 net-_u1-pad15_ net-_u10-pad2_ ? ? ? net-_u22-pad6_ u22
+a7 net-_u1-pad17_ net-_u10-pad2_ ? ? ? net-_u25-pad6_ u25
+a8 net-_u1-pad5_ net-_u10-pad2_ ? ? ? net-_u7-pad6_ u7
+a9 net-_u4-pad6_ net-_u11-pad2_ net-_u5-pad3_ u5
+a10 net-_u7-pad6_ net-_u11-pad2_ net-_u8-pad3_ u8
+a11 net-_u10-pad6_ net-_u11-pad2_ net-_u11-pad3_ u11
+a12 net-_u13-pad6_ net-_u11-pad2_ net-_u14-pad3_ u14
+a13 net-_u16-pad6_ net-_u11-pad2_ net-_u17-pad3_ u17
+a14 net-_u19-pad6_ net-_u11-pad2_ net-_u20-pad3_ u20
+a15 net-_u22-pad6_ net-_u11-pad2_ net-_u23-pad3_ u23
+a16 net-_u25-pad6_ net-_u11-pad2_ net-_u26-pad3_ u26
+a17 net-_u5-pad3_ net-_u1-pad4_ u6
+a18 net-_u8-pad3_ net-_u1-pad6_ u9
+a19 net-_u11-pad3_ net-_u1-pad8_ u12
+a20 net-_u14-pad3_ net-_u1-pad10_ u15
+a21 net-_u17-pad3_ net-_u1-pad12_ u18
+a22 net-_u20-pad3_ net-_u1-pad14_ u21
+a23 net-_u23-pad3_ net-_u1-pad16_ u24
+a24 net-_u26-pad3_ net-_u1-pad18_ u27
+a25 net-_u1-pad3_ net-_u11-pad2_ u3
+a26 net-_u1-pad1_ net-_u10-pad2_ u2
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u10 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u22 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74VHC373-D \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml
new file mode 100644
index 00000000..7eccc7ec
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/74VHC373-D_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_dlatch<field1 name="Enter Data Delay (default=1.0e-9)" /><field2 name="Enter Enable Delay (default=1.0e-9)" /><field3 name="Enter Set Delay (default=1.0e-9)" /><field4 name="Enter Reset Delay (default=1.0)" /><field5 name="Enter IC (default=0)" /><field6 name="Enter value for Data Load (default=1.0e-12)" /><field7 name="Enter value for Enable Load (default=1.0e-12)" /><field8 name="Enter value for Set Load (default=1.0e-12)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /></u4><u13 name="type">d_dlatch<field12 name="Enter Data Delay (default=1.0e-9)" /><field13 name="Enter Enable Delay (default=1.0e-9)" /><field14 name="Enter Set Delay (default=1.0e-9)" /><field15 name="Enter Reset Delay (default=1.0)" /><field16 name="Enter IC (default=0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter value for Enable Load (default=1.0e-12)" /><field19 name="Enter value for Set Load (default=1.0e-12)" /><field20 name="Enter value for Reset Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u13><u10 name="type">d_dlatch<field23 name="Enter Data Delay (default=1.0e-9)" /><field24 name="Enter Enable Delay (default=1.0e-9)" /><field25 name="Enter Set Delay (default=1.0e-9)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter IC (default=0)" /><field28 name="Enter value for Data Load (default=1.0e-12)" /><field29 name="Enter value for Enable Load (default=1.0e-12)" /><field30 name="Enter value for Set Load (default=1.0e-12)" /><field31 name="Enter value for Reset Load (default=1.0e-12)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u10><u16 name="type">d_dlatch<field34 name="Enter Data Delay (default=1.0e-9)" /><field35 name="Enter Enable Delay (default=1.0e-9)" /><field36 name="Enter Set Delay (default=1.0e-9)" /><field37 name="Enter Reset Delay (default=1.0)" /><field38 name="Enter IC (default=0)" /><field39 name="Enter value for Data Load (default=1.0e-12)" /><field40 name="Enter value for Enable Load (default=1.0e-12)" /><field41 name="Enter value for Set Load (default=1.0e-12)" /><field42 name="Enter value for Reset Load (default=1.0e-12)" /><field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /></u16><u19 name="type">d_dlatch<field45 name="Enter Data Delay (default=1.0e-9)" /><field46 name="Enter Enable Delay (default=1.0e-9)" /><field47 name="Enter Set Delay (default=1.0e-9)" /><field48 name="Enter Reset Delay (default=1.0)" /><field49 name="Enter IC (default=0)" /><field50 name="Enter value for Data Load (default=1.0e-12)" /><field51 name="Enter value for Enable Load (default=1.0e-12)" /><field52 name="Enter value for Set Load (default=1.0e-12)" /><field53 name="Enter value for Reset Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /><field55 name="Enter Fall Delay (default=1.0e-9)" /></u19><u22 name="type">d_dlatch<field56 name="Enter Data Delay (default=1.0e-9)" /><field57 name="Enter Enable Delay (default=1.0e-9)" /><field58 name="Enter Set Delay (default=1.0e-9)" /><field59 name="Enter Reset Delay (default=1.0)" /><field60 name="Enter IC (default=0)" /><field61 name="Enter value for Data Load (default=1.0e-12)" /><field62 name="Enter value for Enable Load (default=1.0e-12)" /><field63 name="Enter value for Set Load (default=1.0e-12)" /><field64 name="Enter value for Reset Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u22><u25 name="type">d_dlatch<field67 name="Enter Data Delay (default=1.0e-9)" /><field68 name="Enter Enable Delay (default=1.0e-9)" /><field69 name="Enter Set Delay (default=1.0e-9)" /><field70 name="Enter Reset Delay (default=1.0)" /><field71 name="Enter IC (default=0)" /><field72 name="Enter value for Data Load (default=1.0e-12)" /><field73 name="Enter value for Enable Load (default=1.0e-12)" /><field74 name="Enter value for Set Load (default=1.0e-12)" /><field75 name="Enter value for Reset Load (default=1.0e-12)" /><field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /></u25><u7 name="type">d_dlatch<field78 name="Enter Data Delay (default=1.0e-9)" /><field79 name="Enter Enable Delay (default=1.0e-9)" /><field80 name="Enter Set Delay (default=1.0e-9)" /><field81 name="Enter Reset Delay (default=1.0)" /><field82 name="Enter IC (default=0)" /><field83 name="Enter value for Data Load (default=1.0e-12)" /><field84 name="Enter value for Enable Load (default=1.0e-12)" /><field85 name="Enter value for Set Load (default=1.0e-12)" /><field86 name="Enter value for Reset Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u7><u5 name="type">d_tristate<field89 name="Enter Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /><field91 name="Enter Enable Load (default=1.0e-12)" /></u5><u8 name="type">d_tristate<field92 name="Enter Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /><field94 name="Enter Enable Load (default=1.0e-12)" /></u8><u11 name="type">d_tristate<field95 name="Enter Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /><field97 name="Enter Enable Load (default=1.0e-12)" /></u11><u14 name="type">d_tristate<field98 name="Enter Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Enable Load (default=1.0e-12)" /></u14><u17 name="type">d_tristate<field101 name="Enter Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Enable Load (default=1.0e-12)" /></u17><u20 name="type">d_tristate<field104 name="Enter Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /><field106 name="Enter Enable Load (default=1.0e-12)" /></u20><u23 name="type">d_tristate<field107 name="Enter Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /><field109 name="Enter Enable Load (default=1.0e-12)" /></u23><u26 name="type">d_tristate<field110 name="Enter Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /><field112 name="Enter Enable Load (default=1.0e-12)" /></u26><u6 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u9><u12 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u15><u18 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u18><u21 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u24><u27 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u27><u3 name="type">d_inverter<field137 name="Enter Rise Delay (default=1.0e-9)" /><field138 name="Enter Fall Delay (default=1.0e-9)" /><field139 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_buffer<field140 name="Enter Rise Delay (default=1.0e-9)" /><field141 name="Enter Fall Delay (default=1.0e-9)" /><field142 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74VHC373-D/analysis b/library/SubcircuitLibrary/74VHC373-D/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74VHC373-D/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-05-29 06:55:16 +0000