diff options
Diffstat (limited to 'library/SubcircuitLibrary/74LVC1G57')
8 files changed, 501 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57-cache.lib b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir new file mode 100644 index 00000000..a8fa5835 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir @@ -0,0 +1,19 @@ +* C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\74LVC1G57\74LVC1G57.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/29/25 19:15:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U7 Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U7-Pad3_ d_and +U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter +U6 Net-_U4-Pad2_ Net-_U6-Pad2_ d_inverter +U8 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad3_ d_and +U9 Net-_U7-Pad3_ Net-_U8-Pad3_ Net-_U1-Pad4_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir.out b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir.out new file mode 100644 index 00000000..85dd8c7e --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.cir.out @@ -0,0 +1,44 @@ +* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\74lvc1g57\74lvc1g57.cir + +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_and +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad3_ d_and +* u9 net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad4_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7 +a5 net-_u3-pad2_ net-_u5-pad2_ u5 +a6 net-_u4-pad2_ net-_u6-pad2_ u6 +a7 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u8-pad3_ u8 +a8 [net-_u7-pad3_ net-_u8-pad3_ ] net-_u1-pad4_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.pro b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sch b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sch new file mode 100644 index 00000000..23806ddf --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sch @@ -0,0 +1,231 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U? +U 1 1 6810D6D0 +P 4750 2900 +F 0 "U?" H 4750 2800 60 0000 C CNN +F 1 "d_inverter" H 4750 3050 60 0000 C CNN +F 2 "" H 4800 2850 60 0000 C CNN +F 3 "" H 4800 2850 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 6810D6FB +P 4750 3650 +F 0 "U?" H 4750 3550 60 0000 C CNN +F 1 "d_inverter" H 4750 3800 60 0000 C CNN +F 2 "" H 4800 3600 60 0000 C CNN +F 3 "" H 4800 3600 60 0000 C CNN + 1 4750 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 6810D736 +P 4750 4350 +F 0 "U?" H 4750 4250 60 0000 C CNN +F 1 "d_inverter" H 4750 4500 60 0000 C CNN +F 2 "" H 4800 4300 60 0000 C CNN +F 3 "" H 4800 4300 60 0000 C CNN + 1 4750 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 6810D763 +P 6800 3000 +F 0 "U?" H 6800 3000 60 0000 C CNN +F 1 "d_and" H 6850 3100 60 0000 C CNN +F 2 "" H 6800 3000 60 0000 C CNN +F 3 "" H 6800 3000 60 0000 C CNN + 1 6800 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 6810D7A6 +P 6400 3700 +F 0 "U?" H 6400 3600 60 0000 C CNN +F 1 "d_inverter" H 6400 3850 60 0000 C CNN +F 2 "" H 6450 3650 60 0000 C CNN +F 3 "" H 6450 3650 60 0000 C CNN + 1 6400 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 6810D7E7 +P 6400 4050 +F 0 "U?" H 6400 3950 60 0000 C CNN +F 1 "d_inverter" H 6400 4200 60 0000 C CNN +F 2 "" H 6450 4000 60 0000 C CNN +F 3 "" H 6450 4000 60 0000 C CNN + 1 6400 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 6810D820 +P 7300 3900 +F 0 "U?" H 7300 3900 60 0000 C CNN +F 1 "d_and" H 7350 4000 60 0000 C CNN +F 2 "" H 7300 3900 60 0000 C CNN +F 3 "" H 7300 3900 60 0000 C CNN + 1 7300 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U? +U 1 1 6810D85F +P 8400 3400 +F 0 "U?" H 8400 3400 60 0000 C CNN +F 1 "d_or" H 8400 3500 60 0000 C CNN +F 2 "" H 8400 3400 60 0000 C CNN +F 3 "" H 8400 3400 60 0000 C CNN + 1 8400 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 2900 6350 2900 +Wire Wire Line + 6700 3700 6850 3700 +Wire Wire Line + 6850 3700 6850 3800 +Wire Wire Line + 6700 4050 6850 4050 +Wire Wire Line + 6850 4050 6850 3900 +Wire Wire Line + 5050 3650 6100 3650 +Wire Wire Line + 6100 3650 6100 3700 +Wire Wire Line + 5050 4350 5750 4350 +Wire Wire Line + 5750 4350 5750 3000 +Wire Wire Line + 5750 3000 6350 3000 +Wire Wire Line + 6100 4050 5750 4050 +Connection ~ 5750 4050 +Wire Wire Line + 7750 3850 7850 3850 +Wire Wire Line + 7850 3850 7850 3400 +Wire Wire Line + 7850 3400 7950 3400 +Wire Wire Line + 7250 2950 7450 2950 +Wire Wire Line + 7450 2950 7450 3300 +Wire Wire Line + 7450 3300 7950 3300 +Wire Wire Line + 8850 3350 9100 3350 +Wire Wire Line + 4450 2900 4300 2900 +Wire Wire Line + 4450 3650 4350 3650 +Wire Wire Line + 4450 4350 4400 4350 +$Comp +L PORT U? +U 1 1 6810D9AE +P 4050 2900 +F 0 "U?" H 4100 3000 30 0000 C CNN +F 1 "PORT" H 4050 2900 30 0000 C CNN +F 2 "" H 4050 2900 60 0000 C CNN +F 3 "" H 4050 2900 60 0000 C CNN + 1 4050 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 2 1 6810D9F3 +P 4100 3650 +F 0 "U?" H 4150 3750 30 0000 C CNN +F 1 "PORT" H 4100 3650 30 0000 C CNN +F 2 "" H 4100 3650 60 0000 C CNN +F 3 "" H 4100 3650 60 0000 C CNN + 2 4100 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 3 1 6810DA26 +P 4150 4350 +F 0 "U?" H 4200 4450 30 0000 C CNN +F 1 "PORT" H 4150 4350 30 0000 C CNN +F 2 "" H 4150 4350 60 0000 C CNN +F 3 "" H 4150 4350 60 0000 C CNN + 3 4150 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 4 1 6810DAAE +P 9350 3350 +F 0 "U?" H 9400 3450 30 0000 C CNN +F 1 "PORT" H 9350 3350 30 0000 C CNN +F 2 "" H 9350 3350 60 0000 C CNN +F 3 "" H 9350 3350 60 0000 C CNN + 4 9350 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub new file mode 100644 index 00000000..042fec69 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub @@ -0,0 +1,38 @@ +* Subcircuit 74LVC1G57 +.subckt 74LVC1G57 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\74lvc1g57\74lvc1g57.cir +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_and +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad3_ d_and +* u9 net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad4_ d_or +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7 +a5 net-_u3-pad2_ net-_u5-pad2_ u5 +a6 net-_u4-pad2_ net-_u6-pad2_ u6 +a7 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u8-pad3_ u8 +a8 [net-_u7-pad3_ net-_u8-pad3_ ] net-_u1-pad4_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74LVC1G57
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57_Previous_Values.xml b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57_Previous_Values.xml new file mode 100644 index 00000000..6d94a02d --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u5 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LVC1G57/analysis b/library/SubcircuitLibrary/74LVC1G57/analysis new file mode 100644 index 00000000..af50a95b --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/analysis @@ -0,0 +1 @@ +.tran 0.001e-00 80e-00 0e-00
\ No newline at end of file |