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-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27-cache.lib77
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27.cir20
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27.cir.out48
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27.pro73
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27.sch299
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27.sub42
-rw-r--r--library/SubcircuitLibrary/74HC27/74HC27_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC27/analysis1
8 files changed, 561 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC27/74HC27-cache.lib b/library/SubcircuitLibrary/74HC27/74HC27-cache.lib
new file mode 100644
index 00000000..e5a63afe
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27-cache.lib
@@ -0,0 +1,77 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC27/74HC27.cir b/library/SubcircuitLibrary/74HC27/74HC27.cir
new file mode 100644
index 00000000..51149379
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27.cir
@@ -0,0 +1,20 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC27\74HC27.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/17/2025 4:51:11 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U2-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_or
+U6 Net-_U4-Pad3_ Net-_U1-Pad4_ d_inverter
+U13 Net-_U1-Pad12_ Net-_U1-Pad10_ Net-_U11-Pad1_ d_or
+U11 Net-_U11-Pad1_ Net-_U1-Pad8_ Net-_U11-Pad3_ d_or
+U9 Net-_U11-Pad3_ Net-_U1-Pad6_ d_inverter
+U12 Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or
+U10 Net-_U10-Pad1_ Net-_U1-Pad7_ Net-_U10-Pad3_ d_or
+U8 Net-_U10-Pad3_ Net-_U1-Pad5_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC27/74HC27.cir.out b/library/SubcircuitLibrary/74HC27/74HC27.cir.out
new file mode 100644
index 00000000..22bd055a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27.cir.out
@@ -0,0 +1,48 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc27\74hc27.cir
+
+* u2 net-_u1-pad2_ net-_u1-pad1_ net-_u2-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_or
+* u6 net-_u4-pad3_ net-_u1-pad4_ d_inverter
+* u13 net-_u1-pad12_ net-_u1-pad10_ net-_u11-pad1_ d_or
+* u11 net-_u11-pad1_ net-_u1-pad8_ net-_u11-pad3_ d_or
+* u9 net-_u11-pad3_ net-_u1-pad6_ d_inverter
+* u12 net-_u1-pad11_ net-_u1-pad9_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u1-pad7_ net-_u10-pad3_ d_or
+* u8 net-_u10-pad3_ net-_u1-pad5_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 net-_u4-pad3_ net-_u1-pad4_ u6
+a4 [net-_u1-pad12_ net-_u1-pad10_ ] net-_u11-pad1_ u13
+a5 [net-_u11-pad1_ net-_u1-pad8_ ] net-_u11-pad3_ u11
+a6 net-_u11-pad3_ net-_u1-pad6_ u9
+a7 [net-_u1-pad11_ net-_u1-pad9_ ] net-_u10-pad1_ u12
+a8 [net-_u10-pad1_ net-_u1-pad7_ ] net-_u10-pad3_ u10
+a9 net-_u10-pad3_ net-_u1-pad5_ u8
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC27/74HC27.pro b/library/SubcircuitLibrary/74HC27/74HC27.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC27/74HC27.sch b/library/SubcircuitLibrary/74HC27/74HC27.sch
new file mode 100644
index 00000000..cbf5960a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27.sch
@@ -0,0 +1,299 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 68286D60
+P 2700 2650
+F 0 "U2" H 2700 2650 60 0000 C CNN
+F 1 "d_or" H 2700 2750 60 0000 C CNN
+F 2 "" H 2700 2650 60 0000 C CNN
+F 3 "" H 2700 2650 60 0000 C CNN
+ 1 2700 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 68286DAF
+P 3800 2700
+F 0 "U4" H 3800 2700 60 0000 C CNN
+F 1 "d_or" H 3800 2800 60 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 1 3800 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68286E58
+P 4550 2650
+F 0 "U6" H 4550 2550 60 0000 C CNN
+F 1 "d_inverter" H 4550 2800 60 0000 C CNN
+F 2 "" H 4600 2600 60 0000 C CNN
+F 3 "" H 4600 2600 60 0000 C CNN
+ 1 4550 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3150 2600 3350 2600
+$Comp
+L d_or U13
+U 1 1 68287204
+P 8500 1950
+F 0 "U13" H 8500 1950 60 0000 C CNN
+F 1 "d_or" H 8500 2050 60 0000 C CNN
+F 2 "" H 8500 1950 60 0000 C CNN
+F 3 "" H 8500 1950 60 0000 C CNN
+ 1 8500 1950
+ -1 0 0 1
+$EndComp
+$Comp
+L d_or U11
+U 1 1 6828720A
+P 7400 1900
+F 0 "U11" H 7400 1900 60 0000 C CNN
+F 1 "d_or" H 7400 2000 60 0000 C CNN
+F 2 "" H 7400 1900 60 0000 C CNN
+F 3 "" H 7400 1900 60 0000 C CNN
+ 1 7400 1900
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 68287210
+P 6650 1950
+F 0 "U9" H 6650 1850 60 0000 C CNN
+F 1 "d_inverter" H 6650 2100 60 0000 C CNN
+F 2 "" H 6700 1900 60 0000 C CNN
+F 3 "" H 6700 1900 60 0000 C CNN
+ 1 6650 1950
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 8050 2000 7850 2000
+$Comp
+L d_or U12
+U 1 1 682873F1
+P 8400 3350
+F 0 "U12" H 8400 3350 60 0000 C CNN
+F 1 "d_or" H 8400 3450 60 0000 C CNN
+F 2 "" H 8400 3350 60 0000 C CNN
+F 3 "" H 8400 3350 60 0000 C CNN
+ 1 8400 3350
+ -1 0 0 1
+$EndComp
+$Comp
+L d_or U10
+U 1 1 682873F7
+P 7300 3300
+F 0 "U10" H 7300 3300 60 0000 C CNN
+F 1 "d_or" H 7300 3400 60 0000 C CNN
+F 2 "" H 7300 3300 60 0000 C CNN
+F 3 "" H 7300 3300 60 0000 C CNN
+ 1 7300 3300
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 682873FD
+P 6550 3350
+F 0 "U8" H 6550 3250 60 0000 C CNN
+F 1 "d_inverter" H 6550 3500 60 0000 C CNN
+F 2 "" H 6600 3300 60 0000 C CNN
+F 3 "" H 6600 3300 60 0000 C CNN
+ 1 6550 3350
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7950 3400 7750 3400
+$Comp
+L PORT U1
+U 2 1 68289F92
+P 2000 2550
+F 0 "U1" H 2050 2650 30 0000 C CNN
+F 1 "PORT" H 2000 2550 30 0000 C CNN
+F 2 "" H 2000 2550 60 0000 C CNN
+F 3 "" H 2000 2550 60 0000 C CNN
+ 2 2000 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6828A00F
+P 1600 2650
+F 0 "U1" H 1650 2750 30 0000 C CNN
+F 1 "PORT" H 1600 2650 30 0000 C CNN
+F 2 "" H 1600 2650 60 0000 C CNN
+F 3 "" H 1600 2650 60 0000 C CNN
+ 1 1600 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1850 2650 2250 2650
+$Comp
+L PORT U1
+U 3 1 6828A07E
+P 3100 2700
+F 0 "U1" H 3150 2800 30 0000 C CNN
+F 1 "PORT" H 3100 2700 30 0000 C CNN
+F 2 "" H 3100 2700 60 0000 C CNN
+F 3 "" H 3100 2700 60 0000 C CNN
+ 3 3100 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6828A111
+P 5100 2650
+F 0 "U1" H 5150 2750 30 0000 C CNN
+F 1 "PORT" H 5100 2650 30 0000 C CNN
+F 2 "" H 5100 2650 60 0000 C CNN
+F 3 "" H 5100 2650 60 0000 C CNN
+ 4 5100 2650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6828A16A
+P 9200 1950
+F 0 "U1" H 9250 2050 30 0000 C CNN
+F 1 "PORT" H 9200 1950 30 0000 C CNN
+F 2 "" H 9200 1950 60 0000 C CNN
+F 3 "" H 9200 1950 60 0000 C CNN
+ 10 9200 1950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6828A21D
+P 9650 2050
+F 0 "U1" H 9700 2150 30 0000 C CNN
+F 1 "PORT" H 9650 2050 30 0000 C CNN
+F 2 "" H 9650 2050 60 0000 C CNN
+F 3 "" H 9650 2050 60 0000 C CNN
+ 12 9650 2050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 9400 2050 8950 2050
+$Comp
+L PORT U1
+U 8 1 6828A2A9
+P 8100 1900
+F 0 "U1" H 8150 2000 30 0000 C CNN
+F 1 "PORT" H 8100 1900 30 0000 C CNN
+F 2 "" H 8100 1900 60 0000 C CNN
+F 3 "" H 8100 1900 60 0000 C CNN
+ 8 8100 1900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6828A320
+P 6100 1950
+F 0 "U1" H 6150 2050 30 0000 C CNN
+F 1 "PORT" H 6100 1950 30 0000 C CNN
+F 2 "" H 6100 1950 60 0000 C CNN
+F 3 "" H 6100 1950 60 0000 C CNN
+ 6 6100 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6828A38F
+P 9100 3350
+F 0 "U1" H 9150 3450 30 0000 C CNN
+F 1 "PORT" H 9100 3350 30 0000 C CNN
+F 2 "" H 9100 3350 60 0000 C CNN
+F 3 "" H 9100 3350 60 0000 C CNN
+ 9 9100 3350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6828A3F0
+P 9500 3450
+F 0 "U1" H 9550 3550 30 0000 C CNN
+F 1 "PORT" H 9500 3450 30 0000 C CNN
+F 2 "" H 9500 3450 60 0000 C CNN
+F 3 "" H 9500 3450 60 0000 C CNN
+ 11 9500 3450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 9250 3450 8850 3450
+$Comp
+L PORT U1
+U 7 1 6828A471
+P 8000 3300
+F 0 "U1" H 8050 3400 30 0000 C CNN
+F 1 "PORT" H 8000 3300 30 0000 C CNN
+F 2 "" H 8000 3300 60 0000 C CNN
+F 3 "" H 8000 3300 60 0000 C CNN
+ 7 8000 3300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6828A4D0
+P 6000 3350
+F 0 "U1" H 6050 3450 30 0000 C CNN
+F 1 "PORT" H 6000 3350 30 0000 C CNN
+F 2 "" H 6000 3350 60 0000 C CNN
+F 3 "" H 6000 3350 60 0000 C CNN
+ 5 6000 3350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC27/74HC27.sub b/library/SubcircuitLibrary/74HC27/74HC27.sub
new file mode 100644
index 00000000..ca5677d6
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27.sub
@@ -0,0 +1,42 @@
+* Subcircuit 74HC27
+.subckt 74HC27 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_
+* c:\fossee\esim\library\subcircuitlibrary\74hc27\74hc27.cir
+* u2 net-_u1-pad2_ net-_u1-pad1_ net-_u2-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_or
+* u6 net-_u4-pad3_ net-_u1-pad4_ d_inverter
+* u13 net-_u1-pad12_ net-_u1-pad10_ net-_u11-pad1_ d_or
+* u11 net-_u11-pad1_ net-_u1-pad8_ net-_u11-pad3_ d_or
+* u9 net-_u11-pad3_ net-_u1-pad6_ d_inverter
+* u12 net-_u1-pad11_ net-_u1-pad9_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u1-pad7_ net-_u10-pad3_ d_or
+* u8 net-_u10-pad3_ net-_u1-pad5_ d_inverter
+a1 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 net-_u4-pad3_ net-_u1-pad4_ u6
+a4 [net-_u1-pad12_ net-_u1-pad10_ ] net-_u11-pad1_ u13
+a5 [net-_u11-pad1_ net-_u1-pad8_ ] net-_u11-pad3_ u11
+a6 net-_u11-pad3_ net-_u1-pad6_ u9
+a7 [net-_u1-pad11_ net-_u1-pad9_ ] net-_u10-pad1_ u12
+a8 [net-_u10-pad1_ net-_u1-pad7_ ] net-_u10-pad3_ u10
+a9 net-_u10-pad3_ net-_u1-pad5_ u8
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC27 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC27/74HC27_Previous_Values.xml b/library/SubcircuitLibrary/74HC27/74HC27_Previous_Values.xml
new file mode 100644
index 00000000..6663ddda
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/74HC27_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_or<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u13 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u12 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u12><u10 name="type">d_or<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u10><u8 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC27/analysis b/library/SubcircuitLibrary/74HC27/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC27/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-07-05 01:37:18 +0000