summaryrefslogtreecommitdiff
path: root/library/SubcircuitLibrary/74HC20
diff options
context:
space:
mode:
Diffstat (limited to 'library/SubcircuitLibrary/74HC20')
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20-cache.lib94
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20.cir29
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20.cir.out84
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20.pro73
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20.sch448
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20.sub78
-rw-r--r--library/SubcircuitLibrary/74HC20/74HC20_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC20/analysis1
8 files changed, 808 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC20/74HC20-cache.lib b/library/SubcircuitLibrary/74HC20/74HC20-cache.lib
new file mode 100644
index 00000000..4e86b3d7
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC20/74HC20.cir b/library/SubcircuitLibrary/74HC20/74HC20.cir
new file mode 100644
index 00000000..fe512ed4
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20.cir
@@ -0,0 +1,29 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC20\74HC20.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/25 16:05:56
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter
+U3 Net-_U1-Pad2_ Net-_U10-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U4 Net-_U1-Pad3_ Net-_U11-Pad1_ d_inverter
+U5 Net-_U1-Pad4_ Net-_U11-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nor
+U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U14-Pad3_ d_nand
+U16 Net-_U14-Pad3_ Net-_U16-Pad2_ d_inverter
+U18 Net-_U16-Pad2_ Net-_U1-Pad5_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT
+U6 Net-_U1-Pad6_ Net-_U12-Pad1_ d_inverter
+U7 Net-_U1-Pad7_ Net-_U12-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor
+U8 Net-_U1-Pad8_ Net-_U13-Pad1_ d_inverter
+U9 Net-_U1-Pad9_ Net-_U13-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor
+U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U15-Pad3_ d_nand
+U17 Net-_U15-Pad3_ Net-_U17-Pad2_ d_inverter
+U19 Net-_U17-Pad2_ Net-_U1-Pad10_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/74HC20/74HC20.cir.out b/library/SubcircuitLibrary/74HC20/74HC20.cir.out
new file mode 100644
index 00000000..5f247846
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20.cir.out
@@ -0,0 +1,84 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc20\74hc20.cir
+
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u4 net-_u1-pad3_ net-_u11-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u11-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_nand
+* u16 net-_u14-pad3_ net-_u16-pad2_ d_inverter
+* u18 net-_u16-pad2_ net-_u1-pad5_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port
+* u6 net-_u1-pad6_ net-_u12-pad1_ d_inverter
+* u7 net-_u1-pad7_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_nand
+* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter
+* u19 net-_u17-pad2_ net-_u1-pad10_ d_inverter
+a1 net-_u1-pad1_ net-_u10-pad1_ u2
+a2 net-_u1-pad2_ net-_u10-pad2_ u3
+a3 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a4 net-_u1-pad3_ net-_u11-pad1_ u4
+a5 net-_u1-pad4_ net-_u11-pad2_ u5
+a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14
+a8 net-_u14-pad3_ net-_u16-pad2_ u16
+a9 net-_u16-pad2_ net-_u1-pad5_ u18
+a10 net-_u1-pad6_ net-_u12-pad1_ u6
+a11 net-_u1-pad7_ net-_u12-pad2_ u7
+a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a13 net-_u1-pad8_ net-_u13-pad1_ u8
+a14 net-_u1-pad9_ net-_u13-pad2_ u9
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a16 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15
+a17 net-_u15-pad3_ net-_u17-pad2_ u17
+a18 net-_u17-pad2_ net-_u1-pad10_ u19
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC20/74HC20.pro b/library/SubcircuitLibrary/74HC20/74HC20.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC20/74HC20.sch b/library/SubcircuitLibrary/74HC20/74HC20.sch
new file mode 100644
index 00000000..ee768836
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20.sch
@@ -0,0 +1,448 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U2
+U 1 1 684BFD35
+P 3000 1250
+F 0 "U2" H 3000 1150 60 0000 C CNN
+F 1 "d_inverter" H 3000 1400 60 0000 C CNN
+F 2 "" H 3050 1200 60 0000 C CNN
+F 3 "" H 3050 1200 60 0000 C CNN
+ 1 3000 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 684BFDD9
+P 3000 2250
+F 0 "U3" H 3000 2150 60 0000 C CNN
+F 1 "d_inverter" H 3000 2400 60 0000 C CNN
+F 2 "" H 3050 2200 60 0000 C CNN
+F 3 "" H 3050 2200 60 0000 C CNN
+ 1 3000 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 684BFE19
+P 4200 1650
+F 0 "U10" H 4200 1650 60 0000 C CNN
+F 1 "d_nor" H 4250 1750 60 0000 C CNN
+F 2 "" H 4200 1650 60 0000 C CNN
+F 3 "" H 4200 1650 60 0000 C CNN
+ 1 4200 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 684BFECC
+P 3100 2800
+F 0 "U4" H 3100 2700 60 0000 C CNN
+F 1 "d_inverter" H 3100 2950 60 0000 C CNN
+F 2 "" H 3150 2750 60 0000 C CNN
+F 3 "" H 3150 2750 60 0000 C CNN
+ 1 3100 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 684BFED2
+P 3100 3800
+F 0 "U5" H 3100 3700 60 0000 C CNN
+F 1 "d_inverter" H 3100 3950 60 0000 C CNN
+F 2 "" H 3150 3750 60 0000 C CNN
+F 3 "" H 3150 3750 60 0000 C CNN
+ 1 3100 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 684BFED8
+P 4300 3200
+F 0 "U11" H 4300 3200 60 0000 C CNN
+F 1 "d_nor" H 4350 3300 60 0000 C CNN
+F 2 "" H 4300 3200 60 0000 C CNN
+F 3 "" H 4300 3200 60 0000 C CNN
+ 1 4300 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U14
+U 1 1 684BFEEC
+P 5900 2250
+F 0 "U14" H 5900 2250 60 0000 C CNN
+F 1 "d_nand" H 5950 2350 60 0000 C CNN
+F 2 "" H 5900 2250 60 0000 C CNN
+F 3 "" H 5900 2250 60 0000 C CNN
+ 1 5900 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 684BFF83
+P 7350 2200
+F 0 "U16" H 7350 2100 60 0000 C CNN
+F 1 "d_inverter" H 7350 2350 60 0000 C CNN
+F 2 "" H 7400 2150 60 0000 C CNN
+F 3 "" H 7400 2150 60 0000 C CNN
+ 1 7350 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 684C003E
+P 8350 2200
+F 0 "U18" H 8350 2100 60 0000 C CNN
+F 1 "d_inverter" H 8350 2350 60 0000 C CNN
+F 2 "" H 8400 2150 60 0000 C CNN
+F 3 "" H 8400 2150 60 0000 C CNN
+ 1 8350 2200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3300 1250 3300 1550
+Wire Wire Line
+ 3300 1550 3750 1550
+Wire Wire Line
+ 3300 2250 3300 1650
+Wire Wire Line
+ 3300 1650 3750 1650
+Wire Wire Line
+ 4650 1600 5150 1600
+Wire Wire Line
+ 5150 1600 5150 2150
+Wire Wire Line
+ 5150 2150 5450 2150
+Wire Wire Line
+ 3400 2800 3600 2800
+Wire Wire Line
+ 3600 2800 3600 3100
+Wire Wire Line
+ 3600 3100 3850 3100
+Wire Wire Line
+ 3400 3800 3400 3200
+Wire Wire Line
+ 3400 3200 3850 3200
+Wire Wire Line
+ 4750 3150 4750 2250
+Wire Wire Line
+ 4750 2250 5450 2250
+Wire Wire Line
+ 6350 2200 7050 2200
+Wire Wire Line
+ 7650 2200 8050 2200
+$Comp
+L PORT U1
+U 2 1 684C03E8
+P 2000 2250
+F 0 "U1" H 2050 2350 30 0000 C CNN
+F 1 "PORT" H 2000 2250 30 0000 C CNN
+F 2 "" H 2000 2250 60 0000 C CNN
+F 3 "" H 2000 2250 60 0000 C CNN
+ 2 2000 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684C04F9
+P 2050 1250
+F 0 "U1" H 2100 1350 30 0000 C CNN
+F 1 "PORT" H 2050 1250 30 0000 C CNN
+F 2 "" H 2050 1250 60 0000 C CNN
+F 3 "" H 2050 1250 60 0000 C CNN
+ 1 2050 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684C0557
+P 2100 2800
+F 0 "U1" H 2150 2900 30 0000 C CNN
+F 1 "PORT" H 2100 2800 30 0000 C CNN
+F 2 "" H 2100 2800 60 0000 C CNN
+F 3 "" H 2100 2800 60 0000 C CNN
+ 3 2100 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684C05B8
+P 2100 5150
+F 0 "U1" H 2150 5250 30 0000 C CNN
+F 1 "PORT" H 2100 5150 30 0000 C CNN
+F 2 "" H 2100 5150 60 0000 C CNN
+F 3 "" H 2100 5150 60 0000 C CNN
+ 7 2100 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684C0696
+P 2350 6700
+F 0 "U1" H 2400 6800 30 0000 C CNN
+F 1 "PORT" H 2350 6700 30 0000 C CNN
+F 2 "" H 2350 6700 60 0000 C CNN
+F 3 "" H 2350 6700 60 0000 C CNN
+ 9 2350 6700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2300 1250 2700 1250
+Wire Wire Line
+ 2250 2250 2700 2250
+Wire Wire Line
+ 2350 2800 2800 2800
+Wire Wire Line
+ 2500 3800 2800 3800
+Wire Wire Line
+ 8650 2200 9100 2200
+$Comp
+L d_inverter U6
+U 1 1 684C158C
+P 3100 4150
+F 0 "U6" H 3100 4050 60 0000 C CNN
+F 1 "d_inverter" H 3100 4300 60 0000 C CNN
+F 2 "" H 3150 4100 60 0000 C CNN
+F 3 "" H 3150 4100 60 0000 C CNN
+ 1 3100 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 684C1592
+P 3100 5150
+F 0 "U7" H 3100 5050 60 0000 C CNN
+F 1 "d_inverter" H 3100 5300 60 0000 C CNN
+F 2 "" H 3150 5100 60 0000 C CNN
+F 3 "" H 3150 5100 60 0000 C CNN
+ 1 3100 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 684C1598
+P 4300 4550
+F 0 "U12" H 4300 4550 60 0000 C CNN
+F 1 "d_nor" H 4350 4650 60 0000 C CNN
+F 2 "" H 4300 4550 60 0000 C CNN
+F 3 "" H 4300 4550 60 0000 C CNN
+ 1 4300 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 684C159E
+P 3200 5700
+F 0 "U8" H 3200 5600 60 0000 C CNN
+F 1 "d_inverter" H 3200 5850 60 0000 C CNN
+F 2 "" H 3250 5650 60 0000 C CNN
+F 3 "" H 3250 5650 60 0000 C CNN
+ 1 3200 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 684C15A4
+P 3200 6700
+F 0 "U9" H 3200 6600 60 0000 C CNN
+F 1 "d_inverter" H 3200 6850 60 0000 C CNN
+F 2 "" H 3250 6650 60 0000 C CNN
+F 3 "" H 3250 6650 60 0000 C CNN
+ 1 3200 6700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U13
+U 1 1 684C15AA
+P 4400 6100
+F 0 "U13" H 4400 6100 60 0000 C CNN
+F 1 "d_nor" H 4450 6200 60 0000 C CNN
+F 2 "" H 4400 6100 60 0000 C CNN
+F 3 "" H 4400 6100 60 0000 C CNN
+ 1 4400 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U15
+U 1 1 684C15B0
+P 6000 5150
+F 0 "U15" H 6000 5150 60 0000 C CNN
+F 1 "d_nand" H 6050 5250 60 0000 C CNN
+F 2 "" H 6000 5150 60 0000 C CNN
+F 3 "" H 6000 5150 60 0000 C CNN
+ 1 6000 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U17
+U 1 1 684C15B6
+P 7450 5100
+F 0 "U17" H 7450 5000 60 0000 C CNN
+F 1 "d_inverter" H 7450 5250 60 0000 C CNN
+F 2 "" H 7500 5050 60 0000 C CNN
+F 3 "" H 7500 5050 60 0000 C CNN
+ 1 7450 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 684C15BC
+P 8450 5100
+F 0 "U19" H 8450 5000 60 0000 C CNN
+F 1 "d_inverter" H 8450 5250 60 0000 C CNN
+F 2 "" H 8500 5050 60 0000 C CNN
+F 3 "" H 8500 5050 60 0000 C CNN
+ 1 8450 5100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3400 4150 3400 4450
+Wire Wire Line
+ 3400 4450 3850 4450
+Wire Wire Line
+ 3400 5150 3400 4550
+Wire Wire Line
+ 3400 4550 3850 4550
+Wire Wire Line
+ 4750 4500 5250 4500
+Wire Wire Line
+ 5250 4500 5250 5050
+Wire Wire Line
+ 5250 5050 5550 5050
+Wire Wire Line
+ 3500 5700 3700 5700
+Wire Wire Line
+ 3700 5700 3700 6000
+Wire Wire Line
+ 3700 6000 3950 6000
+Wire Wire Line
+ 3500 6700 3500 6100
+Wire Wire Line
+ 3500 6100 3950 6100
+Wire Wire Line
+ 4850 6050 4850 5150
+Wire Wire Line
+ 4850 5150 5550 5150
+Wire Wire Line
+ 6450 5100 7150 5100
+Wire Wire Line
+ 7750 5100 8150 5100
+$Comp
+L PORT U1
+U 5 1 684C15D2
+P 9350 2200
+F 0 "U1" H 9400 2300 30 0000 C CNN
+F 1 "PORT" H 9350 2200 30 0000 C CNN
+F 2 "" H 9350 2200 60 0000 C CNN
+F 3 "" H 9350 2200 60 0000 C CNN
+ 5 9350 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684C15D8
+P 2250 3800
+F 0 "U1" H 2300 3900 30 0000 C CNN
+F 1 "PORT" H 2250 3800 30 0000 C CNN
+F 2 "" H 2250 3800 60 0000 C CNN
+F 3 "" H 2250 3800 60 0000 C CNN
+ 4 2250 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684C15DE
+P 2150 4150
+F 0 "U1" H 2200 4250 30 0000 C CNN
+F 1 "PORT" H 2150 4150 30 0000 C CNN
+F 2 "" H 2150 4150 60 0000 C CNN
+F 3 "" H 2150 4150 60 0000 C CNN
+ 6 2150 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684C15E4
+P 2200 5700
+F 0 "U1" H 2250 5800 30 0000 C CNN
+F 1 "PORT" H 2200 5700 30 0000 C CNN
+F 2 "" H 2200 5700 60 0000 C CNN
+F 3 "" H 2200 5700 60 0000 C CNN
+ 8 2200 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684C15EA
+P 9450 5100
+F 0 "U1" H 9500 5200 30 0000 C CNN
+F 1 "PORT" H 9450 5100 30 0000 C CNN
+F 2 "" H 9450 5100 60 0000 C CNN
+F 3 "" H 9450 5100 60 0000 C CNN
+ 10 9450 5100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2400 4150 2800 4150
+Wire Wire Line
+ 2350 5150 2800 5150
+Wire Wire Line
+ 2450 5700 2900 5700
+Wire Wire Line
+ 2600 6700 2900 6700
+Wire Wire Line
+ 8750 5100 9200 5100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC20/74HC20.sub b/library/SubcircuitLibrary/74HC20/74HC20.sub
new file mode 100644
index 00000000..c0a3a432
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20.sub
@@ -0,0 +1,78 @@
+* Subcircuit 74HC20
+.subckt 74HC20 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_
+* c:\fossee\esim\library\subcircuitlibrary\74hc20\74hc20.cir
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u4 net-_u1-pad3_ net-_u11-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u11-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_nand
+* u16 net-_u14-pad3_ net-_u16-pad2_ d_inverter
+* u18 net-_u16-pad2_ net-_u1-pad5_ d_inverter
+* u6 net-_u1-pad6_ net-_u12-pad1_ d_inverter
+* u7 net-_u1-pad7_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_nand
+* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter
+* u19 net-_u17-pad2_ net-_u1-pad10_ d_inverter
+a1 net-_u1-pad1_ net-_u10-pad1_ u2
+a2 net-_u1-pad2_ net-_u10-pad2_ u3
+a3 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a4 net-_u1-pad3_ net-_u11-pad1_ u4
+a5 net-_u1-pad4_ net-_u11-pad2_ u5
+a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14
+a8 net-_u14-pad3_ net-_u16-pad2_ u16
+a9 net-_u16-pad2_ net-_u1-pad5_ u18
+a10 net-_u1-pad6_ net-_u12-pad1_ u6
+a11 net-_u1-pad7_ net-_u12-pad2_ u7
+a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a13 net-_u1-pad8_ net-_u13-pad1_ u8
+a14 net-_u1-pad9_ net-_u13-pad2_ u9
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a16 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15
+a17 net-_u15-pad3_ net-_u17-pad2_ u17
+a18 net-_u17-pad2_ net-_u1-pad10_ u19
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC20 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC20/74HC20_Previous_Values.xml b/library/SubcircuitLibrary/74HC20/74HC20_Previous_Values.xml
new file mode 100644
index 00000000..1c1c5813
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/74HC20_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u10 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u10><u4 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u11 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u11><u14 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u16 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u16><u18 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u18><u6 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u7><u12 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u12><u8 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u9><u13 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC20/analysis b/library/SubcircuitLibrary/74HC20/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC20/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-07-05 04:03:03 +0000