summaryrefslogtreecommitdiff
path: root/library/SubcircuitLibrary/74HC147N/74HC147.cir.out
diff options
context:
space:
mode:
Diffstat (limited to 'library/SubcircuitLibrary/74HC147N/74HC147.cir.out')
-rw-r--r--library/SubcircuitLibrary/74HC147N/74HC147.cir.out144
1 files changed, 144 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC147N/74HC147.cir.out b/library/SubcircuitLibrary/74HC147N/74HC147.cir.out
new file mode 100644
index 00000000..433f316c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC147N/74HC147.cir.out
@@ -0,0 +1,144 @@
+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\74hc147\74hc147.cir
+
+.include 3_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u6 net-_u1-pad2_ net-_u3-pad1_ d_inverter
+* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter
+* u15 net-_u1-pad4_ net-_u15-pad2_ d_inverter
+* u20 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u22 net-_u1-pad6_ net-_u13-pad1_ d_inverter
+* u25 net-_u1-pad7_ net-_u25-pad2_ d_inverter
+* u26 net-_u1-pad8_ net-_u26-pad2_ d_inverter
+* u29 net-_u1-pad9_ net-_u29-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u2-pad2_ net-_u11-pad2_ d_nor
+* u4 net-_u3-pad1_ net-_u2-pad2_ net-_u4-pad3_ d_nor
+* u5 net-_u4-pad3_ net-_u1-pad13_ d_buffer
+* u7 net-_u12-pad2_ net-_u11-pad2_ net-_u7-pad3_ d_and
+* u8 net-_u15-pad2_ net-_u11-pad2_ net-_u8-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter
+* u14 net-_u12-pad2_ net-_u11-pad2_ net-_u14-pad3_ d_and
+* u17 net-_u15-pad2_ net-_u11-pad2_ net-_u17-pad3_ d_and
+x2 net-_u25-pad2_ net-_u23-pad2_ net-_u21-pad2_ net-_u11-pad2_ net-_x2-pad5_ 4_and
+x4 net-_u26-pad2_ net-_u23-pad2_ net-_u21-pad2_ net-_u11-pad2_ net-_x3-pad1_ 4_and
+* u24 net-_u12-pad2_ net-_u11-pad2_ net-_u24-pad3_ d_and
+x5 net-_u11-pad1_ net-_u16-pad2_ net-_u11-pad2_ net-_x5-pad4_ 3_and
+x7 net-_u25-pad2_ net-_u23-pad2_ net-_u16-pad2_ net-_u11-pad2_ net-_x6-pad1_ 4_and
+x8 net-_u23-pad2_ net-_u16-pad2_ net-_u11-pad2_ net-_x8-pad4_ 3_and
+x9 net-_u29-pad2_ net-_u27-pad2_ net-_x8-pad4_ net-_u28-pad1_ 3_and
+* u21 net-_u11-pad1_ net-_u21-pad2_ d_inverter
+* u23 net-_u13-pad1_ net-_u23-pad2_ d_inverter
+* u27 net-_u26-pad2_ net-_u27-pad2_ d_inverter
+x1 net-_u13-pad3_ net-_u11-pad3_ net-_u8-pad3_ net-_u7-pad3_ net-_u9-pad1_ 4_OR
+x3 net-_x3-pad1_ net-_x2-pad5_ net-_u17-pad3_ net-_u14-pad3_ net-_u18-pad1_ 4_OR
+x6 net-_x6-pad1_ net-_x5-pad4_ net-_u24-pad3_ net-_u2-pad2_ net-_u28-pad2_ 4_OR
+* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_or
+* u9 net-_u9-pad1_ net-_u10-pad1_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u30 net-_u28-pad3_ net-_u30-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u1-pad12_ d_buffer
+* u19 net-_u18-pad2_ net-_u1-pad11_ d_buffer
+* u31 net-_u30-pad2_ net-_u1-pad10_ d_buffer
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 net-_u1-pad2_ net-_u3-pad1_ u6
+a3 net-_u1-pad3_ net-_u12-pad2_ u12
+a4 net-_u1-pad4_ net-_u15-pad2_ u15
+a5 net-_u1-pad5_ net-_u11-pad1_ u20
+a6 net-_u1-pad6_ net-_u13-pad1_ u22
+a7 net-_u1-pad7_ net-_u25-pad2_ u25
+a8 net-_u1-pad8_ net-_u26-pad2_ u26
+a9 net-_u1-pad9_ net-_u29-pad2_ u29
+a10 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u11-pad2_ u3
+a11 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a12 net-_u4-pad3_ net-_u1-pad13_ u5
+a13 [net-_u12-pad2_ net-_u11-pad2_ ] net-_u7-pad3_ u7
+a14 [net-_u15-pad2_ net-_u11-pad2_ ] net-_u8-pad3_ u8
+a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a16 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a17 net-_u15-pad2_ net-_u16-pad2_ u16
+a18 [net-_u12-pad2_ net-_u11-pad2_ ] net-_u14-pad3_ u14
+a19 [net-_u15-pad2_ net-_u11-pad2_ ] net-_u17-pad3_ u17
+a20 [net-_u12-pad2_ net-_u11-pad2_ ] net-_u24-pad3_ u24
+a21 net-_u11-pad1_ net-_u21-pad2_ u21
+a22 net-_u13-pad1_ net-_u23-pad2_ u23
+a23 net-_u26-pad2_ net-_u27-pad2_ u27
+a24 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a25 net-_u9-pad1_ net-_u10-pad1_ u9
+a26 net-_u18-pad1_ net-_u18-pad2_ u18
+a27 net-_u28-pad3_ net-_u30-pad2_ u30
+a28 net-_u10-pad1_ net-_u1-pad12_ u10
+a29 net-_u18-pad2_ net-_u1-pad11_ u19
+a30 net-_u30-pad2_ net-_u1-pad10_ u31
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
generated by cgit (git 2.34.1) at 2025-06-30 05:28:46 +0000