diff options
Diffstat (limited to 'library/SubcircuitLibrary/54act11030/74_1030.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/54act11030/74_1030.cir.out | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/54act11030/74_1030.cir.out b/library/SubcircuitLibrary/54act11030/74_1030.cir.out new file mode 100644 index 00000000..27abdd10 --- /dev/null +++ b/library/SubcircuitLibrary/54act11030/74_1030.cir.out @@ -0,0 +1,40 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74_1030\74_1030.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_nand +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_nand +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad9_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad9_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |