diff options
Diffstat (limited to 'library/SubcircuitLibrary/3_nor')
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor-cache.lib | 146 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor.cir | 20 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor.cir.out | 32 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor.pro | 73 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor.sch | 332 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor.sub | 26 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/NMOS-180nm.lib | 13 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/PMOS-180nm.lib | 11 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/3_nor/analysis | 1 |
10 files changed, 655 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/3_nor/3_nor-cache.lib b/library/SubcircuitLibrary/3_nor/3_nor-cache.lib new file mode 100644 index 00000000..4ba918af --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir b/library/SubcircuitLibrary/3_nor/3_nor.cir new file mode 100644 index 00000000..b8881701 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.cir @@ -0,0 +1,20 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor\3_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/25 12:25:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M5 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M6 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad1_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M2-Pad1_ eSim_MOS_P +M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +U4 Net-_U3-Pad2_ Net-_U1-Pad6_ d_buffer +U3 Net-_M1-Pad1_ Net-_U3-Pad2_ adc_bridge_1 +U2 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M4-Pad2_ dac_bridge_3 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad3_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir.out b/library/SubcircuitLibrary/3_nor/3_nor.cir.out new file mode 100644 index 00000000..551422c5 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer +* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 +* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ port +a1 net-_u3-pad2_ net-_u1-pad6_ u4 +a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 +a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.pro b/library/SubcircuitLibrary/3_nor/3_nor.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/3_nor/3_nor.sch b/library/SubcircuitLibrary/3_nor/3_nor.sch new file mode 100644 index 00000000..fe1cae25 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.sch @@ -0,0 +1,332 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:3_nor-cache +LIBS:3_norgate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3300 4650 3300 4450 +Wire Wire Line + 3300 1300 3300 4300 +$Comp +L mosfet_n M1 +U 1 1 684BC8E7 +P 4700 3600 +F 0 "M1" H 4700 3450 50 0000 R CNN +F 1 "mosfet_n" H 4800 3550 50 0000 R CNN +F 2 "" H 5000 3300 29 0000 C CNN +F 3 "" H 4800 3400 60 0000 C CNN + 1 4700 3600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 684BC8E8 +P 6050 3600 +F 0 "M5" H 6050 3450 50 0000 R CNN +F 1 "mosfet_n" H 6150 3550 50 0000 R CNN +F 2 "" H 6350 3300 29 0000 C CNN +F 3 "" H 6150 3400 60 0000 C CNN + 1 6050 3600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 684BC8E9 +P 7200 3650 +F 0 "M6" H 7200 3500 50 0000 R CNN +F 1 "mosfet_n" H 7300 3600 50 0000 R CNN +F 2 "" H 7500 3350 29 0000 C CNN +F 3 "" H 7300 3450 60 0000 C CNN + 1 7200 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 684BC8EA +P 5400 1300 +F 0 "M2" H 5350 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 1450 50 0000 R CNN +F 2 "" H 5650 1400 29 0000 C CNN +F 3 "" H 5450 1300 60 0000 C CNN + 1 5400 1300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 684BC8EB +P 5400 1950 +F 0 "M3" H 5350 2000 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 2100 50 0000 R CNN +F 2 "" H 5650 2050 29 0000 C CNN +F 3 "" H 5450 1950 60 0000 C CNN + 1 5400 1950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 684BC8EC +P 5400 2600 +F 0 "M4" H 5350 2650 50 0000 R CNN +F 1 "eSim_MOS_P" H 5450 2750 50 0000 R CNN +F 2 "" H 5650 2700 29 0000 C CNN +F 3 "" H 5450 2600 60 0000 C CNN + 1 5400 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 3600 7400 3600 +Wire Wire Line + 7400 3600 7400 3650 +Connection ~ 6250 3600 +Wire Wire Line + 4900 4000 4900 4250 +Wire Wire Line + 4900 4250 7500 4250 +Wire Wire Line + 7400 4250 7400 4050 +Wire Wire Line + 6250 4000 6250 4250 +Connection ~ 6250 4250 +Wire Wire Line + 5000 3950 5000 4250 +Connection ~ 5000 4250 +Wire Wire Line + 6350 3950 6350 4500 +Connection ~ 6350 4250 +Wire Wire Line + 7500 4250 7500 4000 +Connection ~ 7400 4250 +Wire Wire Line + 5550 1500 5550 1750 +Wire Wire Line + 5550 2150 5550 2400 +Wire Wire Line + 5550 1100 5550 850 +Wire Wire Line + 5550 850 6500 850 +Wire Wire Line + 5650 1450 5950 1450 +Wire Wire Line + 5950 850 5950 2750 +Connection ~ 5950 850 +Wire Wire Line + 5950 2100 5650 2100 +Connection ~ 5950 1450 +Wire Wire Line + 5950 2750 5650 2750 +Connection ~ 5950 2100 +Wire Wire Line + 5550 2800 5550 3600 +Connection ~ 5550 3600 +Wire Wire Line + 3300 3800 4600 3800 +Wire Wire Line + 3300 1300 5250 1300 +Connection ~ 3300 3800 +Wire Wire Line + 3300 4450 5950 4450 +Wire Wire Line + 5950 4450 5950 3800 +Wire Wire Line + 3650 5050 7100 5050 +Wire Wire Line + 7100 5050 7100 3850 +Wire Wire Line + 4200 4450 4200 1950 +Wire Wire Line + 4200 1950 5250 1950 +Connection ~ 4200 4450 +Wire Wire Line + 5350 5050 5350 2800 +Wire Wire Line + 5350 2800 5100 2800 +Wire Wire Line + 5100 2800 5100 2600 +Wire Wire Line + 5100 2600 5250 2600 +Connection ~ 5350 5050 +Connection ~ 5550 3200 +$Comp +L d_buffer U4 +U 1 1 684BC8F1 +P 7800 3100 +F 0 "U4" H 7800 3050 60 0000 C CNN +F 1 "d_buffer" H 7800 3150 60 0000 C CNN +F 2 "" H 7800 3100 60 0000 C CNN +F 3 "" H 7800 3100 60 0000 C CNN + 1 7800 3100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 684BC8F2 +P 6400 3250 +F 0 "U3" H 6400 3250 60 0000 C CNN +F 1 "adc_bridge_1" H 6400 3400 60 0000 C CNN +F 2 "" H 6400 3250 60 0000 C CNN +F 3 "" H 6400 3250 60 0000 C CNN + 1 6400 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 3200 5800 3200 +Wire Wire Line + 6950 3200 6950 3100 +Wire Wire Line + 6950 3100 7300 3100 +Wire Wire Line + 8450 3100 8450 3550 +Wire Wire Line + 8450 3550 8550 3550 +$Comp +L dac_bridge_3 U2 +U 1 1 684BCCBA +P 2350 4600 +F 0 "U2" H 2350 4600 60 0000 C CNN +F 1 "dac_bridge_3" H 2350 4750 60 0000 C CNN +F 2 "" H 2350 4600 60 0000 C CNN +F 3 "" H 2350 4600 60 0000 C CNN + 1 2350 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4550 3100 4550 +Wire Wire Line + 3100 4550 3100 4300 +Wire Wire Line + 3100 4300 3300 4300 +Wire Wire Line + 2900 4650 3300 4650 +Wire Wire Line + 2900 4750 3650 4750 +Wire Wire Line + 3650 4750 3650 5050 +$Comp +L PORT U1 +U 3 1 684BCFDE +P 1050 4500 +F 0 "U1" H 1100 4600 30 0000 C CNN +F 1 "PORT" H 1050 4500 30 0000 C CNN +F 2 "" H 1050 4500 60 0000 C CNN +F 3 "" H 1050 4500 60 0000 C CNN + 3 1050 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 684BD073 +P 950 4650 +F 0 "U1" H 1000 4750 30 0000 C CNN +F 1 "PORT" H 950 4650 30 0000 C CNN +F 2 "" H 950 4650 60 0000 C CNN +F 3 "" H 950 4650 60 0000 C CNN + 1 950 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684BD0CA +P 950 4850 +F 0 "U1" H 1000 4950 30 0000 C CNN +F 1 "PORT" H 950 4850 30 0000 C CNN +F 2 "" H 950 4850 60 0000 C CNN +F 3 "" H 950 4850 60 0000 C CNN + 2 950 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 4500 1750 4500 +Wire Wire Line + 1750 4500 1750 4550 +Wire Wire Line + 1200 4650 1750 4650 +Wire Wire Line + 1200 4850 1200 4750 +Wire Wire Line + 1200 4750 1750 4750 +$Comp +L PORT U1 +U 4 1 684BD531 +P 6500 1100 +F 0 "U1" H 6550 1200 30 0000 C CNN +F 1 "PORT" H 6500 1100 30 0000 C CNN +F 2 "" H 6500 1100 60 0000 C CNN +F 3 "" H 6500 1100 60 0000 C CNN + 4 6500 1100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 684BD700 +P 6600 4500 +F 0 "U1" H 6650 4600 30 0000 C CNN +F 1 "PORT" H 6600 4500 30 0000 C CNN +F 2 "" H 6600 4500 60 0000 C CNN +F 3 "" H 6600 4500 60 0000 C CNN + 5 6600 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 684BDA88 +P 8800 3550 +F 0 "U1" H 8850 3650 30 0000 C CNN +F 1 "PORT" H 8800 3550 30 0000 C CNN +F 2 "" H 8800 3550 60 0000 C CNN +F 3 "" H 8800 3550 60 0000 C CNN + 6 8800 3550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/3_nor/3_nor.sub b/library/SubcircuitLibrary/3_nor/3_nor.sub new file mode 100644 index 00000000..9bbbe57a --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.sub @@ -0,0 +1,26 @@ +* Subcircuit 3_nor +.subckt 3_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ +* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer +* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 +* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 +a1 net-_u3-pad2_ net-_u1-pad6_ u4 +a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 +a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 3_nor
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml new file mode 100644 index 00000000..2c30c1aa --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_buffer<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">adc_bridge<field4 name="Enter value for in_low (default=1.0)" /><field5 name="Enter value for in_high (default=2.0)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /><field7 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">dac_bridge<field8 name="Enter value for out_low (default=0.0)" /><field9 name="Enter value for out_high (default=5.0)" /><field10 name="Enter value for out_undef (default=0.5)" /><field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /></u2></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib b/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib b/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/3_nor/analysis b/library/SubcircuitLibrary/3_nor/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |