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| author | Tanisha1511 | 2025-05-18 23:22:14 +0530 |
|---|---|---|
| committer | Tanisha1511 | 2025-05-18 23:22:14 +0530 |
| commit | 5dd70b0967de8aba54962f6eb9a212b054b019b4 (patch) | |
| tree | 7b914c3275132e27b4a57ea5f76e238ef15e29bd /library/SubcircuitLibrary/SN74LVC1G29/7429.sub | |
| parent | 09da83943f541c7dc196e8bc0f16f754379d6419 (diff) | |
| download | eSim-5dd70b0967de8aba54962f6eb9a212b054b019b4.tar.gz eSim-5dd70b0967de8aba54962f6eb9a212b054b019b4.tar.bz2 eSim-5dd70b0967de8aba54962f6eb9a212b054b019b4.zip | |
SN74LVC1G29 as a 2-of-3 decoder/ demultiplexer IC
Diffstat (limited to 'library/SubcircuitLibrary/SN74LVC1G29/7429.sub')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LVC1G29/7429.sub | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.sub b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub new file mode 100644 index 00000000..a3c8ad39 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub @@ -0,0 +1,38 @@ +* Subcircuit 7429 +.subckt 7429 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\fossee\esim\library\subcircuitlibrary\7429\7429.cir +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u6 net-_u1-pad2_ net-_u4-pad2_ net-_u6-pad3_ d_and +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_and +* u9 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad4_ d_nand +* u7 net-_u2-pad2_ net-_u6-pad3_ net-_u1-pad5_ d_nand +* u8 net-_u2-pad2_ net-_u5-pad3_ net-_u1-pad6_ d_nand +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u6-pad3_ u6 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5 +a6 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u1-pad4_ u9 +a7 [net-_u2-pad2_ net-_u6-pad3_ ] net-_u1-pad5_ u7 +a8 [net-_u2-pad2_ net-_u5-pad3_ ] net-_u1-pad6_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 7429
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