8 files changed, 551 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib b/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib
new file mode 100644
index 00000000..44055200
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429-cache.lib
@@ -0,0 +1,92 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.cir b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir
new file mode 100644
index 00000000..454fdb10
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir
@@ -0,0 +1,19 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\7429\7429.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/12/25 14:38:38
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
+U6  Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U6-Pad3_ d_and		
+U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
+U5  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U5-Pad3_ d_and		
+U9  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad4_ d_nand		
+U7  Net-_U2-Pad2_ Net-_U6-Pad3_ Net-_U1-Pad5_ d_nand		
+U8  Net-_U2-Pad2_ Net-_U5-Pad3_ Net-_U1-Pad6_ d_nand		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out
new file mode 100644
index 00000000..182d14b6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.cir.out
@@ -0,0 +1,44 @@
+* c:\fossee\esim\library\subcircuitlibrary\7429\7429.cir
+
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u6  net-_u1-pad2_ net-_u4-pad2_ net-_u6-pad3_ d_and
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_and
+* u9  net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad4_ d_nand
+* u7  net-_u2-pad2_ net-_u6-pad3_ net-_u1-pad5_ d_nand
+* u8  net-_u2-pad2_ net-_u5-pad3_ net-_u1-pad6_ d_nand
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 net-_u1-pad2_ net-_u3-pad2_ u3
+a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u6-pad3_ u6
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a6 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u1-pad4_ u9
+a7 [net-_u2-pad2_ net-_u6-pad3_ ] net-_u1-pad5_ u7
+a8 [net-_u2-pad2_ net-_u5-pad3_ ] net-_u1-pad6_ u8
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.pro b/library/SubcircuitLibrary/SN74LVC1G29/7429.pro
new file mode 100644
index 00000000..3d81b09e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.pro
@@ -0,0 +1,83 @@
+update=05/12/25 17:58:53
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.sch b/library/SubcircuitLibrary/SN74LVC1G29/7429.sch
new file mode 100644
index 00000000..56a2da46
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.sch
@@ -0,0 +1,273 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U2
+U 1 1 6821B961
+P 2600 2100
+F 0 "U2" H 2600 2000 60  0000 C CNN
+F 1 "d_inverter" H 2600 2250 60  0000 C CNN
+F 2 "" H 2650 2050 60  0000 C CNN
+F 3 "" H 2650 2050 60  0000 C CNN
+	1    2600 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 6821B9A6
+P 3600 2600
+F 0 "U3" H 3600 2500 60  0000 C CNN
+F 1 "d_inverter" H 3600 2750 60  0000 C CNN
+F 2 "" H 3650 2550 60  0000 C CNN
+F 3 "" H 3650 2550 60  0000 C CNN
+	1    3600 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U6
+U 1 1 6821B9C3
+P 5100 3050
+F 0 "U6" H 5100 3050 60  0000 C CNN
+F 1 "d_and" H 5150 3150 60  0000 C CNN
+F 2 "" H 5100 3050 60  0000 C CNN
+F 3 "" H 5100 3050 60  0000 C CNN
+	1    5100 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 6821B9DE
+P 3600 3550
+F 0 "U4" H 3600 3450 60  0000 C CNN
+F 1 "d_inverter" H 3600 3700 60  0000 C CNN
+F 2 "" H 3650 3500 60  0000 C CNN
+F 3 "" H 3650 3500 60  0000 C CNN
+	1    3600 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U5
+U 1 1 6821BA03
+P 5050 4100
+F 0 "U5" H 5050 4100 60  0000 C CNN
+F 1 "d_and" H 5100 4200 60  0000 C CNN
+F 2 "" H 5050 4100 60  0000 C CNN
+F 3 "" H 5050 4100 60  0000 C CNN
+	1    5050 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U9
+U 1 1 6821BA2A
+P 7500 2100
+F 0 "U9" H 7500 2100 60  0000 C CNN
+F 1 "d_nand" H 7550 2200 60  0000 C CNN
+F 2 "" H 7500 2100 60  0000 C CNN
+F 3 "" H 7500 2100 60  0000 C CNN
+	1    7500 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 6821BA51
+P 7450 3150
+F 0 "U7" H 7450 3150 60  0000 C CNN
+F 1 "d_nand" H 7500 3250 60  0000 C CNN
+F 2 "" H 7450 3150 60  0000 C CNN
+F 3 "" H 7450 3150 60  0000 C CNN
+	1    7450 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 6821BA7A
+P 7450 4150
+F 0 "U8" H 7450 4150 60  0000 C CNN
+F 1 "d_nand" H 7500 4250 60  0000 C CNN
+F 2 "" H 7450 4150 60  0000 C CNN
+F 3 "" H 7450 4150 60  0000 C CNN
+	1    7450 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6821BAA5
+P 1750 2100
+F 0 "U1" H 1800 2200 30  0000 C CNN
+F 1 "PORT" H 1750 2100 30  0000 C CNN
+F 2 "" H 1750 2100 60  0000 C CNN
+F 3 "" H 1750 2100 60  0000 C CNN
+	1    1750 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6821BB1D
+P 1750 2550
+F 0 "U1" H 1800 2650 30  0000 C CNN
+F 1 "PORT" H 1750 2550 30  0000 C CNN
+F 2 "" H 1750 2550 60  0000 C CNN
+F 3 "" H 1750 2550 60  0000 C CNN
+	2    1750 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6821BB4A
+P 1750 3550
+F 0 "U1" H 1800 3650 30  0000 C CNN
+F 1 "PORT" H 1750 3550 30  0000 C CNN
+F 2 "" H 1750 3550 60  0000 C CNN
+F 3 "" H 1750 3550 60  0000 C CNN
+	3    1750 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6821BBE9
+P 8500 2050
+F 0 "U1" H 8550 2150 30  0000 C CNN
+F 1 "PORT" H 8500 2050 30  0000 C CNN
+F 2 "" H 8500 2050 60  0000 C CNN
+F 3 "" H 8500 2050 60  0000 C CNN
+	4    8500 2050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6821BC47
+P 8500 3100
+F 0 "U1" H 8550 3200 30  0000 C CNN
+F 1 "PORT" H 8500 3100 30  0000 C CNN
+F 2 "" H 8500 3100 60  0000 C CNN
+F 3 "" H 8500 3100 60  0000 C CNN
+	5    8500 3100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6821BC84
+P 8500 4100
+F 0 "U1" H 8550 4200 30  0000 C CNN
+F 1 "PORT" H 8500 4100 30  0000 C CNN
+F 2 "" H 8500 4100 60  0000 C CNN
+F 3 "" H 8500 4100 60  0000 C CNN
+	6    8500 4100
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2000 2100 2300 2100
+Wire Wire Line
+	2000 2550 3300 2550
+Wire Wire Line
+	3300 2550 3300 2600
+Wire Wire Line
+	2000 3550 3300 3550
+Wire Wire Line
+	3000 2550 3000 4000
+Wire Wire Line
+	3000 2950 4650 2950
+Connection ~ 3000 2550
+Wire Wire Line
+	3900 3550 4650 3550
+Wire Wire Line
+	4650 3550 4650 3050
+Wire Wire Line
+	3000 4000 4600 4000
+Connection ~ 3000 2950
+Wire Wire Line
+	2500 3550 2500 4100
+Wire Wire Line
+	2500 4100 4600 4100
+Connection ~ 2500 3550
+Wire Wire Line
+	2900 2100 6200 2100
+Wire Wire Line
+	6200 2100 6200 2000
+Wire Wire Line
+	6200 2000 7050 2000
+Wire Wire Line
+	3900 2600 6300 2600
+Wire Wire Line
+	6300 2600 6300 2100
+Wire Wire Line
+	6300 2100 7050 2100
+Wire Wire Line
+	5550 3000 6100 3000
+Wire Wire Line
+	6100 3000 6100 3150
+Wire Wire Line
+	6100 3150 7000 3150
+Wire Wire Line
+	6750 2000 6750 4050
+Wire Wire Line
+	6750 3050 7000 3050
+Connection ~ 6750 2000
+Wire Wire Line
+	5500 4050 5900 4050
+Wire Wire Line
+	5900 4050 5900 4150
+Wire Wire Line
+	5900 4150 7000 4150
+Wire Wire Line
+	6750 4050 7000 4050
+Connection ~ 6750 3050
+Wire Wire Line
+	7950 2050 8250 2050
+Wire Wire Line
+	7900 3100 8250 3100
+Wire Wire Line
+	7900 4100 8250 4100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429.sub b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub
new file mode 100644
index 00000000..a3c8ad39
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429.sub
@@ -0,0 +1,38 @@
+* Subcircuit 7429
+.subckt 7429 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\fossee\esim\library\subcircuitlibrary\7429\7429.cir
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u6  net-_u1-pad2_ net-_u4-pad2_ net-_u6-pad3_ d_and
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_and
+* u9  net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad4_ d_nand
+* u7  net-_u2-pad2_ net-_u6-pad3_ net-_u1-pad5_ d_nand
+* u8  net-_u2-pad2_ net-_u5-pad3_ net-_u1-pad6_ d_nand
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 net-_u1-pad2_ net-_u3-pad2_ u3
+a3 [net-_u1-pad2_ net-_u4-pad2_ ] net-_u6-pad3_ u6
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a6 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u1-pad4_ u9
+a7 [net-_u2-pad2_ net-_u6-pad3_ ] net-_u1-pad5_ u7
+a8 [net-_u2-pad2_ net-_u5-pad3_ ] net-_u1-pad6_ u8
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 7429
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml
new file mode 100644
index 00000000..1a454041
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/7429_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G29/analysis b/library/SubcircuitLibrary/SN74LVC1G29/analysis
new file mode 100644
index 00000000..58ce5800
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G29/analysis
@@ -0,0 +1 @@
+.tran 10e-03 10e-00 0e-03
\ No newline at end of file