Merge pull request #290 from Eyantra698Sumanto/masterHEADmaster

Subcircuit Files of ICs(Contributor: Shweta Khune)

1 files changed, 226 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub
new file mode 100644
index 00000000..777e7e3f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub
@@ -0,0 +1,226 @@
+* Subcircuit SN74LS148_IC
+.subckt SN74LS148_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir
+.include 4_and.sub
+.include 5_and.sub
+.include 3_and.sub
+* u23  net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand
+* u24  net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand
+* u25  net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand
+* u26  net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand
+* u29  net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand
+* u30  net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand
+* u31  net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand
+* u32  net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand
+* u41  net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand
+* u42  net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand
+* u48  net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand
+* u49  net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand
+* u50  net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand
+* u53  net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand
+* u5  net-_u2-pad9_ net-_u5-pad2_ d_inverter
+x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and
+x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and
+x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and
+* u16  net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and
+* u35  net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor
+* u36  net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor
+* u43  net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor
+* u44  net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor
+* u47  net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor
+x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and
+x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and
+* u17  net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and
+* u18  net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and
+* u27  net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor
+* u28  net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor
+* u37  net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor
+* u38  net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor
+* u45  net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor
+* u19  net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and
+* u20  net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and
+* u21  net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and
+* u22  net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and
+* u33  net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor
+* u34  net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor
+* u39  net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor
+* u40  net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor
+* u46  net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor
+* u3  net-_u2-pad10_ net-_u12-pad1_ d_inverter
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u4  net-_u2-pad11_ net-_u4-pad2_ d_inverter
+* u6  net-_u2-pad12_ net-_u13-pad1_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u7  net-_u2-pad13_ net-_u14-pad1_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u8  net-_u2-pad14_ net-_u15-pad1_ d_inverter
+* u15  net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u9  net-_u2-pad15_ net-_u16-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u2  net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8
+* u11  net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1
+* u54  net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand
+* u52  net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5
+* u51  net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand
+a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23
+a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24
+a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25
+a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26
+a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29
+a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30
+a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32
+a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41
+a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42
+a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48
+a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49
+a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50
+a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53
+a15 net-_u2-pad9_ net-_u5-pad2_ u5
+a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16
+a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35
+a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36
+a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43
+a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44
+a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47
+a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18
+a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28
+a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37
+a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38
+a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45
+a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19
+a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20
+a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21
+a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22
+a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33
+a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34
+a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39
+a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46
+a38 net-_u2-pad10_ net-_u12-pad1_ u3
+a39 net-_u12-pad1_ net-_u12-pad2_ u12
+a40 net-_u2-pad11_ net-_u4-pad2_ u4
+a41 net-_u2-pad12_ net-_u13-pad1_ u6
+a42 net-_u13-pad1_ net-_u13-pad2_ u13
+a43 net-_u2-pad13_ net-_u14-pad1_ u7
+a44 net-_u14-pad1_ net-_u14-pad2_ u14
+a45 net-_u2-pad14_ net-_u15-pad1_ u8
+a46 net-_u15-pad1_ net-_u15-pad2_ u15
+a47 net-_u2-pad15_ net-_u16-pad1_ u9
+a48 net-_u10-pad1_ net-_u10-pad2_ u10
+a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2
+a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11
+a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54
+a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52
+a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_5, NgSpice Name: dac_bridge
+.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74LS148_IC
\ No newline at end of file