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authorSumanto Kar2024-11-21 23:46:28 +0530
committerGitHub2024-11-21 23:46:28 +0530
commit1992c0efc2805f0683360514b23cdc5517361e00 (patch)
tree23a8b023d2f06b910ade250b20828710db0d2582 /library/SubcircuitLibrary/SN74LS148_sub/3_and.sub
parentc7f8a75e51d3c79aaa994b25849bcb358543f12c (diff)
parent25f132133deed0e2f134ceeb001fb816c747249c (diff)
downloadeSim-1992c0efc2805f0683360514b23cdc5517361e00.tar.gz
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Merge pull request #290 from Eyantra698Sumanto/masterHEADmaster
Subcircuit Files of ICs(Contributor: Shweta Khune)
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS148_sub/3_and.sub')
-rw-r--r--library/SubcircuitLibrary/SN74LS148_sub/3_and.sub14
1 files changed, 14 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub
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+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file