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| author | Sumanto Kar | 2025-02-23 17:37:05 +0530 |
|---|---|---|
| committer | GitHub | 2025-02-23 17:37:05 +0530 |
| commit | 311d0244d6093ebdccee00d072016b7a7a1c9372 (patch) | |
| tree | 02f10e99abea8736d02fc46a12895bcad2743cf6 /library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out | |
| parent | ae99d42b8d2ffeaf91f96d5ffbe5efe91214cf0c (diff) | |
| parent | 053d7b4f66655f04b4965b26ffea0125cab1ccdd (diff) | |
| download | eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.gz eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.tar.bz2 eSim-311d0244d6093ebdccee00d072016b7a7a1c9372.zip | |
Merge pull request #300 from Maanit491/master
Subcircuit files for different ICs
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out new file mode 100644 index 00000000..15fe255d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir + +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |