From 9da74f5f268449a049fc1fe1691a6f8d0f498dc1 Mon Sep 17 00:00:00 2001
From: Maanit
Date: Sun, 16 Feb 2025 19:38:47 +0530
Subject: SN74LS00 is a Quad 2-Input NAND Gate IC

---
 library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out

(limited to 'library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out')

diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out
new file mode 100644
index 00000000..15fe255d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out
@@ -0,0 +1,17 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir
+
+.include NAND_GATE_FINAL.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL
+x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL
+x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL
+x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit